1/*
2 * Copyright (c) 2023 by Rivos Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <0x01>;
9	#size-cells = <0x01>;
10	compatible = "lowrisc,opentitan-earlgrey";
11
12	cpus {
13		#address-cells = <0x01>;
14		#size-cells = <0x00>;
15
16		cpu@0 {
17			device_type = "cpu";
18			reg = <0x00>;
19			status = "okay";
20			compatible = "lowrisc,ibex", "riscv";
21			riscv,isa = "rv32imcb_zicsr_zifencei";
22
23			hlic: interrupt-controller {
24				#interrupt-cells = <0x01>;
25				interrupt-controller;
26				compatible = "riscv,cpu-intc";
27			};
28		};
29	};
30
31	soc {
32		#address-cells = <0x01>;
33		#size-cells = <0x01>;
34		compatible = "simple-bus";
35		ranges;
36
37		flash0: flash@20000000 {
38			reg = <0x20000000 0x100000>;
39			compatible = "soc-nv-flash";
40		};
41
42		ram0: memory@10000000 {
43			device_type = "memory";
44			reg = <0x10000000 0x10000>;
45		};
46
47		mtimer: timer@40100000 {
48			compatible = "lowrisc,machine-timer";
49			reg = <0x40100000 0x200>;
50			interrupts = <7 0>;
51			interrupt-parent = <&hlic>;
52			status = "disabled";
53		};
54
55		aontimer: aontimer@40470000 {
56			compatible = "lowrisc,opentitan-aontimer";
57			reg = <0x40470000 0x1000>;
58			interrupts = <156 1>;
59			interrupt-names = "wdog_bark";
60			interrupt-parent = <&plic>;
61			clock-frequency = <200000>;
62			status = "disabled";
63		};
64
65		pwrmgr: pwrmgr@40400000 {
66			compatible = "lowrisc,opentitan-pwrmgr";
67			reg = <0x40400000 0x80>;
68			status = "okay";
69		};
70
71		plic: interrupt-controller@48000000 {
72			compatible = "sifive,plic-1.0.0";
73			#address-cells = <0>;
74			#interrupt-cells = <2>;
75			interrupt-controller;
76			interrupts-extended = <&hlic 11>;
77			reg = <0x48000000 0x04000000>;
78			riscv,max-priority = <7>;
79			riscv,ndev = <182>;
80			status = "okay";
81		};
82
83		uart0: serial@40000000{
84			reg = <0x40000000 0x1000>;
85			compatible = "lowrisc,opentitan-uart";
86			status = "disabled";
87		};
88
89		spi0: spi@40300000 {
90			compatible = "lowrisc,opentitan-spi";
91			status = "disabled";
92			reg = <0x40300000 0x100>;
93			clock-frequency = <96000000>;
94			#address-cells = <1>;
95			#size-cells = <0>;
96		};
97
98		spi1: spi@40310000 {
99			compatible = "lowrisc,opentitan-spi";
100			status = "disabled";
101			reg = <0x40310000 0x100>;
102			clock-frequency = <48000000>;
103			#address-cells = <1>;
104			#size-cells = <0>;
105		};
106	};
107};
108
109