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Searched refs:TIM_ECR_FIDX_Pos (Results 1 – 25 of 50) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c3048 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
3057 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
3066 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_tim_ex.c2926 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_tim_ex.c2971 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2901 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c3049 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_tim_ex.c3241 … ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | in HAL_TIMEx_ConfigEncoderIndex()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9079 #define TIM_ECR_FIDX_Pos (5U) macro
9080 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32wba52xx.h13247 #define TIM_ECR_FIDX_Pos (5U) macro
13248 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32wba54xx.h13955 #define TIM_ECR_FIDX_Pos (5U) macro
13956 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32wba5mxx.h13973 #define TIM_ECR_FIDX_Pos (5U) macro
13974 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
Dstm32wba55xx.h13973 #define TIM_ECR_FIDX_Pos (5U) macro
13974 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h10256 #define TIM_ECR_FIDX_Pos (5U) macro
10257 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g411xc.h10474 #define TIM_ECR_FIDX_Pos (5U) macro
10475 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g441xx.h11040 #define TIM_ECR_FIDX_Pos (5U) macro
11041 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32gbk1cb.h10782 #define TIM_ECR_FIDX_Pos (5U) macro
10783 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g431xx.h10810 #define TIM_ECR_FIDX_Pos (5U) macro
10811 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g4a1xx.h11550 #define TIM_ECR_FIDX_Pos (5U) macro
11551 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g491xx.h11320 #define TIM_ECR_FIDX_Pos (5U) macro
11321 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g473xx.h12111 #define TIM_ECR_FIDX_Pos (5U) macro
12112 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g471xx.h11543 #define TIM_ECR_FIDX_Pos (5U) macro
11544 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g483xx.h12341 #define TIM_ECR_FIDX_Pos (5U) macro
12342 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g414xx.h14522 #define TIM_ECR_FIDX_Pos (5U) macro
14523 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g474xx.h15690 #define TIM_ECR_FIDX_Pos (5U) macro
15691 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
Dstm32g484xx.h15920 #define TIM_ECR_FIDX_Pos (5U) macro
15921 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h7521 #define TIM_ECR_FIDX_Pos (5U) macro
7522 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020…

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