1 /**
2   ******************************************************************************
3   * @file    stm32g414xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32G414xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2019 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32g414xx
30   * @{
31   */
32 
33 #ifndef __STM32G414xx_H
34 #define __STM32G414xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32G4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32G4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32G4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                                 */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                                   */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                                            */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                                    */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                                  */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                                     */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                                               */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                                 */
77 /******  STM32 specific Interrupt Numbers ***************************************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                                          */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts                     */
80   RTC_TAMP_LSECSS_IRQn        = 2,      /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI               */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                                         */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                                             */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                                               */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                                               */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                                               */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                                               */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                                               */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                                               */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                                    */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                                    */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                                    */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                                    */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                                    */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                                    */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                                    */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                                                     */
97   FDCAN1_IT0_IRQn             = 21,     /*!< FDCAN1 IT0 Interrupt                                                               */
98   FDCAN1_IT1_IRQn             = 22,     /*!< FDCAN1 IT1 Interrupt                                                               */
99   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                                      */
100   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt               */
101   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                                   */
102   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
103   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                                     */
104   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                                              */
105   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                                              */
106   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                                              */
107   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                                               */
108   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                                               */
109   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                                               */
110   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                                               */
111   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                                              */
112   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                                              */
113   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                                            */
114   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                                            */
115   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                                    */
116   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                                    */
117   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break, Transition error and Index error Interrupt                             */
118   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                                              */
119   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt                    */
120   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                                     */
121   LPTIM1_IRQn                 = 49,     /*!< LP TIM1 Interrupt                                                                  */
122   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                                              */
123   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                                             */
124   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                                             */
125   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&3 underrun error  interrupts                                  */
126   TIM7_DAC_IRQn               = 55,     /*!< TIM7 global and DAC2&4 underrun error  interrupts                                  */
127   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                                    */
128   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                                    */
129   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                                    */
130   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                                    */
131   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                                    */
132   COMP1_2_3_IRQn              = 64,     /*!< COMP1, COMP2 and COMP3 Interrupts                                                  */
133   COMP4_5_6_IRQn              = 65,     /*!< COMP4, COMP5 and COMP6                                                             */
134   COMP7_IRQn                  = 66,     /*!< COMP7 Interrupt                                                                    */
135   HRTIM1_Master_IRQn          = 67,     /*!< HRTIM Master Timer global Interrupt                                                */
136   HRTIM1_TIMA_IRQn            = 68,     /*!< HRTIM Timer A global Interrupt                                                     */
137   HRTIM1_TIMB_IRQn            = 69,     /*!< HRTIM Timer B global Interrupt                                                     */
138   HRTIM1_TIMC_IRQn            = 70,     /*!< HRTIM Timer C global Interrupt                                                     */
139   HRTIM1_TIMD_IRQn            = 71,     /*!< HRTIM Timer D global Interrupt                                                     */
140   HRTIM1_TIME_IRQn            = 72,     /*!< HRTIM Timer E global Interrupt                                                     */
141   HRTIM1_FLT_IRQn             = 73,     /*!< HRTIM Fault global Interrupt                                                       */
142   HRTIM1_TIMF_IRQn            = 74,     /*!< HRTIM Timer F global Interrupt                                                     */
143   CRS_IRQn                    = 75,     /*!< CRS global interrupt                                                               */
144   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                                               */
145   AES_IRQn                    = 85,     /*!< AES global interrupt                                                               */
146   RNG_IRQn                    = 90,     /*!< RNG global interrupt                                                               */
147   LPUART1_IRQn                = 91,     /*!< LP UART 1 Interrupt                                                                */
148   I2C3_EV_IRQn                = 92,     /*!< I2C3 Event Interrupt                                                               */
149   I2C3_ER_IRQn                = 93,     /*!< I2C3 Error interrupt                                                               */
150   DMAMUX_OVR_IRQn             = 94,     /*!< DMAMUX overrun global interrupt                                                    */
151   DMA1_Channel8_IRQn          = 96,     /*!< DMA1 Channel 8 interrupt                                                           */
152   DMA2_Channel6_IRQn          = 97,     /*!< DMA2 Channel 6 interrupt                                                           */
153   DMA2_Channel7_IRQn          = 98,     /*!< DMA2 Channel 7 interrupt                                                           */
154   DMA2_Channel8_IRQn          = 99,     /*!< DMA2 Channel 8 interrupt                                                           */
155   CORDIC_IRQn                 = 100,    /*!< CORDIC global Interrupt                                                            */
156   FMAC_IRQn                   = 101     /*!< FMAC global Interrupt                                                              */
157 } IRQn_Type;
158 
159 /**
160   * @}
161   */
162 
163 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
164 #include "system_stm32g4xx.h"
165 #include <stdint.h>
166 
167 /** @addtogroup Peripheral_registers_structures
168   * @{
169   */
170 
171 /**
172   * @brief Analog to Digital Converter
173   */
174 
175 typedef struct
176 {
177   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
178   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
179   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
180   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
181   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
182   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
183   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
184        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
185   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
186   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
187   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
188        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
189   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
190   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
191   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
192   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
193   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
194        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
195        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
196   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
197        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
198   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
199   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
200   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
201   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
202        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
203   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
204   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
205   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
206   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
207        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
208   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
209   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
210        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
211        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
212   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
213   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
214        uint32_t RESERVED10[2];/*!< Reserved,                                             0x0B8 - 0x0BC */
215   __IO uint32_t GCOMP;        /*!< ADC calibration factors,                       Address offset: 0xC0 */
216 } ADC_TypeDef;
217 
218 typedef struct
219 {
220   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
221   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
222   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
223   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
224 } ADC_Common_TypeDef;
225 
226 /**
227   * @brief FD Controller Area Network
228   */
229 
230 typedef struct
231 {
232   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
233   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
234        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
235   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
236   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
237   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
238   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
239   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
240   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
241   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
242   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
243   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
244        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
245   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
246   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
247   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
248        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
249   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
250   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
251   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
252   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
253        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
254   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
255   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
256   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
257        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
258   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
259   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
260   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
261   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
262        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
263   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
264   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
265   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
266   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
267   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
268   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
269   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
270   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
271   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
272   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
273   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
274 } FDCAN_GlobalTypeDef;
275 
276 /**
277   * @brief FD Controller Area Network Configuration
278   */
279 
280 typedef struct
281 {
282   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
283 } FDCAN_Config_TypeDef;
284 
285 /**
286   * @brief Comparator
287   */
288 
289 typedef struct
290 {
291   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
292 } COMP_TypeDef;
293 
294 /**
295   * @brief CRC calculation unit
296   */
297 
298 typedef struct
299 {
300   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
301   __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
302   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
303   uint32_t      RESERVED0;   /*!< Reserved,                                                    0x0C */
304   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
305   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
306 } CRC_TypeDef;
307 
308 /**
309   * @brief Clock Recovery System
310   */
311 typedef struct
312 {
313   __IO uint32_t CR;          /*!< CRS ccontrol register,              Address offset: 0x00 */
314   __IO uint32_t CFGR;        /*!< CRS configuration register,         Address offset: 0x04 */
315   __IO uint32_t ISR;         /*!< CRS interrupt and status register,  Address offset: 0x08 */
316   __IO uint32_t ICR;         /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
317 } CRS_TypeDef;
318 
319 /**
320   * @brief Digital to Analog Converter
321   */
322 
323 typedef struct
324 {
325   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
326   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
327   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
328   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
329   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
330   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
331   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
332   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
333   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
334   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
335   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
336   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
337   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
338   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
339   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
340   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
341   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
342   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
343   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
344   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
345   __IO uint32_t RESERVED[2];
346   __IO uint32_t STR1;        /*!< DAC Sawtooth register,                                   Address offset: 0x58 */
347   __IO uint32_t STR2;        /*!< DAC Sawtooth register,                                   Address offset: 0x5C */
348   __IO uint32_t STMODR;      /*!< DAC Sawtooth Mode register,                              Address offset: 0x60 */
349 } DAC_TypeDef;
350 
351 /**
352   * @brief Debug MCU
353   */
354 
355 typedef struct
356 {
357   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
358   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
359   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
360   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
361   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
362 } DBGMCU_TypeDef;
363 
364 /**
365   * @brief DMA Controller
366   */
367 
368 typedef struct
369 {
370   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
371   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
372   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
373   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
374 } DMA_Channel_TypeDef;
375 
376 typedef struct
377 {
378   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
379   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
380 } DMA_TypeDef;
381 
382 /**
383   * @brief DMA Multiplexer
384   */
385 
386 typedef struct
387 {
388   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
389 }DMAMUX_Channel_TypeDef;
390 
391 typedef struct
392 {
393   __IO uint32_t   CSR;      /*!< DMA Channel Status Register                    Address offset: 0x0080   */
394   __IO uint32_t   CFR;      /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
395 }DMAMUX_ChannelStatus_TypeDef;
396 
397 typedef struct
398 {
399   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
400 }DMAMUX_RequestGen_TypeDef;
401 
402 typedef struct
403 {
404   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
405   __IO uint32_t   RGCFR;        /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
406 }DMAMUX_RequestGenStatus_TypeDef;
407 
408 /**
409   * @brief External Interrupt/Event Controller
410   */
411 
412 typedef struct
413 {
414   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
415   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
416   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
417   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
418   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
419   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
420   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
421   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
422   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
423   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
424   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
425   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
426   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
427   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
428 } EXTI_TypeDef;
429 
430 /**
431   * @brief FLASH Registers
432   */
433 
434 typedef struct
435 {
436   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
437   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
438   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
439   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
440   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
441   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
442   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
443        uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
444   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
445   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
446   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
447   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
448   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
449        uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
450   __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
451   __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
452   __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
453   __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
454        uint32_t RESERVED3[7];     /*!< Reserved3,                                Address offset: 0x54 */
455   __IO uint32_t SEC1R;            /*!< FLASH Securable memory register bank1,    Address offset: 0x70 */
456   __IO uint32_t SEC2R;            /*!< FLASH Securable memory register bank2,    Address offset: 0x74 */
457 } FLASH_TypeDef;
458 
459 /**
460   * @brief FMAC
461   */
462 typedef struct
463 {
464   __IO uint32_t X1BUFCFG;        /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00          */
465   __IO uint32_t X2BUFCFG;        /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04          */
466   __IO uint32_t YBUFCFG;         /*!< FMAC Y Buffer Configuration register,  Address offset: 0x08          */
467   __IO uint32_t PARAM;           /*!< FMAC Parameter register,               Address offset: 0x0C          */
468   __IO uint32_t CR;              /*!< FMAC Control register,                 Address offset: 0x10          */
469   __IO uint32_t SR;              /*!< FMAC Status register,                  Address offset: 0x14          */
470   __IO uint32_t WDATA;           /*!< FMAC Write Data register,              Address offset: 0x18          */
471   __IO uint32_t RDATA;           /*!< FMAC Read Data register,               Address offset: 0x1C          */
472 } FMAC_TypeDef;
473 
474 
475 /**
476   * @brief General Purpose I/O
477   */
478 
479 typedef struct
480 {
481   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
482   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
483   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
484   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
485   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
486   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
487   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
488   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
489   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
490   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
491 } GPIO_TypeDef;
492 
493 /**
494   * @brief Inter-integrated Circuit Interface
495   */
496 
497 typedef struct
498 {
499   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
500   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
501   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
502   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
503   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
504   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
505   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
506   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
507   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
508   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
509   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
510 } I2C_TypeDef;
511 
512 /**
513   * @brief Independent WATCHDOG
514   */
515 
516 typedef struct
517 {
518   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
519   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
520   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
521   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
522   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
523 } IWDG_TypeDef;
524 
525 /**
526   * @brief LPTIMER
527   */
528 
529 typedef struct
530 {
531   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
532   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
533   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
534   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
535   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
536   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
537   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
538   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
539   __IO uint32_t OR;               /*!< LPTIM Option register,                              Address offset: 0x20 */
540 } LPTIM_TypeDef;
541 
542 
543 /**
544   * @brief Power Control
545   */
546 
547 typedef struct
548 {
549   __IO uint32_t CR1;      /*!< PWR power control register 1,        Address offset: 0x00 */
550   __IO uint32_t CR2;      /*!< PWR power control register 2,        Address offset: 0x04 */
551   __IO uint32_t CR3;      /*!< PWR power control register 3,        Address offset: 0x08 */
552   __IO uint32_t CR4;      /*!< PWR power control register 4,        Address offset: 0x0C */
553   __IO uint32_t SR1;      /*!< PWR power status register 1,         Address offset: 0x10 */
554   __IO uint32_t SR2;      /*!< PWR power status register 2,         Address offset: 0x14 */
555   __IO uint32_t SCR;      /*!< PWR power status reset register,     Address offset: 0x18 */
556   uint32_t RESERVED;      /*!< Reserved,                            Address offset: 0x1C */
557   __IO uint32_t PUCRA;    /*!< Pull_up control register of portA,   Address offset: 0x20 */
558   __IO uint32_t PDCRA;    /*!< Pull_Down control register of portA, Address offset: 0x24 */
559   __IO uint32_t PUCRB;    /*!< Pull_up control register of portB,   Address offset: 0x28 */
560   __IO uint32_t PDCRB;    /*!< Pull_Down control register of portB, Address offset: 0x2C */
561   __IO uint32_t PUCRC;    /*!< Pull_up control register of portC,   Address offset: 0x30 */
562   __IO uint32_t PDCRC;    /*!< Pull_Down control register of portC, Address offset: 0x34 */
563   __IO uint32_t PUCRD;    /*!< Pull_up control register of portD,   Address offset: 0x38 */
564   __IO uint32_t PDCRD;    /*!< Pull_Down control register of portD, Address offset: 0x3C */
565   __IO uint32_t PUCRE;    /*!< Pull_up control register of portE,   Address offset: 0x40 */
566   __IO uint32_t PDCRE;    /*!< Pull_Down control register of portE, Address offset: 0x44 */
567   __IO uint32_t PUCRF;    /*!< Pull_up control register of portF,   Address offset: 0x48 */
568   __IO uint32_t PDCRF;    /*!< Pull_Down control register of portF, Address offset: 0x4C */
569   __IO uint32_t PUCRG;    /*!< Pull_up control register of portG,   Address offset: 0x50 */
570   __IO uint32_t PDCRG;    /*!< Pull_Down control register of portG, Address offset: 0x54 */
571   uint32_t RESERVED1[10]; /*!< Reserved                             Address offset: 0x58 - 0x7C */
572   __IO uint32_t CR5;      /*!< PWR power control register 5,        Address offset: 0x80 */
573 } PWR_TypeDef;
574 
575 
576 /**
577   * @brief Reset and Clock Control
578   */
579 
580 typedef struct
581 {
582   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
583   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
584   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
585   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
586   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x10 */
587   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x14 */
588   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
589   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
590   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
591   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x24 */
592   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
593   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
594   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
595   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x34 */
596   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
597   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
598   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
599   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x44 */
600   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
601   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
602   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
603   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x54 */
604   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
605   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
606   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
607   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x64 */
608   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
609   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
610   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
611   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x74 */
612   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
613   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
614   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
615   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x84 */
616   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
617   uint32_t      RESERVED9;   /*!< Reserved,                                                                Address offset: 0x8C */
618   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
619   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
620   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
621   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
622 } RCC_TypeDef;
623 
624 /**
625   * @brief Real-Time Clock
626   */
627 /*
628 * @brief Specific device feature definitions
629 */
630 #define RTC_TAMP_INT_6_SUPPORT
631 #define RTC_TAMP_INT_NB        4u
632 
633 #define RTC_TAMP_NB            3u
634 #define RTC_BACKUP_NB          32u
635 
636 
637 typedef struct
638 {
639   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
640   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
641   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
642   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
643   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
644   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
645   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
646        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
647        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
648   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
649   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
650   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
651   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
652   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
653   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
654        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x3C */
655   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
656   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
657   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
658   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
659   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
660   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
661        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
662   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
663 } RTC_TypeDef;
664 
665 /**
666   * @brief Tamper and backup registers
667   */
668 
669 typedef struct
670 {
671   __IO uint32_t CR1;                     /*!< TAMP configuration register 1,          Address offset: 0x00 */
672   __IO uint32_t CR2;                     /*!< TAMP configuration register 2,          Address offset: 0x04 */
673        uint32_t RESERVED0;               /*!< no configuration register 3,            Address offset: 0x08 */
674   __IO uint32_t FLTCR;                   /*!< TAMP filter control register,           Address offset: 0x0C */
675        uint32_t RESERVED1[6];            /*!< Reserved                                Address offset: 0x10 - 0x24 */
676        uint32_t RESERVED2;               /*!< Reserved                                Address offset: 0x28 */
677   __IO uint32_t IER;                     /*!< TAMP Interrupt enable register,         Address offset: 0x2C */
678   __IO uint32_t SR;                      /*!< TAMP Status register,                   Address offset: 0x30 */
679   __IO uint32_t MISR;                    /*!< TAMP Masked Interrupt Status register   Address offset: 0x34 */
680        uint32_t RESERVED3;               /*!< Reserved                                Address offset: 0x38 */
681   __IO uint32_t SCR;                     /*!< TAMP Status clear register,             Address offset: 0x3C */
682        uint32_t RESERVED4[48];           /*!< Reserved                                Address offset: 0x040 - 0xFC */
683   __IO uint32_t BKP0R;                   /*!< TAMP backup register 0,                 Address offset: 0x100 */
684   __IO uint32_t BKP1R;                   /*!< TAMP backup register 1,                 Address offset: 0x104 */
685   __IO uint32_t BKP2R;                   /*!< TAMP backup register 2,                 Address offset: 0x108 */
686   __IO uint32_t BKP3R;                   /*!< TAMP backup register 3,                 Address offset: 0x10C */
687   __IO uint32_t BKP4R;                   /*!< TAMP backup register 4,                 Address offset: 0x110 */
688   __IO uint32_t BKP5R;                   /*!< TAMP backup register 5,                 Address offset: 0x114 */
689   __IO uint32_t BKP6R;                   /*!< TAMP backup register 6,                 Address offset: 0x118 */
690   __IO uint32_t BKP7R;                   /*!< TAMP backup register 7,                 Address offset: 0x11C */
691   __IO uint32_t BKP8R;                   /*!< TAMP backup register 8,                 Address offset: 0x120 */
692   __IO uint32_t BKP9R;                   /*!< TAMP backup register 9,                 Address offset: 0x124 */
693   __IO uint32_t BKP10R;                  /*!< TAMP backup register 10,                Address offset: 0x128 */
694   __IO uint32_t BKP11R;                  /*!< TAMP backup register 11,                Address offset: 0x12C */
695   __IO uint32_t BKP12R;                  /*!< TAMP backup register 12,                Address offset: 0x130 */
696   __IO uint32_t BKP13R;                  /*!< TAMP backup register 13,                Address offset: 0x134 */
697   __IO uint32_t BKP14R;                  /*!< TAMP backup register 14,                Address offset: 0x138 */
698   __IO uint32_t BKP15R;                  /*!< TAMP backup register 15,                Address offset: 0x13C */
699   __IO uint32_t BKP16R;                  /*!< TAMP backup register 16,                Address offset: 0x140 */
700   __IO uint32_t BKP17R;                  /*!< TAMP backup register 17,                Address offset: 0x144 */
701   __IO uint32_t BKP18R;                  /*!< TAMP backup register 18,                Address offset: 0x148 */
702   __IO uint32_t BKP19R;                  /*!< TAMP backup register 19,                Address offset: 0x14C */
703   __IO uint32_t BKP20R;                  /*!< TAMP backup register 20,                Address offset: 0x150 */
704   __IO uint32_t BKP21R;                  /*!< TAMP backup register 21,                Address offset: 0x154 */
705   __IO uint32_t BKP22R;                  /*!< TAMP backup register 22,                Address offset: 0x158 */
706   __IO uint32_t BKP23R;                  /*!< TAMP backup register 23,                Address offset: 0x15C */
707   __IO uint32_t BKP24R;                  /*!< TAMP backup register 24,                Address offset: 0x160 */
708   __IO uint32_t BKP25R;                  /*!< TAMP backup register 25,                Address offset: 0x164 */
709   __IO uint32_t BKP26R;                  /*!< TAMP backup register 26,                Address offset: 0x168 */
710   __IO uint32_t BKP27R;                  /*!< TAMP backup register 27,                Address offset: 0x16C */
711   __IO uint32_t BKP28R;                  /*!< TAMP backup register 28,                Address offset: 0x170 */
712   __IO uint32_t BKP29R;                  /*!< TAMP backup register 29,                Address offset: 0x174 */
713   __IO uint32_t BKP30R;                  /*!< TAMP backup register 30,                Address offset: 0x178 */
714   __IO uint32_t BKP31R;                  /*!< TAMP backup register 31,                Address offset: 0x17C */
715 } TAMP_TypeDef;
716 
717 
718 /**
719   * @brief Serial Peripheral Interface
720   */
721 
722 typedef struct
723 {
724   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
725   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
726   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
727   __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
728   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
729   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
730   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
731   __IO uint32_t I2SCFGR;     /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
732   __IO uint32_t I2SPR;       /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
733 } SPI_TypeDef;
734 
735 /**
736   * @brief System configuration controller
737   */
738 
739 typedef struct
740 {
741   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                        Address offset: 0x00      */
742   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                     Address offset: 0x04      */
743   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers,   Address offset: 0x08-0x14 */
744   __IO uint32_t SCSR;        /*!< SYSCFG CCMSRAM control and status register,          Address offset: 0x18      */
745   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                     Address offset: 0x1C      */
746   __IO uint32_t SWPR;        /*!< SYSCFG CCMSRAM write protection register,            Address offset: 0x20      */
747   __IO uint32_t SKR;         /*!< SYSCFG CCMSRAM Key Register,                         Address offset: 0x24      */
748 } SYSCFG_TypeDef;
749 
750 /**
751   * @brief TIM
752   */
753 
754 typedef struct
755 {
756   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
757   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
758   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
759   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
760   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
761   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
762   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
763   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
764   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
765   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
766   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
767   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
768   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
769   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
770   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
771   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
772   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
773   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
774   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
775   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
776   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
777   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
778   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
779   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
780   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
781   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
782   __IO uint32_t OR ;         /*!< TIM option register,                      Address offset: 0x68 */
783        uint32_t RESERVED0[220];/*!< Reserved,                               Address offset: 0x6C */
784   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
785   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
786 } TIM_TypeDef;
787 
788 /**
789   * @brief Universal Synchronous Asynchronous Receiver Transmitter
790   */
791 typedef struct
792 {
793   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
794   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
795   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
796   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
797   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
798   __IO uint32_t RTOR;        /*!< USART Receiver Timeout register,          Address offset: 0x14  */
799   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
800   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
801   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
802   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
803   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
804   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
805 } USART_TypeDef;
806 
807 
808 
809 /**
810   * @brief Window WATCHDOG
811   */
812 
813 typedef struct
814 {
815   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
816   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
817   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
818 } WWDG_TypeDef;
819 
820 /**
821   * @brief AES hardware accelerator
822   */
823 
824 typedef struct
825 {
826   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
827   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
828   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
829   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
830   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
831   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
832   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
833   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
834   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
835   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
836   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
837   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
838   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
839   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
840   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
841   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
842   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
843   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
844   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
845   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
846   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
847   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
848   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
849   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
850 } AES_TypeDef;
851 
852 /**
853   * @brief RNG
854   */
855 typedef struct
856 {
857   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
858   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
859   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
860 } RNG_TypeDef;
861 
862 /**
863   * @brief CORDIC
864   */
865 
866 typedef struct
867 {
868   __IO uint32_t CSR;          /*!< CORDIC control and status register,        Address offset: 0x00 */
869   __IO uint32_t WDATA;        /*!< CORDIC argument register,                  Address offset: 0x04 */
870   __IO uint32_t RDATA;        /*!< CORDIC result register,                    Address offset: 0x08 */
871 } CORDIC_TypeDef;
872 
873 
874 /**
875   * @brief High resolution Timer (HRTIM)
876   */
877 
878 #define c7amba_hrtim1_v2_0
879 
880 /* HRTIM master registers definition */
881 typedef struct
882 {
883   __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
884   __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
885   __IO uint32_t MICR;           /*!< HRTIM Master Timer interrupt clear register,              Address offset: 0x08 */
886   __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
887   __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
888   __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
889   __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
890   __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
891   uint32_t      RESERVED0;     /*!< Reserved,                                                                0x20 */
892   __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
893   __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
894   __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
895   uint32_t      RESERVED1[20];  /*!< Reserved,                                                0x30..0x7C */
896 }HRTIM_Master_TypeDef;
897 
898 /* HRTIM Timer A to F registers definition */
899 typedef struct
900 {
901   __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00  */
902   __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04  */
903   __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08  */
904   __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C  */
905   __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10  */
906   __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14  */
907   __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18  */
908   __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C  */
909   __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20  */
910   __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24  */
911   __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28  */
912   __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C  */
913   __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30  */
914   __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
915   __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
916   __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
917   __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
918   __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
919   __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
920   __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
921   __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
922   __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
923   __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
924   __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
925   __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
926   __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
927   __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
928   __IO uint32_t TIMxCR2;    /*!< HRTIM Timerx Control register 2,                            Address offset: 0x6C */
929   __IO uint32_t EEFxR3;     /*!< HRTIM Timerx external event filtering 3 register,           Address offset: 0x70 */
930   uint32_t   RESERVED0[3];  /*!< Reserved,                                                   0x74..0x7C */
931 }HRTIM_Timerx_TypeDef;
932 
933 /* HRTIM common register definition */
934 typedef struct
935 {
936   __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
937   __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
938   __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
939   __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
940   __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
941   __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
942   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
943   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
944   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
945   __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
946   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
947   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
948   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
949   __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
950   __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
951   __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
952   __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
953   __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
954   __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
955   __IO uint32_t DLLCR;      /*!< HRTIM DLL control register,                                 Address offset: 0x4C */
956   __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
957   __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
958   __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
959   __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
960   __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
961   __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
962   __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
963   __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
964   __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
965   __IO uint32_t BDTFUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x74 */
966   __IO uint32_t ADCER;      /*!< HRTIM ADC Extended Trigger register,                        Address offset: 0x78 */
967   __IO uint32_t ADCUR;      /*!< HRTIM ADC Trigger Update register,                          Address offset: 0x7C */
968   __IO uint32_t ADCPS1;     /*!< HRTIM ADC Post Scaler Register 1,                           Address offset: 0x80 */
969   __IO uint32_t ADCPS2;     /*!< HRTIM ADC Post Scaler Register 2,                           Address offset: 0x84 */
970   __IO uint32_t FLTINR3;    /*!< HRTIM Fault input register3,                                Address offset: 0x88 */
971   __IO uint32_t FLTINR4;    /*!< HRTIM Fault input register4,                                Address offset: 0x8C */
972 }HRTIM_Common_TypeDef;
973 
974 /* HRTIM  register definition */
975 typedef struct {
976   HRTIM_Master_TypeDef sMasterRegs;
977   HRTIM_Timerx_TypeDef sTimerxRegs[6];
978   HRTIM_Common_TypeDef sCommonRegs;
979 }HRTIM_TypeDef;
980 
981 /**
982   * @}
983   */
984 
985 /** @addtogroup Peripheral_memory_map
986   * @{
987   */
988 
989 #define FLASH_BASE            (0x08000000UL) /*!< FLASH (up to 256 kB) base address */
990 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 40 KB) base address */
991 #define CCMSRAM_BASE          (0x10000000UL) /*!< CCMSRAM(20 KB) base address */
992 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
993 
994 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(40 KB) base address in the bit-band region */
995 #define CCMSRAM_BB_BASE       (0x22300000UL) /*!< CCMSRAM(20 KB) base address in the bit-band region */
996 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
997 /* Legacy defines */
998 #define SRAM_BASE             SRAM1_BASE
999 #define SRAM_BB_BASE          SRAM1_BB_BASE
1000 
1001 #define SRAM1_SIZE_MAX        (0x0000A000UL) /*!< maximum SRAM1 size (up to 40 KBytes) */
1002 #define CCMSRAM_SIZE          (0x00005000UL) /*!< CCMSRAM size (20 KBytes) */
1003 
1004 /*!< Peripheral memory map */
1005 #define APB1PERIPH_BASE        PERIPH_BASE
1006 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
1007 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
1008 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
1009 
1010 
1011 /*!< APB1 peripherals */
1012 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
1013 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
1014 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
1015 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
1016 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
1017 #define CRS_BASE              (APB1PERIPH_BASE + 0x2000UL)
1018 #define TAMP_BASE             (APB1PERIPH_BASE + 0x2400UL)
1019 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
1020 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
1021 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
1022 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1023 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1024 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1025 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1026 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1027 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1028 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1029 #define FDCAN1_BASE           (APB1PERIPH_BASE + 0x6400UL)
1030 #define FDCAN_CONFIG_BASE     (APB1PERIPH_BASE + 0x6500UL)  /*!< FDCAN configuration registers base address */
1031 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1032 #define I2C3_BASE             (APB1PERIPH_BASE + 0x7800UL)
1033 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
1034 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
1035 #define SRAMCAN_BASE          (APB1PERIPH_BASE + 0xA400UL)
1036 
1037 /*!< APB2 peripherals */
1038 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
1039 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
1040 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
1041 #define COMP3_BASE            (APB2PERIPH_BASE + 0x0208UL)
1042 #define COMP4_BASE            (APB2PERIPH_BASE + 0x020CUL)
1043 #define COMP5_BASE            (APB2PERIPH_BASE + 0x0210UL)
1044 #define COMP6_BASE            (APB2PERIPH_BASE + 0x0214UL)
1045 #define COMP7_BASE            (APB2PERIPH_BASE + 0x0218UL)
1046 
1047 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
1048 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1049 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1050 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400UL)
1051 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
1052 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
1053 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
1054 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800UL)
1055 #define HRTIM1_BASE           (APB2PERIPH_BASE + 0x6800UL)
1056 #define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x0080UL)
1057 #define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x0100UL)
1058 #define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x0180UL)
1059 #define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x0200UL)
1060 #define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x0280UL)
1061 #define HRTIM1_TIMF_BASE      (HRTIM1_BASE + 0x0300UL)
1062 #define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x0380UL)
1063 
1064 /*!< AHB1 peripherals */
1065 #define DMA1_BASE             (AHB1PERIPH_BASE)
1066 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
1067 #define DMAMUX1_BASE          (AHB1PERIPH_BASE + 0x0800UL)
1068 #define CORDIC_BASE           (AHB1PERIPH_BASE + 0x0C00UL)
1069 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
1070 #define FMAC_BASE             (AHB1PERIPH_BASE + 0x1400UL)
1071 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
1072 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1073 
1074 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
1075 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
1076 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
1077 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
1078 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
1079 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
1080 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
1081 #define DMA1_Channel8_BASE    (DMA1_BASE + 0x0094UL)
1082 
1083 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
1084 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
1085 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
1086 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
1087 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
1088 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
1089 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
1090 #define DMA2_Channel8_BASE    (DMA2_BASE + 0x0094UL)
1091 
1092 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
1093 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
1094 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
1095 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
1096 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
1097 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
1098 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
1099 #define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
1100 #define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
1101 #define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
1102 #define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
1103 #define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
1104 #define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
1105 #define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
1106 #define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
1107 #define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
1108 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
1109 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
1110 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
1111 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
1112 
1113 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
1114 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
1115 
1116 /*!< AHB2 peripherals */
1117 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
1118 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
1119 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
1120 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
1121 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
1122 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400UL)
1123 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800UL)
1124 
1125 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08000000UL)
1126 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08000100UL)
1127 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08000300UL)
1128 
1129 #define DAC_BASE              (AHB2PERIPH_BASE + 0x08000800UL)
1130 #define DAC1_BASE             (AHB2PERIPH_BASE + 0x08000800UL)
1131 #define DAC2_BASE             (AHB2PERIPH_BASE + 0x08000C00UL)
1132 #define DAC3_BASE             (AHB2PERIPH_BASE + 0x08001000UL)
1133 #define DAC4_BASE             (AHB2PERIPH_BASE + 0x08001400UL)
1134 #define AES_BASE              (AHB2PERIPH_BASE + 0x08060000UL)
1135 
1136 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
1137 /* Debug MCU registers base address */
1138 #define DBGMCU_BASE           (0xE0042000UL)
1139 
1140 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
1141 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
1142 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
1143 /**
1144   * @}
1145   */
1146 
1147 /** @addtogroup Peripheral_declaration
1148   * @{
1149   */
1150 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1151 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1152 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1153 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1154 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1155 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1156 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
1157 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1158 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1159 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1160 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1161 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1162 #define USART2              ((USART_TypeDef *) USART2_BASE)
1163 #define UART4               ((USART_TypeDef *) UART4_BASE)
1164 #define UART5               ((USART_TypeDef *) UART5_BASE)
1165 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1166 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1167 #define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1168 #define FDCAN_CONFIG        ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1169 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1170 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1171 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1172 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1173 
1174 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1175 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1176 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1177 #define COMP3               ((COMP_TypeDef *) COMP3_BASE)
1178 #define COMP4               ((COMP_TypeDef *) COMP4_BASE)
1179 #define COMP5               ((COMP_TypeDef *) COMP5_BASE)
1180 #define COMP6               ((COMP_TypeDef *) COMP6_BASE)
1181 #define COMP7               ((COMP_TypeDef *) COMP7_BASE)
1182 
1183 
1184 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1185 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1186 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1187 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1188 #define USART1              ((USART_TypeDef *) USART1_BASE)
1189 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1190 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1191 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
1192 #define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
1193 #define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
1194 #define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
1195 #define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
1196 #define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
1197 #define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
1198 #define HRTIM1_TIMF         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE)
1199 #define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
1200 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1201 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1202 #define DMAMUX1             ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1203 #define CORDIC              ((CORDIC_TypeDef *) CORDIC_BASE)
1204 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1205 #define FMAC                ((FMAC_TypeDef *) FMAC_BASE)
1206 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1207 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1208 
1209 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1210 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1211 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1212 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1213 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1214 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1215 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1216 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1217 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1218 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1219 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
1220 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1221 #define DAC2                ((DAC_TypeDef *) DAC2_BASE)
1222 #define DAC3                ((DAC_TypeDef *) DAC3_BASE)
1223 #define DAC4                ((DAC_TypeDef *) DAC4_BASE)
1224 #define AES                 ((AES_TypeDef *) AES_BASE)
1225 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1226 
1227 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1228 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1229 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1230 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1231 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1232 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1233 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1234 #define DMA1_Channel8       ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1235 
1236 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1237 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1238 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1239 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1240 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1241 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1242 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1243 #define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1244 
1245 #define DMAMUX1_Channel0    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1246 #define DMAMUX1_Channel1    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1247 #define DMAMUX1_Channel2    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1248 #define DMAMUX1_Channel3    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1249 #define DMAMUX1_Channel4    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1250 #define DMAMUX1_Channel5    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1251 #define DMAMUX1_Channel6    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1252 #define DMAMUX1_Channel7    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1253 #define DMAMUX1_Channel8    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1254 #define DMAMUX1_Channel9    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1255 #define DMAMUX1_Channel10   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1256 #define DMAMUX1_Channel11   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1257 #define DMAMUX1_Channel12   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1258 #define DMAMUX1_Channel13   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1259 #define DMAMUX1_Channel14   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1260 #define DMAMUX1_Channel15   ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1261 
1262 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1263 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1264 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1265 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1266 
1267 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1268 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1269 
1270 
1271 
1272 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1273 
1274 /**
1275   * @}
1276   */
1277 
1278 /** @addtogroup Exported_constants
1279   * @{
1280   */
1281 
1282   /** @addtogroup Hardware_Constant_Definition
1283     * @{
1284     */
1285 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1286 
1287   /**
1288     * @}
1289     */
1290 
1291 /** @addtogroup Peripheral_Registers_Bits_Definition
1292   * @{
1293   */
1294 
1295 /******************************************************************************/
1296 /*                         Peripheral Registers_Bits_Definition               */
1297 /******************************************************************************/
1298 
1299 /******************************************************************************/
1300 /*                                                                            */
1301 /*                        Analog to Digital Converter                         */
1302 /*                                                                            */
1303 /******************************************************************************/
1304 
1305 /*
1306  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
1307  */
1308 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1309 
1310 /********************  Bit definition for ADC_ISR register  *******************/
1311 #define ADC_ISR_ADRDY_Pos              (0U)
1312 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1313 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1314 #define ADC_ISR_EOSMP_Pos              (1U)
1315 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1316 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1317 #define ADC_ISR_EOC_Pos                (2U)
1318 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1319 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1320 #define ADC_ISR_EOS_Pos                (3U)
1321 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1322 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1323 #define ADC_ISR_OVR_Pos                (4U)
1324 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1325 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1326 #define ADC_ISR_JEOC_Pos               (5U)
1327 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1328 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1329 #define ADC_ISR_JEOS_Pos               (6U)
1330 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1331 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1332 #define ADC_ISR_AWD1_Pos               (7U)
1333 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1334 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1335 #define ADC_ISR_AWD2_Pos               (8U)
1336 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1337 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1338 #define ADC_ISR_AWD3_Pos               (9U)
1339 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1340 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1341 #define ADC_ISR_JQOVF_Pos              (10U)
1342 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1343 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1344 
1345 /********************  Bit definition for ADC_IER register  *******************/
1346 #define ADC_IER_ADRDYIE_Pos            (0U)
1347 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1348 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1349 #define ADC_IER_EOSMPIE_Pos            (1U)
1350 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1351 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1352 #define ADC_IER_EOCIE_Pos              (2U)
1353 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1354 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1355 #define ADC_IER_EOSIE_Pos              (3U)
1356 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1357 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1358 #define ADC_IER_OVRIE_Pos              (4U)
1359 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1360 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1361 #define ADC_IER_JEOCIE_Pos             (5U)
1362 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1363 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1364 #define ADC_IER_JEOSIE_Pos             (6U)
1365 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1366 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1367 #define ADC_IER_AWD1IE_Pos             (7U)
1368 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1369 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1370 #define ADC_IER_AWD2IE_Pos             (8U)
1371 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1372 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1373 #define ADC_IER_AWD3IE_Pos             (9U)
1374 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1375 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1376 #define ADC_IER_JQOVFIE_Pos            (10U)
1377 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1378 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1379 
1380 /********************  Bit definition for ADC_CR register  ********************/
1381 #define ADC_CR_ADEN_Pos                (0U)
1382 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1383 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1384 #define ADC_CR_ADDIS_Pos               (1U)
1385 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1386 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1387 #define ADC_CR_ADSTART_Pos             (2U)
1388 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1389 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1390 #define ADC_CR_JADSTART_Pos            (3U)
1391 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1392 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1393 #define ADC_CR_ADSTP_Pos               (4U)
1394 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1395 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1396 #define ADC_CR_JADSTP_Pos              (5U)
1397 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1398 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1399 #define ADC_CR_ADVREGEN_Pos            (28U)
1400 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1401 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1402 #define ADC_CR_DEEPPWD_Pos             (29U)
1403 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1404 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1405 #define ADC_CR_ADCALDIF_Pos            (30U)
1406 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1407 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1408 #define ADC_CR_ADCAL_Pos               (31U)
1409 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1410 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1411 
1412 /********************  Bit definition for ADC_CFGR register  ******************/
1413 #define ADC_CFGR_DMAEN_Pos             (0U)
1414 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1415 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1416 #define ADC_CFGR_DMACFG_Pos            (1U)
1417 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1418 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1419 
1420 #define ADC_CFGR_RES_Pos               (3U)
1421 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1422 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1423 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1424 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1425 
1426 #define ADC_CFGR_EXTSEL_Pos            (5U)
1427 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1428 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1429 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1430 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1431 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1432 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1433 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1434 
1435 #define ADC_CFGR_EXTEN_Pos             (10U)
1436 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1437 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1438 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1439 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1440 
1441 #define ADC_CFGR_OVRMOD_Pos            (12U)
1442 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1443 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1444 #define ADC_CFGR_CONT_Pos              (13U)
1445 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1446 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1447 #define ADC_CFGR_AUTDLY_Pos            (14U)
1448 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1449 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1450 #define ADC_CFGR_ALIGN_Pos             (15U)
1451 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1452 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1453 #define ADC_CFGR_DISCEN_Pos            (16U)
1454 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1455 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1456 
1457 #define ADC_CFGR_DISCNUM_Pos           (17U)
1458 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1459 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1460 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1461 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1462 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1463 
1464 #define ADC_CFGR_JDISCEN_Pos           (20U)
1465 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1466 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1467 #define ADC_CFGR_JQM_Pos               (21U)
1468 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1469 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1470 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1471 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1472 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1473 #define ADC_CFGR_AWD1EN_Pos            (23U)
1474 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1475 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1476 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1477 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1478 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1479 #define ADC_CFGR_JAUTO_Pos             (25U)
1480 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1481 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1482 
1483 #define ADC_CFGR_AWD1CH_Pos            (26U)
1484 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1485 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1486 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1487 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1488 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1489 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1490 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1491 
1492 #define ADC_CFGR_JQDIS_Pos             (31U)
1493 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1494 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1495 
1496 /********************  Bit definition for ADC_CFGR2 register  *****************/
1497 #define ADC_CFGR2_ROVSE_Pos            (0U)
1498 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1499 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1500 #define ADC_CFGR2_JOVSE_Pos            (1U)
1501 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1502 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1503 
1504 #define ADC_CFGR2_OVSR_Pos             (2U)
1505 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1506 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1507 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1508 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1509 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1510 
1511 #define ADC_CFGR2_OVSS_Pos             (5U)
1512 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1513 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1514 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1515 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1516 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1517 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1518 
1519 #define ADC_CFGR2_TROVS_Pos            (9U)
1520 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1521 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1522 #define ADC_CFGR2_ROVSM_Pos            (10U)
1523 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1524 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1525 
1526 #define ADC_CFGR2_GCOMP_Pos            (16U)
1527 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1528 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1529 
1530 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1531 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1532 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1533 #define ADC_CFGR2_BULB_Pos             (26U)
1534 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1535 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1536 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1537 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1538 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1539 
1540 /********************  Bit definition for ADC_SMPR1 register  *****************/
1541 #define ADC_SMPR1_SMP0_Pos             (0U)
1542 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1543 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1544 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1545 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1546 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1547 
1548 #define ADC_SMPR1_SMP1_Pos             (3U)
1549 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1550 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1551 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1552 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1553 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1554 
1555 #define ADC_SMPR1_SMP2_Pos             (6U)
1556 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1557 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1558 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1559 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1560 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1561 
1562 #define ADC_SMPR1_SMP3_Pos             (9U)
1563 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1564 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1565 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1566 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1567 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1568 
1569 #define ADC_SMPR1_SMP4_Pos             (12U)
1570 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1571 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1572 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1573 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1574 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1575 
1576 #define ADC_SMPR1_SMP5_Pos             (15U)
1577 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1578 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1579 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1580 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1581 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1582 
1583 #define ADC_SMPR1_SMP6_Pos             (18U)
1584 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1585 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1586 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1587 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1588 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1589 
1590 #define ADC_SMPR1_SMP7_Pos             (21U)
1591 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1592 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1593 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1594 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1595 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1596 
1597 #define ADC_SMPR1_SMP8_Pos             (24U)
1598 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1599 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1600 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1601 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1602 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1603 
1604 #define ADC_SMPR1_SMP9_Pos             (27U)
1605 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1606 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1607 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1608 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1609 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1610 
1611 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1612 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1613 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1614 
1615 /********************  Bit definition for ADC_SMPR2 register  *****************/
1616 #define ADC_SMPR2_SMP10_Pos            (0U)
1617 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1618 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1619 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1620 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1621 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1622 
1623 #define ADC_SMPR2_SMP11_Pos            (3U)
1624 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1625 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1626 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1627 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1628 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1629 
1630 #define ADC_SMPR2_SMP12_Pos            (6U)
1631 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1632 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1633 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1634 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1635 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1636 
1637 #define ADC_SMPR2_SMP13_Pos            (9U)
1638 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1639 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1640 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1641 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1642 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1643 
1644 #define ADC_SMPR2_SMP14_Pos            (12U)
1645 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1646 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1647 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1648 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1649 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1650 
1651 #define ADC_SMPR2_SMP15_Pos            (15U)
1652 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1653 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1654 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1655 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1656 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1657 
1658 #define ADC_SMPR2_SMP16_Pos            (18U)
1659 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1660 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1661 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1662 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1663 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1664 
1665 #define ADC_SMPR2_SMP17_Pos            (21U)
1666 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1667 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1668 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1669 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1670 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1671 
1672 #define ADC_SMPR2_SMP18_Pos            (24U)
1673 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1674 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1675 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1676 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1677 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1678 
1679 /********************  Bit definition for ADC_TR1 register  *******************/
1680 #define ADC_TR1_LT1_Pos                (0U)
1681 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1682 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1683 
1684 #define ADC_TR1_AWDFILT_Pos            (12U)
1685 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
1686 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
1687 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
1688 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
1689 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
1690 
1691 #define ADC_TR1_HT1_Pos                (16U)
1692 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1693 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
1694 
1695 /********************  Bit definition for ADC_TR2 register  *******************/
1696 #define ADC_TR2_LT2_Pos                (0U)
1697 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1698 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1699 
1700 #define ADC_TR2_HT2_Pos                (16U)
1701 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1702 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1703 
1704 /********************  Bit definition for ADC_TR3 register  *******************/
1705 #define ADC_TR3_LT3_Pos                (0U)
1706 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1707 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1708 
1709 #define ADC_TR3_HT3_Pos                (16U)
1710 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1711 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1712 
1713 /********************  Bit definition for ADC_SQR1 register  ******************/
1714 #define ADC_SQR1_L_Pos                 (0U)
1715 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1716 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1717 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1718 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1719 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1720 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1721 
1722 #define ADC_SQR1_SQ1_Pos               (6U)
1723 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1724 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1725 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1726 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1727 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1728 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1729 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1730 
1731 #define ADC_SQR1_SQ2_Pos               (12U)
1732 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1733 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1734 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1735 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1736 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1737 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1738 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1739 
1740 #define ADC_SQR1_SQ3_Pos               (18U)
1741 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1742 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1743 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1744 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1745 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1746 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1747 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
1748 
1749 #define ADC_SQR1_SQ4_Pos               (24U)
1750 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1751 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1752 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1753 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1754 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1755 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1756 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1757 
1758 /********************  Bit definition for ADC_SQR2 register  ******************/
1759 #define ADC_SQR2_SQ5_Pos               (0U)
1760 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1761 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1762 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1763 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1764 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1765 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1766 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1767 
1768 #define ADC_SQR2_SQ6_Pos               (6U)
1769 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1770 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1771 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1772 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1773 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1774 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1775 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1776 
1777 #define ADC_SQR2_SQ7_Pos               (12U)
1778 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1779 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1780 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1781 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1782 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1783 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1784 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1785 
1786 #define ADC_SQR2_SQ8_Pos               (18U)
1787 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1788 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1789 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1790 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1791 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1792 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1793 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1794 
1795 #define ADC_SQR2_SQ9_Pos               (24U)
1796 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1797 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1798 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1799 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1800 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1801 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1802 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1803 
1804 /********************  Bit definition for ADC_SQR3 register  ******************/
1805 #define ADC_SQR3_SQ10_Pos              (0U)
1806 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1807 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1808 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1809 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1810 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1811 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1812 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1813 
1814 #define ADC_SQR3_SQ11_Pos              (6U)
1815 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1816 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1817 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1818 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1819 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1820 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1821 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1822 
1823 #define ADC_SQR3_SQ12_Pos              (12U)
1824 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1825 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1826 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1827 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1828 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1829 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1830 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1831 
1832 #define ADC_SQR3_SQ13_Pos              (18U)
1833 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1834 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1835 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1836 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1837 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1838 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1839 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1840 
1841 #define ADC_SQR3_SQ14_Pos              (24U)
1842 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1843 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1844 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1845 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1846 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1847 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1848 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1849 
1850 /********************  Bit definition for ADC_SQR4 register  ******************/
1851 #define ADC_SQR4_SQ15_Pos              (0U)
1852 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1853 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1854 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1855 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1856 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1857 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1858 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1859 
1860 #define ADC_SQR4_SQ16_Pos              (6U)
1861 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1862 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1863 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1864 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1865 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1866 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1867 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1868 
1869 /********************  Bit definition for ADC_DR register  ********************/
1870 #define ADC_DR_RDATA_Pos               (0U)
1871 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1872 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1873 
1874 /********************  Bit definition for ADC_JSQR register  ******************/
1875 #define ADC_JSQR_JL_Pos                (0U)
1876 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1877 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1878 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1879 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1880 
1881 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1882 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
1883 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1884 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1885 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1886 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1887 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1888 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
1889 
1890 #define ADC_JSQR_JEXTEN_Pos            (7U)
1891 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
1892 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1893 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1894 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
1895 
1896 #define ADC_JSQR_JSQ1_Pos              (9U)
1897 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
1898 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1899 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1900 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1901 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1902 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1903 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
1904 
1905 #define ADC_JSQR_JSQ2_Pos              (15U)
1906 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1907 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1908 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1909 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1910 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1911 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1912 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1913 
1914 #define ADC_JSQR_JSQ3_Pos              (21U)
1915 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
1916 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1917 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1918 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1919 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1920 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1921 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
1922 
1923 #define ADC_JSQR_JSQ4_Pos              (27U)
1924 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
1925 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1926 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1927 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1928 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1929 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1930 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
1931 
1932 /********************  Bit definition for ADC_OFR1 register  ******************/
1933 #define ADC_OFR1_OFFSET1_Pos           (0U)
1934 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1935 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1936 
1937 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
1938 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
1939 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
1940 #define ADC_OFR1_SATEN_Pos             (25U)
1941 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
1942 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
1943 
1944 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1945 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1946 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1947 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1948 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1949 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1950 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1951 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1952 
1953 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1954 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1955 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1956 
1957 /********************  Bit definition for ADC_OFR2 register  ******************/
1958 #define ADC_OFR2_OFFSET2_Pos           (0U)
1959 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1960 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1961 
1962 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
1963 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
1964 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
1965 #define ADC_OFR2_SATEN_Pos             (25U)
1966 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
1967 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
1968 
1969 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1970 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1971 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1972 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1973 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1974 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1975 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1976 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1977 
1978 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1979 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1980 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1981 
1982 /********************  Bit definition for ADC_OFR3 register  ******************/
1983 #define ADC_OFR3_OFFSET3_Pos           (0U)
1984 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1985 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1986 
1987 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
1988 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
1989 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
1990 #define ADC_OFR3_SATEN_Pos             (25U)
1991 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
1992 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
1993 
1994 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1995 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1996 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1997 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
1998 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
1999 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2000 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2001 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2002 
2003 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2004 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2005 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2006 
2007 /********************  Bit definition for ADC_OFR4 register  ******************/
2008 #define ADC_OFR4_OFFSET4_Pos           (0U)
2009 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2010 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2011 
2012 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2013 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2014 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2015 #define ADC_OFR4_SATEN_Pos             (25U)
2016 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2017 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2018 
2019 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2020 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2021 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2022 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2023 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2024 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2025 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2026 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2027 
2028 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2029 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2030 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2031 
2032 /********************  Bit definition for ADC_JDR1 register  ******************/
2033 #define ADC_JDR1_JDATA_Pos             (0U)
2034 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2035 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2036 
2037 /********************  Bit definition for ADC_JDR2 register  ******************/
2038 #define ADC_JDR2_JDATA_Pos             (0U)
2039 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2040 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2041 
2042 /********************  Bit definition for ADC_JDR3 register  ******************/
2043 #define ADC_JDR3_JDATA_Pos             (0U)
2044 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2045 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2046 
2047 /********************  Bit definition for ADC_JDR4 register  ******************/
2048 #define ADC_JDR4_JDATA_Pos             (0U)
2049 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2050 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2051 
2052 /********************  Bit definition for ADC_AWD2CR register  ****************/
2053 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2054 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2055 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2056 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2057 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2058 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2059 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2060 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2061 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2062 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2063 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2064 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2065 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2066 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2067 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2068 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2069 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2070 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2071 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2072 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2073 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2074 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2075 
2076 /********************  Bit definition for ADC_AWD3CR register  ****************/
2077 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2078 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2079 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2080 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2081 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2082 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2083 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2084 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2085 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2086 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2087 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2088 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2089 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2090 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2091 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2092 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2093 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2094 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2095 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2096 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2097 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2098 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2099 
2100 /********************  Bit definition for ADC_DIFSEL register  ****************/
2101 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2102 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2103 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2104 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2105 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2106 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2107 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2108 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2109 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2110 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2111 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2112 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2113 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2114 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2115 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2116 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2117 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2118 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2119 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2120 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2121 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2122 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2123 
2124 /********************  Bit definition for ADC_CALFACT register  ***************/
2125 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2126 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2127 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2128 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2129 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2130 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2131 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2132 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2133 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2134 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2135 
2136 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2137 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2138 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2139 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2140 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2141 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2142 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2143 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2144 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2145 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2146 
2147 /********************  Bit definition for ADC_GCOMP register  *****************/
2148 #define ADC_GCOMP_GCOMPCOEFF_Pos       (0U)
2149 #define ADC_GCOMP_GCOMPCOEFF_Msk       (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)  /*!< 0x00003FFF */
2150 #define ADC_GCOMP_GCOMPCOEFF           ADC_GCOMP_GCOMPCOEFF_Msk                /*!< ADC Gain Compensation Coefficient */
2151 
2152 /*************************  ADC Common registers  *****************************/
2153 /********************  Bit definition for ADC_CSR register  *******************/
2154 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2155 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2156 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2157 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2158 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2159 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2160 #define ADC_CSR_EOC_MST_Pos            (2U)
2161 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2162 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2163 #define ADC_CSR_EOS_MST_Pos            (3U)
2164 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2165 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2166 #define ADC_CSR_OVR_MST_Pos            (4U)
2167 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2168 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2169 #define ADC_CSR_JEOC_MST_Pos           (5U)
2170 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2171 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2172 #define ADC_CSR_JEOS_MST_Pos           (6U)
2173 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2174 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2175 #define ADC_CSR_AWD1_MST_Pos           (7U)
2176 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2177 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2178 #define ADC_CSR_AWD2_MST_Pos           (8U)
2179 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2180 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2181 #define ADC_CSR_AWD3_MST_Pos           (9U)
2182 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2183 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2184 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2185 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2186 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2187 
2188 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2189 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2190 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2191 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2192 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2193 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2194 #define ADC_CSR_EOC_SLV_Pos            (18U)
2195 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2196 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2197 #define ADC_CSR_EOS_SLV_Pos            (19U)
2198 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2199 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2200 #define ADC_CSR_OVR_SLV_Pos            (20U)
2201 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2202 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2203 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2204 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2205 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2206 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2207 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2208 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2209 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2210 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2211 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2212 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2213 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2214 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2215 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2216 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2217 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2218 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2219 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2220 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2221 
2222 /********************  Bit definition for ADC_CCR register  *******************/
2223 #define ADC_CCR_DUAL_Pos               (0U)
2224 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2225 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2226 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2227 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2228 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2229 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2230 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2231 
2232 #define ADC_CCR_DELAY_Pos              (8U)
2233 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2234 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2235 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2236 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2237 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2238 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2239 
2240 #define ADC_CCR_DMACFG_Pos             (13U)
2241 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2242 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2243 
2244 #define ADC_CCR_MDMA_Pos               (14U)
2245 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2246 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2247 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2248 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2249 
2250 #define ADC_CCR_CKMODE_Pos             (16U)
2251 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2252 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2253 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2254 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2255 
2256 #define ADC_CCR_PRESC_Pos              (18U)
2257 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2258 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2259 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2260 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2261 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2262 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2263 
2264 #define ADC_CCR_VREFEN_Pos             (22U)
2265 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2266 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2267 #define ADC_CCR_VSENSESEL_Pos          (23U)
2268 #define ADC_CCR_VSENSESEL_Msk          (0x1UL << ADC_CCR_VSENSESEL_Pos)        /*!< 0x00800000 */
2269 #define ADC_CCR_VSENSESEL              ADC_CCR_VSENSESEL_Msk                   /*!< ADC internal path to temperature sensor enable */
2270 #define ADC_CCR_VBATSEL_Pos            (24U)
2271 #define ADC_CCR_VBATSEL_Msk            (0x1UL << ADC_CCR_VBATSEL_Pos)          /*!< 0x01000000 */
2272 #define ADC_CCR_VBATSEL                ADC_CCR_VBATSEL_Msk                     /*!< ADC internal path to battery voltage enable */
2273 
2274 /********************  Bit definition for ADC_CDR register  *******************/
2275 #define ADC_CDR_RDATA_MST_Pos          (0U)
2276 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2277 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2278 
2279 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2280 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2281 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2282 
2283 /******************************************************************************/
2284 /*                                                                            */
2285 /*                       Advanced Encryption Standard (AES)                   */
2286 /*                                                                            */
2287 /******************************************************************************/
2288 /*******************  Bit definition for AES_CR register  *********************/
2289 #define AES_CR_EN_Pos            (0U)
2290 #define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
2291 #define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
2292 #define AES_CR_DATATYPE_Pos      (1U)
2293 #define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
2294 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
2295 #define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
2296 #define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
2297 
2298 #define AES_CR_MODE_Pos          (3U)
2299 #define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
2300 #define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
2301 #define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
2302 #define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
2303 
2304 #define AES_CR_CHMOD_Pos         (5U)
2305 #define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
2306 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
2307 #define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
2308 #define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
2309 #define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
2310 
2311 #define AES_CR_CCFC_Pos          (7U)
2312 #define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
2313 #define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
2314 #define AES_CR_ERRC_Pos          (8U)
2315 #define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
2316 #define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
2317 #define AES_CR_CCFIE_Pos         (9U)
2318 #define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
2319 #define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
2320 #define AES_CR_ERRIE_Pos         (10U)
2321 #define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
2322 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
2323 #define AES_CR_DMAINEN_Pos       (11U)
2324 #define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
2325 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
2326 #define AES_CR_DMAOUTEN_Pos      (12U)
2327 #define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
2328 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
2329 
2330 #define AES_CR_GCMPH_Pos         (13U)
2331 #define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
2332 #define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
2333 #define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
2334 #define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
2335 
2336 #define AES_CR_KEYSIZE_Pos       (18U)
2337 #define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
2338 #define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
2339 #define AES_CR_NPBLB_Pos         (20U)
2340 #define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
2341 #define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in payload last block */
2342 #define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                   /*!< 0x00100000 */
2343 #define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                   /*!< 0x00200000 */
2344 #define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                   /*!< 0x00400000 */
2345 #define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                   /*!< 0x00800000 */
2346 
2347 /*******************  Bit definition for AES_SR register  *********************/
2348 #define AES_SR_CCF_Pos           (0U)
2349 #define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
2350 #define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
2351 #define AES_SR_RDERR_Pos         (1U)
2352 #define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
2353 #define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
2354 #define AES_SR_WRERR_Pos         (2U)
2355 #define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
2356 #define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
2357 #define AES_SR_BUSY_Pos          (3U)
2358 #define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
2359 #define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
2360 
2361 /*******************  Bit definition for AES_DINR register  *******************/
2362 #define AES_DINR_Pos             (0U)
2363 #define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
2364 #define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
2365 
2366 /*******************  Bit definition for AES_DOUTR register  ******************/
2367 #define AES_DOUTR_Pos            (0U)
2368 #define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
2369 #define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
2370 
2371 /*******************  Bit definition for AES_KEYR0 register  ******************/
2372 #define AES_KEYR0_Pos            (0U)
2373 #define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
2374 #define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
2375 
2376 /*******************  Bit definition for AES_KEYR1 register  ******************/
2377 #define AES_KEYR1_Pos            (0U)
2378 #define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
2379 #define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
2380 
2381 /*******************  Bit definition for AES_KEYR2 register  ******************/
2382 #define AES_KEYR2_Pos            (0U)
2383 #define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
2384 #define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
2385 
2386 /*******************  Bit definition for AES_KEYR3 register  ******************/
2387 #define AES_KEYR3_Pos            (0U)
2388 #define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
2389 #define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
2390 
2391 /*******************  Bit definition for AES_KEYR4 register  ******************/
2392 #define AES_KEYR4_Pos            (0U)
2393 #define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
2394 #define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
2395 
2396 /*******************  Bit definition for AES_KEYR5 register  ******************/
2397 #define AES_KEYR5_Pos            (0U)
2398 #define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
2399 #define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
2400 
2401 /*******************  Bit definition for AES_KEYR6 register  ******************/
2402 #define AES_KEYR6_Pos            (0U)
2403 #define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
2404 #define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
2405 
2406 /*******************  Bit definition for AES_KEYR7 register  ******************/
2407 #define AES_KEYR7_Pos            (0U)
2408 #define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
2409 #define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
2410 
2411 /*******************  Bit definition for AES_IVR0 register   ******************/
2412 #define AES_IVR0_Pos             (0U)
2413 #define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
2414 #define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
2415 
2416 /*******************  Bit definition for AES_IVR1 register   ******************/
2417 #define AES_IVR1_Pos             (0U)
2418 #define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
2419 #define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
2420 
2421 /*******************  Bit definition for AES_IVR2 register   ******************/
2422 #define AES_IVR2_Pos             (0U)
2423 #define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
2424 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
2425 
2426 /*******************  Bit definition for AES_IVR3 register   ******************/
2427 #define AES_IVR3_Pos             (0U)
2428 #define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
2429 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
2430 
2431 /*******************  Bit definition for AES_SUSP0R register  ******************/
2432 #define AES_SUSP0R_Pos           (0U)
2433 #define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
2434 #define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
2435 
2436 /*******************  Bit definition for AES_SUSP1R register  ******************/
2437 #define AES_SUSP1R_Pos           (0U)
2438 #define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
2439 #define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
2440 
2441 /*******************  Bit definition for AES_SUSP2R register  ******************/
2442 #define AES_SUSP2R_Pos           (0U)
2443 #define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
2444 #define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
2445 
2446 /*******************  Bit definition for AES_SUSP3R register  ******************/
2447 #define AES_SUSP3R_Pos           (0U)
2448 #define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
2449 #define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
2450 
2451 /*******************  Bit definition for AES_SUSP4R register  ******************/
2452 #define AES_SUSP4R_Pos           (0U)
2453 #define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
2454 #define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
2455 
2456 /*******************  Bit definition for AES_SUSP5R register  ******************/
2457 #define AES_SUSP5R_Pos           (0U)
2458 #define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
2459 #define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
2460 
2461 /*******************  Bit definition for AES_SUSP6R register  ******************/
2462 #define AES_SUSP6R_Pos           (0U)
2463 #define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
2464 #define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
2465 
2466 /*******************  Bit definition for AES_SUSP7R register  ******************/
2467 #define AES_SUSP7R_Pos           (0U)
2468 #define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
2469 #define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
2470 
2471 /******************************************************************************/
2472 /*                                                                            */
2473 /*                      Analog Comparators (COMP)                             */
2474 /*                                                                            */
2475 /******************************************************************************/
2476 /**********************  Bit definition for COMP_CSR register  ****************/
2477 #define COMP_CSR_EN_Pos            (0U)
2478 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
2479 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
2480 
2481 #define COMP_CSR_INMSEL_Pos        (4U)
2482 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
2483 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
2484 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
2485 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
2486 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
2487 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
2488 
2489 #define COMP_CSR_INPSEL_Pos        (8U)
2490 #define COMP_CSR_INPSEL_Msk        (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
2491 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
2492 
2493 #define COMP_CSR_POLARITY_Pos      (15U)
2494 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
2495 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
2496 
2497 #define COMP_CSR_HYST_Pos          (16U)
2498 #define COMP_CSR_HYST_Msk          (0x7UL << COMP_CSR_HYST_Pos)                /*!< 0x00070000 */
2499 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
2500 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
2501 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
2502 #define COMP_CSR_HYST_2            (0x4UL << COMP_CSR_HYST_Pos)                /*!< 0x00040000 */
2503 
2504 #define COMP_CSR_BLANKING_Pos      (19U)
2505 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00380000 */
2506 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
2507 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
2508 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
2509 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00200000 */
2510 
2511 #define COMP_CSR_BRGEN_Pos         (22U)
2512 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
2513 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator scaler bridge enable */
2514 
2515 #define COMP_CSR_SCALEN_Pos        (23U)
2516 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
2517 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator voltage scaler enable */
2518 
2519 #define COMP_CSR_VALUE_Pos         (30U)
2520 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
2521 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
2522 
2523 #define COMP_CSR_LOCK_Pos          (31U)
2524 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
2525 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
2526 
2527 /******************************************************************************/
2528 /*                                                                            */
2529 /*                          CORDIC calculation unit                           */
2530 /*                                                                            */
2531 /******************************************************************************/
2532 /*******************  Bit definition for CORDIC_CSR register  *****************/
2533 #define CORDIC_CSR_FUNC_Pos      (0U)
2534 #define CORDIC_CSR_FUNC_Msk      (0xFUL << CORDIC_CSR_FUNC_Pos)                /*!< 0x0000000F */
2535 #define CORDIC_CSR_FUNC          CORDIC_CSR_FUNC_Msk                           /*!< Function */
2536 #define CORDIC_CSR_FUNC_0        (0x1UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000001 */
2537 #define CORDIC_CSR_FUNC_1        (0x2UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000002 */
2538 #define CORDIC_CSR_FUNC_2        (0x4UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000004 */
2539 #define CORDIC_CSR_FUNC_3        (0x8UL << CORDIC_CSR_FUNC_Pos)                /*!< 0x00000008 */
2540 #define CORDIC_CSR_PRECISION_Pos (4U)
2541 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x000000F0 */
2542 #define CORDIC_CSR_PRECISION     CORDIC_CSR_PRECISION_Msk                      /*!< Precision */
2543 #define CORDIC_CSR_PRECISION_0   (0x1UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000010 */
2544 #define CORDIC_CSR_PRECISION_1   (0x2UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000020 */
2545 #define CORDIC_CSR_PRECISION_2   (0x4UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000040 */
2546 #define CORDIC_CSR_PRECISION_3   (0x8UL << CORDIC_CSR_PRECISION_Pos)           /*!< 0x00000080 */
2547 #define CORDIC_CSR_SCALE_Pos     (8U)
2548 #define CORDIC_CSR_SCALE_Msk     (0x7UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000700 */
2549 #define CORDIC_CSR_SCALE         CORDIC_CSR_SCALE_Msk                          /*!< Scaling factor */
2550 #define CORDIC_CSR_SCALE_0       (0x1UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000100 */
2551 #define CORDIC_CSR_SCALE_1       (0x2UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000200 */
2552 #define CORDIC_CSR_SCALE_2       (0x4UL << CORDIC_CSR_SCALE_Pos)               /*!< 0x00000400 */
2553 #define CORDIC_CSR_IEN_Pos       (16U)
2554 #define CORDIC_CSR_IEN_Msk       (0x1UL << CORDIC_CSR_IEN_Pos)                 /*!< 0x00010000 */
2555 #define CORDIC_CSR_IEN           CORDIC_CSR_IEN_Msk                            /*!< Interrupt Enable */
2556 #define CORDIC_CSR_DMAREN_Pos    (17U)
2557 #define CORDIC_CSR_DMAREN_Msk    (0x1UL << CORDIC_CSR_DMAREN_Pos)              /*!< 0x00020000 */
2558 #define CORDIC_CSR_DMAREN        CORDIC_CSR_DMAREN_Msk                         /*!< DMA Read channel Enable */
2559 #define CORDIC_CSR_DMAWEN_Pos    (18U)
2560 #define CORDIC_CSR_DMAWEN_Msk    (0x1UL << CORDIC_CSR_DMAWEN_Pos)              /*!< 0x00040000 */
2561 #define CORDIC_CSR_DMAWEN        CORDIC_CSR_DMAWEN_Msk                         /*!< DMA Write channel Enable */
2562 #define CORDIC_CSR_NRES_Pos      (19U)
2563 #define CORDIC_CSR_NRES_Msk      (0x1UL << CORDIC_CSR_NRES_Pos)                /*!< 0x00080000 */
2564 #define CORDIC_CSR_NRES          CORDIC_CSR_NRES_Msk                           /*!< Number of results in WDATA register */
2565 #define CORDIC_CSR_NARGS_Pos     (20U)
2566 #define CORDIC_CSR_NARGS_Msk     (0x1UL << CORDIC_CSR_NARGS_Pos)               /*!< 0x00100000 */
2567 #define CORDIC_CSR_NARGS         CORDIC_CSR_NARGS_Msk                          /*!< Number of arguments in RDATA register */
2568 #define CORDIC_CSR_RESSIZE_Pos   (21U)
2569 #define CORDIC_CSR_RESSIZE_Msk   (0x1UL << CORDIC_CSR_RESSIZE_Pos)             /*!< 0x00200000 */
2570 #define CORDIC_CSR_RESSIZE       CORDIC_CSR_RESSIZE_Msk                        /*!< Width of output data */
2571 #define CORDIC_CSR_ARGSIZE_Pos   (22U)
2572 #define CORDIC_CSR_ARGSIZE_Msk   (0x1UL << CORDIC_CSR_ARGSIZE_Pos)             /*!< 0x00400000 */
2573 #define CORDIC_CSR_ARGSIZE       CORDIC_CSR_ARGSIZE_Msk                        /*!< Width of input data */
2574 #define CORDIC_CSR_RRDY_Pos      (31U)
2575 #define CORDIC_CSR_RRDY_Msk      (0x1UL << CORDIC_CSR_RRDY_Pos)                /*!< 0x80000000 */
2576 #define CORDIC_CSR_RRDY          CORDIC_CSR_RRDY_Msk                           /*!< Result Ready Flag */
2577 
2578 /*******************  Bit definition for CORDIC_WDATA register  ***************/
2579 #define CORDIC_WDATA_ARG_Pos     (0U)
2580 #define CORDIC_WDATA_ARG_Msk     (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)        /*!< 0xFFFFFFFF */
2581 #define CORDIC_WDATA_ARG         CORDIC_WDATA_ARG_Msk                          /*!< Input Argument */
2582 
2583 /*******************  Bit definition for CORDIC_RDATA register  ***************/
2584 #define CORDIC_RDATA_RES_Pos     (0U)
2585 #define CORDIC_RDATA_RES_Msk     (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)        /*!< 0xFFFFFFFF */
2586 #define CORDIC_RDATA_RES         CORDIC_RDATA_RES_Msk                          /*!< Output Result */
2587 
2588 /******************************************************************************/
2589 /*                                                                            */
2590 /*                          CRC calculation unit                              */
2591 /*                                                                            */
2592 /******************************************************************************/
2593 /*******************  Bit definition for CRC_DR register  *********************/
2594 #define CRC_DR_DR_Pos            (0U)
2595 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2596 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2597 
2598 /*******************  Bit definition for CRC_IDR register  ********************/
2599 #define CRC_IDR_IDR_Pos          (0U)
2600 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
2601 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
2602 
2603 /********************  Bit definition for CRC_CR register  ********************/
2604 #define CRC_CR_RESET_Pos         (0U)
2605 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2606 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2607 #define CRC_CR_POLYSIZE_Pos      (3U)
2608 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2609 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2610 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2611 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2612 #define CRC_CR_REV_IN_Pos        (5U)
2613 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2614 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2615 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2616 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2617 #define CRC_CR_REV_OUT_Pos       (7U)
2618 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2619 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2620 
2621 /*******************  Bit definition for CRC_INIT register  *******************/
2622 #define CRC_INIT_INIT_Pos        (0U)
2623 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2624 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2625 
2626 /*******************  Bit definition for CRC_POL register  ********************/
2627 #define CRC_POL_POL_Pos          (0U)
2628 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2629 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2630 
2631 /******************************************************************************/
2632 /*                                                                            */
2633 /*                          CRS Clock Recovery System                         */
2634 /******************************************************************************/
2635 
2636 /*******************  Bit definition for CRS_CR register  *********************/
2637 #define CRS_CR_SYNCOKIE_Pos       (0U)
2638 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2639 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2640 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2641 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2642 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2643 #define CRS_CR_ERRIE_Pos          (2U)
2644 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2645 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2646 #define CRS_CR_ESYNCIE_Pos        (3U)
2647 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2648 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2649 #define CRS_CR_CEN_Pos            (5U)
2650 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2651 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2652 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2653 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2654 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2655 #define CRS_CR_SWSYNC_Pos         (7U)
2656 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2657 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2658 #define CRS_CR_TRIM_Pos           (8U)
2659 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2660 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
2661 
2662 /*******************  Bit definition for CRS_CFGR register  *********************/
2663 #define CRS_CFGR_RELOAD_Pos       (0U)
2664 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2665 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2666 #define CRS_CFGR_FELIM_Pos        (16U)
2667 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2668 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2669 
2670 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2671 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2672 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2673 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2674 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2675 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2676 
2677 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2678 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2679 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2680 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2681 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2682 
2683 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2684 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2685 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2686 
2687 /*******************  Bit definition for CRS_ISR register  *********************/
2688 #define CRS_ISR_SYNCOKF_Pos       (0U)
2689 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2690 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2691 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2692 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2693 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2694 #define CRS_ISR_ERRF_Pos          (2U)
2695 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2696 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2697 #define CRS_ISR_ESYNCF_Pos        (3U)
2698 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2699 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2700 #define CRS_ISR_SYNCERR_Pos       (8U)
2701 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2702 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2703 #define CRS_ISR_SYNCMISS_Pos      (9U)
2704 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2705 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2706 #define CRS_ISR_TRIMOVF_Pos       (10U)
2707 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2708 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2709 #define CRS_ISR_FEDIR_Pos         (15U)
2710 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2711 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2712 #define CRS_ISR_FECAP_Pos         (16U)
2713 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2714 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2715 
2716 /*******************  Bit definition for CRS_ICR register  *********************/
2717 #define CRS_ICR_SYNCOKC_Pos       (0U)
2718 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2719 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2720 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2721 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2722 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2723 #define CRS_ICR_ERRC_Pos          (2U)
2724 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2725 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2726 #define CRS_ICR_ESYNCC_Pos        (3U)
2727 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2728 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2729 
2730 /******************************************************************************/
2731 /*                                                                            */
2732 /*                      Digital to Analog Converter                           */
2733 /*                                                                            */
2734 /******************************************************************************/
2735 /*
2736  * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2737  */
2738 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
2739 
2740 /********************  Bit definition for DAC_CR register  ********************/
2741 #define DAC_CR_EN1_Pos              (0U)
2742 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
2743 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
2744 #define DAC_CR_TEN1_Pos             (1U)
2745 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
2746 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
2747 
2748 #define DAC_CR_TSEL1_Pos            (2U)
2749 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
2750 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2751 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
2752 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
2753 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
2754 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
2755 
2756 #define DAC_CR_WAVE1_Pos            (6U)
2757 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
2758 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2759 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
2760 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
2761 
2762 #define DAC_CR_MAMP1_Pos            (8U)
2763 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
2764 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2765 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
2766 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
2767 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
2768 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
2769 
2770 #define DAC_CR_DMAEN1_Pos           (12U)
2771 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
2772 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
2773 #define DAC_CR_DMAUDRIE1_Pos        (13U)
2774 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
2775 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
2776 #define DAC_CR_CEN1_Pos             (14U)
2777 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
2778 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
2779 
2780 #define DAC_CR_HFSEL_Pos            (15U)
2781 #define DAC_CR_HFSEL_Msk            (0x1UL << DAC_CR_HFSEL_Pos)                /*!< 0x00008000 */
2782 #define DAC_CR_HFSEL                DAC_CR_HFSEL_Msk                           /*!<DAC channel 1 and 2 high frequency mode enable >*/
2783 
2784 #define DAC_CR_EN2_Pos              (16U)
2785 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
2786 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
2787 #define DAC_CR_TEN2_Pos             (17U)
2788 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
2789 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
2790 
2791 #define DAC_CR_TSEL2_Pos            (18U)
2792 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
2793 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2794 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
2795 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
2796 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
2797 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
2798 
2799 #define DAC_CR_WAVE2_Pos            (22U)
2800 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
2801 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2802 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
2803 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
2804 
2805 #define DAC_CR_MAMP2_Pos            (24U)
2806 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
2807 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2808 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
2809 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
2810 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
2811 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
2812 
2813 #define DAC_CR_DMAEN2_Pos           (28U)
2814 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
2815 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
2816 #define DAC_CR_DMAUDRIE2_Pos        (29U)
2817 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
2818 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
2819 #define DAC_CR_CEN2_Pos             (30U)
2820 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
2821 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
2822 
2823 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2824 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
2825 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
2826 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
2827 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
2828 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
2829 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
2830 #define DAC_SWTRIGR_SWTRIGB1_Pos    (16U)
2831 #define DAC_SWTRIGR_SWTRIGB1_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)        /*!< 0x00010000 */
2832 #define DAC_SWTRIGR_SWTRIGB1        DAC_SWTRIGR_SWTRIGB1_Msk                   /*!<DAC channel1 software trigger B */
2833 #define DAC_SWTRIGR_SWTRIGB2_Pos    (17U)
2834 #define DAC_SWTRIGR_SWTRIGB2_Msk    (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)        /*!< 0x00020000 */
2835 #define DAC_SWTRIGR_SWTRIGB2        DAC_SWTRIGR_SWTRIGB2_Msk                   /*!<DAC channel2 software trigger B */
2836 
2837 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2838 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
2839 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
2840 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2841 #define DAC_DHR12R1_DACC1DHRB_Pos   (16U)
2842 #define DAC_DHR12R1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)     /*!< 0x0FFF0000 */
2843 #define DAC_DHR12R1_DACC1DHRB       DAC_DHR12R1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Right-aligned data B */
2844 
2845 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2846 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
2847 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2848 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2849 #define DAC_DHR12L1_DACC1DHRB_Pos   (20U)
2850 #define DAC_DHR12L1_DACC1DHRB_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)     /*!< 0xFFF00000 */
2851 #define DAC_DHR12L1_DACC1DHRB       DAC_DHR12L1_DACC1DHRB_Msk                  /*!<DAC channel1 12-bit Left aligned data B */
2852 
2853 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2854 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
2855 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
2856 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2857 #define DAC_DHR8R1_DACC1DHRB_Pos    (8U)
2858 #define DAC_DHR8R1_DACC1DHRB_Msk    (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)       /*!< 0x0000FF00 */
2859 #define DAC_DHR8R1_DACC1DHRB        DAC_DHR8R1_DACC1DHRB_Msk                   /*!<DAC channel1 8-bit Right aligned data B */
2860 
2861 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2862 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
2863 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
2864 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2865 #define DAC_DHR12R2_DACC2DHRB_Pos   (16U)
2866 #define DAC_DHR12R2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)     /*!< 0x0FFF0000 */
2867 #define DAC_DHR12R2_DACC2DHRB       DAC_DHR12R2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Right-aligned data B */
2868 
2869 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2870 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
2871 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
2872 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2873 #define DAC_DHR12L2_DACC2DHRB_Pos   (20U)
2874 #define DAC_DHR12L2_DACC2DHRB_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)     /*!< 0xFFF00000 */
2875 #define DAC_DHR12L2_DACC2DHRB       DAC_DHR12L2_DACC2DHRB_Msk                  /*!<DAC channel2 12-bit Left aligned data B */
2876 
2877 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2878 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
2879 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
2880 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2881 #define DAC_DHR8R2_DACC2DHRB_Pos    (8U)
2882 #define DAC_DHR8R2_DACC2DHRB_Msk    (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)       /*!< 0x0000FF00 */
2883 #define DAC_DHR8R2_DACC2DHRB        DAC_DHR8R2_DACC2DHRB_Msk                   /*!<DAC channel2 8-bit Right aligned data B */
2884 
2885 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2886 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
2887 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
2888 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
2889 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
2890 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
2891 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
2892 
2893 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2894 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
2895 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
2896 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
2897 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
2898 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
2899 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
2900 
2901 /******************  Bit definition for DAC_DHR8RD register  ******************/
2902 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
2903 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
2904 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
2905 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
2906 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
2907 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
2908 
2909 /*******************  Bit definition for DAC_DOR1 register  *******************/
2910 #define DAC_DOR1_DACC1DOR_Pos       (0U)
2911 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
2912 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
2913 #define DAC_DOR1_DACC1DORB_Pos      (16U)
2914 #define DAC_DOR1_DACC1DORB_Msk      (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)        /*!< 0x0FFF0000 */
2915 #define DAC_DOR1_DACC1DORB          DAC_DOR1_DACC1DORB_Msk                     /*!<DAC channel1 data output B */
2916 
2917 /*******************  Bit definition for DAC_DOR2 register  *******************/
2918 #define DAC_DOR2_DACC2DOR_Pos       (0U)
2919 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
2920 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
2921 #define DAC_DOR2_DACC2DORB_Pos      (16U)
2922 #define DAC_DOR2_DACC2DORB_Msk      (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)        /*!< 0x0FFF0000 */
2923 #define DAC_DOR2_DACC2DORB          DAC_DOR2_DACC2DORB_Msk                     /*!<DAC channel2 data output B */
2924 
2925 /********************  Bit definition for DAC_SR register  ********************/
2926 #define DAC_SR_DAC1RDY_Pos          (11U)
2927 #define DAC_SR_DAC1RDY_Msk          (0x1UL << DAC_SR_DAC1RDY_Pos)              /*!< 0x00000800 */
2928 #define DAC_SR_DAC1RDY              DAC_SR_DAC1RDY_Msk                         /*!<DAC channel 1 ready status bit */
2929 #define DAC_SR_DORSTAT1_Pos         (12U)
2930 #define DAC_SR_DORSTAT1_Msk         (0x1UL << DAC_SR_DORSTAT1_Pos)             /*!< 0x00001000 */
2931 #define DAC_SR_DORSTAT1             DAC_SR_DORSTAT1_Msk                        /*!<DAC channel 1 output register status bit */
2932 #define DAC_SR_DMAUDR1_Pos          (13U)
2933 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
2934 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
2935 #define DAC_SR_CAL_FLAG1_Pos        (14U)
2936 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
2937 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
2938 #define DAC_SR_BWST1_Pos            (15U)
2939 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
2940 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
2941 
2942 #define DAC_SR_DAC2RDY_Pos          (27U)
2943 #define DAC_SR_DAC2RDY_Msk          (0x1UL << DAC_SR_DAC2RDY_Pos)              /*!< 0x08000000 */
2944 #define DAC_SR_DAC2RDY              DAC_SR_DAC2RDY_Msk                         /*!<DAC channel 2 ready status bit */
2945 #define DAC_SR_DORSTAT2_Pos         (28U)
2946 #define DAC_SR_DORSTAT2_Msk         (0x1UL << DAC_SR_DORSTAT2_Pos)             /*!< 0x10000000 */
2947 #define DAC_SR_DORSTAT2             DAC_SR_DORSTAT2_Msk                        /*!<DAC channel 2 output register status bit */
2948 #define DAC_SR_DMAUDR2_Pos          (29U)
2949 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
2950 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
2951 #define DAC_SR_CAL_FLAG2_Pos        (30U)
2952 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
2953 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
2954 #define DAC_SR_BWST2_Pos            (31U)
2955 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
2956 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
2957 
2958 /*******************  Bit definition for DAC_CCR register  ********************/
2959 #define DAC_CCR_OTRIM1_Pos          (0U)
2960 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
2961 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
2962 #define DAC_CCR_OTRIM2_Pos          (16U)
2963 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
2964 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
2965 
2966 /*******************  Bit definition for DAC_MCR register  *******************/
2967 #define DAC_MCR_MODE1_Pos           (0U)
2968 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
2969 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
2970 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
2971 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
2972 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
2973 
2974 #define DAC_MCR_DMADOUBLE1_Pos      (8U)
2975 #define DAC_MCR_DMADOUBLE1_Msk      (0x1UL << DAC_MCR_DMADOUBLE1_Pos)          /*!< 0x00000100 */
2976 #define DAC_MCR_DMADOUBLE1          DAC_MCR_DMADOUBLE1_Msk                     /*!<DAC Channel 1 DMA double data mode */
2977 
2978 #define DAC_MCR_SINFORMAT1_Pos      (9U)
2979 #define DAC_MCR_SINFORMAT1_Msk      (0x1UL << DAC_MCR_SINFORMAT1_Pos)          /*!< 0x00000200 */
2980 #define DAC_MCR_SINFORMAT1          DAC_MCR_SINFORMAT1_Msk                     /*!<DAC Channel 1 enable signed format */
2981 
2982 #define DAC_MCR_HFSEL_Pos           (14U)
2983 #define DAC_MCR_HFSEL_Msk           (0x3UL << DAC_MCR_HFSEL_Pos)               /*!< 0x0000C000 */
2984 #define DAC_MCR_HFSEL               DAC_MCR_HFSEL_Msk                          /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2985 #define DAC_MCR_HFSEL_0             (0x1UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00004000 */
2986 #define DAC_MCR_HFSEL_1             (0x2UL << DAC_MCR_HFSEL_Pos)               /*!< 0x00008000 */
2987 
2988 #define DAC_MCR_MODE2_Pos           (16U)
2989 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
2990 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
2991 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
2992 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
2993 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
2994 
2995 #define DAC_MCR_DMADOUBLE2_Pos      (24U)
2996 #define DAC_MCR_DMADOUBLE2_Msk      (0x1UL << DAC_MCR_DMADOUBLE2_Pos)          /*!< 0x01000000 */
2997 #define DAC_MCR_DMADOUBLE2          DAC_MCR_DMADOUBLE2_Msk                     /*!<DAC Channel 2 DMA double data mode */
2998 
2999 #define DAC_MCR_SINFORMAT2_Pos      (25U)
3000 #define DAC_MCR_SINFORMAT2_Msk      (0x1UL << DAC_MCR_SINFORMAT2_Pos)          /*!< 0x02000000 */
3001 #define DAC_MCR_SINFORMAT2          DAC_MCR_SINFORMAT2_Msk                     /*!<DAC Channel 2 enable signed format */
3002 
3003 /******************  Bit definition for DAC_SHSR1 register  ******************/
3004 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
3005 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
3006 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
3007 
3008 /******************  Bit definition for DAC_SHSR2 register  ******************/
3009 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
3010 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
3011 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
3012 
3013 /******************  Bit definition for DAC_SHHR register  ******************/
3014 #define DAC_SHHR_THOLD1_Pos         (0U)
3015 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
3016 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
3017 #define DAC_SHHR_THOLD2_Pos         (16U)
3018 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
3019 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
3020 
3021 /******************  Bit definition for DAC_SHRR register  ******************/
3022 #define DAC_SHRR_TREFRESH1_Pos      (0U)
3023 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
3024 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
3025 #define DAC_SHRR_TREFRESH2_Pos      (16U)
3026 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
3027 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
3028 
3029 /******************  Bit definition for DAC_STR1 register  ******************/
3030 #define DAC_STR1_STRSTDATA1_Pos     (0U)
3031 #define DAC_STR1_STRSTDATA1_Msk     (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)       /*!< 0x00000FFF */
3032 #define DAC_STR1_STRSTDATA1         DAC_STR1_STRSTDATA1_Msk                    /*!<DAC Channel 1 Sawtooth starting value */
3033 #define DAC_STR1_STDIR1_Pos         (12U)
3034 #define DAC_STR1_STDIR1_Msk         (0x1UL << DAC_STR1_STDIR1_Pos)             /*!< 0x00001000 */
3035 #define DAC_STR1_STDIR1             DAC_STR1_STDIR1_Msk                        /*!<DAC Channel 1 Sawtooth direction setting */
3036 
3037 #define DAC_STR1_STINCDATA1_Pos     (16U)
3038 #define DAC_STR1_STINCDATA1_Msk     (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)      /*!< 0xFFFF0000 */
3039 #define DAC_STR1_STINCDATA1         DAC_STR1_STINCDATA1_Msk                    /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
3040 
3041 /******************  Bit definition for DAC_STR2 register  ******************/
3042 #define DAC_STR2_STRSTDATA2_Pos     (0U)
3043 #define DAC_STR2_STRSTDATA2_Msk     (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)       /*!< 0x00000FFF */
3044 #define DAC_STR2_STRSTDATA2         DAC_STR2_STRSTDATA2_Msk                    /*!<DAC Channel 2 Sawtooth starting value */
3045 #define DAC_STR2_STDIR2_Pos         (12U)
3046 #define DAC_STR2_STDIR2_Msk         (0x1UL << DAC_STR2_STDIR2_Pos)             /*!< 0x00001000 */
3047 #define DAC_STR2_STDIR2             DAC_STR2_STDIR2_Msk                        /*!<DAC Channel 2 Sawtooth direction setting */
3048 
3049 #define DAC_STR2_STINCDATA2_Pos     (16U)
3050 #define DAC_STR2_STINCDATA2_Msk     (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)      /*!< 0xFFFF0000 */
3051 #define DAC_STR2_STINCDATA2         DAC_STR2_STINCDATA2_Msk                    /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
3052 
3053 /******************  Bit definition for DAC_STMODR register  ****************/
3054 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
3055 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x0000000F */
3056 #define DAC_STMODR_STRSTTRIGSEL1     DAC_STMODR_STRSTTRIGSEL1_Msk              /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3057 #define DAC_STMODR_STRSTTRIGSEL1_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000001 */
3058 #define DAC_STMODR_STRSTTRIGSEL1_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000002 */
3059 #define DAC_STMODR_STRSTTRIGSEL1_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000004 */
3060 #define DAC_STMODR_STRSTTRIGSEL1_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)   /*!< 0x00000008 */
3061 
3062 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
3063 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x0000000F */
3064 #define DAC_STMODR_STINCTRIGSEL1     DAC_STMODR_STINCTRIGSEL1_Msk              /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
3065 #define DAC_STMODR_STINCTRIGSEL1_0   (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000001 */
3066 #define DAC_STMODR_STINCTRIGSEL1_1   (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000002 */
3067 #define DAC_STMODR_STINCTRIGSEL1_2   (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000004 */
3068 #define DAC_STMODR_STINCTRIGSEL1_3   (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)   /*!< 0x00000008 */
3069 
3070 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
3071 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x0000000F */
3072 #define DAC_STMODR_STRSTTRIGSEL2     DAC_STMODR_STRSTTRIGSEL2_Msk              /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3073 #define DAC_STMODR_STRSTTRIGSEL2_0   (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000001 */
3074 #define DAC_STMODR_STRSTTRIGSEL2_1   (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000002 */
3075 #define DAC_STMODR_STRSTTRIGSEL2_2   (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000004 */
3076 #define DAC_STMODR_STRSTTRIGSEL2_3   (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)   /*!< 0x00000008 */
3077 
3078 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
3079 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x0000000F */
3080 #define DAC_STMODR_STINCTRIGSEL2     DAC_STMODR_STINCTRIGSEL2_Msk              /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
3081 #define DAC_STMODR_STINCTRIGSEL2_0   (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000001 */
3082 #define DAC_STMODR_STINCTRIGSEL2_1   (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000002 */
3083 #define DAC_STMODR_STINCTRIGSEL2_2   (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000004 */
3084 #define DAC_STMODR_STINCTRIGSEL2_3   (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)   /*!< 0x00000008 */
3085 
3086 /******************************************************************************/
3087 /*                                                                            */
3088 /*                                 Debug MCU                                  */
3089 /*                                                                            */
3090 /******************************************************************************/
3091 /********************  Bit definition for DBGMCU_IDCODE register  *************/
3092 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
3093 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
3094 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
3095 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
3096 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
3097 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
3098 
3099 /********************  Bit definition for DBGMCU_CR register  *****************/
3100 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
3101 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
3102 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
3103 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
3104 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
3105 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
3106 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
3107 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
3108 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
3109 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
3110 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
3111 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
3112 
3113 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
3114 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
3115 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
3116 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
3117 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
3118 
3119 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
3120 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
3121 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
3122 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3123 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
3124 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
3125 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3126 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
3127 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
3128 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
3129 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
3130 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
3131 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3132 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
3133 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
3134 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3135 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
3136 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
3137 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
3138 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
3139 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
3140 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3141 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
3142 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
3143 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3144 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
3145 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
3146 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3147 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
3148 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
3149 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3150 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (30U)
3151 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
3152 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
3153 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
3154 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
3155 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
3156 
3157 
3158 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
3159 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
3160 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
3161 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
3162 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
3163 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
3164 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
3165 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
3166 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
3167 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
3168 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
3169 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
3170 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
3171 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
3172 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
3173 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
3174 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos      (26U)
3175 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk      (0x1UL << DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos)/*!< 0x04000000 */
3176 #define DBGMCU_APB2FZ_DBG_HRTIM1_STOP          DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk
3177 
3178 /******************************************************************************/
3179 /*                                                                            */
3180 /*                           DMA Controller (DMA)                             */
3181 /*                                                                            */
3182 /******************************************************************************/
3183 
3184 /*******************  Bit definition for DMA_ISR register  ********************/
3185 #define DMA_ISR_GIF1_Pos       (0U)
3186 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
3187 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
3188 #define DMA_ISR_TCIF1_Pos      (1U)
3189 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
3190 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
3191 #define DMA_ISR_HTIF1_Pos      (2U)
3192 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
3193 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
3194 #define DMA_ISR_TEIF1_Pos      (3U)
3195 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
3196 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
3197 #define DMA_ISR_GIF2_Pos       (4U)
3198 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
3199 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
3200 #define DMA_ISR_TCIF2_Pos      (5U)
3201 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
3202 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
3203 #define DMA_ISR_HTIF2_Pos      (6U)
3204 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
3205 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
3206 #define DMA_ISR_TEIF2_Pos      (7U)
3207 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
3208 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
3209 #define DMA_ISR_GIF3_Pos       (8U)
3210 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
3211 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
3212 #define DMA_ISR_TCIF3_Pos      (9U)
3213 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
3214 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
3215 #define DMA_ISR_HTIF3_Pos      (10U)
3216 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
3217 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
3218 #define DMA_ISR_TEIF3_Pos      (11U)
3219 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
3220 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
3221 #define DMA_ISR_GIF4_Pos       (12U)
3222 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
3223 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
3224 #define DMA_ISR_TCIF4_Pos      (13U)
3225 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
3226 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
3227 #define DMA_ISR_HTIF4_Pos      (14U)
3228 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
3229 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
3230 #define DMA_ISR_TEIF4_Pos      (15U)
3231 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
3232 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
3233 #define DMA_ISR_GIF5_Pos       (16U)
3234 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
3235 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
3236 #define DMA_ISR_TCIF5_Pos      (17U)
3237 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
3238 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
3239 #define DMA_ISR_HTIF5_Pos      (18U)
3240 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
3241 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
3242 #define DMA_ISR_TEIF5_Pos      (19U)
3243 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
3244 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
3245 #define DMA_ISR_GIF6_Pos       (20U)
3246 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
3247 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
3248 #define DMA_ISR_TCIF6_Pos      (21U)
3249 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
3250 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
3251 #define DMA_ISR_HTIF6_Pos      (22U)
3252 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
3253 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
3254 #define DMA_ISR_TEIF6_Pos      (23U)
3255 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
3256 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
3257 #define DMA_ISR_GIF7_Pos       (24U)
3258 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
3259 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
3260 #define DMA_ISR_TCIF7_Pos      (25U)
3261 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
3262 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
3263 #define DMA_ISR_HTIF7_Pos      (26U)
3264 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
3265 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
3266 #define DMA_ISR_TEIF7_Pos      (27U)
3267 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
3268 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
3269 #define DMA_ISR_GIF8_Pos       (28U)
3270 #define DMA_ISR_GIF8_Msk       (0x1UL << DMA_ISR_GIF8_Pos)                     /*!< 0x10000000 */
3271 #define DMA_ISR_GIF8           DMA_ISR_GIF8_Msk                                /*!< Channel 8 Global interrupt flag */
3272 #define DMA_ISR_TCIF8_Pos      (29U)
3273 #define DMA_ISR_TCIF8_Msk      (0x1UL << DMA_ISR_TCIF8_Pos)                    /*!< 0x20000000 */
3274 #define DMA_ISR_TCIF8          DMA_ISR_TCIF8_Msk                               /*!< Channel 8 Transfer Complete flag */
3275 #define DMA_ISR_HTIF8_Pos      (30U)
3276 #define DMA_ISR_HTIF8_Msk      (0x1UL << DMA_ISR_HTIF8_Pos)                    /*!< 0x40000000 */
3277 #define DMA_ISR_HTIF8          DMA_ISR_HTIF8_Msk                               /*!< Channel 8 Half Transfer flag */
3278 #define DMA_ISR_TEIF8_Pos      (31U)
3279 #define DMA_ISR_TEIF8_Msk      (0x1UL << DMA_ISR_TEIF8_Pos)                    /*!< 0x80000000 */
3280 #define DMA_ISR_TEIF8          DMA_ISR_TEIF8_Msk                               /*!< Channel 8 Transfer Error flag */
3281 
3282 /*******************  Bit definition for DMA_IFCR register  *******************/
3283 #define DMA_IFCR_CGIF1_Pos     (0U)
3284 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
3285 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
3286 #define DMA_IFCR_CTCIF1_Pos    (1U)
3287 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
3288 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
3289 #define DMA_IFCR_CHTIF1_Pos    (2U)
3290 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
3291 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
3292 #define DMA_IFCR_CTEIF1_Pos    (3U)
3293 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
3294 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
3295 #define DMA_IFCR_CGIF2_Pos     (4U)
3296 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
3297 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
3298 #define DMA_IFCR_CTCIF2_Pos    (5U)
3299 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
3300 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
3301 #define DMA_IFCR_CHTIF2_Pos    (6U)
3302 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
3303 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
3304 #define DMA_IFCR_CTEIF2_Pos    (7U)
3305 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
3306 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
3307 #define DMA_IFCR_CGIF3_Pos     (8U)
3308 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
3309 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
3310 #define DMA_IFCR_CTCIF3_Pos    (9U)
3311 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
3312 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
3313 #define DMA_IFCR_CHTIF3_Pos    (10U)
3314 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
3315 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
3316 #define DMA_IFCR_CTEIF3_Pos    (11U)
3317 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
3318 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
3319 #define DMA_IFCR_CGIF4_Pos     (12U)
3320 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
3321 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
3322 #define DMA_IFCR_CTCIF4_Pos    (13U)
3323 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
3324 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
3325 #define DMA_IFCR_CHTIF4_Pos    (14U)
3326 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
3327 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
3328 #define DMA_IFCR_CTEIF4_Pos    (15U)
3329 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
3330 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
3331 #define DMA_IFCR_CGIF5_Pos     (16U)
3332 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
3333 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
3334 #define DMA_IFCR_CTCIF5_Pos    (17U)
3335 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
3336 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
3337 #define DMA_IFCR_CHTIF5_Pos    (18U)
3338 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
3339 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
3340 #define DMA_IFCR_CTEIF5_Pos    (19U)
3341 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
3342 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
3343 #define DMA_IFCR_CGIF6_Pos     (20U)
3344 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
3345 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
3346 #define DMA_IFCR_CTCIF6_Pos    (21U)
3347 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
3348 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
3349 #define DMA_IFCR_CHTIF6_Pos    (22U)
3350 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
3351 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
3352 #define DMA_IFCR_CTEIF6_Pos    (23U)
3353 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
3354 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
3355 #define DMA_IFCR_CGIF7_Pos     (24U)
3356 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
3357 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
3358 #define DMA_IFCR_CTCIF7_Pos    (25U)
3359 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
3360 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
3361 #define DMA_IFCR_CHTIF7_Pos    (26U)
3362 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
3363 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
3364 #define DMA_IFCR_CTEIF7_Pos    (27U)
3365 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
3366 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
3367 #define DMA_IFCR_CGIF8_Pos     (28U)
3368 #define DMA_IFCR_CGIF8_Msk     (0x1UL << DMA_IFCR_CGIF8_Pos)                   /*!< 0x10000000 */
3369 #define DMA_IFCR_CGIF8         DMA_IFCR_CGIF8_Msk                              /*!< Channel 8 Global interrupt clear */
3370 #define DMA_IFCR_CTCIF8_Pos    (29U)
3371 #define DMA_IFCR_CTCIF8_Msk    (0x1UL << DMA_IFCR_CTCIF8_Pos)                  /*!< 0x20000000 */
3372 #define DMA_IFCR_CTCIF8        DMA_IFCR_CTCIF8_Msk                             /*!< Channel 8 Transfer Complete clear */
3373 #define DMA_IFCR_CHTIF8_Pos    (30U)
3374 #define DMA_IFCR_CHTIF8_Msk    (0x1UL << DMA_IFCR_CHTIF8_Pos)                  /*!< 0x40000000 */
3375 #define DMA_IFCR_CHTIF8        DMA_IFCR_CHTIF8_Msk                             /*!< Channel 8 Half Transfer clear */
3376 #define DMA_IFCR_CTEIF8_Pos    (31U)
3377 #define DMA_IFCR_CTEIF8_Msk    (0x1UL << DMA_IFCR_CTEIF8_Pos)                  /*!< 0x80000000 */
3378 #define DMA_IFCR_CTEIF8        DMA_IFCR_CTEIF8_Msk                             /*!< Channel 8 Transfer Error clear */
3379 
3380 /*******************  Bit definition for DMA_CCR register  ********************/
3381 #define DMA_CCR_EN_Pos         (0U)
3382 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
3383 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
3384 #define DMA_CCR_TCIE_Pos       (1U)
3385 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
3386 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
3387 #define DMA_CCR_HTIE_Pos       (2U)
3388 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
3389 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
3390 #define DMA_CCR_TEIE_Pos       (3U)
3391 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
3392 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
3393 #define DMA_CCR_DIR_Pos        (4U)
3394 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
3395 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
3396 #define DMA_CCR_CIRC_Pos       (5U)
3397 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
3398 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
3399 #define DMA_CCR_PINC_Pos       (6U)
3400 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
3401 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
3402 #define DMA_CCR_MINC_Pos       (7U)
3403 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
3404 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
3405 
3406 #define DMA_CCR_PSIZE_Pos      (8U)
3407 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
3408 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
3409 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
3410 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
3411 
3412 #define DMA_CCR_MSIZE_Pos      (10U)
3413 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
3414 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
3415 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
3416 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
3417 
3418 #define DMA_CCR_PL_Pos         (12U)
3419 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
3420 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
3421 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
3422 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
3423 
3424 #define DMA_CCR_MEM2MEM_Pos    (14U)
3425 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
3426 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
3427 
3428 /******************  Bit definition for DMA_CNDTR register  *******************/
3429 #define DMA_CNDTR_NDT_Pos      (0U)
3430 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
3431 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
3432 
3433 /******************  Bit definition for DMA_CPAR register  ********************/
3434 #define DMA_CPAR_PA_Pos        (0U)
3435 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
3436 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
3437 
3438 /******************  Bit definition for DMA_CMAR register  ********************/
3439 #define DMA_CMAR_MA_Pos        (0U)
3440 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
3441 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
3442 
3443 /******************************************************************************/
3444 /*                                                                            */
3445 /*                             DMAMUX Controller                              */
3446 /*                                                                            */
3447 /******************************************************************************/
3448 
3449 /********************  Bits definition for DMAMUX_CxCR register  **************/
3450 #define DMAMUX_CxCR_DMAREQ_ID_Pos                    (0U)
3451 #define DMAMUX_CxCR_DMAREQ_ID_Msk                    (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3452 #define DMAMUX_CxCR_DMAREQ_ID                        DMAMUX_CxCR_DMAREQ_ID_Msk
3453 #define DMAMUX_CxCR_DMAREQ_ID_0                      (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3454 #define DMAMUX_CxCR_DMAREQ_ID_1                      (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3455 #define DMAMUX_CxCR_DMAREQ_ID_2                      (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3456 #define DMAMUX_CxCR_DMAREQ_ID_3                      (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3457 #define DMAMUX_CxCR_DMAREQ_ID_4                      (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3458 #define DMAMUX_CxCR_DMAREQ_ID_5                      (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3459 #define DMAMUX_CxCR_DMAREQ_ID_6                      (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3460 #define DMAMUX_CxCR_DMAREQ_ID_7                      (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3461 
3462 #define DMAMUX_CxCR_SOIE_Pos                         (8U)
3463 #define DMAMUX_CxCR_SOIE_Msk                         (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3464 #define DMAMUX_CxCR_SOIE                             DMAMUX_CxCR_SOIE_Msk
3465 
3466 #define DMAMUX_CxCR_EGE_Pos                          (9U)
3467 #define DMAMUX_CxCR_EGE_Msk                          (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3468 #define DMAMUX_CxCR_EGE                              DMAMUX_CxCR_EGE_Msk
3469 
3470 #define DMAMUX_CxCR_SE_Pos                           (16U)
3471 #define DMAMUX_CxCR_SE_Msk                           (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3472 #define DMAMUX_CxCR_SE                               DMAMUX_CxCR_SE_Msk
3473 
3474 #define DMAMUX_CxCR_SPOL_Pos                         (17U)
3475 #define DMAMUX_CxCR_SPOL_Msk                         (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3476 #define DMAMUX_CxCR_SPOL                             DMAMUX_CxCR_SPOL_Msk
3477 #define DMAMUX_CxCR_SPOL_0                           (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3478 #define DMAMUX_CxCR_SPOL_1                           (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3479 
3480 #define DMAMUX_CxCR_NBREQ_Pos                        (19U)
3481 #define DMAMUX_CxCR_NBREQ_Msk                        (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3482 #define DMAMUX_CxCR_NBREQ                            DMAMUX_CxCR_NBREQ_Msk
3483 #define DMAMUX_CxCR_NBREQ_0                          (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3484 #define DMAMUX_CxCR_NBREQ_1                          (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3485 #define DMAMUX_CxCR_NBREQ_2                          (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3486 #define DMAMUX_CxCR_NBREQ_3                          (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3487 #define DMAMUX_CxCR_NBREQ_4                          (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3488 
3489 #define DMAMUX_CxCR_SYNC_ID_Pos                      (24U)
3490 #define DMAMUX_CxCR_SYNC_ID_Msk                      (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3491 #define DMAMUX_CxCR_SYNC_ID                          DMAMUX_CxCR_SYNC_ID_Msk
3492 #define DMAMUX_CxCR_SYNC_ID_0                        (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3493 #define DMAMUX_CxCR_SYNC_ID_1                        (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3494 #define DMAMUX_CxCR_SYNC_ID_2                        (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3495 #define DMAMUX_CxCR_SYNC_ID_3                        (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3496 #define DMAMUX_CxCR_SYNC_ID_4                        (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3497 
3498 /********************  Bits definition for DMAMUX_CSR register  ****************/
3499 #define DMAMUX_CSR_SOF0_Pos                          (0U)
3500 #define DMAMUX_CSR_SOF0_Msk                          (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3501 #define DMAMUX_CSR_SOF0                              DMAMUX_CSR_SOF0_Msk
3502 #define DMAMUX_CSR_SOF1_Pos                          (1U)
3503 #define DMAMUX_CSR_SOF1_Msk                          (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3504 #define DMAMUX_CSR_SOF1                              DMAMUX_CSR_SOF1_Msk
3505 #define DMAMUX_CSR_SOF2_Pos                          (2U)
3506 #define DMAMUX_CSR_SOF2_Msk                          (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3507 #define DMAMUX_CSR_SOF2                              DMAMUX_CSR_SOF2_Msk
3508 #define DMAMUX_CSR_SOF3_Pos                          (3U)
3509 #define DMAMUX_CSR_SOF3_Msk                          (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3510 #define DMAMUX_CSR_SOF3                              DMAMUX_CSR_SOF3_Msk
3511 #define DMAMUX_CSR_SOF4_Pos                          (4U)
3512 #define DMAMUX_CSR_SOF4_Msk                          (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3513 #define DMAMUX_CSR_SOF4                              DMAMUX_CSR_SOF4_Msk
3514 #define DMAMUX_CSR_SOF5_Pos                          (5U)
3515 #define DMAMUX_CSR_SOF5_Msk                          (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3516 #define DMAMUX_CSR_SOF5                              DMAMUX_CSR_SOF5_Msk
3517 #define DMAMUX_CSR_SOF6_Pos                          (6U)
3518 #define DMAMUX_CSR_SOF6_Msk                          (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3519 #define DMAMUX_CSR_SOF6                              DMAMUX_CSR_SOF6_Msk
3520 #define DMAMUX_CSR_SOF7_Pos                          (7U)
3521 #define DMAMUX_CSR_SOF7_Msk                          (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3522 #define DMAMUX_CSR_SOF7                              DMAMUX_CSR_SOF7_Msk
3523 #define DMAMUX_CSR_SOF8_Pos                          (8U)
3524 #define DMAMUX_CSR_SOF8_Msk                          (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3525 #define DMAMUX_CSR_SOF8                              DMAMUX_CSR_SOF8_Msk
3526 #define DMAMUX_CSR_SOF9_Pos                          (9U)
3527 #define DMAMUX_CSR_SOF9_Msk                          (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3528 #define DMAMUX_CSR_SOF9                              DMAMUX_CSR_SOF9_Msk
3529 #define DMAMUX_CSR_SOF10_Pos                         (10U)
3530 #define DMAMUX_CSR_SOF10_Msk                         (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3531 #define DMAMUX_CSR_SOF10                             DMAMUX_CSR_SOF10_Msk
3532 #define DMAMUX_CSR_SOF11_Pos                         (11U)
3533 #define DMAMUX_CSR_SOF11_Msk                         (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3534 #define DMAMUX_CSR_SOF11                              DMAMUX_CSR_SOF11_Msk
3535 #define DMAMUX_CSR_SOF12_Pos                         (12U)
3536 #define DMAMUX_CSR_SOF12_Msk                         (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3537 #define DMAMUX_CSR_SOF12                             DMAMUX_CSR_SOF12_Msk
3538 #define DMAMUX_CSR_SOF13_Pos                         (13U)
3539 #define DMAMUX_CSR_SOF13_Msk                         (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3540 #define DMAMUX_CSR_SOF13                             DMAMUX_CSR_SOF13_Msk
3541 #define DMAMUX_CSR_SOF14_Pos                         (14U)
3542 #define DMAMUX_CSR_SOF14_Msk                         (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3543 #define DMAMUX_CSR_SOF14                             DMAMUX_CSR_SOF14_Msk
3544 #define DMAMUX_CSR_SOF15_Pos                         (15U)
3545 #define DMAMUX_CSR_SOF15_Msk                         (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3546 #define DMAMUX_CSR_SOF15                             DMAMUX_CSR_SOF15_Msk
3547 
3548 /********************  Bits definition for DMAMUX_CFR register  ****************/
3549 #define DMAMUX_CFR_CSOF0_Pos                         (0U)
3550 #define DMAMUX_CFR_CSOF0_Msk                         (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3551 #define DMAMUX_CFR_CSOF0                             DMAMUX_CFR_CSOF0_Msk
3552 #define DMAMUX_CFR_CSOF1_Pos                         (1U)
3553 #define DMAMUX_CFR_CSOF1_Msk                         (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3554 #define DMAMUX_CFR_CSOF1                             DMAMUX_CFR_CSOF1_Msk
3555 #define DMAMUX_CFR_CSOF2_Pos                         (2U)
3556 #define DMAMUX_CFR_CSOF2_Msk                         (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3557 #define DMAMUX_CFR_CSOF2                             DMAMUX_CFR_CSOF2_Msk
3558 #define DMAMUX_CFR_CSOF3_Pos                         (3U)
3559 #define DMAMUX_CFR_CSOF3_Msk                         (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3560 #define DMAMUX_CFR_CSOF3                             DMAMUX_CFR_CSOF3_Msk
3561 #define DMAMUX_CFR_CSOF4_Pos                         (4U)
3562 #define DMAMUX_CFR_CSOF4_Msk                         (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3563 #define DMAMUX_CFR_CSOF4                             DMAMUX_CFR_CSOF4_Msk
3564 #define DMAMUX_CFR_CSOF5_Pos                         (5U)
3565 #define DMAMUX_CFR_CSOF5_Msk                         (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3566 #define DMAMUX_CFR_CSOF5                             DMAMUX_CFR_CSOF5_Msk
3567 #define DMAMUX_CFR_CSOF6_Pos                         (6U)
3568 #define DMAMUX_CFR_CSOF6_Msk                         (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3569 #define DMAMUX_CFR_CSOF6                             DMAMUX_CFR_CSOF6_Msk
3570 #define DMAMUX_CFR_CSOF7_Pos                         (7U)
3571 #define DMAMUX_CFR_CSOF7_Msk                         (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3572 #define DMAMUX_CFR_CSOF7                             DMAMUX_CFR_CSOF7_Msk
3573 #define DMAMUX_CFR_CSOF8_Pos                         (8U)
3574 #define DMAMUX_CFR_CSOF8_Msk                         (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3575 #define DMAMUX_CFR_CSOF8                             DMAMUX_CFR_CSOF8_Msk
3576 #define DMAMUX_CFR_CSOF9_Pos                         (9U)
3577 #define DMAMUX_CFR_CSOF9_Msk                         (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3578 #define DMAMUX_CFR_CSOF9                             DMAMUX_CFR_CSOF9_Msk
3579 #define DMAMUX_CFR_CSOF10_Pos                        (10U)
3580 #define DMAMUX_CFR_CSOF10_Msk                        (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3581 #define DMAMUX_CFR_CSOF10                            DMAMUX_CFR_CSOF10_Msk
3582 #define DMAMUX_CFR_CSOF11_Pos                        (11U)
3583 #define DMAMUX_CFR_CSOF11_Msk                        (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3584 #define DMAMUX_CFR_CSOF11                            DMAMUX_CFR_CSOF11_Msk
3585 #define DMAMUX_CFR_CSOF12_Pos                        (12U)
3586 #define DMAMUX_CFR_CSOF12_Msk                        (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3587 #define DMAMUX_CFR_CSOF12                            DMAMUX_CFR_CSOF12_Msk
3588 #define DMAMUX_CFR_CSOF13_Pos                        (13U)
3589 #define DMAMUX_CFR_CSOF13_Msk                        (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3590 #define DMAMUX_CFR_CSOF13                            DMAMUX_CFR_CSOF13_Msk
3591 #define DMAMUX_CFR_CSOF14_Pos                        (14U)
3592 #define DMAMUX_CFR_CSOF14_Msk                        (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3593 #define DMAMUX_CFR_CSOF14                            DMAMUX_CFR_CSOF14_Msk
3594 #define DMAMUX_CFR_CSOF15_Pos                        (15U)
3595 #define DMAMUX_CFR_CSOF15_Msk                        (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3596 #define DMAMUX_CFR_CSOF15                            DMAMUX_CFR_CSOF15_Msk
3597 
3598 /********************  Bits definition for DMAMUX_RGxCR register  ************/
3599 #define DMAMUX_RGxCR_SIG_ID_Pos                      (0U)
3600 #define DMAMUX_RGxCR_SIG_ID_Msk                      (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3601 #define DMAMUX_RGxCR_SIG_ID                          DMAMUX_RGxCR_SIG_ID_Msk
3602 #define DMAMUX_RGxCR_SIG_ID_0                        (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3603 #define DMAMUX_RGxCR_SIG_ID_1                        (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3604 #define DMAMUX_RGxCR_SIG_ID_2                        (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3605 #define DMAMUX_RGxCR_SIG_ID_3                        (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3606 #define DMAMUX_RGxCR_SIG_ID_4                        (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3607 
3608 #define DMAMUX_RGxCR_OIE_Pos                         (8U)
3609 #define DMAMUX_RGxCR_OIE_Msk                         (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3610 #define DMAMUX_RGxCR_OIE                             DMAMUX_RGxCR_OIE_Msk
3611 
3612 #define DMAMUX_RGxCR_GE_Pos                          (16U)
3613 #define DMAMUX_RGxCR_GE_Msk                          (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3614 #define DMAMUX_RGxCR_GE                              DMAMUX_RGxCR_GE_Msk
3615 
3616 #define DMAMUX_RGxCR_GPOL_Pos                        (17U)
3617 #define DMAMUX_RGxCR_GPOL_Msk                        (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3618 #define DMAMUX_RGxCR_GPOL                            DMAMUX_RGxCR_GPOL_Msk
3619 #define DMAMUX_RGxCR_GPOL_0                          (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3620 #define DMAMUX_RGxCR_GPOL_1                          (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3621 
3622 #define DMAMUX_RGxCR_GNBREQ_Pos                      (19U)
3623 #define DMAMUX_RGxCR_GNBREQ_Msk                      (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3624 #define DMAMUX_RGxCR_GNBREQ                          DMAMUX_RGxCR_GNBREQ_Msk
3625 #define DMAMUX_RGxCR_GNBREQ_0                        (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3626 #define DMAMUX_RGxCR_GNBREQ_1                        (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3627 #define DMAMUX_RGxCR_GNBREQ_2                        (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3628 #define DMAMUX_RGxCR_GNBREQ_3                        (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3629 #define DMAMUX_RGxCR_GNBREQ_4                        (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3630 
3631 /********************  Bits definition for DMAMUX_RGSR register  **************/
3632 #define DMAMUX_RGSR_OF0_Pos                          (0U)
3633 #define DMAMUX_RGSR_OF0_Msk                          (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3634 #define DMAMUX_RGSR_OF0                              DMAMUX_RGSR_OF0_Msk
3635 #define DMAMUX_RGSR_OF1_Pos                          (1U)
3636 #define DMAMUX_RGSR_OF1_Msk                          (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3637 #define DMAMUX_RGSR_OF1                              DMAMUX_RGSR_OF1_Msk
3638 #define DMAMUX_RGSR_OF2_Pos                          (2U)
3639 #define DMAMUX_RGSR_OF2_Msk                          (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3640 #define DMAMUX_RGSR_OF2                              DMAMUX_RGSR_OF2_Msk
3641 #define DMAMUX_RGSR_OF3_Pos                          (3U)
3642 #define DMAMUX_RGSR_OF3_Msk                          (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3643 #define DMAMUX_RGSR_OF3                              DMAMUX_RGSR_OF3_Msk
3644 
3645 /********************  Bits definition for DMAMUX_RGCFR register  ************/
3646 #define DMAMUX_RGCFR_COF0_Pos                        (0U)
3647 #define DMAMUX_RGCFR_COF0_Msk                        (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3648 #define DMAMUX_RGCFR_COF0                            DMAMUX_RGCFR_COF0_Msk
3649 #define DMAMUX_RGCFR_COF1_Pos                        (1U)
3650 #define DMAMUX_RGCFR_COF1_Msk                        (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3651 #define DMAMUX_RGCFR_COF1                            DMAMUX_RGCFR_COF1_Msk
3652 #define DMAMUX_RGCFR_COF2_Pos                        (2U)
3653 #define DMAMUX_RGCFR_COF2_Msk                        (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3654 #define DMAMUX_RGCFR_COF2                            DMAMUX_RGCFR_COF2_Msk
3655 #define DMAMUX_RGCFR_COF3_Pos                        (3U)
3656 #define DMAMUX_RGCFR_COF3_Msk                        (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3657 #define DMAMUX_RGCFR_COF3                            DMAMUX_RGCFR_COF3_Msk
3658 
3659 /******************** Bits definition for DMAMUX_IPHW_CFGR2  ******************/
3660 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos       (0U)
3661 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3662 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3663 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos       (1U)
3664 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3665 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3666 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos       (2U)
3667 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3668 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3669 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos       (3U)
3670 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3671 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3672 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos       (4U)
3673 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3674 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3675 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos       (5U)
3676 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3677 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3678 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos       (6U)
3679 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3680 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3681 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos       (7U)
3682 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk       (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3683 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7           DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3684 
3685 /******************** Bits definition for DMAMUX_IPHW_CFGR1  ******************/
3686 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos       (0U)
3687 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3688 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3689 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos       (1U)
3690 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3691 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3692 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos       (2U)
3693 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3694 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3695 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos       (3U)
3696 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3697 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3698 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos       (4U)
3699 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3700 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3701 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos       (5U)
3702 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3703 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3704 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos       (6U)
3705 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3706 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3707 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos       (7U)
3708 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk       (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3709 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7           DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3710 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos    (8U)
3711 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3712 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3713 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos    (9U)
3714 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3715 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3716 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos    (10U)
3717 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3718 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3719 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos    (11U)
3720 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3721 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3722 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos    (12U)
3723 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3724 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3725 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos    (13U)
3726 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3727 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3728 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos    (14U)
3729 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3730 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3731 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos    (15U)
3732 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk    (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3733 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7        DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3734 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos          (16U)
3735 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3736 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3737 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos          (17U)
3738 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3739 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3740 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos          (18U)
3741 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3742 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3743 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos          (19U)
3744 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3745 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3746 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos          (20U)
3747 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3748 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3749 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos          (21U)
3750 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3751 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3752 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos          (22U)
3753 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3754 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3755 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos          (23U)
3756 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk          (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3757 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7              DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3758 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos        (24U)
3759 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3760 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3761 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos        (25U)
3762 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3763 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3764 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos        (26U)
3765 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3766 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3767 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos        (27U)
3768 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3769 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3770 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos        (28U)
3771 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3772 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3773 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos        (29U)
3774 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3775 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3776 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos        (30U)
3777 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3778 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3779 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos        (31U)
3780 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk        (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3781 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7            DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3782 
3783 
3784 /******************************************************************************/
3785 /*                                                                            */
3786 /*                    External Interrupt/Event Controller                     */
3787 /*                                                                            */
3788 /******************************************************************************/
3789 /*******************  Bit definition for EXTI_IMR1 register  ******************/
3790 #define EXTI_IMR1_IM0_Pos        (0U)
3791 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
3792 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
3793 #define EXTI_IMR1_IM1_Pos        (1U)
3794 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
3795 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
3796 #define EXTI_IMR1_IM2_Pos        (2U)
3797 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
3798 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
3799 #define EXTI_IMR1_IM3_Pos        (3U)
3800 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
3801 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
3802 #define EXTI_IMR1_IM4_Pos        (4U)
3803 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
3804 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
3805 #define EXTI_IMR1_IM5_Pos        (5U)
3806 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
3807 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
3808 #define EXTI_IMR1_IM6_Pos        (6U)
3809 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
3810 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
3811 #define EXTI_IMR1_IM7_Pos        (7U)
3812 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
3813 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
3814 #define EXTI_IMR1_IM8_Pos        (8U)
3815 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
3816 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
3817 #define EXTI_IMR1_IM9_Pos        (9U)
3818 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
3819 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
3820 #define EXTI_IMR1_IM10_Pos       (10U)
3821 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
3822 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
3823 #define EXTI_IMR1_IM11_Pos       (11U)
3824 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
3825 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
3826 #define EXTI_IMR1_IM12_Pos       (12U)
3827 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
3828 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
3829 #define EXTI_IMR1_IM13_Pos       (13U)
3830 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
3831 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
3832 #define EXTI_IMR1_IM14_Pos       (14U)
3833 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
3834 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
3835 #define EXTI_IMR1_IM15_Pos       (15U)
3836 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
3837 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
3838 #define EXTI_IMR1_IM16_Pos       (16U)
3839 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
3840 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
3841 #define EXTI_IMR1_IM17_Pos       (17U)
3842 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
3843 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
3844 #define EXTI_IMR1_IM18_Pos       (18U)
3845 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
3846 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
3847 #define EXTI_IMR1_IM19_Pos       (19U)
3848 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
3849 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
3850 #define EXTI_IMR1_IM20_Pos       (20U)
3851 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
3852 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
3853 #define EXTI_IMR1_IM21_Pos       (21U)
3854 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
3855 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
3856 #define EXTI_IMR1_IM22_Pos       (22U)
3857 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
3858 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
3859 #define EXTI_IMR1_IM23_Pos       (23U)
3860 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
3861 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
3862 #define EXTI_IMR1_IM24_Pos       (24U)
3863 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
3864 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
3865 #define EXTI_IMR1_IM25_Pos       (25U)
3866 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
3867 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
3868 #define EXTI_IMR1_IM26_Pos       (26U)
3869 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
3870 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
3871 #define EXTI_IMR1_IM27_Pos       (27U)
3872 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
3873 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
3874 #define EXTI_IMR1_IM28_Pos       (28U)
3875 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
3876 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
3877 #define EXTI_IMR1_IM29_Pos       (29U)
3878 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
3879 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
3880 #define EXTI_IMR1_IM30_Pos       (30U)
3881 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
3882 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
3883 #define EXTI_IMR1_IM31_Pos       (31U)
3884 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
3885 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
3886 #define EXTI_IMR1_IM_Pos         (0U)
3887 #define EXTI_IMR1_IM_Msk         (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0xFFFFFFFF */
3888 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
3889 
3890 /*******************  Bit definition for EXTI_EMR1 register  ******************/
3891 #define EXTI_EMR1_EM0_Pos        (0U)
3892 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
3893 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
3894 #define EXTI_EMR1_EM1_Pos        (1U)
3895 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
3896 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
3897 #define EXTI_EMR1_EM2_Pos        (2U)
3898 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
3899 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
3900 #define EXTI_EMR1_EM3_Pos        (3U)
3901 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
3902 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
3903 #define EXTI_EMR1_EM4_Pos        (4U)
3904 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
3905 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
3906 #define EXTI_EMR1_EM5_Pos        (5U)
3907 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
3908 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
3909 #define EXTI_EMR1_EM6_Pos        (6U)
3910 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
3911 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
3912 #define EXTI_EMR1_EM7_Pos        (7U)
3913 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
3914 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
3915 #define EXTI_EMR1_EM8_Pos        (8U)
3916 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
3917 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
3918 #define EXTI_EMR1_EM9_Pos        (9U)
3919 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
3920 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
3921 #define EXTI_EMR1_EM10_Pos       (10U)
3922 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
3923 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
3924 #define EXTI_EMR1_EM11_Pos       (11U)
3925 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
3926 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
3927 #define EXTI_EMR1_EM12_Pos       (12U)
3928 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
3929 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
3930 #define EXTI_EMR1_EM13_Pos       (13U)
3931 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
3932 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
3933 #define EXTI_EMR1_EM14_Pos       (14U)
3934 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
3935 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
3936 #define EXTI_EMR1_EM15_Pos       (15U)
3937 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
3938 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
3939 #define EXTI_EMR1_EM16_Pos       (16U)
3940 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
3941 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
3942 #define EXTI_EMR1_EM17_Pos       (17U)
3943 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
3944 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
3945 #define EXTI_EMR1_EM18_Pos       (18U)
3946 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
3947 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
3948 #define EXTI_EMR1_EM19_Pos       (19U)
3949 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
3950 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
3951 #define EXTI_EMR1_EM20_Pos       (20U)
3952 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
3953 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
3954 #define EXTI_EMR1_EM21_Pos       (21U)
3955 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
3956 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
3957 #define EXTI_EMR1_EM22_Pos       (22U)
3958 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
3959 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
3960 #define EXTI_EMR1_EM23_Pos       (23U)
3961 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
3962 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
3963 #define EXTI_EMR1_EM24_Pos       (24U)
3964 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
3965 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
3966 #define EXTI_EMR1_EM25_Pos       (25U)
3967 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
3968 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
3969 #define EXTI_EMR1_EM26_Pos       (26U)
3970 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
3971 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
3972 #define EXTI_EMR1_EM27_Pos       (27U)
3973 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
3974 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
3975 #define EXTI_EMR1_EM28_Pos       (28U)
3976 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
3977 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
3978 #define EXTI_EMR1_EM29_Pos       (29U)
3979 #define EXTI_EMR1_EM29_Msk       (0x1UL << EXTI_EMR1_EM29_Pos)                 /*!< 0x20000000 */
3980 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
3981 #define EXTI_EMR1_EM30_Pos       (30U)
3982 #define EXTI_EMR1_EM30_Msk       (0x1UL << EXTI_EMR1_EM30_Pos)                 /*!< 0x40000000 */
3983 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
3984 #define EXTI_EMR1_EM31_Pos       (31U)
3985 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
3986 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
3987 
3988 /******************  Bit definition for EXTI_RTSR1 register  ******************/
3989 #define EXTI_RTSR1_RT0_Pos       (0U)
3990 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
3991 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
3992 #define EXTI_RTSR1_RT1_Pos       (1U)
3993 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
3994 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
3995 #define EXTI_RTSR1_RT2_Pos       (2U)
3996 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
3997 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
3998 #define EXTI_RTSR1_RT3_Pos       (3U)
3999 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
4000 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
4001 #define EXTI_RTSR1_RT4_Pos       (4U)
4002 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
4003 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
4004 #define EXTI_RTSR1_RT5_Pos       (5U)
4005 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
4006 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
4007 #define EXTI_RTSR1_RT6_Pos       (6U)
4008 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
4009 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
4010 #define EXTI_RTSR1_RT7_Pos       (7U)
4011 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
4012 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
4013 #define EXTI_RTSR1_RT8_Pos       (8U)
4014 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
4015 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
4016 #define EXTI_RTSR1_RT9_Pos       (9U)
4017 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
4018 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
4019 #define EXTI_RTSR1_RT10_Pos      (10U)
4020 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
4021 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
4022 #define EXTI_RTSR1_RT11_Pos      (11U)
4023 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
4024 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
4025 #define EXTI_RTSR1_RT12_Pos      (12U)
4026 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
4027 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
4028 #define EXTI_RTSR1_RT13_Pos      (13U)
4029 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
4030 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
4031 #define EXTI_RTSR1_RT14_Pos      (14U)
4032 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
4033 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
4034 #define EXTI_RTSR1_RT15_Pos      (15U)
4035 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
4036 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
4037 #define EXTI_RTSR1_RT16_Pos      (16U)
4038 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
4039 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
4040 #define EXTI_RTSR1_RT17_Pos      (17U)
4041 #define EXTI_RTSR1_RT17_Msk      (0x1UL << EXTI_RTSR1_RT17_Pos)                /*!< 0x00020000 */
4042 #define EXTI_RTSR1_RT17          EXTI_RTSR1_RT17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
4043 #define EXTI_RTSR1_RT19_Pos      (19U)
4044 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
4045 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
4046 #define EXTI_RTSR1_RT20_Pos      (20U)
4047 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
4048 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
4049 #define EXTI_RTSR1_RT21_Pos      (21U)
4050 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
4051 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
4052 #define EXTI_RTSR1_RT22_Pos      (22U)
4053 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
4054 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
4055 #define EXTI_RTSR1_RT29_Pos      (29U)
4056 #define EXTI_RTSR1_RT29_Msk      (0x1UL << EXTI_RTSR1_RT29_Pos)                /*!< 0x20000000 */
4057 #define EXTI_RTSR1_RT29          EXTI_RTSR1_RT29_Msk                           /*!< Rising trigger event configuration bit of line 29 */
4058 #define EXTI_RTSR1_RT30_Pos      (30U)
4059 #define EXTI_RTSR1_RT30_Msk      (0x1UL << EXTI_RTSR1_RT30_Pos)                /*!< 0x40000000 */
4060 #define EXTI_RTSR1_RT30          EXTI_RTSR1_RT30_Msk                           /*!< Rising trigger event configuration bit of line 30 */
4061 #define EXTI_RTSR1_RT31_Pos      (31U)
4062 #define EXTI_RTSR1_RT31_Msk      (0x1UL << EXTI_RTSR1_RT31_Pos)                /*!< 0x80000000 */
4063 #define EXTI_RTSR1_RT31          EXTI_RTSR1_RT31_Msk                           /*!< Rising trigger event configuration bit of line 31 */
4064 
4065 /******************  Bit definition for EXTI_FTSR1 register  ******************/
4066 #define EXTI_FTSR1_FT0_Pos       (0U)
4067 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
4068 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
4069 #define EXTI_FTSR1_FT1_Pos       (1U)
4070 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
4071 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
4072 #define EXTI_FTSR1_FT2_Pos       (2U)
4073 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
4074 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
4075 #define EXTI_FTSR1_FT3_Pos       (3U)
4076 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
4077 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
4078 #define EXTI_FTSR1_FT4_Pos       (4U)
4079 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
4080 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
4081 #define EXTI_FTSR1_FT5_Pos       (5U)
4082 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
4083 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
4084 #define EXTI_FTSR1_FT6_Pos       (6U)
4085 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
4086 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
4087 #define EXTI_FTSR1_FT7_Pos       (7U)
4088 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
4089 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
4090 #define EXTI_FTSR1_FT8_Pos       (8U)
4091 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
4092 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
4093 #define EXTI_FTSR1_FT9_Pos       (9U)
4094 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
4095 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
4096 #define EXTI_FTSR1_FT10_Pos      (10U)
4097 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
4098 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
4099 #define EXTI_FTSR1_FT11_Pos      (11U)
4100 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
4101 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
4102 #define EXTI_FTSR1_FT12_Pos      (12U)
4103 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
4104 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
4105 #define EXTI_FTSR1_FT13_Pos      (13U)
4106 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
4107 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
4108 #define EXTI_FTSR1_FT14_Pos      (14U)
4109 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
4110 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
4111 #define EXTI_FTSR1_FT15_Pos      (15U)
4112 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
4113 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
4114 #define EXTI_FTSR1_FT16_Pos      (16U)
4115 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
4116 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
4117 #define EXTI_FTSR1_FT17_Pos      (17U)
4118 #define EXTI_FTSR1_FT17_Msk      (0x1UL << EXTI_FTSR1_FT17_Pos)                /*!< 0x00020000 */
4119 #define EXTI_FTSR1_FT17          EXTI_FTSR1_FT17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
4120 #define EXTI_FTSR1_FT19_Pos      (19U)
4121 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
4122 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
4123 #define EXTI_FTSR1_FT20_Pos      (20U)
4124 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
4125 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
4126 #define EXTI_FTSR1_FT21_Pos      (21U)
4127 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
4128 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
4129 #define EXTI_FTSR1_FT22_Pos      (22U)
4130 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
4131 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
4132 #define EXTI_FTSR1_FT29_Pos      (29U)
4133 #define EXTI_FTSR1_FT29_Msk      (0x1UL << EXTI_FTSR1_FT29_Pos)                /*!< 0x20000000 */
4134 #define EXTI_FTSR1_FT29          EXTI_FTSR1_FT29_Msk                           /*!< Falling trigger event configuration bit of line 29 */
4135 #define EXTI_FTSR1_FT30_Pos      (30U)
4136 #define EXTI_FTSR1_FT30_Msk      (0x1UL << EXTI_FTSR1_FT30_Pos)                /*!< 0x40000000 */
4137 #define EXTI_FTSR1_FT30          EXTI_FTSR1_FT30_Msk                           /*!< Falling trigger event configuration bit of line 30 */
4138 #define EXTI_FTSR1_FT31_Pos      (31U)
4139 #define EXTI_FTSR1_FT31_Msk      (0x1UL << EXTI_FTSR1_FT31_Pos)                /*!< 0x80000000 */
4140 #define EXTI_FTSR1_FT31          EXTI_FTSR1_FT31_Msk                           /*!< Falling trigger event configuration bit of line 31 */
4141 
4142 /******************  Bit definition for EXTI_SWIER1 register  *****************/
4143 #define EXTI_SWIER1_SWI0_Pos     (0U)
4144 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
4145 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
4146 #define EXTI_SWIER1_SWI1_Pos     (1U)
4147 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
4148 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
4149 #define EXTI_SWIER1_SWI2_Pos     (2U)
4150 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
4151 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
4152 #define EXTI_SWIER1_SWI3_Pos     (3U)
4153 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
4154 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
4155 #define EXTI_SWIER1_SWI4_Pos     (4U)
4156 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
4157 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
4158 #define EXTI_SWIER1_SWI5_Pos     (5U)
4159 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
4160 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
4161 #define EXTI_SWIER1_SWI6_Pos     (6U)
4162 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
4163 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
4164 #define EXTI_SWIER1_SWI7_Pos     (7U)
4165 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
4166 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
4167 #define EXTI_SWIER1_SWI8_Pos     (8U)
4168 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
4169 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
4170 #define EXTI_SWIER1_SWI9_Pos     (9U)
4171 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
4172 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
4173 #define EXTI_SWIER1_SWI10_Pos    (10U)
4174 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
4175 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
4176 #define EXTI_SWIER1_SWI11_Pos    (11U)
4177 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
4178 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
4179 #define EXTI_SWIER1_SWI12_Pos    (12U)
4180 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
4181 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
4182 #define EXTI_SWIER1_SWI13_Pos    (13U)
4183 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
4184 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
4185 #define EXTI_SWIER1_SWI14_Pos    (14U)
4186 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
4187 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
4188 #define EXTI_SWIER1_SWI15_Pos    (15U)
4189 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
4190 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
4191 #define EXTI_SWIER1_SWI16_Pos    (16U)
4192 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
4193 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
4194 #define EXTI_SWIER1_SWI17_Pos    (17U)
4195 #define EXTI_SWIER1_SWI17_Msk    (0x1UL << EXTI_SWIER1_SWI17_Pos)              /*!< 0x00020000 */
4196 #define EXTI_SWIER1_SWI17        EXTI_SWIER1_SWI17_Msk                         /*!< Software Interrupt on line 17 */
4197 #define EXTI_SWIER1_SWI19_Pos    (19U)
4198 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
4199 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
4200 #define EXTI_SWIER1_SWI20_Pos    (20U)
4201 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
4202 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
4203 #define EXTI_SWIER1_SWI21_Pos    (21U)
4204 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
4205 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
4206 #define EXTI_SWIER1_SWI22_Pos    (22U)
4207 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
4208 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
4209 #define EXTI_SWIER1_SWI29_Pos    (29U)
4210 #define EXTI_SWIER1_SWI29_Msk    (0x1UL << EXTI_SWIER1_SWI29_Pos)              /*!< 0x20000000 */
4211 #define EXTI_SWIER1_SWI29        EXTI_SWIER1_SWI29_Msk                         /*!< Software Interrupt on line 29 */
4212 #define EXTI_SWIER1_SWI30_Pos    (30U)
4213 #define EXTI_SWIER1_SWI30_Msk    (0x1UL << EXTI_SWIER1_SWI30_Pos)              /*!< 0x40000000 */
4214 #define EXTI_SWIER1_SWI30        EXTI_SWIER1_SWI30_Msk                         /*!< Software Interrupt on line 30 */
4215 #define EXTI_SWIER1_SWI31_Pos    (31U)
4216 #define EXTI_SWIER1_SWI31_Msk    (0x1UL << EXTI_SWIER1_SWI31_Pos)              /*!< 0x80000000 */
4217 #define EXTI_SWIER1_SWI31        EXTI_SWIER1_SWI31_Msk                         /*!< Software Interrupt on line 31 */
4218 
4219 /*******************  Bit definition for EXTI_PR1 register  *******************/
4220 #define EXTI_PR1_PIF0_Pos        (0U)
4221 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
4222 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
4223 #define EXTI_PR1_PIF1_Pos        (1U)
4224 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
4225 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
4226 #define EXTI_PR1_PIF2_Pos        (2U)
4227 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
4228 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
4229 #define EXTI_PR1_PIF3_Pos        (3U)
4230 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
4231 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
4232 #define EXTI_PR1_PIF4_Pos        (4U)
4233 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
4234 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
4235 #define EXTI_PR1_PIF5_Pos        (5U)
4236 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
4237 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
4238 #define EXTI_PR1_PIF6_Pos        (6U)
4239 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
4240 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
4241 #define EXTI_PR1_PIF7_Pos        (7U)
4242 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
4243 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
4244 #define EXTI_PR1_PIF8_Pos        (8U)
4245 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
4246 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
4247 #define EXTI_PR1_PIF9_Pos        (9U)
4248 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
4249 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
4250 #define EXTI_PR1_PIF10_Pos       (10U)
4251 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
4252 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
4253 #define EXTI_PR1_PIF11_Pos       (11U)
4254 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
4255 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
4256 #define EXTI_PR1_PIF12_Pos       (12U)
4257 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
4258 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
4259 #define EXTI_PR1_PIF13_Pos       (13U)
4260 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
4261 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
4262 #define EXTI_PR1_PIF14_Pos       (14U)
4263 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
4264 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
4265 #define EXTI_PR1_PIF15_Pos       (15U)
4266 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
4267 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
4268 #define EXTI_PR1_PIF16_Pos       (16U)
4269 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
4270 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
4271 #define EXTI_PR1_PIF17_Pos       (17U)
4272 #define EXTI_PR1_PIF17_Msk       (0x1UL << EXTI_PR1_PIF17_Pos)                 /*!< 0x00020000 */
4273 #define EXTI_PR1_PIF17           EXTI_PR1_PIF17_Msk                            /*!< Pending bit for line 17 */
4274 #define EXTI_PR1_PIF19_Pos       (19U)
4275 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
4276 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
4277 #define EXTI_PR1_PIF20_Pos       (20U)
4278 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
4279 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
4280 #define EXTI_PR1_PIF21_Pos       (21U)
4281 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
4282 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
4283 #define EXTI_PR1_PIF22_Pos       (22U)
4284 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
4285 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
4286 #define EXTI_PR1_PIF29_Pos       (29U)
4287 #define EXTI_PR1_PIF29_Msk       (0x1UL << EXTI_PR1_PIF29_Pos)                 /*!< 0x20000000 */
4288 #define EXTI_PR1_PIF29           EXTI_PR1_PIF29_Msk                            /*!< Pending bit for line 29 */
4289 #define EXTI_PR1_PIF30_Pos       (30U)
4290 #define EXTI_PR1_PIF30_Msk       (0x1UL << EXTI_PR1_PIF30_Pos)                 /*!< 0x40000000 */
4291 #define EXTI_PR1_PIF30           EXTI_PR1_PIF30_Msk                            /*!< Pending bit for line 30 */
4292 #define EXTI_PR1_PIF31_Pos       (31U)
4293 #define EXTI_PR1_PIF31_Msk       (0x1UL << EXTI_PR1_PIF31_Pos)                 /*!< 0x80000000 */
4294 #define EXTI_PR1_PIF31           EXTI_PR1_PIF31_Msk                            /*!< Pending bit for line 31 */
4295 
4296 /*******************  Bit definition for EXTI_IMR2 register  ******************/
4297 #define EXTI_IMR2_IM32_Pos       (0U)
4298 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
4299 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
4300 #define EXTI_IMR2_IM33_Pos       (1U)
4301 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
4302 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
4303 #define EXTI_IMR2_IM34_Pos       (2U)
4304 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
4305 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
4306 #define EXTI_IMR2_IM35_Pos       (3U)
4307 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
4308 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
4309 #define EXTI_IMR2_IM36_Pos       (4U)
4310 #define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
4311 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
4312 #define EXTI_IMR2_IM37_Pos       (5U)
4313 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
4314 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
4315 #define EXTI_IMR2_IM38_Pos       (6U)
4316 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
4317 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
4318 #define EXTI_IMR2_IM39_Pos       (7U)
4319 #define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
4320 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
4321 #define EXTI_IMR2_IM40_Pos       (8U)
4322 #define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
4323 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
4324 #define EXTI_IMR2_IM41_Pos       (9U)
4325 #define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
4326 #define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< Interrupt Mask on line 41 */
4327 #define EXTI_IMR2_IM42_Pos       (10U)
4328 #define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
4329 #define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< Interrupt Mask on line 42 */
4330 #define EXTI_IMR2_IM_Pos         (0U)
4331 #define EXTI_IMR2_IM_Msk         (0x7FFUL << EXTI_IMR2_IM_Pos)                 /*!< 0x000007FF */
4332 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
4333 
4334 /*******************  Bit definition for EXTI_EMR2 register  ******************/
4335 #define EXTI_EMR2_EM32_Pos       (0U)
4336 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
4337 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
4338 #define EXTI_EMR2_EM33_Pos       (1U)
4339 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
4340 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
4341 #define EXTI_EMR2_EM34_Pos       (2U)
4342 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
4343 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
4344 #define EXTI_EMR2_EM35_Pos       (3U)
4345 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
4346 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
4347 #define EXTI_EMR2_EM36_Pos       (4U)
4348 #define EXTI_EMR2_EM36_Msk       (0x1UL << EXTI_EMR2_EM36_Pos)                 /*!< 0x00000010 */
4349 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
4350 #define EXTI_EMR2_EM37_Pos       (5U)
4351 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
4352 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
4353 #define EXTI_EMR2_EM38_Pos       (6U)
4354 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
4355 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
4356 #define EXTI_EMR2_EM39_Pos       (7U)
4357 #define EXTI_EMR2_EM39_Msk       (0x1UL << EXTI_EMR2_EM39_Pos)                 /*!< 0x00000080 */
4358 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
4359 #define EXTI_EMR2_EM40_Pos       (8U)
4360 #define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
4361 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
4362 #define EXTI_EMR2_EM41_Pos       (9U)
4363 #define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
4364 #define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< Event Mask on line 41 */
4365 #define EXTI_EMR2_EM42_Pos       (10U)
4366 #define EXTI_EMR2_EM42_Msk       (0x1UL << EXTI_EMR2_EM42_Pos)                 /*!< 0x00000400 */
4367 #define EXTI_EMR2_EM42           EXTI_EMR2_EM42_Msk                            /*!< Event Mask on line 42 */
4368 #define EXTI_EMR2_EM_Pos         (0U)
4369 #define EXTI_EMR2_EM_Msk         (0x7FFUL << EXTI_EMR2_EM_Pos)                 /*!< 0x000007FF */
4370 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
4371 
4372 /******************  Bit definition for EXTI_RTSR2 register  ******************/
4373 #define EXTI_RTSR2_RT32_Pos      (0U)
4374 #define EXTI_RTSR2_RT32_Msk      (0x1UL << EXTI_RTSR2_RT32_Pos)                /*!< 0x00000001 */
4375 #define EXTI_RTSR2_RT32          EXTI_RTSR2_RT32_Msk                           /*!< Rising trigger event configuration bit of line 32 */
4376 #define EXTI_RTSR2_RT33_Pos      (1U)
4377 #define EXTI_RTSR2_RT33_Msk      (0x1UL << EXTI_RTSR2_RT33_Pos)                /*!< 0x00000002 */
4378 #define EXTI_RTSR2_RT33          EXTI_RTSR2_RT33_Msk                           /*!< Rising trigger event configuration bit of line 33 */
4379 #define EXTI_RTSR2_RT38_Pos      (6U)
4380 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
4381 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
4382 #define EXTI_RTSR2_RT39_Pos      (7U)
4383 #define EXTI_RTSR2_RT39_Msk      (0x1UL << EXTI_RTSR2_RT39_Pos)                /*!< 0x00000080 */
4384 #define EXTI_RTSR2_RT39          EXTI_RTSR2_RT39_Msk                           /*!< Rising trigger event configuration bit of line 39 */
4385 #define EXTI_RTSR2_RT40_Pos      (8U)
4386 #define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
4387 #define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
4388 #define EXTI_RTSR2_RT41_Pos      (9U)
4389 #define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
4390 #define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
4391 
4392 /******************  Bit definition for EXTI_FTSR2 register  ******************/
4393 #define EXTI_FTSR2_FT32_Pos      (0U)
4394 #define EXTI_FTSR2_FT32_Msk      (0x1UL << EXTI_FTSR2_FT32_Pos)                /*!< 0x00000001 */
4395 #define EXTI_FTSR2_FT32          EXTI_FTSR2_FT32_Msk                           /*!< Falling trigger event configuration bit of line 32 */
4396 #define EXTI_FTSR2_FT33_Pos      (1U)
4397 #define EXTI_FTSR2_FT33_Msk      (0x1UL << EXTI_FTSR2_FT33_Pos)                /*!< 0x00000002 */
4398 #define EXTI_FTSR2_FT33          EXTI_FTSR2_FT33_Msk                           /*!< Falling trigger event configuration bit of line 33 */
4399 #define EXTI_FTSR2_FT38_Pos      (6U)
4400 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
4401 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 37 */
4402 #define EXTI_FTSR2_FT39_Pos      (7U)
4403 #define EXTI_FTSR2_FT39_Msk      (0x1UL << EXTI_FTSR2_FT39_Pos)                /*!< 0x00000080 */
4404 #define EXTI_FTSR2_FT39          EXTI_FTSR2_FT39_Msk                           /*!< Falling trigger event configuration bit of line 39 */
4405 #define EXTI_FTSR2_FT40_Pos      (8U)
4406 #define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
4407 #define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
4408 #define EXTI_FTSR2_FT41_Pos      (9U)
4409 #define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
4410 #define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
4411 
4412 /******************  Bit definition for EXTI_SWIER2 register  *****************/
4413 #define EXTI_SWIER2_SWI32_Pos    (0U)
4414 #define EXTI_SWIER2_SWI32_Msk    (0x1UL << EXTI_SWIER2_SWI32_Pos)              /*!< 0x00000001 */
4415 #define EXTI_SWIER2_SWI32        EXTI_SWIER2_SWI32_Msk                         /*!< Software Interrupt on line 32 */
4416 #define EXTI_SWIER2_SWI33_Pos    (1U)
4417 #define EXTI_SWIER2_SWI33_Msk    (0x1UL << EXTI_SWIER2_SWI33_Pos)              /*!< 0x00000002 */
4418 #define EXTI_SWIER2_SWI33        EXTI_SWIER2_SWI33_Msk                         /*!< Software Interrupt on line 33 */
4419 #define EXTI_SWIER2_SWI38_Pos    (6U)
4420 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
4421 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
4422 #define EXTI_SWIER2_SWI39_Pos    (7U)
4423 #define EXTI_SWIER2_SWI39_Msk    (0x1UL << EXTI_SWIER2_SWI39_Pos)              /*!< 0x00000080 */
4424 #define EXTI_SWIER2_SWI39        EXTI_SWIER2_SWI39_Msk                         /*!< Software Interrupt on line 39 */
4425 #define EXTI_SWIER2_SWI40_Pos    (8U)
4426 #define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
4427 #define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
4428 #define EXTI_SWIER2_SWI41_Pos    (9U)
4429 #define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
4430 #define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
4431 
4432 /*******************  Bit definition for EXTI_PR2 register  *******************/
4433 #define EXTI_PR2_PIF32_Pos       (0U)
4434 #define EXTI_PR2_PIF32_Msk       (0x1UL << EXTI_PR2_PIF32_Pos)                 /*!< 0x00000001 */
4435 #define EXTI_PR2_PIF32           EXTI_PR2_PIF32_Msk                            /*!< Pending bit for line 32 */
4436 #define EXTI_PR2_PIF33_Pos       (1U)
4437 #define EXTI_PR2_PIF33_Msk       (0x1UL << EXTI_PR2_PIF33_Pos)                 /*!< 0x00000002 */
4438 #define EXTI_PR2_PIF33           EXTI_PR2_PIF33_Msk                            /*!< Pending bit for line 33 */
4439 #define EXTI_PR2_PIF38_Pos       (6U)
4440 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
4441 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
4442 #define EXTI_PR2_PIF39_Pos       (7U)
4443 #define EXTI_PR2_PIF39_Msk       (0x1UL << EXTI_PR2_PIF39_Pos)                 /*!< 0x00000080 */
4444 #define EXTI_PR2_PIF39           EXTI_PR2_PIF39_Msk                            /*!< Pending bit for line 39 */
4445 #define EXTI_PR2_PIF40_Pos       (8U)
4446 #define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
4447 #define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
4448 #define EXTI_PR2_PIF41_Pos       (9U)
4449 #define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
4450 #define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
4451 
4452 /******************************************************************************/
4453 /*                                                                            */
4454 /*                 Flexible Datarate Controller Area Network                  */
4455 /*                                                                            */
4456 /******************************************************************************/
4457 /*!<FDCAN control and status registers */
4458 /*****************  Bit definition for FDCAN_CREL register  *******************/
4459 #define FDCAN_CREL_DAY_Pos        (0U)
4460 #define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
4461 #define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
4462 #define FDCAN_CREL_MON_Pos        (8U)
4463 #define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
4464 #define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
4465 #define FDCAN_CREL_YEAR_Pos       (16U)
4466 #define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
4467 #define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
4468 #define FDCAN_CREL_SUBSTEP_Pos    (20U)
4469 #define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
4470 #define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
4471 #define FDCAN_CREL_STEP_Pos       (24U)
4472 #define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
4473 #define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
4474 #define FDCAN_CREL_REL_Pos        (28U)
4475 #define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
4476 #define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
4477 
4478 /*****************  Bit definition for FDCAN_ENDN register  *******************/
4479 #define FDCAN_ENDN_ETV_Pos        (0U)
4480 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
4481 #define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                    */
4482 
4483 /*****************  Bit definition for FDCAN_DBTP register  *******************/
4484 #define FDCAN_DBTP_DSJW_Pos       (0U)
4485 #define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
4486 #define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
4487 #define FDCAN_DBTP_DTSEG2_Pos     (4U)
4488 #define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
4489 #define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
4490 #define FDCAN_DBTP_DTSEG1_Pos     (8U)
4491 #define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
4492 #define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
4493 #define FDCAN_DBTP_DBRP_Pos       (16U)
4494 #define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
4495 #define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
4496 #define FDCAN_DBTP_TDC_Pos        (23U)
4497 #define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
4498 #define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
4499 
4500 /*****************  Bit definition for FDCAN_TEST register  *******************/
4501 #define FDCAN_TEST_LBCK_Pos       (4U)
4502 #define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
4503 #define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
4504 #define FDCAN_TEST_TX_Pos         (5U)
4505 #define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
4506 #define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
4507 #define FDCAN_TEST_RX_Pos         (7U)
4508 #define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
4509 #define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
4510 
4511 /*****************  Bit definition for FDCAN_RWD register  ********************/
4512 #define FDCAN_RWD_WDC_Pos         (0U)
4513 #define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
4514 #define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
4515 #define FDCAN_RWD_WDV_Pos         (8U)
4516 #define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
4517 #define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
4518 
4519 /*****************  Bit definition for FDCAN_CCCR register  ********************/
4520 #define FDCAN_CCCR_INIT_Pos       (0U)
4521 #define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
4522 #define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
4523 #define FDCAN_CCCR_CCE_Pos        (1U)
4524 #define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
4525 #define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
4526 #define FDCAN_CCCR_ASM_Pos        (2U)
4527 #define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
4528 #define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
4529 #define FDCAN_CCCR_CSA_Pos        (3U)
4530 #define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
4531 #define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
4532 #define FDCAN_CCCR_CSR_Pos        (4U)
4533 #define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
4534 #define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
4535 #define FDCAN_CCCR_MON_Pos        (5U)
4536 #define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
4537 #define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
4538 #define FDCAN_CCCR_DAR_Pos        (6U)
4539 #define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
4540 #define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
4541 #define FDCAN_CCCR_TEST_Pos       (7U)
4542 #define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
4543 #define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
4544 #define FDCAN_CCCR_FDOE_Pos       (8U)
4545 #define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
4546 #define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
4547 #define FDCAN_CCCR_BRSE_Pos       (9U)
4548 #define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
4549 #define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
4550 #define FDCAN_CCCR_PXHD_Pos       (12U)
4551 #define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
4552 #define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
4553 #define FDCAN_CCCR_EFBI_Pos       (13U)
4554 #define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
4555 #define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
4556 #define FDCAN_CCCR_TXP_Pos        (14U)
4557 #define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
4558 #define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
4559 #define FDCAN_CCCR_NISO_Pos       (15U)
4560 #define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
4561 #define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
4562 
4563 /*****************  Bit definition for FDCAN_NBTP register  ********************/
4564 #define FDCAN_NBTP_NTSEG2_Pos     (0U)
4565 #define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
4566 #define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
4567 #define FDCAN_NBTP_NTSEG1_Pos     (8U)
4568 #define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
4569 #define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
4570 #define FDCAN_NBTP_NBRP_Pos       (16U)
4571 #define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
4572 #define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
4573 #define FDCAN_NBTP_NSJW_Pos       (25U)
4574 #define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
4575 #define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
4576 
4577 /*****************  Bit definition for FDCAN_TSCC register  ********************/
4578 #define FDCAN_TSCC_TSS_Pos        (0U)
4579 #define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
4580 #define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
4581 #define FDCAN_TSCC_TCP_Pos        (16U)
4582 #define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
4583 #define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
4584 
4585 /*****************  Bit definition for FDCAN_TSCV register  ********************/
4586 #define FDCAN_TSCV_TSC_Pos        (0U)
4587 #define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
4588 #define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
4589 
4590 /*****************  Bit definition for FDCAN_TOCC register  ********************/
4591 #define FDCAN_TOCC_ETOC_Pos       (0U)
4592 #define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
4593 #define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
4594 #define FDCAN_TOCC_TOS_Pos        (1U)
4595 #define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
4596 #define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
4597 #define FDCAN_TOCC_TOP_Pos        (16U)
4598 #define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
4599 #define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
4600 
4601 /*****************  Bit definition for FDCAN_TOCV register  ********************/
4602 #define FDCAN_TOCV_TOC_Pos        (0U)
4603 #define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
4604 #define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
4605 
4606 /*****************  Bit definition for FDCAN_ECR register  *********************/
4607 #define FDCAN_ECR_TEC_Pos         (0U)
4608 #define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                /*!< 0x000000FF */
4609 #define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
4610 #define FDCAN_ECR_REC_Pos         (8U)
4611 #define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
4612 #define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
4613 #define FDCAN_ECR_RP_Pos          (15U)
4614 #define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
4615 #define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
4616 #define FDCAN_ECR_CEL_Pos         (16U)
4617 #define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
4618 #define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
4619 
4620 /*****************  Bit definition for FDCAN_PSR register  *********************/
4621 #define FDCAN_PSR_LEC_Pos         (0U)
4622 #define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
4623 #define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
4624 #define FDCAN_PSR_ACT_Pos         (3U)
4625 #define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
4626 #define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
4627 #define FDCAN_PSR_EP_Pos          (5U)
4628 #define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
4629 #define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
4630 #define FDCAN_PSR_EW_Pos          (6U)
4631 #define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
4632 #define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
4633 #define FDCAN_PSR_BO_Pos          (7U)
4634 #define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
4635 #define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
4636 #define FDCAN_PSR_DLEC_Pos        (8U)
4637 #define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
4638 #define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
4639 #define FDCAN_PSR_RESI_Pos        (11U)
4640 #define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
4641 #define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
4642 #define FDCAN_PSR_RBRS_Pos        (12U)
4643 #define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
4644 #define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
4645 #define FDCAN_PSR_REDL_Pos        (13U)
4646 #define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
4647 #define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
4648 #define FDCAN_PSR_PXE_Pos         (14U)
4649 #define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
4650 #define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
4651 #define FDCAN_PSR_TDCV_Pos        (16U)
4652 #define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
4653 #define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
4654 
4655 /*****************  Bit definition for FDCAN_TDCR register  ********************/
4656 #define FDCAN_TDCR_TDCF_Pos       (0U)
4657 #define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
4658 #define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
4659 #define FDCAN_TDCR_TDCO_Pos       (8U)
4660 #define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
4661 #define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
4662 
4663 /*****************  Bit definition for FDCAN_IR register  **********************/
4664 #define FDCAN_IR_RF0N_Pos         (0U)
4665 #define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
4666 #define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
4667 #define FDCAN_IR_RF0F_Pos         (1U)
4668 #define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000002 */
4669 #define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
4670 #define FDCAN_IR_RF0L_Pos         (2U)
4671 #define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000004 */
4672 #define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
4673 #define FDCAN_IR_RF1N_Pos         (3U)
4674 #define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000008 */
4675 #define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
4676 #define FDCAN_IR_RF1F_Pos         (4U)
4677 #define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000010 */
4678 #define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
4679 #define FDCAN_IR_RF1L_Pos         (5U)
4680 #define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000020 */
4681 #define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
4682 #define FDCAN_IR_HPM_Pos          (6U)
4683 #define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000040 */
4684 #define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
4685 #define FDCAN_IR_TC_Pos           (7U)
4686 #define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000080 */
4687 #define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
4688 #define FDCAN_IR_TCF_Pos          (8U)
4689 #define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000100 */
4690 #define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
4691 #define FDCAN_IR_TFE_Pos          (9U)
4692 #define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000200 */
4693 #define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
4694 #define FDCAN_IR_TEFN_Pos         (10U)
4695 #define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00000400 */
4696 #define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
4697 #define FDCAN_IR_TEFF_Pos         (11U)
4698 #define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00000800 */
4699 #define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
4700 #define FDCAN_IR_TEFL_Pos         (12U)
4701 #define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00001000 */
4702 #define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
4703 #define FDCAN_IR_TSW_Pos          (13U)
4704 #define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00002000 */
4705 #define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
4706 #define FDCAN_IR_MRAF_Pos         (14U)
4707 #define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00004000 */
4708 #define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
4709 #define FDCAN_IR_TOO_Pos          (15U)
4710 #define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00008000 */
4711 #define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
4712 #define FDCAN_IR_ELO_Pos          (16U)
4713 #define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00010000 */
4714 #define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
4715 #define FDCAN_IR_EP_Pos           (17U)
4716 #define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00020000 */
4717 #define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
4718 #define FDCAN_IR_EW_Pos           (18U)
4719 #define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x00040000 */
4720 #define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
4721 #define FDCAN_IR_BO_Pos           (19U)
4722 #define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x00080000 */
4723 #define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
4724 #define FDCAN_IR_WDI_Pos          (20U)
4725 #define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x00100000 */
4726 #define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
4727 #define FDCAN_IR_PEA_Pos          (21U)
4728 #define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x00200000 */
4729 #define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
4730 #define FDCAN_IR_PED_Pos          (22U)
4731 #define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x00400000 */
4732 #define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
4733 #define FDCAN_IR_ARA_Pos          (23U)
4734 #define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x00800000 */
4735 #define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
4736 
4737 /*****************  Bit definition for FDCAN_IE register  **********************/
4738 #define FDCAN_IE_RF0NE_Pos        (0U)
4739 #define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
4740 #define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable             */
4741 #define FDCAN_IE_RF0FE_Pos        (1U)
4742 #define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000002 */
4743 #define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                    */
4744 #define FDCAN_IE_RF0LE_Pos        (2U)
4745 #define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000004 */
4746 #define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable            */
4747 #define FDCAN_IE_RF1NE_Pos        (3U)
4748 #define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000008 */
4749 #define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable             */
4750 #define FDCAN_IE_RF1FE_Pos        (4U)
4751 #define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000010 */
4752 #define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                    */
4753 #define FDCAN_IE_RF1LE_Pos        (5U)
4754 #define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000020 */
4755 #define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable            */
4756 #define FDCAN_IE_HPME_Pos         (6U)
4757 #define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000040 */
4758 #define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable             */
4759 #define FDCAN_IE_TCE_Pos          (7U)
4760 #define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000080 */
4761 #define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable            */
4762 #define FDCAN_IE_TCFE_Pos         (8U)
4763 #define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000100 */
4764 #define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable*/
4765 #define FDCAN_IE_TFEE_Pos         (9U)
4766 #define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000200 */
4767 #define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                     */
4768 #define FDCAN_IE_TEFNE_Pos        (10U)
4769 #define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00000400 */
4770 #define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable           */
4771 #define FDCAN_IE_TEFFE_Pos        (11U)
4772 #define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00000800 */
4773 #define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                */
4774 #define FDCAN_IE_TEFLE_Pos        (12U)
4775 #define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00001000 */
4776 #define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable        */
4777 #define FDCAN_IE_TSWE_Pos         (13U)
4778 #define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00002000 */
4779 #define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable              */
4780 #define FDCAN_IE_MRAFE_Pos        (14U)
4781 #define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00004000 */
4782 #define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable        */
4783 #define FDCAN_IE_TOOE_Pos         (15U)
4784 #define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00008000 */
4785 #define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                  */
4786 #define FDCAN_IE_ELOE_Pos         (16U)
4787 #define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00010000 */
4788 #define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable            */
4789 #define FDCAN_IE_EPE_Pos          (17U)
4790 #define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00020000 */
4791 #define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                     */
4792 #define FDCAN_IE_EWE_Pos          (18U)
4793 #define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x00040000 */
4794 #define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                    */
4795 #define FDCAN_IE_BOE_Pos          (19U)
4796 #define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x00080000 */
4797 #define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                    */
4798 #define FDCAN_IE_WDIE_Pos         (20U)
4799 #define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x00100000 */
4800 #define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                */
4801 #define FDCAN_IE_PEAE_Pos         (21U)
4802 #define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x00200000 */
4803 #define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable*/
4804 #define FDCAN_IE_PEDE_Pos         (22U)
4805 #define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x00400000 */
4806 #define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable      */
4807 #define FDCAN_IE_ARAE_Pos         (23U)
4808 #define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x00800000 */
4809 #define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable        */
4810 
4811 /*****************  Bit definition for FDCAN_ILS register  **********************/
4812 #define FDCAN_ILS_RXFIFO0_Pos     (0U)
4813 #define FDCAN_ILS_RXFIFO0_Msk     (0x1UL << FDCAN_ILS_RXFIFO0_Pos)             /*!< 0x00000001 */
4814 #define FDCAN_ILS_RXFIFO0         FDCAN_ILS_RXFIFO0_Msk                        /*!<Rx FIFO 0 Message Lost
4815                                                                                    Rx FIFO 0 is Full
4816                                                                                    Rx FIFO 0 Has New Message                */
4817 #define FDCAN_ILS_RXFIFO1_Pos     (1U)
4818 #define FDCAN_ILS_RXFIFO1_Msk     (0x1UL << FDCAN_ILS_RXFIFO1_Pos)             /*!< 0x00000002 */
4819 #define FDCAN_ILS_RXFIFO1         FDCAN_ILS_RXFIFO1_Msk                        /*!<Rx FIFO 1 Message Lost
4820                                                                                    Rx FIFO 1 is Full
4821                                                                                    Rx FIFO 1 Has New Message                */
4822 #define FDCAN_ILS_SMSG_Pos        (2U)
4823 #define FDCAN_ILS_SMSG_Msk        (0x1UL << FDCAN_ILS_SMSG_Pos)                /*!< 0x00000004 */
4824 #define FDCAN_ILS_SMSG            FDCAN_ILS_SMSG_Msk                           /*!<Transmission Cancellation Finished
4825                                                                                    Transmission Completed
4826                                                                                    High Priority Message                    */
4827 #define FDCAN_ILS_TFERR_Pos       (3U)
4828 #define FDCAN_ILS_TFERR_Msk       (0x1UL << FDCAN_ILS_TFERR_Pos)               /*!< 0x00000008 */
4829 #define FDCAN_ILS_TFERR           FDCAN_ILS_TFERR_Msk                          /*!<Tx Event FIFO Element Lost
4830                                                                                    Tx Event FIFO Full
4831                                                                                    Tx Event FIFO New Entry
4832                                                                                    Tx FIFO Empty Interrupt Line             */
4833 #define FDCAN_ILS_MISC_Pos        (4U)
4834 #define FDCAN_ILS_MISC_Msk        (0x1UL << FDCAN_ILS_MISC_Pos)                /*!< 0x00000010 */
4835 #define FDCAN_ILS_MISC            FDCAN_ILS_MISC_Msk                           /*!<Timeout Occurred
4836                                                                                     Message RAM Access Failure
4837                                                                                     Timestamp Wraparound                    */
4838 #define FDCAN_ILS_BERR_Pos        (5U)
4839 #define FDCAN_ILS_BERR_Msk        (0x1UL << FDCAN_ILS_BERR_Pos)                /*!< 0x00000020 */
4840 #define FDCAN_ILS_BERR            FDCAN_ILS_BERR_Msk                           /*!<Error Passive
4841                                                                                    Error Logging Overflow                   */
4842 #define FDCAN_ILS_PERR_Pos        (6U)
4843 #define FDCAN_ILS_PERR_Msk        (0x1UL << FDCAN_ILS_PERR_Pos)                /*!< 0x00000040 */
4844 #define FDCAN_ILS_PERR            FDCAN_ILS_PERR_Msk                           /*!<Access to Reserved Address Line
4845                                                                                    Protocol Error in Data Phase Line
4846                                                                                    Protocol Error in Arbitration Phase Line
4847                                                                                    Watchdog Interrupt Line
4848                                                                                    Bus_Off Status
4849                                                                                    Warning Status                           */
4850 
4851 /*****************  Bit definition for FDCAN_ILE register  **********************/
4852 #define FDCAN_ILE_EINT0_Pos       (0U)
4853 #define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
4854 #define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                  */
4855 #define FDCAN_ILE_EINT1_Pos       (1U)
4856 #define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
4857 #define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                  */
4858 
4859 /*****************  Bit definition for FDCAN_RXGFC register  ********************/
4860 #define FDCAN_RXGFC_RRFE_Pos      (0U)
4861 #define FDCAN_RXGFC_RRFE_Msk      (0x1UL << FDCAN_RXGFC_RRFE_Pos)              /*!< 0x00000001 */
4862 #define FDCAN_RXGFC_RRFE          FDCAN_RXGFC_RRFE_Msk                         /*!<Reject Remote Frames Extended            */
4863 #define FDCAN_RXGFC_RRFS_Pos      (1U)
4864 #define FDCAN_RXGFC_RRFS_Msk      (0x1UL << FDCAN_RXGFC_RRFS_Pos)              /*!< 0x00000002 */
4865 #define FDCAN_RXGFC_RRFS          FDCAN_RXGFC_RRFS_Msk                         /*!<Reject Remote Frames Standard            */
4866 #define FDCAN_RXGFC_ANFE_Pos      (2U)
4867 #define FDCAN_RXGFC_ANFE_Msk      (0x3UL << FDCAN_RXGFC_ANFE_Pos)              /*!< 0x0000000C */
4868 #define FDCAN_RXGFC_ANFE          FDCAN_RXGFC_ANFE_Msk                         /*!<Accept Non-matching Frames Extended      */
4869 #define FDCAN_RXGFC_ANFS_Pos      (4U)
4870 #define FDCAN_RXGFC_ANFS_Msk      (0x3UL << FDCAN_RXGFC_ANFS_Pos)              /*!< 0x00000030 */
4871 #define FDCAN_RXGFC_ANFS          FDCAN_RXGFC_ANFS_Msk                         /*!<Accept Non-matching Frames Standard      */
4872 #define FDCAN_RXGFC_F1OM_Pos      (8U)
4873 #define FDCAN_RXGFC_F1OM_Msk      (0x1UL << FDCAN_RXGFC_F1OM_Pos)              /*!< 0x00000100 */
4874 #define FDCAN_RXGFC_F1OM          FDCAN_RXGFC_F1OM_Msk                         /*!<FIFO 1 operation mode                    */
4875 #define FDCAN_RXGFC_F0OM_Pos      (9U)
4876 #define FDCAN_RXGFC_F0OM_Msk      (0x1UL << FDCAN_RXGFC_F0OM_Pos)              /*!< 0x00000200 */
4877 #define FDCAN_RXGFC_F0OM          FDCAN_RXGFC_F0OM_Msk                         /*!<FIFO 0 operation mode                    */
4878 #define FDCAN_RXGFC_LSS_Pos       (16U)
4879 #define FDCAN_RXGFC_LSS_Msk       (0x1FUL << FDCAN_RXGFC_LSS_Pos)              /*!< 0x001F0000 */
4880 #define FDCAN_RXGFC_LSS           FDCAN_RXGFC_LSS_Msk                          /*!<List Size Standard                       */
4881 #define FDCAN_RXGFC_LSE_Pos       (24U)
4882 #define FDCAN_RXGFC_LSE_Msk       (0xFUL << FDCAN_RXGFC_LSE_Pos)               /*!< 0x0F000000 */
4883 #define FDCAN_RXGFC_LSE           FDCAN_RXGFC_LSE_Msk                          /*!<List Size Extended                       */
4884 
4885 /*****************  Bit definition for FDCAN_XIDAM register  ********************/
4886 #define FDCAN_XIDAM_EIDM_Pos      (0U)
4887 #define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
4888 #define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                         */
4889 
4890 /*****************  Bit definition for FDCAN_HPMS register  *********************/
4891 #define FDCAN_HPMS_BIDX_Pos       (0U)
4892 #define FDCAN_HPMS_BIDX_Msk       (0x7UL << FDCAN_HPMS_BIDX_Pos)               /*!< 0x00000007 */
4893 #define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                             */
4894 #define FDCAN_HPMS_MSI_Pos        (6U)
4895 #define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
4896 #define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                */
4897 #define FDCAN_HPMS_FIDX_Pos       (8U)
4898 #define FDCAN_HPMS_FIDX_Msk       (0x1FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00001F00 */
4899 #define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                             */
4900 #define FDCAN_HPMS_FLST_Pos       (15U)
4901 #define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
4902 #define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                              */
4903 
4904 /*****************  Bit definition for FDCAN_RXF0S register  ********************/
4905 #define FDCAN_RXF0S_F0FL_Pos      (0U)
4906 #define FDCAN_RXF0S_F0FL_Msk      (0xFUL << FDCAN_RXF0S_F0FL_Pos)              /*!< 0x0000000F */
4907 #define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                     */
4908 #define FDCAN_RXF0S_F0GI_Pos      (8U)
4909 #define FDCAN_RXF0S_F0GI_Msk      (0x3UL << FDCAN_RXF0S_F0GI_Pos)              /*!< 0x00000300 */
4910 #define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                      */
4911 #define FDCAN_RXF0S_F0PI_Pos      (16U)
4912 #define FDCAN_RXF0S_F0PI_Msk      (0x3UL << FDCAN_RXF0S_F0PI_Pos)              /*!< 0x00030000 */
4913 #define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                      */
4914 #define FDCAN_RXF0S_F0F_Pos       (24U)
4915 #define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
4916 #define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                           */
4917 #define FDCAN_RXF0S_RF0L_Pos      (25U)
4918 #define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
4919 #define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                   */
4920 
4921 /*****************  Bit definition for FDCAN_RXF0A register  ********************/
4922 #define FDCAN_RXF0A_F0AI_Pos      (0U)
4923 #define FDCAN_RXF0A_F0AI_Msk      (0x7UL << FDCAN_RXF0A_F0AI_Pos)              /*!< 0x00000007 */
4924 #define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index              */
4925 
4926 /*****************  Bit definition for FDCAN_RXF1S register  ********************/
4927 #define FDCAN_RXF1S_F1FL_Pos      (0U)
4928 #define FDCAN_RXF1S_F1FL_Msk      (0xFUL << FDCAN_RXF1S_F1FL_Pos)              /*!< 0x0000000F */
4929 #define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                     */
4930 #define FDCAN_RXF1S_F1GI_Pos      (8U)
4931 #define FDCAN_RXF1S_F1GI_Msk      (0x3UL << FDCAN_RXF1S_F1GI_Pos)              /*!< 0x00000300 */
4932 #define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                      */
4933 #define FDCAN_RXF1S_F1PI_Pos      (16U)
4934 #define FDCAN_RXF1S_F1PI_Msk      (0x3UL << FDCAN_RXF1S_F1PI_Pos)              /*!< 0x00030000 */
4935 #define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                      */
4936 #define FDCAN_RXF1S_F1F_Pos       (24U)
4937 #define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
4938 #define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                           */
4939 #define FDCAN_RXF1S_RF1L_Pos      (25U)
4940 #define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
4941 #define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                   */
4942 
4943 /*****************  Bit definition for FDCAN_RXF1A register  ********************/
4944 #define FDCAN_RXF1A_F1AI_Pos      (0U)
4945 #define FDCAN_RXF1A_F1AI_Msk      (0x7UL << FDCAN_RXF1A_F1AI_Pos)              /*!< 0x00000007 */
4946 #define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index              */
4947 
4948 /*****************  Bit definition for FDCAN_TXBC register  *********************/
4949 #define FDCAN_TXBC_TFQM_Pos       (24U)
4950 #define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x01000000 */
4951 #define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                       */
4952 
4953 /*****************  Bit definition for FDCAN_TXFQS register  *********************/
4954 #define FDCAN_TXFQS_TFFL_Pos      (0U)
4955 #define FDCAN_TXFQS_TFFL_Msk      (0x7UL << FDCAN_TXFQS_TFFL_Pos)              /*!< 0x00000007 */
4956 #define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                       */
4957 #define FDCAN_TXFQS_TFGI_Pos      (8U)
4958 #define FDCAN_TXFQS_TFGI_Msk      (0x3UL << FDCAN_TXFQS_TFGI_Pos)              /*!< 0x00000300 */
4959 #define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                        */
4960 #define FDCAN_TXFQS_TFQPI_Pos     (16U)
4961 #define FDCAN_TXFQS_TFQPI_Msk     (0x3UL << FDCAN_TXFQS_TFQPI_Pos)             /*!< 0x00030000 */
4962 #define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                  */
4963 #define FDCAN_TXFQS_TFQF_Pos      (21U)
4964 #define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
4965 #define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                       */
4966 
4967 /*****************  Bit definition for FDCAN_TXBRP register  *********************/
4968 #define FDCAN_TXBRP_TRP_Pos       (0U)
4969 #define FDCAN_TXBRP_TRP_Msk       (0x7UL << FDCAN_TXBRP_TRP_Pos)               /*!< 0x00000007 */
4970 #define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending             */
4971 
4972 /*****************  Bit definition for FDCAN_TXBAR register  *********************/
4973 #define FDCAN_TXBAR_AR_Pos        (0U)
4974 #define FDCAN_TXBAR_AR_Msk        (0x7UL << FDCAN_TXBAR_AR_Pos)                /*!< 0x00000007 */
4975 #define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                              */
4976 
4977 /*****************  Bit definition for FDCAN_TXBCR register  *********************/
4978 #define FDCAN_TXBCR_CR_Pos        (0U)
4979 #define FDCAN_TXBCR_CR_Msk        (0x7UL << FDCAN_TXBCR_CR_Pos)                /*!< 0x00000007 */
4980 #define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                     */
4981 
4982 /*****************  Bit definition for FDCAN_TXBTO register  *********************/
4983 #define FDCAN_TXBTO_TO_Pos        (0U)
4984 #define FDCAN_TXBTO_TO_Msk        (0x7UL << FDCAN_TXBTO_TO_Pos)                /*!< 0x00000007 */
4985 #define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                    */
4986 
4987 /*****************  Bit definition for FDCAN_TXBCF register  *********************/
4988 #define FDCAN_TXBCF_CF_Pos        (0U)
4989 #define FDCAN_TXBCF_CF_Msk        (0x7UL << FDCAN_TXBCF_CF_Pos)                /*!< 0x00000007 */
4990 #define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                    */
4991 
4992 /*****************  Bit definition for FDCAN_TXBTIE register  ********************/
4993 #define FDCAN_TXBTIE_TIE_Pos      (0U)
4994 #define FDCAN_TXBTIE_TIE_Msk      (0x7UL << FDCAN_TXBTIE_TIE_Pos)              /*!< 0x00000007 */
4995 #define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable            */
4996 
4997 /*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
4998 #define FDCAN_TXBCIE_CFIE_Pos     (0U)
4999 #define FDCAN_TXBCIE_CFIE_Msk     (0x7UL << FDCAN_TXBCIE_CFIE_Pos)             /*!< 0x00000007 */
5000 #define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable   */
5001 
5002 /*****************  Bit definition for FDCAN_TXEFS register  *********************/
5003 #define FDCAN_TXEFS_EFFL_Pos      (0U)
5004 #define FDCAN_TXEFS_EFFL_Msk      (0x7UL << FDCAN_TXEFS_EFFL_Pos)              /*!< 0x00000007 */
5005 #define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                    */
5006 #define FDCAN_TXEFS_EFGI_Pos      (8U)
5007 #define FDCAN_TXEFS_EFGI_Msk      (0x3UL << FDCAN_TXEFS_EFGI_Pos)              /*!< 0x00000300 */
5008 #define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                     */
5009 #define FDCAN_TXEFS_EFPI_Pos      (16U)
5010 #define FDCAN_TXEFS_EFPI_Msk      (0x3UL << FDCAN_TXEFS_EFPI_Pos)              /*!< 0x00030000 */
5011 #define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                     */
5012 #define FDCAN_TXEFS_EFF_Pos       (24U)
5013 #define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
5014 #define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                          */
5015 #define FDCAN_TXEFS_TEFL_Pos      (25U)
5016 #define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
5017 #define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost               */
5018 
5019 /*****************  Bit definition for FDCAN_TXEFA register  *********************/
5020 #define FDCAN_TXEFA_EFAI_Pos      (0U)
5021 #define FDCAN_TXEFA_EFAI_Msk      (0x3UL << FDCAN_TXEFA_EFAI_Pos)              /*!< 0x00000003 */
5022 #define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index             */
5023 
5024 
5025 /*!<FDCAN config registers */
5026 /*****************  Bit definition for FDCAN_CKDIV register  *********************/
5027 #define FDCAN_CKDIV_PDIV_Pos      (0U)
5028 #define FDCAN_CKDIV_PDIV_Msk      (0xFUL << FDCAN_CKDIV_PDIV_Pos)              /*!< 0x0000000F */
5029 #define FDCAN_CKDIV_PDIV          FDCAN_CKDIV_PDIV_Msk                         /*!<Input Clock Divider                      */
5030 
5031 /******************************************************************************/
5032 /*                                                                            */
5033 /*                                    FLASH                                   */
5034 /*                                                                            */
5035 /******************************************************************************/
5036 /*******************  Bits definition for FLASH_ACR register  *****************/
5037 #define FLASH_ACR_LATENCY_Pos             (0U)
5038 #define FLASH_ACR_LATENCY_Msk             (0xFUL << FLASH_ACR_LATENCY_Pos)     /*!< 0x0000000F */
5039 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
5040 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
5041 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
5042 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
5043 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
5044 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
5045 #define FLASH_ACR_LATENCY_5WS             (0x00000005U)
5046 #define FLASH_ACR_LATENCY_6WS             (0x00000006U)
5047 #define FLASH_ACR_LATENCY_7WS             (0x00000007U)
5048 #define FLASH_ACR_LATENCY_8WS             (0x00000008U)
5049 #define FLASH_ACR_LATENCY_9WS             (0x00000009U)
5050 #define FLASH_ACR_LATENCY_10WS            (0x0000000AU)
5051 #define FLASH_ACR_LATENCY_11WS            (0x0000000BU)
5052 #define FLASH_ACR_LATENCY_12WS            (0x0000000CU)
5053 #define FLASH_ACR_LATENCY_13WS            (0x0000000DU)
5054 #define FLASH_ACR_LATENCY_14WS            (0x0000000EU)
5055 #define FLASH_ACR_LATENCY_15WS            (0x0000000FU)
5056 #define FLASH_ACR_PRFTEN_Pos              (8U)
5057 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
5058 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
5059 #define FLASH_ACR_ICEN_Pos                (9U)
5060 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
5061 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
5062 #define FLASH_ACR_DCEN_Pos                (10U)
5063 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
5064 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
5065 #define FLASH_ACR_ICRST_Pos               (11U)
5066 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
5067 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
5068 #define FLASH_ACR_DCRST_Pos               (12U)
5069 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
5070 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
5071 #define FLASH_ACR_RUN_PD_Pos              (13U)
5072 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
5073 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
5074 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
5075 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
5076 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
5077 #define FLASH_ACR_DBG_SWEN_Pos            (18U)
5078 #define FLASH_ACR_DBG_SWEN_Msk            (0x1UL << FLASH_ACR_DBG_SWEN_Pos)    /*!< 0x00040000 */
5079 #define FLASH_ACR_DBG_SWEN                FLASH_ACR_DBG_SWEN_Msk               /*!< Software disable for debugger */
5080 
5081 /*******************  Bits definition for FLASH_SR register  ******************/
5082 #define FLASH_SR_EOP_Pos                  (0U)
5083 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
5084 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
5085 #define FLASH_SR_OPERR_Pos                (1U)
5086 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
5087 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
5088 #define FLASH_SR_PROGERR_Pos              (3U)
5089 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
5090 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
5091 #define FLASH_SR_WRPERR_Pos               (4U)
5092 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
5093 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
5094 #define FLASH_SR_PGAERR_Pos               (5U)
5095 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
5096 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
5097 #define FLASH_SR_SIZERR_Pos               (6U)
5098 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
5099 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
5100 #define FLASH_SR_PGSERR_Pos               (7U)
5101 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
5102 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
5103 #define FLASH_SR_MISERR_Pos               (8U)
5104 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
5105 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
5106 #define FLASH_SR_FASTERR_Pos              (9U)
5107 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
5108 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
5109 #define FLASH_SR_RDERR_Pos                (14U)
5110 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
5111 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
5112 #define FLASH_SR_OPTVERR_Pos              (15U)
5113 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
5114 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
5115 #define FLASH_SR_BSY_Pos                  (16U)
5116 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
5117 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
5118 
5119 /*******************  Bits definition for FLASH_CR register  ******************/
5120 #define FLASH_CR_PG_Pos                   (0U)
5121 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
5122 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
5123 #define FLASH_CR_PER_Pos                  (1U)
5124 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
5125 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
5126 #define FLASH_CR_MER1_Pos                 (2U)
5127 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
5128 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
5129 #define FLASH_CR_PNB_Pos                  (3U)
5130 #define FLASH_CR_PNB_Msk                  (0x7FUL << FLASH_CR_PNB_Pos)         /*!< 0x000003F8 */
5131 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
5132 #define FLASH_CR_BKER_Pos                 (11U)
5133 #define FLASH_CR_BKER_Msk                 (0x1UL << FLASH_CR_BKER_Pos)         /*!< 0x00000800 */
5134 #define FLASH_CR_BKER                     FLASH_CR_BKER_Msk
5135 #define FLASH_CR_MER2_Pos                 (15U)
5136 #define FLASH_CR_MER2_Msk                 (0x1UL << FLASH_CR_MER2_Pos)         /*!< 0x00008000 */
5137 #define FLASH_CR_MER2                     FLASH_CR_MER2_Msk
5138 #define FLASH_CR_STRT_Pos                 (16U)
5139 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
5140 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
5141 #define FLASH_CR_OPTSTRT_Pos              (17U)
5142 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
5143 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
5144 #define FLASH_CR_FSTPG_Pos                (18U)
5145 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
5146 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
5147 #define FLASH_CR_EOPIE_Pos                (24U)
5148 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
5149 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
5150 #define FLASH_CR_ERRIE_Pos                (25U)
5151 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
5152 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
5153 #define FLASH_CR_RDERRIE_Pos              (26U)
5154 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
5155 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
5156 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
5157 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
5158 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
5159 #define FLASH_CR_SEC_PROT1_Pos            (28U)
5160 #define FLASH_CR_SEC_PROT1_Msk            (0x1UL << FLASH_CR_SEC_PROT1_Pos)    /*!< 0x10000000 */
5161 #define FLASH_CR_SEC_PROT1                FLASH_CR_SEC_PROT1_Msk
5162 #define FLASH_CR_SEC_PROT2_Pos            (29U)
5163 #define FLASH_CR_SEC_PROT2_Msk            (0x1UL << FLASH_CR_SEC_PROT2_Pos)    /*!< 0x20000000 */
5164 #define FLASH_CR_SEC_PROT2                FLASH_CR_SEC_PROT2_Msk
5165 #define FLASH_CR_OPTLOCK_Pos              (30U)
5166 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
5167 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
5168 #define FLASH_CR_LOCK_Pos                 (31U)
5169 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
5170 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
5171 
5172 /*******************  Bits definition for FLASH_ECCR register  ***************/
5173 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
5174 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
5175 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
5176 #define FLASH_ECCR_BK_ECC_Pos             (21U)
5177 #define FLASH_ECCR_BK_ECC_Msk             (0x1UL << FLASH_ECCR_BK_ECC_Pos)     /*!< 0x00200000 */
5178 #define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk
5179 #define FLASH_ECCR_SYSF_ECC_Pos           (22U)
5180 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00400000 */
5181 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
5182 #define FLASH_ECCR_ECCIE_Pos              (24U)
5183 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
5184 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
5185 #define FLASH_ECCR_ECCC2_Pos              (28U)
5186 #define FLASH_ECCR_ECCC2_Msk              (0x1UL << FLASH_ECCR_ECCC2_Pos)      /*!< 0x10000000 */
5187 #define FLASH_ECCR_ECCC2                  FLASH_ECCR_ECCC2_Msk
5188 #define FLASH_ECCR_ECCD2_Pos              (29U)
5189 #define FLASH_ECCR_ECCD2_Msk              (0x1UL << FLASH_ECCR_ECCD2_Pos)      /*!< 0x20000000 */
5190 #define FLASH_ECCR_ECCD2                  FLASH_ECCR_ECCD2_Msk
5191 #define FLASH_ECCR_ECCC_Pos               (30U)
5192 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
5193 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
5194 #define FLASH_ECCR_ECCD_Pos               (31U)
5195 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
5196 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
5197 
5198 /*******************  Bits definition for FLASH_OPTR register  ***************/
5199 #define FLASH_OPTR_RDP_Pos                (0U)
5200 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
5201 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
5202 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
5203 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
5204 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
5205 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
5206 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
5207 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
5208 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
5209 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
5210 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
5211 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
5212 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
5213 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
5214 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
5215 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
5216 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
5217 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
5218 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
5219 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
5220 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
5221 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
5222 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
5223 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
5224 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
5225 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
5226 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
5227 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
5228 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
5229 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
5230 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
5231 #define FLASH_OPTR_BFB2_Pos               (20U)
5232 #define FLASH_OPTR_BFB2_Msk               (0x1UL << FLASH_OPTR_BFB2_Pos)       /*!< 0x00100000 */
5233 #define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk
5234 #define FLASH_OPTR_DBANK_Pos              (22U)
5235 #define FLASH_OPTR_DBANK_Msk              (0x1UL << FLASH_OPTR_DBANK_Pos)      /*!< 0x00400000 */
5236 #define FLASH_OPTR_DBANK                  FLASH_OPTR_DBANK_Msk
5237 #define FLASH_OPTR_nBOOT1_Pos             (23U)
5238 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
5239 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
5240 #define FLASH_OPTR_SRAM_PE_Pos            (24U)
5241 #define FLASH_OPTR_SRAM_PE_Msk            (0x1UL << FLASH_OPTR_SRAM_PE_Pos)    /*!< 0x01000000 */
5242 #define FLASH_OPTR_SRAM_PE                FLASH_OPTR_SRAM_PE_Msk
5243 #define FLASH_OPTR_CCMSRAM_RST_Pos        (25U)
5244 #define FLASH_OPTR_CCMSRAM_RST_Msk        (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
5245 #define FLASH_OPTR_CCMSRAM_RST            FLASH_OPTR_CCMSRAM_RST_Msk
5246 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
5247 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
5248 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
5249 #define FLASH_OPTR_nBOOT0_Pos             (27U)
5250 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
5251 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
5252 #define FLASH_OPTR_NRST_MODE_Pos          (28U)
5253 #define FLASH_OPTR_NRST_MODE_Msk          (0x3UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x30000000 */
5254 #define FLASH_OPTR_NRST_MODE              FLASH_OPTR_NRST_MODE_Msk
5255 #define FLASH_OPTR_NRST_MODE_0            (0x1UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x10000000 */
5256 #define FLASH_OPTR_NRST_MODE_1            (0x2UL << FLASH_OPTR_NRST_MODE_Pos)  /*!< 0x20000000 */
5257 #define FLASH_OPTR_IRHEN_Pos              (30U)
5258 #define FLASH_OPTR_IRHEN_Msk              (0x1UL << FLASH_OPTR_IRHEN_Pos)      /*!< 0x40000000 */
5259 #define FLASH_OPTR_IRHEN                  FLASH_OPTR_IRHEN_Msk
5260 
5261 /******************  Bits definition for FLASH_PCROP1SR register  **********/
5262 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
5263 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
5264 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
5265 
5266 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
5267 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
5268 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
5269 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
5270 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
5271 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
5272 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
5273 
5274 /******************  Bits definition for FLASH_WRP1AR register  ***************/
5275 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
5276 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
5277 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
5278 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
5279 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
5280 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
5281 
5282 /******************  Bits definition for FLASH_WRPB1R register  ***************/
5283 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
5284 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
5285 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
5286 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
5287 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5288 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
5289 
5290 /******************  Bits definition for FLASH_PCROP2SR register  **********/
5291 #define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)
5292 #define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
5293 #define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk
5294 
5295 /******************  Bits definition for FLASH_PCROP2ER register  ***********/
5296 #define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)
5297 #define FLASH_PCROP2ER_PCROP2_END_Msk     (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
5298 #define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk
5299 
5300 /******************  Bits definition for FLASH_WRP2AR register  ***************/
5301 #define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)
5302 #define FLASH_WRP2AR_WRP2A_STRT_Msk       (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
5303 #define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk
5304 #define FLASH_WRP2AR_WRP2A_END_Pos        (16U)
5305 #define FLASH_WRP2AR_WRP2A_END_Msk        (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
5306 #define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk
5307 
5308 /******************  Bits definition for FLASH_WRP2BR register  ***************/
5309 #define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)
5310 #define FLASH_WRP2BR_WRP2B_STRT_Msk       (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
5311 #define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk
5312 #define FLASH_WRP2BR_WRP2B_END_Pos        (16U)
5313 #define FLASH_WRP2BR_WRP2B_END_Msk        (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
5314 #define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk
5315 
5316 /******************  Bits definition for FLASH_SEC1R register  **************/
5317 #define FLASH_SEC1R_SEC_SIZE1_Pos         (0U)
5318 #define FLASH_SEC1R_SEC_SIZE1_Msk         (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5319 #define FLASH_SEC1R_SEC_SIZE1             FLASH_SEC1R_SEC_SIZE1_Msk
5320 #define FLASH_SEC1R_BOOT_LOCK_Pos         (16U)
5321 #define FLASH_SEC1R_BOOT_LOCK_Msk         (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5322 #define FLASH_SEC1R_BOOT_LOCK             FLASH_SEC1R_BOOT_LOCK_Msk
5323 
5324 /******************  Bits definition for FLASH_SEC2R register  **************/
5325 #define FLASH_SEC2R_SEC_SIZE2_Pos         (0U)
5326 #define FLASH_SEC2R_SEC_SIZE2_Msk         (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
5327 #define FLASH_SEC2R_SEC_SIZE2             FLASH_SEC2R_SEC_SIZE2_Msk
5328 
5329 /******************************************************************************/
5330 /*                                                                            */
5331 /*                Filter Mathematical ACcelerator unit (FMAC)                 */
5332 /*                                                                            */
5333 /******************************************************************************/
5334 /*****************  Bit definition for FMAC_X1BUFCFG register  ****************/
5335 #define FMAC_X1BUFCFG_X1_BASE_Pos     (0U)
5336 #define FMAC_X1BUFCFG_X1_BASE_Msk     (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)    /*!< 0x000000FF */
5337 #define FMAC_X1BUFCFG_X1_BASE         FMAC_X1BUFCFG_X1_BASE_Msk                /*!< Base address of X1 buffer */
5338 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5339 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5340 #define FMAC_X1BUFCFG_X1_BUF_SIZE     FMAC_X1BUFCFG_X1_BUF_SIZE_Msk            /*!< Allocated size of X1 buffer in 16-bit words */
5341 #define FMAC_X1BUFCFG_FULL_WM_Pos     (24U)
5342 #define FMAC_X1BUFCFG_FULL_WM_Msk     (0x3UL  << FMAC_X1BUFCFG_FULL_WM_Pos)    /*!< 0x03000000 */
5343 #define FMAC_X1BUFCFG_FULL_WM         FMAC_X1BUFCFG_FULL_WM_Msk                /*!< Watermark for buffer full flag */
5344 /*****************  Bit definition for FMAC_X2BUFCFG register  ****************/
5345 #define FMAC_X2BUFCFG_X2_BASE_Pos     (0U)
5346 #define FMAC_X2BUFCFG_X2_BASE_Msk     (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)    /*!< 0x000000FF */
5347 #define FMAC_X2BUFCFG_X2_BASE         FMAC_X2BUFCFG_X2_BASE_Msk                /*!< Base address of X2 buffer */
5348 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5349 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5350 #define FMAC_X2BUFCFG_X2_BUF_SIZE     FMAC_X2BUFCFG_X2_BUF_SIZE_Msk            /*!< Size of X2 buffer in 16-bit words */
5351 /*****************  Bit definition for FMAC_YBUFCFG register  *****************/
5352 #define FMAC_YBUFCFG_Y_BASE_Pos       (0U)
5353 #define FMAC_YBUFCFG_Y_BASE_Msk       (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)      /*!< 0x000000FF */
5354 #define FMAC_YBUFCFG_Y_BASE           FMAC_YBUFCFG_Y_BASE_Msk                  /*!< Base address of Y buffer */
5355 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos   (8U)
5356 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk   (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)  /*!< 0x0000FF00 */
5357 #define FMAC_YBUFCFG_Y_BUF_SIZE       FMAC_YBUFCFG_Y_BUF_SIZE_Msk              /*!< Size of Y buffer in 16-bit words */
5358 #define FMAC_YBUFCFG_EMPTY_WM_Pos     (24U)
5359 #define FMAC_YBUFCFG_EMPTY_WM_Msk     (0x3UL  << FMAC_YBUFCFG_EMPTY_WM_Pos)    /*!< 0x03000000 */
5360 #define FMAC_YBUFCFG_EMPTY_WM         FMAC_YBUFCFG_EMPTY_WM_Msk                /*!< Watermark for buffer empty flag */
5361 /******************  Bit definition for FMAC_PARAM register  ******************/
5362 #define FMAC_PARAM_P_Pos              (0U)
5363 #define FMAC_PARAM_P_Msk              (0xFFUL << FMAC_PARAM_P_Pos)             /*!< 0x000000FF */
5364 #define FMAC_PARAM_P                  FMAC_PARAM_P_Msk                         /*!< Input parameter P */
5365 #define FMAC_PARAM_Q_Pos              (8U)
5366 #define FMAC_PARAM_Q_Msk              (0xFFUL << FMAC_PARAM_Q_Pos)             /*!< 0x0000FF00 */
5367 #define FMAC_PARAM_Q                  FMAC_PARAM_Q_Msk                         /*!< Input parameter Q */
5368 #define FMAC_PARAM_R_Pos              (16U)
5369 #define FMAC_PARAM_R_Msk              (0xFFUL << FMAC_PARAM_R_Pos)             /*!< 0x00FF0000 */
5370 #define FMAC_PARAM_R                  FMAC_PARAM_R_Msk                         /*!< Input parameter R */
5371 #define FMAC_PARAM_FUNC_Pos           (24U)
5372 #define FMAC_PARAM_FUNC_Msk           (0x7FUL << FMAC_PARAM_FUNC_Pos)          /*!< 0x7F000000 */
5373 #define FMAC_PARAM_FUNC               FMAC_PARAM_FUNC_Msk                      /*!< Function */
5374 #define FMAC_PARAM_FUNC_0             (0x1UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x01000000 */
5375 #define FMAC_PARAM_FUNC_1             (0x2UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x02000000 */
5376 #define FMAC_PARAM_FUNC_2             (0x4UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x04000000 */
5377 #define FMAC_PARAM_FUNC_3             (0x8UL  << FMAC_PARAM_FUNC_Pos)          /*!< 0x08000000 */
5378 #define FMAC_PARAM_FUNC_4             (0x10UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x10000000 */
5379 #define FMAC_PARAM_FUNC_5             (0x20UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x20000000 */
5380 #define FMAC_PARAM_FUNC_6             (0x40UL << FMAC_PARAM_FUNC_Pos)          /*!< 0x40000000 */
5381 #define FMAC_PARAM_START_Pos          (31U)
5382 #define FMAC_PARAM_START_Msk          (0x1UL  << FMAC_PARAM_START_Pos)         /*!< 0x80000000 */
5383 #define FMAC_PARAM_START              FMAC_PARAM_START_Msk                     /*!< Enable execution */
5384 /********************  Bit definition for FMAC_CR register  *******************/
5385 #define FMAC_CR_RIEN_Pos              (0U)
5386 #define FMAC_CR_RIEN_Msk              (0x1UL  << FMAC_CR_RIEN_Pos)             /*!< 0x00000001 */
5387 #define FMAC_CR_RIEN                  FMAC_CR_RIEN_Msk                         /*!< Enable read interrupt */
5388 #define FMAC_CR_WIEN_Pos              (1U)
5389 #define FMAC_CR_WIEN_Msk              (0x1UL  << FMAC_CR_WIEN_Pos)             /*!< 0x00000002 */
5390 #define FMAC_CR_WIEN                  FMAC_CR_WIEN_Msk                         /*!< Enable write interrupt */
5391 #define FMAC_CR_OVFLIEN_Pos           (2U)
5392 #define FMAC_CR_OVFLIEN_Msk           (0x1UL  << FMAC_CR_OVFLIEN_Pos)          /*!< 0x00000004 */
5393 #define FMAC_CR_OVFLIEN               FMAC_CR_OVFLIEN_Msk                      /*!< Enable overflow error interrupts */
5394 #define FMAC_CR_UNFLIEN_Pos           (3U)
5395 #define FMAC_CR_UNFLIEN_Msk           (0x1UL  << FMAC_CR_UNFLIEN_Pos)          /*!< 0x00000008 */
5396 #define FMAC_CR_UNFLIEN               FMAC_CR_UNFLIEN_Msk                      /*!< Enable underflow error interrupts */
5397 #define FMAC_CR_SATIEN_Pos            (4U)
5398 #define FMAC_CR_SATIEN_Msk            (0x1UL  << FMAC_CR_SATIEN_Pos)           /*!< 0x00000010 */
5399 #define FMAC_CR_SATIEN                FMAC_CR_SATIEN_Msk                       /*!< Enable saturation error interrupts */
5400 #define FMAC_CR_DMAREN_Pos            (8U)
5401 #define FMAC_CR_DMAREN_Msk            (0x1UL  << FMAC_CR_DMAREN_Pos)           /*!< 0x00000100 */
5402 #define FMAC_CR_DMAREN                FMAC_CR_DMAREN_Msk                       /*!< Enable DMA read channel requests */
5403 #define FMAC_CR_DMAWEN_Pos            (9U)
5404 #define FMAC_CR_DMAWEN_Msk            (0x1UL  << FMAC_CR_DMAWEN_Pos)           /*!< 0x00000200 */
5405 #define FMAC_CR_DMAWEN                FMAC_CR_DMAWEN_Msk                       /*!< Enable DMA write channel requests */
5406 #define FMAC_CR_CLIPEN_Pos            (15U)
5407 #define FMAC_CR_CLIPEN_Msk            (0x1UL  << FMAC_CR_CLIPEN_Pos)           /*!< 0x00008000 */
5408 #define FMAC_CR_CLIPEN                FMAC_CR_CLIPEN_Msk                       /*!< Enable clipping */
5409 #define FMAC_CR_RESET_Pos             (16U)
5410 #define FMAC_CR_RESET_Msk             (0x1UL  << FMAC_CR_RESET_Pos)            /*!< 0x00010000 */
5411 #define FMAC_CR_RESET                 FMAC_CR_RESET_Msk                        /*!< Reset filter mathematical accelerator unit */
5412 /*******************  Bit definition for FMAC_SR register  ********************/
5413 #define FMAC_SR_YEMPTY_Pos            (0U)
5414 #define FMAC_SR_YEMPTY_Msk            (0x1UL  << FMAC_SR_YEMPTY_Pos)           /*!< 0x00000001 */
5415 #define FMAC_SR_YEMPTY                FMAC_SR_YEMPTY_Msk                       /*!< Y buffer empty flag */
5416 #define FMAC_SR_X1FULL_Pos            (1U)
5417 #define FMAC_SR_X1FULL_Msk            (0x1UL  << FMAC_SR_X1FULL_Pos)           /*!< 0x00000002 */
5418 #define FMAC_SR_X1FULL                FMAC_SR_X1FULL_Msk                       /*!< X1 buffer full flag */
5419 #define FMAC_SR_OVFL_Pos              (8U)
5420 #define FMAC_SR_OVFL_Msk              (0x1UL  << FMAC_SR_OVFL_Pos)             /*!< 0x00000100 */
5421 #define FMAC_SR_OVFL                  FMAC_SR_OVFL_Msk                         /*!< Overflow error flag */
5422 #define FMAC_SR_UNFL_Pos              (9U)
5423 #define FMAC_SR_UNFL_Msk              (0x1UL  << FMAC_SR_UNFL_Pos)             /*!< 0x00000200 */
5424 #define FMAC_SR_UNFL                  FMAC_SR_UNFL_Msk                         /*!< Underflow error flag */
5425 #define FMAC_SR_SAT_Pos               (10U)
5426 #define FMAC_SR_SAT_Msk               (0x1UL  << FMAC_SR_SAT_Pos)              /*!< 0x00000400 */
5427 #define FMAC_SR_SAT                   FMAC_SR_SAT_Msk                          /*!< Saturation error flag */
5428 /******************  Bit definition for FMAC_WDATA register  ******************/
5429 #define FMAC_WDATA_WDATA_Pos          (0U)
5430 #define FMAC_WDATA_WDATA_Msk          (0xFFFFUL << FMAC_WDATA_WDATA_Pos)       /*!< 0x0000FFFF */
5431 #define FMAC_WDATA_WDATA              FMAC_WDATA_WDATA_Msk                     /*!< Write data */
5432 /******************  Bit definition for FMACX_RDATA register  *****************/
5433 #define FMAC_RDATA_RDATA_Pos          (0U)
5434 #define FMAC_RDATA_RDATA_Msk          (0xFFFFUL << FMAC_RDATA_RDATA_Pos)       /*!< 0x0000FFFF */
5435 #define FMAC_RDATA_RDATA              FMAC_RDATA_RDATA_Msk                     /*!< Read data */
5436 
5437 
5438 /******************************************************************************/
5439 /*                                                                            */
5440 /*                       General Purpose IOs (GPIO)                           */
5441 /*                                                                            */
5442 /******************************************************************************/
5443 /******************  Bits definition for GPIO_MODER register  *****************/
5444 #define GPIO_MODER_MODE0_Pos           (0U)
5445 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
5446 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
5447 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
5448 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
5449 #define GPIO_MODER_MODE1_Pos           (2U)
5450 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
5451 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
5452 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
5453 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
5454 #define GPIO_MODER_MODE2_Pos           (4U)
5455 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
5456 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
5457 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
5458 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
5459 #define GPIO_MODER_MODE3_Pos           (6U)
5460 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
5461 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
5462 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
5463 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
5464 #define GPIO_MODER_MODE4_Pos           (8U)
5465 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
5466 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
5467 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
5468 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
5469 #define GPIO_MODER_MODE5_Pos           (10U)
5470 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
5471 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
5472 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
5473 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
5474 #define GPIO_MODER_MODE6_Pos           (12U)
5475 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
5476 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
5477 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
5478 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
5479 #define GPIO_MODER_MODE7_Pos           (14U)
5480 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
5481 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
5482 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
5483 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
5484 #define GPIO_MODER_MODE8_Pos           (16U)
5485 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
5486 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
5487 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
5488 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
5489 #define GPIO_MODER_MODE9_Pos           (18U)
5490 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
5491 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
5492 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
5493 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
5494 #define GPIO_MODER_MODE10_Pos          (20U)
5495 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
5496 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
5497 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
5498 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
5499 #define GPIO_MODER_MODE11_Pos          (22U)
5500 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
5501 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
5502 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
5503 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
5504 #define GPIO_MODER_MODE12_Pos          (24U)
5505 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
5506 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
5507 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
5508 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
5509 #define GPIO_MODER_MODE13_Pos          (26U)
5510 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
5511 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
5512 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
5513 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
5514 #define GPIO_MODER_MODE14_Pos          (28U)
5515 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
5516 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
5517 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
5518 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
5519 #define GPIO_MODER_MODE15_Pos          (30U)
5520 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
5521 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
5522 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
5523 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
5524 
5525 /* Legacy defines */
5526 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
5527 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
5528 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
5529 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
5530 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
5531 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
5532 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
5533 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
5534 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
5535 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
5536 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
5537 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
5538 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
5539 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
5540 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
5541 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
5542 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
5543 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
5544 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
5545 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
5546 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
5547 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
5548 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
5549 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
5550 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
5551 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
5552 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
5553 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
5554 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
5555 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
5556 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
5557 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
5558 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
5559 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
5560 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
5561 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
5562 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
5563 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
5564 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
5565 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
5566 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
5567 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
5568 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
5569 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
5570 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
5571 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
5572 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
5573 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
5574 
5575 /******************  Bits definition for GPIO_OTYPER register  ****************/
5576 #define GPIO_OTYPER_OT0_Pos            (0U)
5577 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
5578 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
5579 #define GPIO_OTYPER_OT1_Pos            (1U)
5580 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
5581 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
5582 #define GPIO_OTYPER_OT2_Pos            (2U)
5583 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
5584 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
5585 #define GPIO_OTYPER_OT3_Pos            (3U)
5586 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
5587 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
5588 #define GPIO_OTYPER_OT4_Pos            (4U)
5589 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
5590 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
5591 #define GPIO_OTYPER_OT5_Pos            (5U)
5592 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
5593 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
5594 #define GPIO_OTYPER_OT6_Pos            (6U)
5595 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
5596 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
5597 #define GPIO_OTYPER_OT7_Pos            (7U)
5598 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
5599 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
5600 #define GPIO_OTYPER_OT8_Pos            (8U)
5601 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
5602 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
5603 #define GPIO_OTYPER_OT9_Pos            (9U)
5604 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
5605 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
5606 #define GPIO_OTYPER_OT10_Pos           (10U)
5607 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
5608 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
5609 #define GPIO_OTYPER_OT11_Pos           (11U)
5610 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
5611 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
5612 #define GPIO_OTYPER_OT12_Pos           (12U)
5613 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
5614 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
5615 #define GPIO_OTYPER_OT13_Pos           (13U)
5616 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
5617 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
5618 #define GPIO_OTYPER_OT14_Pos           (14U)
5619 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
5620 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
5621 #define GPIO_OTYPER_OT15_Pos           (15U)
5622 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
5623 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
5624 
5625 /* Legacy defines */
5626 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
5627 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
5628 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
5629 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
5630 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
5631 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
5632 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
5633 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
5634 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
5635 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
5636 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
5637 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
5638 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
5639 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
5640 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
5641 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
5642 
5643 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
5644 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
5645 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
5646 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
5647 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
5648 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
5649 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
5650 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
5651 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
5652 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
5653 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
5654 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
5655 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
5656 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
5657 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
5658 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
5659 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
5660 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
5661 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
5662 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
5663 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
5664 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
5665 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
5666 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
5667 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
5668 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
5669 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
5670 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
5671 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
5672 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
5673 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
5674 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
5675 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
5676 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
5677 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
5678 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
5679 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
5680 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
5681 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
5682 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
5683 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
5684 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
5685 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
5686 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
5687 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
5688 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
5689 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
5690 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
5691 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
5692 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
5693 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
5694 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
5695 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
5696 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
5697 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
5698 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
5699 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
5700 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
5701 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
5702 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
5703 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
5704 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
5705 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
5706 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
5707 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
5708 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
5709 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
5710 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
5711 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
5712 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
5713 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
5714 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
5715 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
5716 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
5717 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
5718 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
5719 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
5720 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
5721 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
5722 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
5723 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
5724 
5725 /* Legacy defines */
5726 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
5727 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
5728 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
5729 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
5730 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
5731 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
5732 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
5733 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
5734 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
5735 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
5736 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
5737 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
5738 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
5739 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
5740 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
5741 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
5742 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
5743 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
5744 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
5745 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
5746 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
5747 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
5748 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
5749 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
5750 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
5751 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
5752 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
5753 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
5754 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
5755 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
5756 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
5757 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
5758 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
5759 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
5760 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
5761 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
5762 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
5763 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
5764 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
5765 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
5766 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
5767 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
5768 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
5769 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
5770 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
5771 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
5772 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
5773 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
5774 
5775 /******************  Bits definition for GPIO_PUPDR register  *****************/
5776 #define GPIO_PUPDR_PUPD0_Pos           (0U)
5777 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
5778 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
5779 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
5780 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
5781 #define GPIO_PUPDR_PUPD1_Pos           (2U)
5782 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
5783 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
5784 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
5785 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
5786 #define GPIO_PUPDR_PUPD2_Pos           (4U)
5787 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
5788 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
5789 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
5790 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
5791 #define GPIO_PUPDR_PUPD3_Pos           (6U)
5792 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
5793 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
5794 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
5795 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
5796 #define GPIO_PUPDR_PUPD4_Pos           (8U)
5797 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
5798 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
5799 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
5800 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
5801 #define GPIO_PUPDR_PUPD5_Pos           (10U)
5802 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
5803 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
5804 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
5805 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
5806 #define GPIO_PUPDR_PUPD6_Pos           (12U)
5807 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
5808 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
5809 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
5810 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
5811 #define GPIO_PUPDR_PUPD7_Pos           (14U)
5812 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
5813 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
5814 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
5815 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
5816 #define GPIO_PUPDR_PUPD8_Pos           (16U)
5817 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
5818 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
5819 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
5820 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
5821 #define GPIO_PUPDR_PUPD9_Pos           (18U)
5822 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
5823 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
5824 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
5825 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
5826 #define GPIO_PUPDR_PUPD10_Pos          (20U)
5827 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
5828 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
5829 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
5830 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
5831 #define GPIO_PUPDR_PUPD11_Pos          (22U)
5832 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
5833 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
5834 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
5835 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
5836 #define GPIO_PUPDR_PUPD12_Pos          (24U)
5837 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
5838 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
5839 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
5840 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
5841 #define GPIO_PUPDR_PUPD13_Pos          (26U)
5842 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
5843 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
5844 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
5845 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
5846 #define GPIO_PUPDR_PUPD14_Pos          (28U)
5847 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
5848 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
5849 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
5850 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
5851 #define GPIO_PUPDR_PUPD15_Pos          (30U)
5852 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
5853 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
5854 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
5855 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
5856 
5857 /* Legacy defines */
5858 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
5859 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
5860 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
5861 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
5862 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
5863 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
5864 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
5865 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
5866 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
5867 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
5868 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
5869 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
5870 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
5871 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
5872 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
5873 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
5874 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
5875 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
5876 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
5877 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
5878 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
5879 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
5880 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
5881 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
5882 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
5883 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
5884 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
5885 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
5886 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
5887 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
5888 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
5889 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
5890 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
5891 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
5892 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
5893 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
5894 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
5895 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
5896 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
5897 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
5898 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
5899 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
5900 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
5901 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
5902 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
5903 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
5904 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
5905 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
5906 
5907 /******************  Bits definition for GPIO_IDR register  *******************/
5908 #define GPIO_IDR_ID0_Pos               (0U)
5909 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
5910 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
5911 #define GPIO_IDR_ID1_Pos               (1U)
5912 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
5913 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
5914 #define GPIO_IDR_ID2_Pos               (2U)
5915 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
5916 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
5917 #define GPIO_IDR_ID3_Pos               (3U)
5918 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
5919 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
5920 #define GPIO_IDR_ID4_Pos               (4U)
5921 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
5922 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
5923 #define GPIO_IDR_ID5_Pos               (5U)
5924 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
5925 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
5926 #define GPIO_IDR_ID6_Pos               (6U)
5927 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
5928 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
5929 #define GPIO_IDR_ID7_Pos               (7U)
5930 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
5931 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
5932 #define GPIO_IDR_ID8_Pos               (8U)
5933 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
5934 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
5935 #define GPIO_IDR_ID9_Pos               (9U)
5936 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
5937 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
5938 #define GPIO_IDR_ID10_Pos              (10U)
5939 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
5940 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
5941 #define GPIO_IDR_ID11_Pos              (11U)
5942 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
5943 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
5944 #define GPIO_IDR_ID12_Pos              (12U)
5945 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
5946 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
5947 #define GPIO_IDR_ID13_Pos              (13U)
5948 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
5949 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
5950 #define GPIO_IDR_ID14_Pos              (14U)
5951 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
5952 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
5953 #define GPIO_IDR_ID15_Pos              (15U)
5954 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
5955 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
5956 
5957 /* Legacy defines */
5958 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
5959 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
5960 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
5961 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
5962 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
5963 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
5964 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
5965 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
5966 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
5967 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
5968 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
5969 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
5970 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
5971 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
5972 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
5973 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
5974 
5975 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5976 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
5977 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
5978 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
5979 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
5980 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
5981 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
5982 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
5983 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
5984 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
5985 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
5986 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
5987 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
5988 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
5989 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
5990 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
5991 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
5992 
5993 /******************  Bits definition for GPIO_ODR register  *******************/
5994 #define GPIO_ODR_OD0_Pos               (0U)
5995 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
5996 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
5997 #define GPIO_ODR_OD1_Pos               (1U)
5998 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
5999 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
6000 #define GPIO_ODR_OD2_Pos               (2U)
6001 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
6002 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
6003 #define GPIO_ODR_OD3_Pos               (3U)
6004 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
6005 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
6006 #define GPIO_ODR_OD4_Pos               (4U)
6007 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
6008 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
6009 #define GPIO_ODR_OD5_Pos               (5U)
6010 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
6011 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
6012 #define GPIO_ODR_OD6_Pos               (6U)
6013 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
6014 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
6015 #define GPIO_ODR_OD7_Pos               (7U)
6016 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
6017 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
6018 #define GPIO_ODR_OD8_Pos               (8U)
6019 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
6020 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
6021 #define GPIO_ODR_OD9_Pos               (9U)
6022 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
6023 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
6024 #define GPIO_ODR_OD10_Pos              (10U)
6025 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
6026 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
6027 #define GPIO_ODR_OD11_Pos              (11U)
6028 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
6029 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
6030 #define GPIO_ODR_OD12_Pos              (12U)
6031 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
6032 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
6033 #define GPIO_ODR_OD13_Pos              (13U)
6034 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
6035 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
6036 #define GPIO_ODR_OD14_Pos              (14U)
6037 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
6038 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
6039 #define GPIO_ODR_OD15_Pos              (15U)
6040 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
6041 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
6042 
6043 /* Legacy defines */
6044 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
6045 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
6046 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
6047 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
6048 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
6049 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
6050 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
6051 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
6052 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
6053 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
6054 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
6055 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
6056 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
6057 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
6058 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
6059 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
6060 
6061 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
6062 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
6063 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
6064 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
6065 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
6066 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
6067 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
6068 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
6069 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
6070 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
6071 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
6072 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
6073 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
6074 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
6075 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
6076 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
6077 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
6078 
6079 /******************  Bits definition for GPIO_BSRR register  ******************/
6080 #define GPIO_BSRR_BS0_Pos              (0U)
6081 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
6082 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
6083 #define GPIO_BSRR_BS1_Pos              (1U)
6084 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
6085 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
6086 #define GPIO_BSRR_BS2_Pos              (2U)
6087 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
6088 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
6089 #define GPIO_BSRR_BS3_Pos              (3U)
6090 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
6091 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
6092 #define GPIO_BSRR_BS4_Pos              (4U)
6093 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
6094 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
6095 #define GPIO_BSRR_BS5_Pos              (5U)
6096 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
6097 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
6098 #define GPIO_BSRR_BS6_Pos              (6U)
6099 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
6100 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
6101 #define GPIO_BSRR_BS7_Pos              (7U)
6102 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
6103 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
6104 #define GPIO_BSRR_BS8_Pos              (8U)
6105 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
6106 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
6107 #define GPIO_BSRR_BS9_Pos              (9U)
6108 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
6109 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
6110 #define GPIO_BSRR_BS10_Pos             (10U)
6111 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
6112 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
6113 #define GPIO_BSRR_BS11_Pos             (11U)
6114 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
6115 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
6116 #define GPIO_BSRR_BS12_Pos             (12U)
6117 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
6118 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
6119 #define GPIO_BSRR_BS13_Pos             (13U)
6120 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
6121 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
6122 #define GPIO_BSRR_BS14_Pos             (14U)
6123 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
6124 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
6125 #define GPIO_BSRR_BS15_Pos             (15U)
6126 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
6127 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
6128 #define GPIO_BSRR_BR0_Pos              (16U)
6129 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
6130 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
6131 #define GPIO_BSRR_BR1_Pos              (17U)
6132 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
6133 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
6134 #define GPIO_BSRR_BR2_Pos              (18U)
6135 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
6136 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
6137 #define GPIO_BSRR_BR3_Pos              (19U)
6138 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
6139 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
6140 #define GPIO_BSRR_BR4_Pos              (20U)
6141 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
6142 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
6143 #define GPIO_BSRR_BR5_Pos              (21U)
6144 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
6145 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
6146 #define GPIO_BSRR_BR6_Pos              (22U)
6147 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
6148 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
6149 #define GPIO_BSRR_BR7_Pos              (23U)
6150 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
6151 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
6152 #define GPIO_BSRR_BR8_Pos              (24U)
6153 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
6154 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
6155 #define GPIO_BSRR_BR9_Pos              (25U)
6156 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
6157 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
6158 #define GPIO_BSRR_BR10_Pos             (26U)
6159 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
6160 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
6161 #define GPIO_BSRR_BR11_Pos             (27U)
6162 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
6163 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
6164 #define GPIO_BSRR_BR12_Pos             (28U)
6165 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
6166 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
6167 #define GPIO_BSRR_BR13_Pos             (29U)
6168 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
6169 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
6170 #define GPIO_BSRR_BR14_Pos             (30U)
6171 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
6172 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
6173 #define GPIO_BSRR_BR15_Pos             (31U)
6174 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
6175 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
6176 
6177 /* Legacy defines */
6178 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
6179 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
6180 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
6181 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
6182 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
6183 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
6184 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
6185 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
6186 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
6187 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
6188 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
6189 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
6190 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
6191 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
6192 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
6193 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
6194 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
6195 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
6196 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
6197 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
6198 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
6199 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
6200 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
6201 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
6202 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
6203 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
6204 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
6205 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
6206 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
6207 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
6208 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
6209 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
6210 
6211 /****************** Bit definition for GPIO_LCKR register *********************/
6212 #define GPIO_LCKR_LCK0_Pos             (0U)
6213 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6214 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
6215 #define GPIO_LCKR_LCK1_Pos             (1U)
6216 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6217 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
6218 #define GPIO_LCKR_LCK2_Pos             (2U)
6219 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6220 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
6221 #define GPIO_LCKR_LCK3_Pos             (3U)
6222 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6223 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
6224 #define GPIO_LCKR_LCK4_Pos             (4U)
6225 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6226 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
6227 #define GPIO_LCKR_LCK5_Pos             (5U)
6228 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6229 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
6230 #define GPIO_LCKR_LCK6_Pos             (6U)
6231 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6232 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
6233 #define GPIO_LCKR_LCK7_Pos             (7U)
6234 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6235 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
6236 #define GPIO_LCKR_LCK8_Pos             (8U)
6237 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6238 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
6239 #define GPIO_LCKR_LCK9_Pos             (9U)
6240 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6241 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
6242 #define GPIO_LCKR_LCK10_Pos            (10U)
6243 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6244 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
6245 #define GPIO_LCKR_LCK11_Pos            (11U)
6246 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6247 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
6248 #define GPIO_LCKR_LCK12_Pos            (12U)
6249 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6250 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
6251 #define GPIO_LCKR_LCK13_Pos            (13U)
6252 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6253 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
6254 #define GPIO_LCKR_LCK14_Pos            (14U)
6255 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6256 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
6257 #define GPIO_LCKR_LCK15_Pos            (15U)
6258 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6259 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
6260 #define GPIO_LCKR_LCKK_Pos             (16U)
6261 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6262 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
6263 
6264 /****************** Bit definition for GPIO_AFRL register *********************/
6265 #define GPIO_AFRL_AFSEL0_Pos           (0U)
6266 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6267 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
6268 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6269 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6270 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6271 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6272 #define GPIO_AFRL_AFSEL1_Pos           (4U)
6273 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6274 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
6275 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6276 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6277 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6278 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6279 #define GPIO_AFRL_AFSEL2_Pos           (8U)
6280 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6281 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
6282 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6283 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6284 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6285 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6286 #define GPIO_AFRL_AFSEL3_Pos           (12U)
6287 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6288 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
6289 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6290 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6291 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6292 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6293 #define GPIO_AFRL_AFSEL4_Pos           (16U)
6294 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6295 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
6296 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6297 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6298 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6299 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6300 #define GPIO_AFRL_AFSEL5_Pos           (20U)
6301 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6302 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
6303 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6304 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6305 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6306 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6307 #define GPIO_AFRL_AFSEL6_Pos           (24U)
6308 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6309 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
6310 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6311 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6312 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6313 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6314 #define GPIO_AFRL_AFSEL7_Pos           (28U)
6315 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6316 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
6317 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6318 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6319 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6320 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6321 
6322 /* Legacy defines */
6323 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
6324 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
6325 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
6326 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
6327 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
6328 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
6329 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
6330 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
6331 
6332 /****************** Bit definition for GPIO_AFRH register *********************/
6333 #define GPIO_AFRH_AFSEL8_Pos           (0U)
6334 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6335 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
6336 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6337 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6338 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6339 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6340 #define GPIO_AFRH_AFSEL9_Pos           (4U)
6341 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6342 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
6343 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6344 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6345 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6346 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6347 #define GPIO_AFRH_AFSEL10_Pos          (8U)
6348 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6349 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
6350 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6351 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6352 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6353 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6354 #define GPIO_AFRH_AFSEL11_Pos          (12U)
6355 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6356 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
6357 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6358 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6359 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6360 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6361 #define GPIO_AFRH_AFSEL12_Pos          (16U)
6362 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6363 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
6364 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6365 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6366 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6367 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6368 #define GPIO_AFRH_AFSEL13_Pos          (20U)
6369 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6370 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
6371 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6372 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6373 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6374 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6375 #define GPIO_AFRH_AFSEL14_Pos          (24U)
6376 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6377 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
6378 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6379 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6380 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6381 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6382 #define GPIO_AFRH_AFSEL15_Pos          (28U)
6383 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6384 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
6385 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6386 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6387 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6388 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6389 
6390 /* Legacy defines */
6391 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
6392 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
6393 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
6394 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
6395 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
6396 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
6397 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
6398 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
6399 
6400 /******************  Bits definition for GPIO_BRR register  ******************/
6401 #define GPIO_BRR_BR0_Pos               (0U)
6402 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6403 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
6404 #define GPIO_BRR_BR1_Pos               (1U)
6405 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6406 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
6407 #define GPIO_BRR_BR2_Pos               (2U)
6408 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6409 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
6410 #define GPIO_BRR_BR3_Pos               (3U)
6411 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6412 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
6413 #define GPIO_BRR_BR4_Pos               (4U)
6414 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6415 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
6416 #define GPIO_BRR_BR5_Pos               (5U)
6417 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6418 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
6419 #define GPIO_BRR_BR6_Pos               (6U)
6420 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6421 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
6422 #define GPIO_BRR_BR7_Pos               (7U)
6423 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6424 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
6425 #define GPIO_BRR_BR8_Pos               (8U)
6426 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6427 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
6428 #define GPIO_BRR_BR9_Pos               (9U)
6429 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6430 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
6431 #define GPIO_BRR_BR10_Pos              (10U)
6432 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6433 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
6434 #define GPIO_BRR_BR11_Pos              (11U)
6435 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6436 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
6437 #define GPIO_BRR_BR12_Pos              (12U)
6438 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6439 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
6440 #define GPIO_BRR_BR13_Pos              (13U)
6441 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6442 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
6443 #define GPIO_BRR_BR14_Pos              (14U)
6444 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6445 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
6446 #define GPIO_BRR_BR15_Pos              (15U)
6447 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6448 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
6449 
6450 /* Legacy defines */
6451 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
6452 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
6453 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
6454 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
6455 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
6456 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
6457 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
6458 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
6459 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
6460 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
6461 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
6462 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
6463 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
6464 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
6465 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
6466 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
6467 
6468 /******************************************************************************/
6469 /*                                                                            */
6470 /*                        High Resolution Timer (HRTIM)                       */
6471 /*                                                                            */
6472 /******************************************************************************/
6473 /******************** Master Timer control register ***************************/
6474 #define HRTIM_MCR_CK_PSC_Pos          (0U)
6475 #define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
6476 #define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
6477 #define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000001 */
6478 #define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000002 */
6479 #define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000004 */
6480 #define HRTIM_MCR_CONT_Pos            (3U)
6481 #define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
6482 #define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
6483 #define HRTIM_MCR_RETRIG_Pos          (4U)
6484 #define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
6485 #define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
6486 #define HRTIM_MCR_HALF_Pos            (5U)
6487 #define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
6488 #define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
6489 #define HRTIM_MCR_INTLVD_Pos          (6U)
6490 #define HRTIM_MCR_INTLVD_Msk          (0x3UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x000000C0 */
6491 #define HRTIM_MCR_INTLVD              HRTIM_MCR_INTLVD_Msk                     /*!< Interleaved mode */
6492 #define HRTIM_MCR_INTLVD_0            (0x1UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x00000040 */
6493 #define HRTIM_MCR_INTLVD_1            (0x2UL << HRTIM_MCR_INTLVD_Pos)          /*!< 0x00000080 */
6494 #define HRTIM_MCR_SYNC_IN_Pos         (8U)
6495 #define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
6496 #define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
6497 #define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000100 */
6498 #define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000200 */
6499 #define HRTIM_MCR_SYNCRSTM_Pos        (10U)
6500 #define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
6501 #define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
6502 #define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
6503 #define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
6504 #define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
6505 #define HRTIM_MCR_SYNC_OUT_Pos        (12U)
6506 #define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
6507 #define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
6508 #define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00001000 */
6509 #define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00002000 */
6510 #define HRTIM_MCR_SYNC_SRC_Pos        (14U)
6511 #define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
6512 #define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
6513 #define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x00004000 */
6514 #define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x00008000 */
6515 #define HRTIM_MCR_MCEN_Pos            (16U)
6516 #define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
6517 #define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
6518 #define HRTIM_MCR_TACEN_Pos           (17U)
6519 #define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
6520 #define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
6521 #define HRTIM_MCR_TBCEN_Pos           (18U)
6522 #define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
6523 #define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
6524 #define HRTIM_MCR_TCCEN_Pos           (19U)
6525 #define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
6526 #define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
6527 #define HRTIM_MCR_TDCEN_Pos           (20U)
6528 #define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
6529 #define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
6530 #define HRTIM_MCR_TECEN_Pos           (21U)
6531 #define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
6532 #define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
6533 #define HRTIM_MCR_TFCEN_Pos           (22U)
6534 #define HRTIM_MCR_TFCEN_Msk           (0x1UL << HRTIM_MCR_TFCEN_Pos)           /*!< 0x00400000 */
6535 #define HRTIM_MCR_TFCEN               HRTIM_MCR_TFCEN_Msk                      /*!< Timer F counter enable */
6536 #define HRTIM_MCR_DACSYNC_Pos         (25U)
6537 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
6538 #define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
6539 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x02000000 */
6540 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x04000000 */
6541 #define HRTIM_MCR_PREEN_Pos           (27U)
6542 #define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
6543 #define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
6544 #define HRTIM_MCR_MREPU_Pos           (29U)
6545 #define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
6546 #define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
6547 #define HRTIM_MCR_BRSTDMA_Pos         (30U)
6548 #define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
6549 #define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
6550 #define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0x40000000 */
6551 #define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0x80000000 */
6552 
6553 /******************** Master Timer Interrupt status register ******************/
6554 #define HRTIM_MISR_MCMP1_Pos          (0U)
6555 #define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
6556 #define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
6557 #define HRTIM_MISR_MCMP2_Pos          (1U)
6558 #define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
6559 #define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
6560 #define HRTIM_MISR_MCMP3_Pos          (2U)
6561 #define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
6562 #define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
6563 #define HRTIM_MISR_MCMP4_Pos          (3U)
6564 #define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
6565 #define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
6566 #define HRTIM_MISR_MREP_Pos           (4U)
6567 #define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
6568 #define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
6569 #define HRTIM_MISR_SYNC_Pos           (5U)
6570 #define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
6571 #define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
6572 #define HRTIM_MISR_MUPD_Pos           (6U)
6573 #define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
6574 #define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
6575 
6576 /******************** Master Timer Interrupt clear register *******************/
6577 #define HRTIM_MICR_MCMP1_Pos          (0U)
6578 #define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
6579 #define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
6580 #define HRTIM_MICR_MCMP2_Pos          (1U)
6581 #define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
6582 #define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
6583 #define HRTIM_MICR_MCMP3_Pos          (2U)
6584 #define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
6585 #define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
6586 #define HRTIM_MICR_MCMP4_Pos          (3U)
6587 #define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
6588 #define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
6589 #define HRTIM_MICR_MREP_Pos           (4U)
6590 #define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
6591 #define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
6592 #define HRTIM_MICR_SYNC_Pos           (5U)
6593 #define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
6594 #define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
6595 #define HRTIM_MICR_MUPD_Pos           (6U)
6596 #define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
6597 #define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
6598 
6599 /******************** Master Timer DMA/Interrupt enable register **************/
6600 #define HRTIM_MDIER_MCMP1IE_Pos       (0U)
6601 #define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
6602 #define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
6603 #define HRTIM_MDIER_MCMP2IE_Pos       (1U)
6604 #define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
6605 #define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
6606 #define HRTIM_MDIER_MCMP3IE_Pos       (2U)
6607 #define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
6608 #define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
6609 #define HRTIM_MDIER_MCMP4IE_Pos       (3U)
6610 #define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
6611 #define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
6612 #define HRTIM_MDIER_MREPIE_Pos        (4U)
6613 #define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
6614 #define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
6615 #define HRTIM_MDIER_SYNCIE_Pos        (5U)
6616 #define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
6617 #define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
6618 #define HRTIM_MDIER_MUPDIE_Pos        (6U)
6619 #define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
6620 #define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
6621 #define HRTIM_MDIER_MCMP1DE_Pos       (16U)
6622 #define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
6623 #define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
6624 #define HRTIM_MDIER_MCMP2DE_Pos       (17U)
6625 #define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
6626 #define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
6627 #define HRTIM_MDIER_MCMP3DE_Pos       (18U)
6628 #define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
6629 #define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
6630 #define HRTIM_MDIER_MCMP4DE_Pos       (19U)
6631 #define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
6632 #define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
6633 #define HRTIM_MDIER_MREPDE_Pos        (20U)
6634 #define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
6635 #define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
6636 #define HRTIM_MDIER_SYNCDE_Pos        (21U)
6637 #define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
6638 #define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
6639 #define HRTIM_MDIER_MUPDDE_Pos        (22U)
6640 #define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
6641 #define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
6642 
6643 /*******************  Bit definition for HRTIM_MCNTR register  ****************/
6644 #define HRTIM_MCNTR_MCNTR_Pos         (0U)
6645 #define HRTIM_MCNTR_MCNTR_Msk         (0x0000FFFFUL << HRTIM_MCNTR_MCNTR_Pos)  /*!< 0x0000FFFF */
6646 #define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
6647 
6648 /*******************  Bit definition for HRTIM_MPER register  *****************/
6649 #define HRTIM_MPER_MPER_Pos           (0U)
6650 #define HRTIM_MPER_MPER_Msk           (0x0000FFFFUL << HRTIM_MPER_MPER_Pos)    /*!< 0x0000FFFF */
6651 #define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
6652 
6653 /*******************  Bit definition for HRTIM_MREP register  *****************/
6654 #define HRTIM_MREP_MREP_Pos           (0U)
6655 #define HRTIM_MREP_MREP_Msk           (0x000000FFUL << HRTIM_MREP_MREP_Pos)    /*!< 0x000000FF */
6656 #define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
6657 
6658 /*******************  Bit definition for HRTIM_MCMP1R register  *****************/
6659 #define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
6660 #define HRTIM_MCMP1R_MCMP1R_Msk       (0x0000FFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)/*!< 0x0000FFFF */
6661 #define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
6662 
6663 /*******************  Bit definition for HRTIM_MCMP2R register  *****************/
6664 #define HRTIM_MCMP2R_MCMP2R_Pos       (0U)
6665 #define HRTIM_MCMP2R_MCMP2R_Msk       (0x0000FFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)/*!< 0x0000FFFF */
6666 #define HRTIM_MCMP2R_MCMP2R           HRTIM_MCMP2R_MCMP2R_Msk                  /*!<Compare Value */
6667 
6668 /*******************  Bit definition for HRTIM_MCMP3R register  *****************/
6669 #define HRTIM_MCMP3R_MCMP3R_Pos       (0U)
6670 #define HRTIM_MCMP3R_MCMP3R_Msk       (0x0000FFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)/*!< 0x0000FFFF */
6671 #define HRTIM_MCMP3R_MCMP3R           HRTIM_MCMP3R_MCMP3R_Msk                  /*!<Compare Value */
6672 
6673 /*******************  Bit definition for HRTIM_MCMP4R register  *****************/
6674 #define HRTIM_MCMP4R_MCMP4R_Pos       (0U)
6675 #define HRTIM_MCMP4R_MCMP4R_Msk       (0x0000FFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)/*!< 0x0000FFFF */
6676 #define HRTIM_MCMP4R_MCMP4R           HRTIM_MCMP4R_MCMP4R_Msk                  /*!<Compare Value */
6677 
6678 /* Legacy defines */
6679 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
6680 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
6681 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
6682 
6683 /******************** Slave control register **********************************/
6684 #define HRTIM_TIMCR_CK_PSC_Pos        (0U)
6685 #define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
6686 #define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
6687 #define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000001 */
6688 #define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000002 */
6689 #define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000004 */
6690 #define HRTIM_TIMCR_CONT_Pos          (3U)
6691 #define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
6692 #define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
6693 #define HRTIM_TIMCR_RETRIG_Pos        (4U)
6694 #define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
6695 #define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
6696 #define HRTIM_TIMCR_HALF_Pos          (5U)
6697 #define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
6698 #define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
6699 #define HRTIM_TIMCR_PSHPLL_Pos        (6U)
6700 #define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
6701 #define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
6702 #define HRTIM_TIMCR_INTLVD_Pos        (7U)
6703 #define HRTIM_TIMCR_INTLVD_Msk        (0x3UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000180 */
6704 #define HRTIM_TIMCR_INTLVD            HRTIM_TIMCR_INTLVD_Msk                   /*!< Interleaved mode */
6705 #define HRTIM_TIMCR_INTLVD_0          (0x1UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000080 */
6706 #define HRTIM_TIMCR_INTLVD_1          (0x2UL << HRTIM_TIMCR_INTLVD_Pos)        /*!< 0x00000100 */
6707 #define HRTIM_TIMCR_RSYNCU_Pos        (9U)
6708 #define HRTIM_TIMCR_RSYNCU_Msk        (0x1UL << HRTIM_TIMCR_RSYNCU_Pos)        /*!< 0x00000200 */
6709 #define HRTIM_TIMCR_RSYNCU            HRTIM_TIMCR_RSYNCU_Msk                   /*!< Resynchronization update */
6710 #define HRTIM_TIMCR_SYNCRST_Pos       (10U)
6711 #define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
6712 #define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
6713 #define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
6714 #define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
6715 #define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
6716 #define HRTIM_TIMCR_DELCMP2_Pos       (12U)
6717 #define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
6718 #define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
6719 #define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00001000 */
6720 #define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00002000 */
6721 #define HRTIM_TIMCR_DELCMP4_Pos       (14U)
6722 #define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
6723 #define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
6724 #define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x00004000 */
6725 #define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x00008000 */
6726 #define HRTIM_TIMCR_TFU_Pos           (16U)
6727 #define HRTIM_TIMCR_TFU_Msk           (0x1UL << HRTIM_TIMCR_TFU_Pos)           /*!< 0x00010000 */
6728 #define HRTIM_TIMCR_TFU               HRTIM_TIMCR_TFU_Msk                      /*!< Slave Timer F update reserved for TIM F */
6729 #define HRTIM_TIMCR_TREPU_Pos         (17U)
6730 #define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
6731 #define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
6732 #define HRTIM_TIMCR_TRSTU_Pos         (18U)
6733 #define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
6734 #define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
6735 #define HRTIM_TIMCR_TAU_Pos           (19U)
6736 #define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
6737 #define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
6738 #define HRTIM_TIMCR_TBU_Pos           (20U)
6739 #define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
6740 #define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
6741 #define HRTIM_TIMCR_TCU_Pos           (21U)
6742 #define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
6743 #define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
6744 #define HRTIM_TIMCR_TDU_Pos           (22U)
6745 #define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
6746 #define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
6747 #define HRTIM_TIMCR_TEU_Pos           (23U)
6748 #define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
6749 #define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
6750 #define HRTIM_TIMCR_MSTU_Pos          (24U)
6751 #define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x02000000 */
6752 #define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
6753 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
6754 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
6755 #define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
6756 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x02000000 */
6757 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x04000000 */
6758 #define HRTIM_TIMCR_PREEN_Pos         (27U)
6759 #define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
6760 #define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
6761 #define HRTIM_TIMCR_UPDGAT_Pos        (28U)
6762 #define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
6763 #define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
6764 #define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x10000000 */
6765 #define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x20000000 */
6766 #define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x40000000 */
6767 #define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0x80000000 */
6768 
6769 /******************** Slave Interrupt status register **************************/
6770 #define HRTIM_TIMISR_CMP1_Pos         (0U)
6771 #define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
6772 #define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
6773 #define HRTIM_TIMISR_CMP2_Pos         (1U)
6774 #define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
6775 #define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
6776 #define HRTIM_TIMISR_CMP3_Pos         (2U)
6777 #define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
6778 #define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
6779 #define HRTIM_TIMISR_CMP4_Pos         (3U)
6780 #define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
6781 #define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
6782 #define HRTIM_TIMISR_REP_Pos          (4U)
6783 #define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
6784 #define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
6785 #define HRTIM_TIMISR_UPD_Pos          (6U)
6786 #define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
6787 #define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
6788 #define HRTIM_TIMISR_CPT1_Pos         (7U)
6789 #define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
6790 #define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
6791 #define HRTIM_TIMISR_CPT2_Pos         (8U)
6792 #define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
6793 #define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
6794 #define HRTIM_TIMISR_SET1_Pos         (9U)
6795 #define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
6796 #define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
6797 #define HRTIM_TIMISR_RST1_Pos         (10U)
6798 #define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
6799 #define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
6800 #define HRTIM_TIMISR_SET2_Pos         (11U)
6801 #define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
6802 #define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
6803 #define HRTIM_TIMISR_RST2_Pos         (12U)
6804 #define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
6805 #define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
6806 #define HRTIM_TIMISR_RST_Pos          (13U)
6807 #define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
6808 #define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
6809 #define HRTIM_TIMISR_DLYPRT_Pos       (14U)
6810 #define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
6811 #define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
6812 #define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
6813 #define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
6814 #define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
6815 #define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
6816 #define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
6817 #define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
6818 #define HRTIM_TIMISR_O1STAT_Pos       (18U)
6819 #define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
6820 #define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
6821 #define HRTIM_TIMISR_O2STAT_Pos       (19U)
6822 #define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
6823 #define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
6824 #define HRTIM_TIMISR_O1CPY_Pos        (20U)
6825 #define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
6826 #define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
6827 #define HRTIM_TIMISR_O2CPY_Pos        (21U)
6828 #define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
6829 #define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
6830 
6831 /******************** Slave Interrupt clear register **************************/
6832 #define HRTIM_TIMICR_CMP1C_Pos        (0U)
6833 #define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
6834 #define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
6835 #define HRTIM_TIMICR_CMP2C_Pos        (1U)
6836 #define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
6837 #define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
6838 #define HRTIM_TIMICR_CMP3C_Pos        (2U)
6839 #define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
6840 #define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
6841 #define HRTIM_TIMICR_CMP4C_Pos        (3U)
6842 #define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
6843 #define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
6844 #define HRTIM_TIMICR_REPC_Pos         (4U)
6845 #define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
6846 #define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
6847 #define HRTIM_TIMICR_UPDC_Pos         (6U)
6848 #define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
6849 #define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
6850 #define HRTIM_TIMICR_CPT1C_Pos        (7U)
6851 #define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
6852 #define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
6853 #define HRTIM_TIMICR_CPT2C_Pos        (8U)
6854 #define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
6855 #define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
6856 #define HRTIM_TIMICR_SET1C_Pos        (9U)
6857 #define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
6858 #define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
6859 #define HRTIM_TIMICR_RST1C_Pos        (10U)
6860 #define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
6861 #define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
6862 #define HRTIM_TIMICR_SET2C_Pos        (11U)
6863 #define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
6864 #define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
6865 #define HRTIM_TIMICR_RST2C_Pos        (12U)
6866 #define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
6867 #define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
6868 #define HRTIM_TIMICR_RSTC_Pos         (13U)
6869 #define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
6870 #define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
6871 #define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
6872 #define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
6873 #define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output delay protection clear flag */
6874 
6875 /******************** Slave DMA/Interrupt enable register *********************/
6876 #define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
6877 #define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
6878 #define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
6879 #define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
6880 #define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
6881 #define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
6882 #define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
6883 #define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
6884 #define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
6885 #define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
6886 #define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
6887 #define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
6888 #define HRTIM_TIMDIER_REPIE_Pos       (4U)
6889 #define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
6890 #define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
6891 #define HRTIM_TIMDIER_UPDIE_Pos       (6U)
6892 #define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
6893 #define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
6894 #define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
6895 #define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
6896 #define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
6897 #define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
6898 #define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
6899 #define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
6900 #define HRTIM_TIMDIER_SET1IE_Pos      (9U)
6901 #define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
6902 #define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
6903 #define HRTIM_TIMDIER_RST1IE_Pos      (10U)
6904 #define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
6905 #define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
6906 #define HRTIM_TIMDIER_SET2IE_Pos      (11U)
6907 #define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
6908 #define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
6909 #define HRTIM_TIMDIER_RST2IE_Pos      (12U)
6910 #define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
6911 #define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
6912 #define HRTIM_TIMDIER_RSTIE_Pos       (13U)
6913 #define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
6914 #define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
6915 #define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
6916 #define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
6917 #define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
6918 
6919 #define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
6920 #define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
6921 #define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
6922 #define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
6923 #define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
6924 #define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
6925 #define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
6926 #define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
6927 #define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
6928 #define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
6929 #define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
6930 #define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
6931 #define HRTIM_TIMDIER_REPDE_Pos       (20U)
6932 #define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
6933 #define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
6934 #define HRTIM_TIMDIER_UPDDE_Pos       (22U)
6935 #define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
6936 #define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
6937 #define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
6938 #define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
6939 #define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
6940 #define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
6941 #define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
6942 #define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
6943 #define HRTIM_TIMDIER_SET1DE_Pos      (25U)
6944 #define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
6945 #define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
6946 #define HRTIM_TIMDIER_RST1DE_Pos      (26U)
6947 #define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
6948 #define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
6949 #define HRTIM_TIMDIER_SET2DE_Pos      (27U)
6950 #define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
6951 #define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
6952 #define HRTIM_TIMDIER_RST2DE_Pos      (28U)
6953 #define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
6954 #define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
6955 #define HRTIM_TIMDIER_RSTDE_Pos       (29U)
6956 #define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
6957 #define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
6958 #define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
6959 #define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
6960 #define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
6961 
6962 /******************  Bit definition for HRTIM_CNTR register  ****************/
6963 #define HRTIM_CNTR_CNTR_Pos           (0U)
6964 #define HRTIM_CNTR_CNTR_Msk           (0x0000FFFFUL << HRTIM_CNTR_CNTR_Pos)    /*!< 0x0000FFFF */
6965 #define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
6966 
6967 /*******************  Bit definition for HRTIM_PER register  *****************/
6968 #define HRTIM_PER_PER_Pos             (0U)
6969 #define HRTIM_PER_PER_Msk             (0x0000FFFFUL << HRTIM_PER_PER_Pos)      /*!< 0x0000FFFF */
6970 #define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
6971 
6972 /*******************  Bit definition for HRTIM_REP register  *****************/
6973 #define HRTIM_REP_REP_Pos             (0U)
6974 #define HRTIM_REP_REP_Msk             (0x000000FFUL << HRTIM_REP_REP_Pos)      /*!< 0x000000FF */
6975 #define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
6976 
6977 /*******************  Bit definition for HRTIM_CMP1R register  *****************/
6978 #define HRTIM_CMP1R_CMP1R_Pos         (0U)
6979 #define HRTIM_CMP1R_CMP1R_Msk         (0x0000FFFFUL << HRTIM_CMP1R_CMP1R_Pos)  /*!< 0x0000FFFF */
6980 #define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
6981 
6982 /*******************  Bit definition for HRTIM_CMP1CR register  *****************/
6983 #define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
6984 #define HRTIM_CMP1CR_CMP1CR_Msk       (0x0000FFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)/*!< 0x0000FFFF */
6985 #define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
6986 
6987 /*******************  Bit definition for HRTIM_CMP2R register  *****************/
6988 #define HRTIM_CMP2R_CMP2R_Pos         (0U)
6989 #define HRTIM_CMP2R_CMP2R_Msk         (0x0000FFFFUL << HRTIM_CMP2R_CMP2R_Pos)  /*!< 0x0000FFFF */
6990 #define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
6991 
6992 /*******************  Bit definition for HRTIM_CMP3R register  *****************/
6993 #define HRTIM_CMP3R_CMP3R_Pos         (0U)
6994 #define HRTIM_CMP3R_CMP3R_Msk         (0x0000FFFFUL << HRTIM_CMP3R_CMP3R_Pos)  /*!< 0x0000FFFF */
6995 #define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
6996 
6997 /*******************  Bit definition for HRTIM_CMP4R register  *****************/
6998 #define HRTIM_CMP4R_CMP4R_Pos         (0U)
6999 #define HRTIM_CMP4R_CMP4R_Msk         (0x0000FFFFUL << HRTIM_CMP4R_CMP4R_Pos)  /*!< 0x0000FFFF */
7000 #define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
7001 
7002 /*******************  Bit definition for HRTIM_CPT1R register  ****************/
7003 #define HRTIM_CPT1R_CPT1R_Pos         (0U)
7004 #define HRTIM_CPT1R_CPT1R_Msk         (0x0000FFFFUL << HRTIM_CPT1R_CPT1R_Pos)  /*!< 0x0000FFFF */
7005 #define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture 1 Value */
7006 #define HRTIM_CPT1R_DIR_Pos           (16U)
7007 #define HRTIM_CPT1R_DIR_Msk           (0x1UL << HRTIM_CPT1R_DIR_Pos)           /*!< 0x00010000 */
7008 #define HRTIM_CPT1R_DIR               HRTIM_CPT1R_DIR_Msk                      /*!< Capture 1 direction> */
7009 
7010 /*******************  Bit definition for HRTIM_CPT2R register  ****************/
7011 #define HRTIM_CPT2R_CPT2R_Pos         (0U)
7012 #define HRTIM_CPT2R_CPT2R_Msk         (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos)  /*!< 0x0000FFFF */
7013 #define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture 2 Value */
7014 #define HRTIM_CPT2R_DIR_Pos           (16U)
7015 #define HRTIM_CPT2R_DIR_Msk           (0x1UL << HRTIM_CPT2R_DIR_Pos)           /*!< 0x00010000 */
7016 #define HRTIM_CPT2R_DIR               HRTIM_CPT2R_DIR_Msk                      /*!< Capture 2 direction */
7017 
7018 /******************** Bit definition for Slave Deadtime register **************/
7019 #define HRTIM_DTR_DTR_Pos             (0U)
7020 #define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
7021 #define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
7022 #define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000001 */
7023 #define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000002 */
7024 #define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000004 */
7025 #define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000008 */
7026 #define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000010 */
7027 #define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000020 */
7028 #define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000040 */
7029 #define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000080 */
7030 #define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)           /*!< 0x00000100 */
7031 #define HRTIM_DTR_SDTR_Pos            (9U)
7032 #define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
7033 #define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
7034 #define HRTIM_DTR_DTPRSC_Pos          (10U)
7035 #define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
7036 #define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
7037 #define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00000400 */
7038 #define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00000800 */
7039 #define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001000 */
7040 #define HRTIM_DTR_DTRSLK_Pos          (14U)
7041 #define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
7042 #define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
7043 #define HRTIM_DTR_DTRLK_Pos           (15U)
7044 #define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
7045 #define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
7046 #define HRTIM_DTR_DTF_Pos             (16U)
7047 #define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
7048 #define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
7049 #define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00010000 */
7050 #define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00020000 */
7051 #define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00040000 */
7052 #define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00080000 */
7053 #define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00100000 */
7054 #define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00200000 */
7055 #define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00400000 */
7056 #define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)           /*!< 0x00800000 */
7057 #define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)           /*!< 0x01000000 */
7058 #define HRTIM_DTR_SDTF_Pos            (25U)
7059 #define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
7060 #define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
7061 #define HRTIM_DTR_DTFSLK_Pos          (30U)
7062 #define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
7063 #define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
7064 #define HRTIM_DTR_DTFLK_Pos           (31U)
7065 #define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
7066 #define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
7067 
7068 /**** Bit definition for Slave Output 1 set register **************************/
7069 #define HRTIM_SET1R_SST_Pos           (0U)
7070 #define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
7071 #define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
7072 #define HRTIM_SET1R_RESYNC_Pos        (1U)
7073 #define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
7074 #define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
7075 #define HRTIM_SET1R_PER_Pos           (2U)
7076 #define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
7077 #define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
7078 #define HRTIM_SET1R_CMP1_Pos          (3U)
7079 #define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
7080 #define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
7081 #define HRTIM_SET1R_CMP2_Pos          (4U)
7082 #define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
7083 #define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
7084 #define HRTIM_SET1R_CMP3_Pos          (5U)
7085 #define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
7086 #define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
7087 #define HRTIM_SET1R_CMP4_Pos          (6U)
7088 #define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
7089 #define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
7090 
7091 #define HRTIM_SET1R_MSTPER_Pos        (7U)
7092 #define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
7093 #define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
7094 #define HRTIM_SET1R_MSTCMP1_Pos       (8U)
7095 #define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
7096 #define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
7097 #define HRTIM_SET1R_MSTCMP2_Pos       (9U)
7098 #define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
7099 #define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
7100 #define HRTIM_SET1R_MSTCMP3_Pos       (10U)
7101 #define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
7102 #define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
7103 #define HRTIM_SET1R_MSTCMP4_Pos       (11U)
7104 #define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
7105 #define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
7106 
7107 #define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
7108 #define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7109 #define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7110 #define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
7111 #define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7112 #define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7113 #define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
7114 #define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7115 #define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7116 #define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
7117 #define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7118 #define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7119 #define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
7120 #define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7121 #define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7122 #define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
7123 #define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7124 #define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7125 #define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
7126 #define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7127 #define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7128 #define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
7129 #define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7130 #define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7131 #define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
7132 #define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7133 #define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7134 
7135 #define HRTIM_SET1R_EXTVNT1_Pos       (21U)
7136 #define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
7137 #define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
7138 #define HRTIM_SET1R_EXTVNT2_Pos       (22U)
7139 #define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
7140 #define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
7141 #define HRTIM_SET1R_EXTVNT3_Pos       (23U)
7142 #define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
7143 #define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
7144 #define HRTIM_SET1R_EXTVNT4_Pos       (24U)
7145 #define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
7146 #define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
7147 #define HRTIM_SET1R_EXTVNT5_Pos       (25U)
7148 #define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
7149 #define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
7150 #define HRTIM_SET1R_EXTVNT6_Pos       (26U)
7151 #define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
7152 #define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
7153 #define HRTIM_SET1R_EXTVNT7_Pos       (27U)
7154 #define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
7155 #define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
7156 #define HRTIM_SET1R_EXTVNT8_Pos       (28U)
7157 #define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
7158 #define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
7159 #define HRTIM_SET1R_EXTVNT9_Pos       (29U)
7160 #define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
7161 #define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
7162 #define HRTIM_SET1R_EXTVNT10_Pos      (30U)
7163 #define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
7164 #define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
7165 
7166 #define HRTIM_SET1R_UPDATE_Pos        (31U)
7167 #define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
7168 #define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7169 
7170 /**** Bit definition for Slave Output 1 reset register ************************/
7171 #define HRTIM_RST1R_SRT_Pos           (0U)
7172 #define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
7173 #define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
7174 #define HRTIM_RST1R_RESYNC_Pos        (1U)
7175 #define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
7176 #define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
7177 #define HRTIM_RST1R_PER_Pos           (2U)
7178 #define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
7179 #define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
7180 #define HRTIM_RST1R_CMP1_Pos          (3U)
7181 #define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
7182 #define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
7183 #define HRTIM_RST1R_CMP2_Pos          (4U)
7184 #define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
7185 #define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
7186 #define HRTIM_RST1R_CMP3_Pos          (5U)
7187 #define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
7188 #define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
7189 #define HRTIM_RST1R_CMP4_Pos          (6U)
7190 #define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
7191 #define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
7192 
7193 #define HRTIM_RST1R_MSTPER_Pos        (7U)
7194 #define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
7195 #define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
7196 #define HRTIM_RST1R_MSTCMP1_Pos       (8U)
7197 #define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
7198 #define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
7199 #define HRTIM_RST1R_MSTCMP2_Pos       (9U)
7200 #define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
7201 #define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
7202 #define HRTIM_RST1R_MSTCMP3_Pos       (10U)
7203 #define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
7204 #define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
7205 #define HRTIM_RST1R_MSTCMP4_Pos       (11U)
7206 #define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
7207 #define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
7208 
7209 #define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
7210 #define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7211 #define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7212 #define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
7213 #define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7214 #define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7215 #define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
7216 #define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7217 #define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7218 #define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
7219 #define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7220 #define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7221 #define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
7222 #define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7223 #define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7224 #define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
7225 #define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7226 #define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7227 #define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
7228 #define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7229 #define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7230 #define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
7231 #define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7232 #define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7233 #define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
7234 #define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7235 #define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7236 
7237 #define HRTIM_RST1R_EXTVNT1_Pos       (21U)
7238 #define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
7239 #define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
7240 #define HRTIM_RST1R_EXTVNT2_Pos       (22U)
7241 #define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
7242 #define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
7243 #define HRTIM_RST1R_EXTVNT3_Pos       (23U)
7244 #define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
7245 #define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
7246 #define HRTIM_RST1R_EXTVNT4_Pos       (24U)
7247 #define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
7248 #define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
7249 #define HRTIM_RST1R_EXTVNT5_Pos       (25U)
7250 #define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
7251 #define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
7252 #define HRTIM_RST1R_EXTVNT6_Pos       (26U)
7253 #define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
7254 #define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
7255 #define HRTIM_RST1R_EXTVNT7_Pos       (27U)
7256 #define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
7257 #define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
7258 #define HRTIM_RST1R_EXTVNT8_Pos       (28U)
7259 #define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
7260 #define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
7261 #define HRTIM_RST1R_EXTVNT9_Pos       (29U)
7262 #define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
7263 #define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
7264 #define HRTIM_RST1R_EXTVNT10_Pos      (30U)
7265 #define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
7266 #define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
7267 #define HRTIM_RST1R_UPDATE_Pos        (31U)
7268 #define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
7269 #define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7270 
7271 /**** Bit definition for Slave Output 2 set register **************************/
7272 #define HRTIM_SET2R_SST_Pos           (0U)
7273 #define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
7274 #define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
7275 #define HRTIM_SET2R_RESYNC_Pos        (1U)
7276 #define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
7277 #define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
7278 #define HRTIM_SET2R_PER_Pos           (2U)
7279 #define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
7280 #define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
7281 #define HRTIM_SET2R_CMP1_Pos          (3U)
7282 #define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
7283 #define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
7284 #define HRTIM_SET2R_CMP2_Pos          (4U)
7285 #define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
7286 #define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
7287 #define HRTIM_SET2R_CMP3_Pos          (5U)
7288 #define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
7289 #define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
7290 #define HRTIM_SET2R_CMP4_Pos          (6U)
7291 #define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
7292 #define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
7293 
7294 #define HRTIM_SET2R_MSTPER_Pos        (7U)
7295 #define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
7296 #define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
7297 #define HRTIM_SET2R_MSTCMP1_Pos       (8U)
7298 #define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
7299 #define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
7300 #define HRTIM_SET2R_MSTCMP2_Pos       (9U)
7301 #define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
7302 #define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
7303 #define HRTIM_SET2R_MSTCMP3_Pos       (10U)
7304 #define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
7305 #define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
7306 #define HRTIM_SET2R_MSTCMP4_Pos       (11U)
7307 #define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
7308 #define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
7309 
7310 #define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
7311 #define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7312 #define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7313 #define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
7314 #define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7315 #define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7316 #define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
7317 #define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7318 #define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7319 #define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
7320 #define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7321 #define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7322 #define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
7323 #define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7324 #define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7325 #define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
7326 #define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7327 #define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7328 #define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
7329 #define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7330 #define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7331 #define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
7332 #define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7333 #define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7334 #define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
7335 #define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7336 #define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7337 
7338 #define HRTIM_SET2R_EXTVNT1_Pos       (21U)
7339 #define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
7340 #define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
7341 #define HRTIM_SET2R_EXTVNT2_Pos       (22U)
7342 #define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
7343 #define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
7344 #define HRTIM_SET2R_EXTVNT3_Pos       (23U)
7345 #define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
7346 #define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
7347 #define HRTIM_SET2R_EXTVNT4_Pos       (24U)
7348 #define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
7349 #define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
7350 #define HRTIM_SET2R_EXTVNT5_Pos       (25U)
7351 #define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
7352 #define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
7353 #define HRTIM_SET2R_EXTVNT6_Pos       (26U)
7354 #define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
7355 #define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
7356 #define HRTIM_SET2R_EXTVNT7_Pos       (27U)
7357 #define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
7358 #define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
7359 #define HRTIM_SET2R_EXTVNT8_Pos       (28U)
7360 #define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
7361 #define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
7362 #define HRTIM_SET2R_EXTVNT9_Pos       (29U)
7363 #define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
7364 #define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
7365 #define HRTIM_SET2R_EXTVNT10_Pos      (30U)
7366 #define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
7367 #define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
7368 
7369 #define HRTIM_SET2R_UPDATE_Pos        (31U)
7370 #define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
7371 #define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7372 
7373 /**** Bit definition for Slave Output 2 reset register ************************/
7374 #define HRTIM_RST2R_SRT_Pos           (0U)
7375 #define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
7376 #define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
7377 #define HRTIM_RST2R_RESYNC_Pos        (1U)
7378 #define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
7379 #define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
7380 #define HRTIM_RST2R_PER_Pos           (2U)
7381 #define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
7382 #define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
7383 #define HRTIM_RST2R_CMP1_Pos          (3U)
7384 #define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
7385 #define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
7386 #define HRTIM_RST2R_CMP2_Pos          (4U)
7387 #define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
7388 #define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
7389 #define HRTIM_RST2R_CMP3_Pos          (5U)
7390 #define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
7391 #define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
7392 #define HRTIM_RST2R_CMP4_Pos          (6U)
7393 #define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
7394 #define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
7395 #define HRTIM_RST2R_MSTPER_Pos        (7U)
7396 #define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
7397 #define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
7398 #define HRTIM_RST2R_MSTCMP1_Pos       (8U)
7399 #define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
7400 #define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
7401 #define HRTIM_RST2R_MSTCMP2_Pos       (9U)
7402 #define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
7403 #define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
7404 #define HRTIM_RST2R_MSTCMP3_Pos       (10U)
7405 #define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
7406 #define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
7407 #define HRTIM_RST2R_MSTCMP4_Pos       (11U)
7408 #define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
7409 #define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
7410 
7411 #define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
7412 #define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
7413 #define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
7414 #define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
7415 #define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
7416 #define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
7417 #define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
7418 #define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
7419 #define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
7420 #define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
7421 #define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
7422 #define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
7423 #define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
7424 #define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
7425 #define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
7426 #define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
7427 #define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
7428 #define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
7429 #define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
7430 #define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
7431 #define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
7432 #define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
7433 #define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
7434 #define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
7435 #define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
7436 #define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
7437 #define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
7438 
7439 #define HRTIM_RST2R_EXTVNT1_Pos       (21U)
7440 #define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
7441 #define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
7442 #define HRTIM_RST2R_EXTVNT2_Pos       (22U)
7443 #define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
7444 #define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
7445 #define HRTIM_RST2R_EXTVNT3_Pos       (23U)
7446 #define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
7447 #define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
7448 #define HRTIM_RST2R_EXTVNT4_Pos       (24U)
7449 #define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
7450 #define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
7451 #define HRTIM_RST2R_EXTVNT5_Pos       (25U)
7452 #define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
7453 #define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
7454 #define HRTIM_RST2R_EXTVNT6_Pos       (26U)
7455 #define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
7456 #define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
7457 #define HRTIM_RST2R_EXTVNT7_Pos       (27U)
7458 #define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
7459 #define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
7460 #define HRTIM_RST2R_EXTVNT8_Pos       (28U)
7461 #define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
7462 #define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
7463 #define HRTIM_RST2R_EXTVNT9_Pos       (29U)
7464 #define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
7465 #define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
7466 #define HRTIM_RST2R_EXTVNT10_Pos      (30U)
7467 #define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
7468 #define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
7469 #define HRTIM_RST2R_UPDATE_Pos        (31U)
7470 #define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
7471 #define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
7472 
7473 /**** Bit definition for Slave external event filtering  register 1 ***********/
7474 #define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
7475 #define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
7476 #define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
7477 #define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
7478 #define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
7479 #define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
7480 #define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000002 */
7481 #define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000004 */
7482 #define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000008 */
7483 #define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x00000010 */
7484 
7485 #define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
7486 #define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
7487 #define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
7488 #define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
7489 #define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
7490 #define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
7491 #define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000080 */
7492 #define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000100 */
7493 #define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000200 */
7494 #define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000400 */
7495 
7496 #define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
7497 #define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
7498 #define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
7499 #define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
7500 #define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
7501 #define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
7502 #define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00002000 */
7503 #define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00004000 */
7504 #define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00008000 */
7505 #define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x00010000 */
7506 
7507 #define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
7508 #define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
7509 #define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
7510 #define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
7511 #define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
7512 #define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
7513 #define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00080000 */
7514 #define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00100000 */
7515 #define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00200000 */
7516 #define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00400000 */
7517 
7518 #define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
7519 #define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
7520 #define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
7521 #define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
7522 #define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
7523 #define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
7524 #define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x02000000 */
7525 #define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x04000000 */
7526 #define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x08000000 */
7527 #define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x10000000 */
7528 
7529 /**** Bit definition for Slave external event filtering  register 2 ***********/
7530 #define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
7531 #define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
7532 #define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
7533 #define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
7534 #define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
7535 #define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
7536 #define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000002 */
7537 #define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000004 */
7538 #define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000008 */
7539 #define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x00000010 */
7540 
7541 #define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
7542 #define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
7543 #define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
7544 #define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
7545 #define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
7546 #define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
7547 #define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000080 */
7548 #define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000100 */
7549 #define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000200 */
7550 #define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000400 */
7551 
7552 #define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
7553 #define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
7554 #define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
7555 #define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
7556 #define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
7557 #define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
7558 #define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00002000 */
7559 #define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00004000 */
7560 #define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00008000 */
7561 #define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x00010000 */
7562 
7563 #define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
7564 #define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
7565 #define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
7566 #define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
7567 #define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
7568 #define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
7569 #define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00080000 */
7570 #define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00100000 */
7571 #define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00200000 */
7572 #define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00400000 */
7573 
7574 #define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
7575 #define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
7576 #define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
7577 #define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
7578 #define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
7579 #define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
7580 #define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x02000000 */
7581 #define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x04000000 */
7582 #define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x08000000 */
7583 #define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x10000000 */
7584 
7585 /**** Bit definition for Slave Timer reset register ***************************/
7586 
7587 #define HRTIM_RSTR_TIMFCMP1_Pos       (0U)
7588 #define HRTIM_RSTR_TIMFCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos)       /*!< 0x00000001 */
7589 #define HRTIM_RSTR_TIMFCMP1           HRTIM_RSTR_TIMFCMP1_Msk                  /*!< Timer F compare 1 */
7590 #define HRTIM_RSTR_UPDATE_Pos         (1U)
7591 #define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
7592 #define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
7593 #define HRTIM_RSTR_CMP2_Pos           (2U)
7594 #define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
7595 #define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
7596 #define HRTIM_RSTR_CMP4_Pos           (3U)
7597 #define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
7598 #define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
7599 #define HRTIM_RSTR_MSTPER_Pos         (4U)
7600 #define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
7601 #define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
7602 #define HRTIM_RSTR_MSTCMP1_Pos        (5U)
7603 #define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
7604 #define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
7605 #define HRTIM_RSTR_MSTCMP2_Pos        (6U)
7606 #define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
7607 #define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
7608 #define HRTIM_RSTR_MSTCMP3_Pos        (7U)
7609 #define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
7610 #define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
7611 #define HRTIM_RSTR_MSTCMP4_Pos        (8U)
7612 #define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
7613 #define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
7614 #define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
7615 #define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
7616 #define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
7617 #define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
7618 #define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
7619 #define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
7620 #define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
7621 #define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
7622 #define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
7623 #define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
7624 #define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
7625 #define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
7626 #define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
7627 #define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
7628 #define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
7629 #define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
7630 #define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
7631 #define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
7632 #define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
7633 #define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
7634 #define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
7635 #define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
7636 #define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
7637 #define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
7638 #define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
7639 #define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
7640 #define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
7641 #define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
7642 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
7643 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
7644 
7645 /* Slave Timer A reset enable bits upon other slave timers events */
7646 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
7647 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
7648 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
7649 #define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
7650 #define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
7651 #define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
7652 #define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
7653 #define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
7654 #define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
7655 
7656 #define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
7657 #define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
7658 #define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
7659 #define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
7660 #define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
7661 #define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
7662 #define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
7663 #define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
7664 #define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
7665 
7666 #define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
7667 #define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
7668 #define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
7669 #define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
7670 #define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
7671 #define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
7672 #define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
7673 #define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
7674 #define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
7675 
7676 #define HRTIM_RSTR_TIMECMP1_Pos       (28U)
7677 #define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
7678 #define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
7679 #define HRTIM_RSTR_TIMECMP2_Pos       (29U)
7680 #define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
7681 #define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
7682 #define HRTIM_RSTR_TIMECMP4_Pos       (30U)
7683 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
7684 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
7685 
7686 #define HRTIM_RSTR_TIMFCMP2_Pos       (31U)
7687 #define HRTIM_RSTR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos)       /*!< 0x80000000 */
7688 #define HRTIM_RSTR_TIMFCMP2           HRTIM_RSTR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
7689 
7690 /* Slave Timer B reset enable bits upon other slave timers events */
7691 #define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
7692 #define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)        /*!< 0x00080000 */
7693 #define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
7694 #define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
7695 #define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)        /*!< 0x00100000 */
7696 #define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
7697 #define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
7698 #define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)        /*!< 0x00200000 */
7699 #define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
7700 
7701 #define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
7702 #define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)        /*!< 0x00400000 */
7703 #define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
7704 #define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
7705 #define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)        /*!< 0x00800000 */
7706 #define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
7707 #define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
7708 #define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)        /*!< 0x01000000 */
7709 #define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
7710 
7711 #define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
7712 #define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)        /*!< 0x02000000 */
7713 #define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
7714 #define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
7715 #define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)        /*!< 0x04000000 */
7716 #define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
7717 #define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
7718 #define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)        /*!< 0x08000000 */
7719 #define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
7720 
7721 #define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
7722 #define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)        /*!< 0x10000000 */
7723 #define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
7724 #define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
7725 #define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)        /*!< 0x20000000 */
7726 #define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
7727 #define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
7728 #define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)        /*!< 0x40000000 */
7729 #define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
7730 
7731 #define HRTIM_RSTBR_TIMFCMP2_Pos       (31U)
7732 #define HRTIM_RSTBR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos)       /*!< 0x80000000 */
7733 #define HRTIM_RSTBR_TIMFCMP2           HRTIM_RSTBR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
7734 
7735 /* Slave Timer C reset enable bits upon other slave timers events */
7736 #define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
7737 #define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)        /*!< 0x00080000 */
7738 #define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
7739 #define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
7740 #define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)        /*!< 0x00100000 */
7741 #define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
7742 #define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
7743 #define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)        /*!< 0x00200000 */
7744 #define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
7745 
7746 #define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
7747 #define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)        /*!< 0x00400000 */
7748 #define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
7749 #define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
7750 #define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)        /*!< 0x00800000 */
7751 #define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
7752 #define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
7753 #define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)        /*!< 0x01000000 */
7754 #define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
7755 
7756 #define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
7757 #define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)        /*!< 0x02000000 */
7758 #define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
7759 #define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
7760 #define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)        /*!< 0x04000000 */
7761 #define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
7762 #define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
7763 #define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)        /*!< 0x08000000 */
7764 #define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
7765 
7766 #define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
7767 #define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)        /*!< 0x10000000 */
7768 #define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
7769 #define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
7770 #define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)        /*!< 0x20000000 */
7771 #define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
7772 #define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
7773 #define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)        /*!< 0x40000000 */
7774 #define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
7775 
7776 #define HRTIM_RSTCR_TIMFCMP2_Pos       (31U)
7777 #define HRTIM_RSTCR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos)       /*!< 0x80000000 */
7778 #define HRTIM_RSTCR_TIMFCMP2           HRTIM_RSTCR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
7779 
7780 /* Slave Timer D reset enable bits upon other slave timers events */
7781 #define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
7782 #define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)        /*!< 0x00080000 */
7783 #define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
7784 #define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
7785 #define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)        /*!< 0x00100000 */
7786 #define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
7787 #define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
7788 #define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)        /*!< 0x00200000 */
7789 #define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
7790 
7791 #define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
7792 #define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)        /*!< 0x00400000 */
7793 #define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
7794 #define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
7795 #define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)        /*!< 0x00800000 */
7796 #define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
7797 #define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
7798 #define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)        /*!< 0x01000000 */
7799 #define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
7800 
7801 #define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
7802 #define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)        /*!< 0x02000000 */
7803 #define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
7804 #define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
7805 #define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)        /*!< 0x04000000 */
7806 #define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
7807 #define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
7808 #define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)        /*!< 0x08000000 */
7809 #define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
7810 
7811 #define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
7812 #define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)        /*!< 0x10000000 */
7813 #define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
7814 #define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
7815 #define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)        /*!< 0x20000000 */
7816 #define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
7817 #define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
7818 #define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)        /*!< 0x40000000 */
7819 #define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
7820 
7821 #define HRTIM_RSTDR_TIMFCMP2_Pos       (31U)
7822 #define HRTIM_RSTDR_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos)       /*!< 0x80000000 */
7823 #define HRTIM_RSTDR_TIMFCMP2           HRTIM_RSTDR_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
7824 
7825 /* Slave Timer E reset enable bits upon other slave timers events */
7826 #define HRTIM_RSTER_TIMACMP1_Pos       (19U)
7827 #define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)        /*!< 0x00080000 */
7828 #define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                  /*!< Timer A compare 1 */
7829 #define HRTIM_RSTER_TIMACMP2_Pos       (20U)
7830 #define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)        /*!< 0x00100000 */
7831 #define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                  /*!< Timer A compare 2 */
7832 #define HRTIM_RSTER_TIMACMP4_Pos       (21U)
7833 #define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)        /*!< 0x00200000 */
7834 #define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                  /*!< Timer A compare 4 */
7835 
7836 #define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
7837 #define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)        /*!< 0x00400000 */
7838 #define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
7839 #define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
7840 #define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)        /*!< 0x00800000 */
7841 #define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
7842 #define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
7843 #define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)        /*!< 0x01000000 */
7844 #define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
7845 
7846 #define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
7847 #define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)        /*!< 0x02000000 */
7848 #define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
7849 #define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
7850 #define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)        /*!< 0x04000000 */
7851 #define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
7852 #define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
7853 #define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)        /*!< 0x08000000 */
7854 #define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
7855 
7856 #define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
7857 #define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)        /*!< 0x10000000 */
7858 #define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
7859 #define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
7860 #define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)        /*!< 0x20000000 */
7861 #define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
7862 #define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
7863 #define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)        /*!< 0x40000000 */
7864 #define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
7865 
7866 #define HRTIM_RSTER_TIMFCMP2_Pos       (31U)
7867 #define HRTIM_RSTER_TIMFCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos)       /*!< 0x80000000 */
7868 #define HRTIM_RSTER_TIMFCMP2           HRTIM_RSTER_TIMFCMP2_Msk                  /*!< Timer F compare 2 */
7869 
7870 /* Slave Timer F reset enable bits upon other slave timers events */
7871 #define HRTIM_RSTFR_TIMACMP1_Pos       (19U)
7872 #define HRTIM_RSTFR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos)        /*!< 0x00080000 */
7873 #define HRTIM_RSTFR_TIMACMP1           HRTIM_RSTFR_TIMACMP1_Msk                  /*!< Timer A compare 1 */
7874 #define HRTIM_RSTFR_TIMACMP2_Pos       (20U)
7875 #define HRTIM_RSTFR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos)        /*!< 0x00100000 */
7876 #define HRTIM_RSTFR_TIMACMP2           HRTIM_RSTFR_TIMACMP2_Msk                  /*!< Timer A compare 2 */
7877 #define HRTIM_RSTFR_TIMACMP4_Pos       (21U)
7878 #define HRTIM_RSTFR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos)        /*!< 0x00200000 */
7879 #define HRTIM_RSTFR_TIMACMP4           HRTIM_RSTFR_TIMACMP4_Msk                  /*!< Timer A compare 4 */
7880 
7881 #define HRTIM_RSTFR_TIMBCMP1_Pos       (22U)
7882 #define HRTIM_RSTFR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos)        /*!< 0x00400000 */
7883 #define HRTIM_RSTFR_TIMBCMP1           HRTIM_RSTFR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
7884 #define HRTIM_RSTFR_TIMBCMP2_Pos       (23U)
7885 #define HRTIM_RSTFR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos)        /*!< 0x00800000 */
7886 #define HRTIM_RSTFR_TIMBCMP2           HRTIM_RSTFR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
7887 #define HRTIM_RSTFR_TIMBCMP4_Pos       (24U)
7888 #define HRTIM_RSTFR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos)        /*!< 0x01000000 */
7889 #define HRTIM_RSTFR_TIMBCMP4           HRTIM_RSTFR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
7890 
7891 #define HRTIM_RSTFR_TIMCCMP1_Pos       (25U)
7892 #define HRTIM_RSTFR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos)        /*!< 0x02000000 */
7893 #define HRTIM_RSTFR_TIMCCMP1           HRTIM_RSTFR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
7894 #define HRTIM_RSTFR_TIMCCMP2_Pos       (26U)
7895 #define HRTIM_RSTFR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos)        /*!< 0x04000000 */
7896 #define HRTIM_RSTFR_TIMCCMP2           HRTIM_RSTFR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
7897 #define HRTIM_RSTFR_TIMCCMP4_Pos       (27U)
7898 #define HRTIM_RSTFR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos)        /*!< 0x08000000 */
7899 #define HRTIM_RSTFR_TIMCCMP4           HRTIM_RSTFR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
7900 
7901 #define HRTIM_RSTFR_TIMDCMP1_Pos       (28U)
7902 #define HRTIM_RSTFR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos)        /*!< 0x10000000 */
7903 #define HRTIM_RSTFR_TIMDCMP1           HRTIM_RSTFR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
7904 #define HRTIM_RSTFR_TIMDCMP2_Pos       (29U)
7905 #define HRTIM_RSTFR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos)        /*!< 0x20000000 */
7906 #define HRTIM_RSTFR_TIMDCMP2           HRTIM_RSTFR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
7907 #define HRTIM_RSTFR_TIMDCMP4_Pos       (30U)
7908 #define HRTIM_RSTFR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos)        /*!< 0x40000000 */
7909 #define HRTIM_RSTFR_TIMDCMP4           HRTIM_RSTFR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
7910 
7911 #define HRTIM_RSTFR_TIMECMP2_Pos       (31U)
7912 #define HRTIM_RSTFR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos)       /*!< 0x80000000 */
7913 #define HRTIM_RSTFR_TIMECMP2           HRTIM_RSTFR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
7914 
7915 /**** Bit definition for Slave Timer Chopper register *************************/
7916 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
7917 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
7918 #define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
7919 #define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000001 */
7920 #define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000002 */
7921 #define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000004 */
7922 #define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x00000008 */
7923 
7924 #define HRTIM_CHPR_CARDTY_Pos         (4U)
7925 #define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
7926 #define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
7927 #define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000010 */
7928 #define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000020 */
7929 #define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000040 */
7930 
7931 #define HRTIM_CHPR_STRPW_Pos          (7U)
7932 #define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
7933 #define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
7934 #define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000080 */
7935 #define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000100 */
7936 #define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000200 */
7937 #define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000400 */
7938 
7939 /**** Bit definition for Slave Timer Capture 1 control register ***************/
7940 #define HRTIM_CPT1CR_SWCPT_Pos        (0U)
7941 #define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
7942 #define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
7943 #define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
7944 #define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
7945 #define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
7946 #define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
7947 #define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
7948 #define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
7949 #define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
7950 #define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
7951 #define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
7952 #define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
7953 #define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
7954 #define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
7955 #define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
7956 #define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
7957 #define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
7958 #define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
7959 #define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
7960 #define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
7961 #define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
7962 #define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
7963 #define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
7964 #define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
7965 #define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
7966 #define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
7967 #define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
7968 #define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
7969 #define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
7970 #define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
7971 #define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
7972 #define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
7973 #define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
7974 #define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
7975 #define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
7976 
7977 #define HRTIM_CPT1CR_TF1SET_Pos       (0U)
7978 #define HRTIM_CPT1CR_TF1SET_Msk       (0x1UL << HRTIM_CPT1CR_TF1SET_Pos)       /*!< 0x00000001 */
7979 #define HRTIM_CPT1CR_TF1SET           HRTIM_CPT1CR_TF1SET_Msk                  /*!< Timer F output 1 set */
7980 #define HRTIM_CPT1CR_TF1RST_Pos       (1U)
7981 #define HRTIM_CPT1CR_TF1RST_Msk       (0x1UL << HRTIM_CPT1CR_TF1RST_Pos)       /*!< 0x00000002 */
7982 #define HRTIM_CPT1CR_TF1RST           HRTIM_CPT1CR_TF1RST_Msk                  /*!< Timer F output 1 reset */
7983 #define HRTIM_CPT1CR_TIMFCMP1_Pos     (2U)
7984 #define HRTIM_CPT1CR_TIMFCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos)     /*!< 0x00000004 */
7985 #define HRTIM_CPT1CR_TIMFCMP1         HRTIM_CPT1CR_TIMFCMP1_Msk                /*!< Timer F compare 1 */
7986 #define HRTIM_CPT1CR_TIMFCMP2_Pos     (3U)
7987 #define HRTIM_CPT1CR_TIMFCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos)     /*!< 0x00000008 */
7988 #define HRTIM_CPT1CR_TIMFCMP2         HRTIM_CPT1CR_TIMFCMP2_Msk                /*!< Timer F compare 2 */
7989 
7990 #define HRTIM_CPT1CR_TA1SET_Pos       (12U)
7991 #define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
7992 #define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
7993 #define HRTIM_CPT1CR_TA1RST_Pos       (13U)
7994 #define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
7995 #define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
7996 #define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
7997 #define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
7998 #define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
7999 #define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
8000 #define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
8001 #define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
8002 
8003 #define HRTIM_CPT1CR_TB1SET_Pos       (16U)
8004 #define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
8005 #define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
8006 #define HRTIM_CPT1CR_TB1RST_Pos       (17U)
8007 #define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
8008 #define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
8009 #define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
8010 #define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
8011 #define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
8012 #define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
8013 #define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
8014 #define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
8015 
8016 #define HRTIM_CPT1CR_TC1SET_Pos       (20U)
8017 #define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
8018 #define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
8019 #define HRTIM_CPT1CR_TC1RST_Pos       (21U)
8020 #define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
8021 #define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
8022 #define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
8023 #define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
8024 #define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
8025 #define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
8026 #define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
8027 #define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
8028 
8029 #define HRTIM_CPT1CR_TD1SET_Pos       (24U)
8030 #define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
8031 #define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
8032 #define HRTIM_CPT1CR_TD1RST_Pos       (25U)
8033 #define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
8034 #define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
8035 #define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
8036 #define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
8037 #define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
8038 #define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
8039 #define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
8040 #define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
8041 
8042 #define HRTIM_CPT1CR_TE1SET_Pos       (28U)
8043 #define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
8044 #define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
8045 #define HRTIM_CPT1CR_TE1RST_Pos       (29U)
8046 #define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
8047 #define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
8048 #define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
8049 #define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
8050 #define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
8051 #define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
8052 #define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
8053 #define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
8054 
8055 /**** Bit definition for Slave Timer Capture 2 control register ***************/
8056 #define HRTIM_CPT2CR_SWCPT_Pos        (0U)
8057 #define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
8058 #define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
8059 #define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
8060 #define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
8061 #define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
8062 #define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
8063 #define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
8064 #define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
8065 #define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
8066 #define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
8067 #define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
8068 #define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
8069 #define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
8070 #define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
8071 #define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
8072 #define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
8073 #define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
8074 #define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
8075 #define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
8076 #define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
8077 #define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
8078 #define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
8079 #define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
8080 #define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
8081 #define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
8082 #define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
8083 #define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
8084 #define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
8085 #define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
8086 #define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
8087 #define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
8088 #define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
8089 #define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
8090 #define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
8091 #define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
8092 
8093 #define HRTIM_CPT2CR_TF1SET_Pos       (0U)
8094 #define HRTIM_CPT2CR_TF1SET_Msk       (0x1UL << HRTIM_CPT2CR_TF1SET_Pos)       /*!< 0x00000001 */
8095 #define HRTIM_CPT2CR_TF1SET           HRTIM_CPT2CR_TF1SET_Msk                  /*!< Timer F output 1 set */
8096 #define HRTIM_CPT2CR_TF1RST_Pos       (1U)
8097 #define HRTIM_CPT2CR_TF1RST_Msk       (0x1UL << HRTIM_CPT2CR_TF1RST_Pos)       /*!< 0x00000002 */
8098 #define HRTIM_CPT2CR_TF1RST           HRTIM_CPT2CR_TF1RST_Msk                  /*!< Timer F output 1 reset */
8099 #define HRTIM_CPT2CR_TIMFCMP1_Pos     (2U)
8100 #define HRTIM_CPT2CR_TIMFCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos)     /*!< 0x00000004 */
8101 #define HRTIM_CPT2CR_TIMFCMP1         HRTIM_CPT2CR_TIMFCMP1_Msk                /*!< Timer F compare 1 */
8102 #define HRTIM_CPT2CR_TIMFCMP2_Pos     (3U)
8103 #define HRTIM_CPT2CR_TIMFCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos)     /*!< 0x00000008 */
8104 #define HRTIM_CPT2CR_TIMFCMP2         HRTIM_CPT2CR_TIMFCMP2_Msk                /*!< Timer F compare 2 */
8105 
8106 #define HRTIM_CPT2CR_TA1SET_Pos       (12U)
8107 #define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
8108 #define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
8109 #define HRTIM_CPT2CR_TA1RST_Pos       (13U)
8110 #define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
8111 #define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
8112 #define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
8113 #define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
8114 #define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
8115 #define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
8116 #define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
8117 #define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
8118 
8119 #define HRTIM_CPT2CR_TB1SET_Pos       (16U)
8120 #define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
8121 #define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
8122 #define HRTIM_CPT2CR_TB1RST_Pos       (17U)
8123 #define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
8124 #define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
8125 #define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
8126 #define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
8127 #define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
8128 #define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
8129 #define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
8130 #define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
8131 
8132 #define HRTIM_CPT2CR_TC1SET_Pos       (20U)
8133 #define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
8134 #define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
8135 #define HRTIM_CPT2CR_TC1RST_Pos       (21U)
8136 #define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
8137 #define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
8138 #define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
8139 #define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
8140 #define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
8141 #define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
8142 #define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
8143 #define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
8144 
8145 #define HRTIM_CPT2CR_TD1SET_Pos       (24U)
8146 #define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
8147 #define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
8148 #define HRTIM_CPT2CR_TD1RST_Pos       (25U)
8149 #define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
8150 #define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
8151 #define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
8152 #define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
8153 #define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
8154 #define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
8155 #define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
8156 #define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
8157 
8158 #define HRTIM_CPT2CR_TE1SET_Pos       (28U)
8159 #define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
8160 #define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
8161 #define HRTIM_CPT2CR_TE1RST_Pos       (29U)
8162 #define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
8163 #define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
8164 #define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
8165 #define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
8166 #define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
8167 #define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
8168 #define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
8169 #define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
8170 
8171 /**** Bit definition for Slave Timer Output register **************************/
8172 #define HRTIM_OUTR_POL1_Pos           (1U)
8173 #define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
8174 #define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
8175 #define HRTIM_OUTR_IDLM1_Pos          (2U)
8176 #define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
8177 #define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
8178 #define HRTIM_OUTR_IDLES1_Pos         (3U)
8179 #define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
8180 #define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
8181 #define HRTIM_OUTR_FAULT1_Pos         (4U)
8182 #define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
8183 #define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
8184 #define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000010 */
8185 #define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000020 */
8186 #define HRTIM_OUTR_CHP1_Pos           (6U)
8187 #define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
8188 #define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
8189 #define HRTIM_OUTR_DIDL1_Pos          (7U)
8190 #define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
8191 #define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
8192 
8193 #define HRTIM_OUTR_DTEN_Pos           (8U)
8194 #define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
8195 #define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
8196 #define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
8197 #define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
8198 #define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
8199 #define HRTIM_OUTR_DLYPRT_Pos         (10U)
8200 #define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
8201 #define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
8202 #define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00000400 */
8203 #define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00000800 */
8204 #define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001000 */
8205 #define HRTIM_OUTR_BIAR_Pos           (14U)
8206 #define HRTIM_OUTR_BIAR_Msk           (0x1UL << HRTIM_OUTR_BIAR_Pos)           /*!< 0x00004000 */
8207 #define HRTIM_OUTR_BIAR               HRTIM_OUTR_BIAR_Msk                      /*!< Slave output Balanced Idle Automatic resume */
8208 #define HRTIM_OUTR_POL2_Pos           (17U)
8209 #define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
8210 #define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
8211 #define HRTIM_OUTR_IDLM2_Pos          (18U)
8212 #define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
8213 #define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
8214 #define HRTIM_OUTR_IDLES2_Pos         (19U)
8215 #define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
8216 #define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
8217 #define HRTIM_OUTR_FAULT2_Pos         (20U)
8218 #define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
8219 #define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
8220 #define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00100000 */
8221 #define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00200000 */
8222 #define HRTIM_OUTR_CHP2_Pos           (22U)
8223 #define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
8224 #define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
8225 #define HRTIM_OUTR_DIDL2_Pos          (23U)
8226 #define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
8227 #define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
8228 
8229 /**** Bit definition for Timerx Fault register ***************************/
8230 #define HRTIM_FLTR_FLT1EN_Pos         (0U)
8231 #define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
8232 #define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
8233 #define HRTIM_FLTR_FLT2EN_Pos         (1U)
8234 #define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
8235 #define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
8236 #define HRTIM_FLTR_FLT3EN_Pos         (2U)
8237 #define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
8238 #define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
8239 #define HRTIM_FLTR_FLT4EN_Pos         (3U)
8240 #define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
8241 #define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
8242 #define HRTIM_FLTR_FLT5EN_Pos         (4U)
8243 #define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
8244 #define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
8245 #define HRTIM_FLTR_FLT6EN_Pos         (5U)
8246 #define HRTIM_FLTR_FLT6EN_Msk         (0x1UL << HRTIM_FLTR_FLT6EN_Pos)         /*!< 0x00000020 */
8247 #define HRTIM_FLTR_FLT6EN             HRTIM_FLTR_FLT6EN_Msk                    /*!< Fault 6 enable */
8248 #define HRTIM_FLTR_FLTLCK_Pos         (31U)
8249 #define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
8250 #define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
8251 
8252 /**** Bit definition for HRTIM Timerx control register 2 ****************/
8253 #define HRTIM_TIMCR2_DCDE_Pos           (0U)
8254 #define HRTIM_TIMCR2_DCDE_Msk           (0x1UL << HRTIM_TIMCR2_DCDE_Pos)           /*!< 0x00000001 */
8255 #define HRTIM_TIMCR2_DCDE               HRTIM_TIMCR2_DCDE_Msk                      /*!< Dual Channel DAC trigger enable */
8256 #define HRTIM_TIMCR2_DCDS_Pos           (1U)
8257 #define HRTIM_TIMCR2_DCDS_Msk           (0x1UL << HRTIM_TIMCR2_DCDS_Pos)           /*!< 0x00000002 */
8258 #define HRTIM_TIMCR2_DCDS               HRTIM_TIMCR2_DCDS_Msk                      /*!< Dual Channel DAC step trigger */
8259 #define HRTIM_TIMCR2_DCDR_Pos           (2U)
8260 #define HRTIM_TIMCR2_DCDR_Msk           (0x1UL << HRTIM_TIMCR2_DCDR_Pos)           /*!< 0x00000004 */
8261 #define HRTIM_TIMCR2_DCDR               HRTIM_TIMCR2_DCDR_Msk                      /*!< Dual Channel DAC reset trigger */
8262 #define HRTIM_TIMCR2_UDM_Pos           (4U)
8263 #define HRTIM_TIMCR2_UDM_Msk           (0x1UL << HRTIM_TIMCR2_UDM_Pos)             /*!< 0x00000010 */
8264 #define HRTIM_TIMCR2_UDM               HRTIM_TIMCR2_UDM_Msk                        /*!< Up-Down Mode*/
8265 #define HRTIM_TIMCR2_ROM_Pos           (6U)
8266 #define HRTIM_TIMCR2_ROM_Msk           (0x3UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x000000C0 */
8267 #define HRTIM_TIMCR2_ROM               HRTIM_TIMCR2_ROM_Msk                        /*!< Roll-over Mode */
8268 #define HRTIM_TIMCR2_ROM_0             (0x1UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x00000040 */
8269 #define HRTIM_TIMCR2_ROM_1             (0x2UL << HRTIM_TIMCR2_ROM_Pos)             /*!< 0x00000080 */
8270 #define HRTIM_TIMCR2_OUTROM_Pos        (8U)
8271 #define HRTIM_TIMCR2_OUTROM_Msk        (0x3UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000300 */
8272 #define HRTIM_TIMCR2_OUTROM            HRTIM_TIMCR2_OUTROM_Msk                     /*!< Output Roll-Over Mode */
8273 #define HRTIM_TIMCR2_OUTROM_0          (0x1UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000100 */
8274 #define HRTIM_TIMCR2_OUTROM_1          (0x2UL << HRTIM_TIMCR2_OUTROM_Pos)          /*!< 0x00000200 */
8275 #define HRTIM_TIMCR2_ADROM_Pos         (10U)
8276 #define HRTIM_TIMCR2_ADROM_Msk         (0x3UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000C00 */
8277 #define HRTIM_TIMCR2_ADROM             HRTIM_TIMCR2_ADROM_Msk                      /*!< ADC Roll-Over Mode */
8278 #define HRTIM_TIMCR2_ADROM_0           (0x1UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000400 */
8279 #define HRTIM_TIMCR2_ADROM_1           (0x2UL << HRTIM_TIMCR2_ADROM_Pos)           /*!< 0x00000800 */
8280 #define HRTIM_TIMCR2_BMROM_Pos         (12U)
8281 #define HRTIM_TIMCR2_BMROM_Msk         (0x3UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00003000 */
8282 #define HRTIM_TIMCR2_BMROM             HRTIM_TIMCR2_BMROM_Msk                      /*!< Burst Mode Rollover Mode */
8283 #define HRTIM_TIMCR2_BMROM_0           (0x1UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00001000 */
8284 #define HRTIM_TIMCR2_BMROM_1           (0x2UL << HRTIM_TIMCR2_BMROM_Pos)           /*!< 0x00002000 */
8285 #define HRTIM_TIMCR2_FEROM_Pos         (14U)
8286 #define HRTIM_TIMCR2_FEROM_Msk         (0x3UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x0000C000 */
8287 #define HRTIM_TIMCR2_FEROM             HRTIM_TIMCR2_FEROM_Msk                      /*!< Fault and Event Rollover Mode */
8288 #define HRTIM_TIMCR2_FEROM_0           (0x1UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x00004000 */
8289 #define HRTIM_TIMCR2_FEROM_1           (0x2UL << HRTIM_TIMCR2_FEROM_Pos)           /*!< 0x00008000 */
8290 #define HRTIM_TIMCR2_GTCMP1_Pos        (16U)
8291 #define HRTIM_TIMCR2_GTCMP1_Msk        (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos)          /*!< 0x00010000 */
8292 #define HRTIM_TIMCR2_GTCMP1            HRTIM_TIMCR2_GTCMP1_Msk                     /*!< Greater than Compare 1 PWM mode */
8293 #define HRTIM_TIMCR2_GTCMP3_Pos        (17U)
8294 #define HRTIM_TIMCR2_GTCMP3_Msk        (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos)          /*!< 0x00020000 */
8295 #define HRTIM_TIMCR2_GTCMP3            HRTIM_TIMCR2_GTCMP3_Msk                     /*!< Greater than Compare 3 PWM mode */
8296 #define HRTIM_TIMCR2_TRGHLF_Pos        (20U)
8297 #define HRTIM_TIMCR2_TRGHLF_Msk        (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos)          /*!< 0x00100000 */
8298 #define HRTIM_TIMCR2_TRGHLF            HRTIM_TIMCR2_TRGHLF_Msk                     /*!< Triggered-Half mode */
8299 
8300 /**** Bit definition for Slave external event filtering  register 3 ***********/
8301 #define HRTIM_EEFR3_EEVACE_Pos        (0U)
8302 #define HRTIM_EEFR3_EEVACE_Msk        (0x1UL << HRTIM_EEFR3_EEVACE_Pos)       /*!< 0x00000001 */
8303 #define HRTIM_EEFR3_EEVACE            HRTIM_EEFR3_EEVACE_Msk                  /*!< External Event A Counter Enable */
8304 #define HRTIM_EEFR3_EEVACRES_Pos      (1U)
8305 #define HRTIM_EEFR3_EEVACRES_Msk      (0x1UL << HRTIM_EEFR3_EEVACRES_Pos)     /*!< 0x00000002 */
8306 #define HRTIM_EEFR3_EEVACRES          HRTIM_EEFR3_EEVACRES_Msk                /*!< External Event A Counter Reset */
8307 #define HRTIM_EEFR3_EEVARSTM_Pos      (2U)
8308 #define HRTIM_EEFR3_EEVARSTM_Msk      (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos)     /*!< 0x00000004 */
8309 #define HRTIM_EEFR3_EEVARSTM          HRTIM_EEFR3_EEVARSTM_Msk                /*!< External Event A Counter Reset Mode */
8310 #define HRTIM_EEFR3_EEVASEL_Pos       (4U)
8311 #define HRTIM_EEFR3_EEVASEL_Msk       (0xFUL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x000000F0 */
8312 #define HRTIM_EEFR3_EEVASEL           HRTIM_EEFR3_EEVASEL_Msk                 /*!< External Event A Selection */
8313 #define HRTIM_EEFR3_EEVASEL_0         (0x1UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000010 */
8314 #define HRTIM_EEFR3_EEVASEL_1         (0x2UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000020 */
8315 #define HRTIM_EEFR3_EEVASEL_2         (0x4UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000040 */
8316 #define HRTIM_EEFR3_EEVASEL_3         (0x8UL << HRTIM_EEFR3_EEVASEL_Pos)      /*!< 0x00000080 */
8317 #define HRTIM_EEFR3_EEVACNT_Pos       (8U)
8318 #define HRTIM_EEFR3_EEVACNT_Msk       (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00003F00 */
8319 #define HRTIM_EEFR3_EEVACNT           HRTIM_EEFR3_EEVACNT_Msk                 /*!< External Event A Selection */
8320 #define HRTIM_EEFR3_EEVACNT_0         (0x1UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000100 */
8321 #define HRTIM_EEFR3_EEVACNT_1         (0x2UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000200 */
8322 #define HRTIM_EEFR3_EEVACNT_2         (0x4UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000400 */
8323 #define HRTIM_EEFR3_EEVACNT_3         (0x8UL << HRTIM_EEFR3_EEVACNT_Pos)      /*!< 0x00000800 */
8324 #define HRTIM_EEFR3_EEVACNT_4         (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00001000 */
8325 #define HRTIM_EEFR3_EEVACNT_5         (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x00002000 */
8326 #define HRTIM_EEFR3_EEVBCE_Pos        (16U)
8327 #define HRTIM_EEFR3_EEVBCE_Msk        (0x1UL << HRTIM_EEFR3_EEVBCE_Pos)       /*!< 0x00010000 */
8328 #define HRTIM_EEFR3_EEVBCE            HRTIM_EEFR3_EEVBCE_Msk                  /*!< External Event B Counter Enable */
8329 #define HRTIM_EEFR3_EEVBCRES_Pos      (17U)
8330 #define HRTIM_EEFR3_EEVBCRES_Msk      (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos)     /*!< 0x00020000 */
8331 #define HRTIM_EEFR3_EEVBCRES          HRTIM_EEFR3_EEVBCRES_Msk                /*!< External Event B Counter Reset */
8332 #define HRTIM_EEFR3_EEVBRSTM_Pos      (18U)
8333 #define HRTIM_EEFR3_EEVBRSTM_Msk      (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos)     /*!< 0x00040000 */
8334 #define HRTIM_EEFR3_EEVBRSTM          HRTIM_EEFR3_EEVBRSTM_Msk                /*!< External Event B Counter Reset Mode */
8335 #define HRTIM_EEFR3_EEVBSEL_Pos       (20U)
8336 #define HRTIM_EEFR3_EEVBSEL_Msk       (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00F00000 */
8337 #define HRTIM_EEFR3_EEVBSEL           HRTIM_EEFR3_EEVBSEL_Msk                 /*!< External Event B Selection */
8338 #define HRTIM_EEFR3_EEVBSEL_0         (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00100000 */
8339 #define HRTIM_EEFR3_EEVBSEL_1         (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00200000 */
8340 #define HRTIM_EEFR3_EEVBSEL_2         (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00400000 */
8341 #define HRTIM_EEFR3_EEVBSEL_3         (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos)      /*!< 0x00800000 */
8342 #define HRTIM_EEFR3_EEVBCNT_Pos       (24U)
8343 #define HRTIM_EEFR3_EEVBCNT_Msk       (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos)     /*!< 0x3F000000 */
8344 #define HRTIM_EEFR3_EEVBCNT           HRTIM_EEFR3_EEVBCNT_Msk                 /*!< External Event B Counter */
8345 #define HRTIM_EEFR3_EEVBCNT_0         (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x01000000 */
8346 #define HRTIM_EEFR3_EEVBCNT_1         (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x02000000 */
8347 #define HRTIM_EEFR3_EEVBCNT_2         (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x04000000 */
8348 #define HRTIM_EEFR3_EEVBCNT_3         (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos)      /*!< 0x08000000 */
8349 #define HRTIM_EEFR3_EEVBCNT_4         (0x10UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x10000000 */
8350 #define HRTIM_EEFR3_EEVBCNT_5         (0x20UL << HRTIM_EEFR3_EEVACNT_Pos)     /*!< 0x20000000 */
8351 
8352 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
8353 #define HRTIM_CR1_MUDIS_Pos           (0U)
8354 #define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)          /*!< 0x00000001 */
8355 #define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                     /*!< Master update disable*/
8356 #define HRTIM_CR1_TAUDIS_Pos          (1U)
8357 #define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)         /*!< 0x00000002 */
8358 #define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                    /*!< Timer A update disable*/
8359 #define HRTIM_CR1_TBUDIS_Pos          (2U)
8360 #define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)         /*!< 0x00000004 */
8361 #define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                    /*!< Timer B update disable*/
8362 #define HRTIM_CR1_TCUDIS_Pos          (3U)
8363 #define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)         /*!< 0x00000008 */
8364 #define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                    /*!< Timer C update disable*/
8365 #define HRTIM_CR1_TDUDIS_Pos          (4U)
8366 #define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)         /*!< 0x00000010 */
8367 #define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                    /*!< Timer D update disable*/
8368 #define HRTIM_CR1_TEUDIS_Pos          (5U)
8369 #define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)         /*!< 0x00000020 */
8370 #define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                    /*!< Timer E update disable*/
8371 #define HRTIM_CR1_TFUDIS_Pos          (6U)
8372 #define HRTIM_CR1_TFUDIS_Msk          (0x1UL << HRTIM_CR1_TFUDIS_Pos)         /*!< 0x00000040 */
8373 #define HRTIM_CR1_TFUDIS              HRTIM_CR1_TFUDIS_Msk                    /*!< Timer F update disable*/
8374 #define HRTIM_CR1_ADC1USRC_Pos        (16U)
8375 #define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00070000 */
8376 #define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                  /*!< ADC Trigger 1 update source */
8377 #define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00010000 */
8378 #define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00020000 */
8379 #define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)       /*!< 0x00040000 */
8380 #define HRTIM_CR1_ADC2USRC_Pos        (19U)
8381 #define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00380000 */
8382 #define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                  /*!< ADC Trigger 2 update source */
8383 #define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00080000 */
8384 #define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00100000 */
8385 #define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)       /*!< 0x00200000 */
8386 #define HRTIM_CR1_ADC3USRC_Pos        (22U)
8387 #define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x01C00000 */
8388 #define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                  /*!< ADC Trigger 3 update source */
8389 #define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x00400000 */
8390 #define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x00800000 */
8391 #define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)       /*!< 0x01000000 */
8392 #define HRTIM_CR1_ADC4USRC_Pos        (25U)
8393 #define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x0E000000 */
8394 #define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                  /*!< ADC Trigger 4 update source */
8395 #define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x02000000 */
8396 #define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x04000000 */
8397 #define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)       /*!< 0x0800000 */
8398 
8399 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
8400 #define HRTIM_CR2_MSWU_Pos            (0U)
8401 #define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)           /*!< 0x00000001 */
8402 #define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                      /*!< Master software update */
8403 #define HRTIM_CR2_TASWU_Pos           (1U)
8404 #define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)          /*!< 0x00000002 */
8405 #define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                     /*!< Timer A software update */
8406 #define HRTIM_CR2_TBSWU_Pos           (2U)
8407 #define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)          /*!< 0x00000004 */
8408 #define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                     /*!< Timer B software update */
8409 #define HRTIM_CR2_TCSWU_Pos           (3U)
8410 #define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)          /*!< 0x00000008 */
8411 #define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                     /*!< Timer C software update */
8412 #define HRTIM_CR2_TDSWU_Pos           (4U)
8413 #define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)          /*!< 0x00000010 */
8414 #define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                     /*!< Timer D software update */
8415 #define HRTIM_CR2_TESWU_Pos           (5U)
8416 #define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)          /*!< 0x00000020 */
8417 #define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                     /*!< Timer E software update */
8418 #define HRTIM_CR2_TFSWU_Pos           (6U)
8419 #define HRTIM_CR2_TFSWU_Msk           (0x1UL << HRTIM_CR2_TFSWU_Pos)          /*!< 0x00000040 */
8420 #define HRTIM_CR2_TFSWU               HRTIM_CR2_TFSWU_Msk                     /*!< Timer F software update */
8421 #define HRTIM_CR2_MRST_Pos            (8U)
8422 #define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)           /*!< 0x00000100 */
8423 #define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                      /*!< Master count software reset */
8424 #define HRTIM_CR2_TARST_Pos           (9U)
8425 #define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)          /*!< 0x00000200 */
8426 #define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                     /*!< Timer A count software reset */
8427 #define HRTIM_CR2_TBRST_Pos           (10U)
8428 #define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)          /*!< 0x00000400 */
8429 #define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                     /*!< Timer B count software reset */
8430 #define HRTIM_CR2_TCRST_Pos           (11U)
8431 #define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)          /*!< 0x00000800 */
8432 #define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                     /*!< Timer C count software reset */
8433 #define HRTIM_CR2_TDRST_Pos           (12U)
8434 #define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)          /*!< 0x00001000 */
8435 #define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                     /*!< Timer D count software reset */
8436 #define HRTIM_CR2_TERST_Pos           (13U)
8437 #define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)          /*!< 0x00002000 */
8438 #define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                     /*!< Timer E count software reset */
8439 #define HRTIM_CR2_TFRST_Pos           (14U)
8440 #define HRTIM_CR2_TFRST_Msk           (0x1UL << HRTIM_CR2_TFRST_Pos)          /*!< 0x00004000 */
8441 #define HRTIM_CR2_TFRST               HRTIM_CR2_TFRST_Msk                     /*!< Timer F count software reset */
8442 #define HRTIM_CR2_SWPA_Pos            (16U)
8443 #define HRTIM_CR2_SWPA_Msk            (0x1UL << HRTIM_CR2_SWPA_Pos)           /*!< 0x00010000 */
8444 #define HRTIM_CR2_SWPA                HRTIM_CR2_SWPA_Msk                      /*!< Timer A swap outputs */
8445 #define HRTIM_CR2_SWPB_Pos            (17U)
8446 #define HRTIM_CR2_SWPB_Msk            (0x1UL << HRTIM_CR2_SWPB_Pos)           /*!< 0x00020000 */
8447 #define HRTIM_CR2_SWPB                HRTIM_CR2_SWPB_Msk                      /*!< Timer B swap outputs */
8448 #define HRTIM_CR2_SWPC_Pos            (18U)
8449 #define HRTIM_CR2_SWPC_Msk            (0x1UL << HRTIM_CR2_SWPC_Pos)           /*!< 0x00040000 */
8450 #define HRTIM_CR2_SWPC                HRTIM_CR2_SWPC_Msk                      /*!< Timer C swap outputs */
8451 #define HRTIM_CR2_SWPD_Pos            (19U)
8452 #define HRTIM_CR2_SWPD_Msk            (0x1UL << HRTIM_CR2_SWPD_Pos)           /*!< 0x00080000 */
8453 #define HRTIM_CR2_SWPD                HRTIM_CR2_SWPD_Msk                      /*!< Timer D swap outputs */
8454 #define HRTIM_CR2_SWPE_Pos            (20U)
8455 #define HRTIM_CR2_SWPE_Msk            (0x1UL << HRTIM_CR2_SWPE_Pos)           /*!< 0x00100000 */
8456 #define HRTIM_CR2_SWPE                HRTIM_CR2_SWPE_Msk                      /*!< Timer E swap outputs */
8457 #define HRTIM_CR2_SWPF_Pos            (21U)
8458 #define HRTIM_CR2_SWPF_Msk            (0x1UL << HRTIM_CR2_SWPF_Pos)           /*!< 0x00200000 */
8459 #define HRTIM_CR2_SWPF                HRTIM_CR2_SWPF_Msk                      /*!< Timer F swap outputs */
8460 
8461 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
8462 #define HRTIM_ISR_FLT1_Pos            (0U)
8463 #define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
8464 #define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
8465 #define HRTIM_ISR_FLT2_Pos            (1U)
8466 #define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
8467 #define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
8468 #define HRTIM_ISR_FLT3_Pos            (2U)
8469 #define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
8470 #define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
8471 #define HRTIM_ISR_FLT4_Pos            (3U)
8472 #define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
8473 #define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
8474 #define HRTIM_ISR_FLT5_Pos            (4U)
8475 #define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
8476 #define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
8477 #define HRTIM_ISR_SYSFLT_Pos          (5U)
8478 #define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
8479 #define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
8480 #define HRTIM_ISR_FLT6_Pos            (6U)
8481 #define HRTIM_ISR_FLT6_Msk            (0x1UL << HRTIM_ISR_FLT6_Pos)            /*!< 0x00000040 */
8482 #define HRTIM_ISR_FLT6                HRTIM_ISR_FLT6_Msk                       /*!< Fault 6 interrupt flag */
8483 #define HRTIM_ISR_DLLRDY_Pos          (16U)
8484 #define HRTIM_ISR_DLLRDY_Msk          (0x1UL << HRTIM_ISR_DLLRDY_Pos)          /*!< 0x00010000 */
8485 #define HRTIM_ISR_DLLRDY              HRTIM_ISR_DLLRDY_Msk                     /*!< DLL ready interrupt flag */
8486 #define HRTIM_ISR_BMPER_Pos           (17U)
8487 #define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
8488 #define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
8489 
8490 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
8491 #define HRTIM_ICR_FLT1C_Pos           (0U)
8492 #define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
8493 #define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
8494 #define HRTIM_ICR_FLT2C_Pos           (1U)
8495 #define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
8496 #define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
8497 #define HRTIM_ICR_FLT3C_Pos           (2U)
8498 #define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
8499 #define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
8500 #define HRTIM_ICR_FLT4C_Pos           (3U)
8501 #define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
8502 #define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
8503 #define HRTIM_ICR_FLT5C_Pos           (4U)
8504 #define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
8505 #define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
8506 #define HRTIM_ICR_SYSFLTC_Pos         (5U)
8507 #define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
8508 #define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
8509 
8510 #define HRTIM_ICR_FLT6C_Pos           (6U)
8511 #define HRTIM_ICR_FLT6C_Msk           (0x1UL << HRTIM_ICR_FLT6C_Pos)           /*!< 0x00000040 */
8512 #define HRTIM_ICR_FLT6C               HRTIM_ICR_FLT6C_Msk                      /*!< Fault 6 interrupt flag clear */
8513 
8514 #define HRTIM_ICR_DLLRDYC_Pos         (16U)
8515 #define HRTIM_ICR_DLLRDYC_Msk         (0x1UL << HRTIM_ICR_DLLRDYC_Pos)         /*!< 0x00010000 */
8516 #define HRTIM_ICR_DLLRDYC             HRTIM_ICR_DLLRDYC_Msk                    /*!< DLL ready interrupt flag clear */
8517 #define HRTIM_ICR_BMPERC_Pos          (17U)
8518 #define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
8519 #define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
8520 
8521 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
8522 #define HRTIM_IER_FLT1_Pos            (0U)
8523 #define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
8524 #define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
8525 #define HRTIM_IER_FLT2_Pos            (1U)
8526 #define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
8527 #define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
8528 #define HRTIM_IER_FLT3_Pos            (2U)
8529 #define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
8530 #define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
8531 #define HRTIM_IER_FLT4_Pos            (3U)
8532 #define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
8533 #define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
8534 #define HRTIM_IER_FLT5_Pos            (4U)
8535 #define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
8536 #define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
8537 #define HRTIM_IER_SYSFLT_Pos          (5U)
8538 #define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
8539 #define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
8540 #define HRTIM_IER_FLT6_Pos            (6U)
8541 #define HRTIM_IER_FLT6_Msk            (0x1UL << HRTIM_IER_FLT6_Pos)            /*!< 0x00000040 */
8542 #define HRTIM_IER_FLT6                HRTIM_IER_FLT6_Msk                       /*!< Fault 6 interrupt enable */
8543 
8544 #define HRTIM_IER_DLLRDY_Pos          (16U)
8545 #define HRTIM_IER_DLLRDY_Msk          (0x1UL << HRTIM_IER_DLLRDY_Pos)          /*!< 0x00010000 */
8546 #define HRTIM_IER_DLLRDY              HRTIM_IER_DLLRDY_Msk                     /*!< DLL ready interrupt enable */
8547 #define HRTIM_IER_BMPER_Pos           (17U)
8548 #define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
8549 #define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
8550 
8551 /**** Bit definition for Common HRTIM Timer output enable register ************/
8552 #define HRTIM_OENR_TA1OEN_Pos         (0U)
8553 #define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
8554 #define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
8555 #define HRTIM_OENR_TA2OEN_Pos         (1U)
8556 #define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
8557 #define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
8558 #define HRTIM_OENR_TB1OEN_Pos         (2U)
8559 #define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
8560 #define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
8561 #define HRTIM_OENR_TB2OEN_Pos         (3U)
8562 #define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
8563 #define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
8564 #define HRTIM_OENR_TC1OEN_Pos         (4U)
8565 #define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
8566 #define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
8567 #define HRTIM_OENR_TC2OEN_Pos         (5U)
8568 #define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
8569 #define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
8570 #define HRTIM_OENR_TD1OEN_Pos         (6U)
8571 #define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
8572 #define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
8573 #define HRTIM_OENR_TD2OEN_Pos         (7U)
8574 #define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
8575 #define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
8576 #define HRTIM_OENR_TE1OEN_Pos         (8U)
8577 #define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
8578 #define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
8579 #define HRTIM_OENR_TE2OEN_Pos         (9U)
8580 #define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
8581 #define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
8582 #define HRTIM_OENR_TF1OEN_Pos         (10U)
8583 #define HRTIM_OENR_TF1OEN_Msk         (0x1UL << HRTIM_OENR_TF1OEN_Pos)         /*!< 0x00000400 */
8584 #define HRTIM_OENR_TF1OEN             HRTIM_OENR_TF1OEN_Msk                    /*!< Timer F Output 1 enable */
8585 #define HRTIM_OENR_TF2OEN_Pos         (11U)
8586 #define HRTIM_OENR_TF2OEN_Msk         (0x1UL << HRTIM_OENR_TF2OEN_Pos)         /*!< 0x00000800 */
8587 #define HRTIM_OENR_TF2OEN             HRTIM_OENR_TF2OEN_Msk                    /*!< Timer F Output 2 enable */
8588 
8589 /**** Bit definition for Common HRTIM Timer output disable register ***********/
8590 #define HRTIM_ODISR_TA1ODIS_Pos       (0U)
8591 #define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
8592 #define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
8593 #define HRTIM_ODISR_TA2ODIS_Pos       (1U)
8594 #define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
8595 #define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
8596 #define HRTIM_ODISR_TB1ODIS_Pos       (2U)
8597 #define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
8598 #define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
8599 #define HRTIM_ODISR_TB2ODIS_Pos       (3U)
8600 #define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
8601 #define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
8602 #define HRTIM_ODISR_TC1ODIS_Pos       (4U)
8603 #define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
8604 #define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
8605 #define HRTIM_ODISR_TC2ODIS_Pos       (5U)
8606 #define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
8607 #define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
8608 #define HRTIM_ODISR_TD1ODIS_Pos       (6U)
8609 #define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
8610 #define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
8611 #define HRTIM_ODISR_TD2ODIS_Pos       (7U)
8612 #define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
8613 #define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
8614 #define HRTIM_ODISR_TE1ODIS_Pos       (8U)
8615 #define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
8616 #define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
8617 #define HRTIM_ODISR_TE2ODIS_Pos       (9U)
8618 #define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
8619 #define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
8620 #define HRTIM_ODISR_TF1ODIS_Pos       (10U)
8621 #define HRTIM_ODISR_TF1ODIS_Msk       (0x1UL << HRTIM_ODISR_TF1ODIS_Pos)       /*!< 0x00000100 */
8622 #define HRTIM_ODISR_TF1ODIS           HRTIM_ODISR_TF1ODIS_Msk                  /*!< Timer F Output 1 disable */
8623 #define HRTIM_ODISR_TF2ODIS_Pos       (11U)
8624 #define HRTIM_ODISR_TF2ODIS_Msk       (0x1UL << HRTIM_ODISR_TF2ODIS_Pos)       /*!< 0x00000200 */
8625 #define HRTIM_ODISR_TF2ODIS           HRTIM_ODISR_TF2ODIS_Msk                  /*!< Timer F Output 2 disable */
8626 
8627 /**** Bit definition for Common HRTIM Timer output disable status register *****/
8628 #define HRTIM_ODSR_TA1ODS_Pos         (0U)
8629 #define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
8630 #define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
8631 #define HRTIM_ODSR_TA2ODS_Pos         (1U)
8632 #define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
8633 #define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
8634 #define HRTIM_ODSR_TB1ODS_Pos         (2U)
8635 #define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
8636 #define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
8637 #define HRTIM_ODSR_TB2ODS_Pos         (3U)
8638 #define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
8639 #define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
8640 #define HRTIM_ODSR_TC1ODS_Pos         (4U)
8641 #define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
8642 #define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
8643 #define HRTIM_ODSR_TC2ODS_Pos         (5U)
8644 #define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
8645 #define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
8646 #define HRTIM_ODSR_TD1ODS_Pos         (6U)
8647 #define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
8648 #define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
8649 #define HRTIM_ODSR_TD2ODS_Pos         (7U)
8650 #define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
8651 #define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
8652 #define HRTIM_ODSR_TE1ODS_Pos         (8U)
8653 #define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
8654 #define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
8655 #define HRTIM_ODSR_TE2ODS_Pos         (9U)
8656 #define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
8657 #define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
8658 #define HRTIM_ODSR_TF1ODS_Pos         (10U)
8659 #define HRTIM_ODSR_TF1ODS_Msk         (0x1UL << HRTIM_ODSR_TF1ODS_Pos)         /*!< 0x00000100 */
8660 #define HRTIM_ODSR_TF1ODS             HRTIM_ODSR_TF1ODS_Msk                    /*!< Timer F Output 1 disable status */
8661 #define HRTIM_ODSR_TF2ODS_Pos         (11U)
8662 #define HRTIM_ODSR_TF2ODS_Msk         (0x1UL << HRTIM_ODSR_TF2ODS_Pos)         /*!< 0x00000200 */
8663 #define HRTIM_ODSR_TF2ODS             HRTIM_ODSR_TF2ODS_Msk                    /*!< Timer F Output 2 disable status */
8664 
8665 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
8666 #define HRTIM_BMCR_BME_Pos            (0U)
8667 #define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
8668 #define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enable */
8669 #define HRTIM_BMCR_BMOM_Pos           (1U)
8670 #define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
8671 #define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
8672 #define HRTIM_BMCR_BMCLK_Pos          (2U)
8673 #define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
8674 #define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
8675 #define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000004 */
8676 #define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000008 */
8677 #define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000010 */
8678 #define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x00000020 */
8679 #define HRTIM_BMCR_BMPRSC_Pos         (6U)
8680 #define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
8681 #define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
8682 #define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000040 */
8683 #define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000080 */
8684 #define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000100 */
8685 #define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x00000200 */
8686 #define HRTIM_BMCR_BMPREN_Pos         (10U)
8687 #define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
8688 #define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
8689 #define HRTIM_BMCR_MTBM_Pos           (16U)
8690 #define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
8691 #define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
8692 #define HRTIM_BMCR_TABM_Pos           (17U)
8693 #define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
8694 #define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
8695 #define HRTIM_BMCR_TBBM_Pos           (18U)
8696 #define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
8697 #define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
8698 #define HRTIM_BMCR_TCBM_Pos           (19U)
8699 #define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
8700 #define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
8701 #define HRTIM_BMCR_TDBM_Pos           (20U)
8702 #define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
8703 #define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
8704 #define HRTIM_BMCR_TEBM_Pos           (21U)
8705 #define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
8706 #define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
8707 
8708 #define HRTIM_BMCR_TFBM_Pos           (22U)
8709 #define HRTIM_BMCR_TFBM_Msk           (0x1UL << HRTIM_BMCR_TFBM_Pos)           /*!< 0x00400000 */
8710 #define HRTIM_BMCR_TFBM               HRTIM_BMCR_TFBM_Msk                      /*!< Timer F Burst mode */
8711 
8712 #define HRTIM_BMCR_BMSTAT_Pos         (31U)
8713 #define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
8714 #define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
8715 
8716 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
8717 #define HRTIM_BMTRGR_SW_Pos           (0U)
8718 #define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
8719 #define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
8720 #define HRTIM_BMTRGR_MSTRST_Pos       (1U)
8721 #define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
8722 #define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
8723 #define HRTIM_BMTRGR_MSTREP_Pos       (2U)
8724 #define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
8725 #define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
8726 #define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
8727 #define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
8728 #define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
8729 #define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
8730 #define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
8731 #define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
8732 #define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
8733 #define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
8734 #define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
8735 #define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
8736 #define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
8737 #define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
8738 #define HRTIM_BMTRGR_TARST_Pos        (7U)
8739 #define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
8740 #define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
8741 #define HRTIM_BMTRGR_TAREP_Pos        (8U)
8742 #define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
8743 #define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
8744 #define HRTIM_BMTRGR_TACMP1_Pos       (9U)
8745 #define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
8746 #define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
8747 #define HRTIM_BMTRGR_TACMP2_Pos       (10U)
8748 #define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
8749 #define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
8750 #define HRTIM_BMTRGR_TBRST_Pos        (11U)
8751 #define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
8752 #define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
8753 #define HRTIM_BMTRGR_TBREP_Pos        (12U)
8754 #define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
8755 #define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
8756 #define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
8757 #define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
8758 #define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
8759 #define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
8760 #define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
8761 #define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
8762 #define HRTIM_BMTRGR_TCRST_Pos        (15U)
8763 #define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
8764 #define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
8765 #define HRTIM_BMTRGR_TCREP_Pos        (16U)
8766 #define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
8767 #define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
8768 #define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
8769 #define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
8770 #define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
8771 #define HRTIM_BMTRGR_TFRST_Pos        (18U)
8772 #define HRTIM_BMTRGR_TFRST_Msk        (0x1UL << HRTIM_BMTRGR_TFRST_Pos)        /*!< 0x00040000 */
8773 #define HRTIM_BMTRGR_TFRST            HRTIM_BMTRGR_TFRST_Msk                   /*!< Timer F reset */
8774 #define HRTIM_BMTRGR_TDRST_Pos        (19U)
8775 #define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
8776 #define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
8777 #define HRTIM_BMTRGR_TDREP_Pos        (20U)
8778 #define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
8779 #define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
8780 #define HRTIM_BMTRGR_TFREP_Pos        (21U)
8781 #define HRTIM_BMTRGR_TFREP_Msk        (0x1UL << HRTIM_BMTRGR_TFREP_Pos)        /*!< 0x00200000 */
8782 #define HRTIM_BMTRGR_TFREP            HRTIM_BMTRGR_TFREP_Msk                   /*!< Timer F repetition*/
8783 #define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
8784 #define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
8785 #define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
8786 #define HRTIM_BMTRGR_TFCMP1_Pos       (23U)
8787 #define HRTIM_BMTRGR_TFCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos)       /*!< 0x00800000 */
8788 #define HRTIM_BMTRGR_TFCMP1            HRTIM_BMTRGR_TFCMP1_Msk                 /*!< Timer F compare 1 */
8789 #define HRTIM_BMTRGR_TEREP_Pos        (24U)
8790 #define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
8791 #define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
8792 #define HRTIM_BMTRGR_TECMP1_Pos       (25U)
8793 #define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
8794 #define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
8795 #define HRTIM_BMTRGR_TECMP2_Pos       (26U)
8796 #define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
8797 #define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
8798 #define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
8799 #define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
8800 #define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
8801 #define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
8802 #define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
8803 #define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
8804 #define HRTIM_BMTRGR_EEV7_Pos         (29U)
8805 #define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
8806 #define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
8807 #define HRTIM_BMTRGR_EEV8_Pos         (30U)
8808 #define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
8809 #define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
8810 #define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
8811 #define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
8812 #define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
8813 
8814 /*******************  Bit definition for HRTIM_BMCMPR register  ***************/
8815 #define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
8816 #define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
8817 #define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
8818 
8819 /*******************  Bit definition for HRTIM_BMPER register  ****************/
8820 #define HRTIM_BMPER_BMPER_Pos         (0U)
8821 #define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
8822 #define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
8823 
8824 /*******************  Bit definition for HRTIM_EECR1 register  ****************/
8825 #define HRTIM_EECR1_EE1SRC_Pos        (0U)
8826 #define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
8827 #define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
8828 #define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000001 */
8829 #define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000002 */
8830 #define HRTIM_EECR1_EE1POL_Pos        (2U)
8831 #define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
8832 #define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
8833 #define HRTIM_EECR1_EE1SNS_Pos        (3U)
8834 #define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
8835 #define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
8836 #define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000008 */
8837 #define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000010 */
8838 #define HRTIM_EECR1_EE1FAST_Pos       (5U)
8839 #define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
8840 #define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
8841 
8842 #define HRTIM_EECR1_EE2SRC_Pos        (6U)
8843 #define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
8844 #define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
8845 #define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x00000040 */
8846 #define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x00000080 */
8847 #define HRTIM_EECR1_EE2POL_Pos        (8U)
8848 #define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
8849 #define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
8850 #define HRTIM_EECR1_EE2SNS_Pos        (9U)
8851 #define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
8852 #define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
8853 #define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000200 */
8854 #define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000400 */
8855 #define HRTIM_EECR1_EE2FAST_Pos       (11U)
8856 #define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
8857 #define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
8858 
8859 #define HRTIM_EECR1_EE3SRC_Pos        (12U)
8860 #define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
8861 #define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
8862 #define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00001000 */
8863 #define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00002000 */
8864 #define HRTIM_EECR1_EE3POL_Pos        (14U)
8865 #define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
8866 #define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
8867 #define HRTIM_EECR1_EE3SNS_Pos        (15U)
8868 #define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
8869 #define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
8870 #define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00008000 */
8871 #define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00010000 */
8872 #define HRTIM_EECR1_EE3FAST_Pos       (17U)
8873 #define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
8874 #define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
8875 
8876 #define HRTIM_EECR1_EE4SRC_Pos        (18U)
8877 #define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
8878 #define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
8879 #define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x00040000 */
8880 #define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x00080000 */
8881 #define HRTIM_EECR1_EE4POL_Pos        (20U)
8882 #define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
8883 #define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
8884 #define HRTIM_EECR1_EE4SNS_Pos        (21U)
8885 #define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
8886 #define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
8887 #define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00200000 */
8888 #define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00400000 */
8889 #define HRTIM_EECR1_EE4FAST_Pos       (23U)
8890 #define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
8891 #define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
8892 
8893 #define HRTIM_EECR1_EE5SRC_Pos        (24U)
8894 #define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
8895 #define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
8896 #define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x01000000 */
8897 #define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x02000000 */
8898 #define HRTIM_EECR1_EE5POL_Pos        (26U)
8899 #define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
8900 #define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
8901 #define HRTIM_EECR1_EE5SNS_Pos        (27U)
8902 #define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
8903 #define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
8904 #define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x08000000 */
8905 #define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x10000000 */
8906 #define HRTIM_EECR1_EE5FAST_Pos       (29U)
8907 #define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
8908 #define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
8909 
8910 /*******************  Bit definition for HRTIM_EECR2 register  ****************/
8911 #define HRTIM_EECR2_EE6SRC_Pos        (0U)
8912 #define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
8913 #define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
8914 #define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000001 */
8915 #define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000002 */
8916 #define HRTIM_EECR2_EE6POL_Pos        (2U)
8917 #define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
8918 #define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
8919 #define HRTIM_EECR2_EE6SNS_Pos        (3U)
8920 #define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
8921 #define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
8922 #define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000008 */
8923 #define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000010 */
8924 
8925 #define HRTIM_EECR2_EE7SRC_Pos        (6U)
8926 #define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
8927 #define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
8928 #define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x00000040 */
8929 #define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x00000080 */
8930 #define HRTIM_EECR2_EE7POL_Pos        (8U)
8931 #define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
8932 #define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
8933 #define HRTIM_EECR2_EE7SNS_Pos        (9U)
8934 #define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
8935 #define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
8936 #define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000200 */
8937 #define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000400 */
8938 
8939 #define HRTIM_EECR2_EE8SRC_Pos        (12U)
8940 #define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
8941 #define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
8942 #define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00001000 */
8943 #define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00002000 */
8944 #define HRTIM_EECR2_EE8POL_Pos        (14U)
8945 #define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
8946 #define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
8947 #define HRTIM_EECR2_EE8SNS_Pos        (15U)
8948 #define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
8949 #define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
8950 #define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00008000 */
8951 #define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00010000 */
8952 
8953 #define HRTIM_EECR2_EE9SRC_Pos        (18U)
8954 #define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
8955 #define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
8956 #define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x00040000 */
8957 #define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x00080000 */
8958 #define HRTIM_EECR2_EE9POL_Pos        (20U)
8959 #define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
8960 #define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
8961 #define HRTIM_EECR2_EE9SNS_Pos        (21U)
8962 #define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
8963 #define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
8964 #define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00200000 */
8965 #define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00400000 */
8966 
8967 #define HRTIM_EECR2_EE10SRC_Pos       (24U)
8968 #define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
8969 #define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
8970 #define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x01000000 */
8971 #define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x02000000 */
8972 #define HRTIM_EECR2_EE10POL_Pos       (26U)
8973 #define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
8974 #define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
8975 #define HRTIM_EECR2_EE10SNS_Pos       (27U)
8976 #define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
8977 #define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
8978 #define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x08000000 */
8979 #define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x10000000 */
8980 
8981 /*******************  Bit definition for HRTIM_EECR3 register  ****************/
8982 #define HRTIM_EECR3_EE6F_Pos          (0U)
8983 #define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
8984 #define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
8985 #define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000001 */
8986 #define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000002 */
8987 #define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000004 */
8988 #define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x00000008 */
8989 #define HRTIM_EECR3_EE7F_Pos          (6U)
8990 #define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
8991 #define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
8992 #define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000040 */
8993 #define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000080 */
8994 #define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000100 */
8995 #define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x00000200 */
8996 #define HRTIM_EECR3_EE8F_Pos          (12U)
8997 #define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
8998 #define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
8999 #define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00001000 */
9000 #define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00002000 */
9001 #define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00004000 */
9002 #define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x00008000 */
9003 #define HRTIM_EECR3_EE9F_Pos          (18U)
9004 #define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
9005 #define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
9006 #define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00040000 */
9007 #define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00080000 */
9008 #define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00100000 */
9009 #define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x00200000 */
9010 #define HRTIM_EECR3_EE10F_Pos         (24U)
9011 #define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
9012 #define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
9013 #define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x01000000 */
9014 #define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x02000000 */
9015 #define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x04000000 */
9016 #define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x08000000 */
9017 #define HRTIM_EECR3_EEVSD_Pos         (30U)
9018 #define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
9019 #define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
9020 #define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0x40000000 */
9021 #define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0x80000000 */
9022 
9023 /*******************  Bit definition for HRTIM_ADC1R register  ****************/
9024 #define HRTIM_ADC1R_AD1MC1_Pos        (0U)
9025 #define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
9026 #define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
9027 #define HRTIM_ADC1R_AD1MC2_Pos        (1U)
9028 #define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
9029 #define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
9030 #define HRTIM_ADC1R_AD1MC3_Pos        (2U)
9031 #define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
9032 #define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
9033 #define HRTIM_ADC1R_AD1MC4_Pos        (3U)
9034 #define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
9035 #define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
9036 #define HRTIM_ADC1R_AD1MPER_Pos       (4U)
9037 #define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
9038 #define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
9039 #define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
9040 #define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
9041 #define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
9042 #define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
9043 #define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
9044 #define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
9045 #define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
9046 #define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
9047 #define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
9048 #define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
9049 #define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
9050 #define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
9051 #define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
9052 #define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
9053 #define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
9054 
9055 #define HRTIM_ADC1R_AD1TFC2_Pos       (10U)
9056 #define HRTIM_ADC1R_AD1TFC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC2_Pos)       /*!< 0x00000400 */
9057 #define HRTIM_ADC1R_AD1TFC2           HRTIM_ADC1R_AD1TFC2_Msk                  /*!< ADC Trigger 1 on Timer F compare 2 */
9058 
9059 #define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
9060 #define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
9061 #define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
9062 #define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
9063 #define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
9064 #define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
9065 #define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
9066 #define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
9067 #define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
9068 #define HRTIM_ADC1R_AD1TARST_Pos      (14U)
9069 #define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
9070 #define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
9071 
9072 #define HRTIM_ADC1R_AD1TFC3_Pos       (15U)
9073 #define HRTIM_ADC1R_AD1TFC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC3_Pos)       /*!< 0x00008000 */
9074 #define HRTIM_ADC1R_AD1TFC3           HRTIM_ADC1R_AD1TFC3_Msk                  /*!< ADC Trigger 1 on Timer F compare 3 */
9075 
9076 #define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
9077 #define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
9078 #define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
9079 #define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
9080 #define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
9081 #define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
9082 #define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
9083 #define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
9084 #define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
9085 #define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
9086 #define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
9087 #define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
9088 
9089 #define HRTIM_ADC1R_AD1TFC4_Pos       (20U)
9090 #define HRTIM_ADC1R_AD1TFC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TFC4_Pos)       /*!< 0x00100000 */
9091 #define HRTIM_ADC1R_AD1TFC4           HRTIM_ADC1R_AD1TFC4_Msk                  /*!< ADC Trigger 1 on Timer F compare 4 */
9092 
9093 #define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
9094 #define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
9095 #define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
9096 #define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
9097 #define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
9098 #define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
9099 #define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
9100 #define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
9101 #define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
9102 
9103 #define HRTIM_ADC1R_AD1TFPER_Pos      (24U)
9104 #define HRTIM_ADC1R_AD1TFPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TFPER_Pos)      /*!< 0x01000000 */
9105 #define HRTIM_ADC1R_AD1TFPER          HRTIM_ADC1R_AD1TFPER_Msk                 /*!< ADC Trigger 1 on Timer F period */
9106 
9107 #define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
9108 #define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
9109 #define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
9110 #define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
9111 #define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
9112 #define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
9113 #define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
9114 #define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
9115 #define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
9116 
9117 #define HRTIM_ADC1R_AD1TFRST_Pos      (28U)
9118 #define HRTIM_ADC1R_AD1TFRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TFRST_Pos)      /*!< 0x10000000 */
9119 #define HRTIM_ADC1R_AD1TFRST          HRTIM_ADC1R_AD1TFRST_Msk                 /*!< ADC Trigger 1 on Timer F reset */
9120 
9121 #define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
9122 #define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
9123 #define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
9124 #define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
9125 #define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
9126 #define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
9127 #define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
9128 #define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
9129 #define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E compare period */
9130 
9131 /*******************  Bit definition for HRTIM_ADC2R register  ****************/
9132 #define HRTIM_ADC2R_AD2MC1_Pos        (0U)
9133 #define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
9134 #define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
9135 #define HRTIM_ADC2R_AD2MC2_Pos        (1U)
9136 #define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
9137 #define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
9138 #define HRTIM_ADC2R_AD2MC3_Pos        (2U)
9139 #define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
9140 #define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
9141 #define HRTIM_ADC2R_AD2MC4_Pos        (3U)
9142 #define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
9143 #define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
9144 #define HRTIM_ADC2R_AD2MPER_Pos       (4U)
9145 #define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
9146 #define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
9147 #define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
9148 #define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
9149 #define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
9150 #define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
9151 #define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
9152 #define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
9153 #define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
9154 #define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
9155 #define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
9156 #define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
9157 #define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
9158 #define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
9159 #define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
9160 #define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
9161 #define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
9162 #define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
9163 #define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
9164 #define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
9165 
9166 #define HRTIM_ADC2R_AD2TFC2_Pos       (11U)
9167 #define HRTIM_ADC2R_AD2TFC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC2_Pos)       /*!< 0x00000800 */
9168 #define HRTIM_ADC2R_AD2TFC2           HRTIM_ADC2R_AD2TFC2_Msk                  /*!< ADC Trigger 2 on Timer F compare 2 */
9169 
9170 #define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
9171 #define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
9172 #define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
9173 #define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
9174 #define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
9175 #define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
9176 #define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
9177 #define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
9178 #define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
9179 
9180 #define HRTIM_ADC2R_AD2TFC3_Pos       (15U)
9181 #define HRTIM_ADC2R_AD2TFC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC3_Pos)       /*!< 0x00008000 */
9182 #define HRTIM_ADC2R_AD2TFC3           HRTIM_ADC2R_AD2TFC3_Msk                  /*!< ADC Trigger 2 on Timer F compare 3 */
9183 
9184 #define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
9185 #define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
9186 #define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
9187 #define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
9188 #define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
9189 #define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
9190 #define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
9191 #define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
9192 #define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
9193 
9194 #define HRTIM_ADC2R_AD2TFC4_Pos       (19U)
9195 #define HRTIM_ADC2R_AD2TFC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TFC4_Pos)       /*!< 0x00080000 */
9196 #define HRTIM_ADC2R_AD2TFC4           HRTIM_ADC2R_AD2TFC4_Msk                  /*!< ADC Trigger 2 on Timer F compare 4 */
9197 
9198 #define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
9199 #define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
9200 #define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
9201 #define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
9202 #define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
9203 #define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
9204 #define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
9205 #define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
9206 #define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
9207 #define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
9208 #define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
9209 #define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
9210 
9211 #define HRTIM_ADC2R_AD2TFPER_Pos      (24U)
9212 #define HRTIM_ADC2R_AD2TFPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TFPER_Pos)      /*!< 0x01000000 */
9213 #define HRTIM_ADC2R_AD2TFPER          HRTIM_ADC2R_AD2TFPER_Msk                 /*!< ADC Trigger 2 on Timer F period */
9214 
9215 #define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
9216 #define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
9217 #define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
9218 #define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
9219 #define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
9220 #define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
9221 #define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
9222 #define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
9223 #define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
9224 #define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
9225 #define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
9226 #define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
9227 #define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
9228 #define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
9229 #define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
9230 #define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
9231 #define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
9232 #define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
9233 #define HRTIM_ADC2R_AD2TERST_Pos      (31U)
9234 #define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
9235 #define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
9236 
9237 /*******************  Bit definition for HRTIM_ADC3R register  ****************/
9238 #define HRTIM_ADC3R_AD3MC1_Pos        (0U)
9239 #define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
9240 #define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
9241 #define HRTIM_ADC3R_AD3MC2_Pos        (1U)
9242 #define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
9243 #define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
9244 #define HRTIM_ADC3R_AD3MC3_Pos        (2U)
9245 #define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
9246 #define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
9247 #define HRTIM_ADC3R_AD3MC4_Pos        (3U)
9248 #define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
9249 #define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
9250 #define HRTIM_ADC3R_AD3MPER_Pos       (4U)
9251 #define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
9252 #define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
9253 #define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
9254 #define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
9255 #define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
9256 #define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
9257 #define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
9258 #define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
9259 #define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
9260 #define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
9261 #define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
9262 #define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
9263 #define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
9264 #define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
9265 #define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
9266 #define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
9267 #define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
9268 
9269 #define HRTIM_ADC3R_AD3TFC2_Pos       (10U)
9270 #define HRTIM_ADC3R_AD3TFC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC2_Pos)       /*!< 0x00000400 */
9271 #define HRTIM_ADC3R_AD3TFC2           HRTIM_ADC3R_AD3TFC2_Msk                  /*!< ADC Trigger 3 on Timer F compare 2 */
9272 
9273 #define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
9274 #define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
9275 #define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
9276 #define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
9277 #define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
9278 #define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
9279 #define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
9280 #define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
9281 #define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
9282 #define HRTIM_ADC3R_AD3TARST_Pos      (14U)
9283 #define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
9284 #define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
9285 
9286 #define HRTIM_ADC3R_AD3TFC3_Pos       (15U)
9287 #define HRTIM_ADC3R_AD3TFC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC3_Pos)       /*!< 0x00008000 */
9288 #define HRTIM_ADC3R_AD3TFC3           HRTIM_ADC3R_AD3TFC3_Msk                  /*!< ADC Trigger 3 on Timer F compare 3 */
9289 
9290 #define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
9291 #define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
9292 #define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
9293 #define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
9294 #define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
9295 #define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
9296 #define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
9297 #define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
9298 #define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
9299 #define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
9300 #define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
9301 #define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
9302 
9303 #define HRTIM_ADC3R_AD3TFC4_Pos       (20U)
9304 #define HRTIM_ADC3R_AD3TFC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TFC4_Pos)       /*!< 0x00100000 */
9305 #define HRTIM_ADC3R_AD3TFC4           HRTIM_ADC3R_AD3TFC4_Msk                  /*!< ADC Trigger 3 on Timer F compare 4 */
9306 
9307 #define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
9308 #define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
9309 #define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
9310 #define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
9311 #define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
9312 #define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
9313 #define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
9314 #define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
9315 #define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
9316 
9317 #define HRTIM_ADC3R_AD3TFPER_Pos      (24U)
9318 #define HRTIM_ADC3R_AD3TFPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TFPER_Pos)      /*!< 0x01000000 */
9319 #define HRTIM_ADC3R_AD3TFPER          HRTIM_ADC3R_AD3TFPER_Msk                 /*!< ADC Trigger 3 on Timer F period */
9320 
9321 #define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
9322 #define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
9323 #define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
9324 #define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
9325 #define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
9326 #define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
9327 #define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
9328 #define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
9329 #define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
9330 
9331 #define HRTIM_ADC3R_AD3TFRST_Pos      (28U)
9332 #define HRTIM_ADC3R_AD3TFRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TFRST_Pos)      /*!< 0x10000000 */
9333 #define HRTIM_ADC3R_AD3TFRST          HRTIM_ADC3R_AD3TFRST_Msk                 /*!< ADC Trigger 3 on Timer F reset */
9334 
9335 #define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
9336 #define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
9337 #define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
9338 #define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
9339 #define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
9340 #define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
9341 #define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
9342 #define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
9343 #define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
9344 
9345 /*******************  Bit definition for HRTIM_ADC4R register  ****************/
9346 #define HRTIM_ADC4R_AD4MC1_Pos        (0U)
9347 #define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
9348 #define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
9349 #define HRTIM_ADC4R_AD4MC2_Pos        (1U)
9350 #define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
9351 #define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
9352 #define HRTIM_ADC4R_AD4MC3_Pos        (2U)
9353 #define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
9354 #define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
9355 #define HRTIM_ADC4R_AD4MC4_Pos        (3U)
9356 #define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
9357 #define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
9358 #define HRTIM_ADC4R_AD4MPER_Pos       (4U)
9359 #define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
9360 #define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
9361 #define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
9362 #define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
9363 #define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
9364 #define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
9365 #define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
9366 #define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
9367 #define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
9368 #define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
9369 #define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
9370 #define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
9371 #define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
9372 #define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
9373 #define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
9374 #define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
9375 #define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
9376 #define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
9377 #define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
9378 #define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
9379 
9380 #define HRTIM_ADC4R_AD4TFC2_Pos       (11U)
9381 #define HRTIM_ADC4R_AD4TFC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC2_Pos)       /*!< 0x00000800 */
9382 #define HRTIM_ADC4R_AD4TFC2           HRTIM_ADC4R_AD4TFC2_Msk                  /*!< ADC Trigger 4 on Timer F compare 2 */
9383 
9384 #define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
9385 #define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
9386 #define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
9387 #define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
9388 #define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
9389 #define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
9390 #define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
9391 #define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
9392 #define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
9393 
9394 #define HRTIM_ADC4R_AD4TFC3_Pos       (15U)
9395 #define HRTIM_ADC4R_AD4TFC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC3_Pos)       /*!< 0x00008000 */
9396 #define HRTIM_ADC4R_AD4TFC3           HRTIM_ADC4R_AD4TFC3_Msk                  /*!< ADC Trigger 4 on Timer F compare 3 */
9397 
9398 #define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
9399 #define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
9400 #define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
9401 #define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
9402 #define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
9403 #define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
9404 #define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
9405 #define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
9406 #define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
9407 
9408 #define HRTIM_ADC4R_AD4TFC4_Pos       (19U)
9409 #define HRTIM_ADC4R_AD4TFC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TFC4_Pos)       /*!< 0x00080000 */
9410 #define HRTIM_ADC4R_AD4TFC4           HRTIM_ADC4R_AD4TFC4_Msk                  /*!< ADC Trigger 4 on Timer F compare 4 */
9411 
9412 #define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
9413 #define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
9414 #define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
9415 #define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
9416 #define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
9417 #define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
9418 #define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
9419 #define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
9420 #define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
9421 #define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
9422 #define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
9423 #define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
9424 
9425 #define HRTIM_ADC4R_AD4TFPER_Pos      (24U)
9426 #define HRTIM_ADC4R_AD4TFPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TFPER_Pos)      /*!< 0x01000000 */
9427 #define HRTIM_ADC4R_AD4TFPER          HRTIM_ADC4R_AD4TFPER_Msk                 /*!< ADC Trigger 4 on Timer F period */
9428 
9429 #define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
9430 #define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
9431 #define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
9432 #define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
9433 #define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
9434 #define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
9435 #define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
9436 #define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
9437 #define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
9438 #define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
9439 #define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
9440 #define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
9441 #define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
9442 #define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
9443 #define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
9444 #define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
9445 #define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
9446 #define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
9447 #define HRTIM_ADC4R_AD4TERST_Pos      (31U)
9448 #define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
9449 #define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
9450 
9451 /*******************  Bit definition for HRTIM_DLLCR register  ****************/
9452 #define HRTIM_DLLCR_CAL_Pos           (0U)
9453 #define HRTIM_DLLCR_CAL_Msk           (0x1UL << HRTIM_DLLCR_CAL_Pos)           /*!< 0x00000001 */
9454 #define HRTIM_DLLCR_CAL               HRTIM_DLLCR_CAL_Msk                      /*!< DLL calibration start */
9455 #define HRTIM_DLLCR_CALEN_Pos         (1U)
9456 #define HRTIM_DLLCR_CALEN_Msk         (0x1UL << HRTIM_DLLCR_CALEN_Pos)         /*!< 0x00000002 */
9457 #define HRTIM_DLLCR_CALEN             HRTIM_DLLCR_CALEN_Msk                    /*!< DLL calibration enable */
9458 #define HRTIM_DLLCR_CALRTE_Pos        (2U)
9459 #define HRTIM_DLLCR_CALRTE_Msk        (0x3UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x0000000C */
9460 #define HRTIM_DLLCR_CALRTE            HRTIM_DLLCR_CALRTE_Msk                   /*!< DLL calibration rate */
9461 #define HRTIM_DLLCR_CALRTE_0          (0x1UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x00000004 */
9462 #define HRTIM_DLLCR_CALRTE_1          (0x2UL << HRTIM_DLLCR_CALRTE_Pos)        /*!< 0x00000008 */
9463 
9464 /*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
9465 #define HRTIM_FLTINR1_FLT1E_Pos       (0U)
9466 #define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
9467 #define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
9468 #define HRTIM_FLTINR1_FLT1P_Pos       (1U)
9469 #define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
9470 #define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
9471 #define HRTIM_FLTINR1_FLT1SRC_0_Pos   (2U)
9472 #define HRTIM_FLTINR1_FLT1SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT1SRC_0_Pos)   /*!< 0x00000004 */
9473 #define HRTIM_FLTINR1_FLT1SRC_0       HRTIM_FLTINR1_FLT1SRC_0_Msk              /*!< Fault 1 source bit 0 */
9474 #define HRTIM_FLTINR1_FLT1F_Pos       (3U)
9475 #define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
9476 #define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
9477 #define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000008 */
9478 #define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000010 */
9479 #define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000020 */
9480 #define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000040 */
9481 #define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
9482 #define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
9483 #define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
9484 #define HRTIM_FLTINR1_FLT2E_Pos       (8U)
9485 #define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
9486 #define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
9487 #define HRTIM_FLTINR1_FLT2P_Pos       (9U)
9488 #define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
9489 #define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
9490 #define HRTIM_FLTINR1_FLT2SRC_0_Pos   (10U)
9491 #define HRTIM_FLTINR1_FLT2SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT2SRC_0_Pos)    /*!< 0x00000400 */
9492 #define HRTIM_FLTINR1_FLT2SRC_0       HRTIM_FLTINR1_FLT2SRC_0_Msk               /*!< Fault 2 source bit 0 */
9493 #define HRTIM_FLTINR1_FLT2F_Pos       (11U)
9494 #define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
9495 #define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
9496 #define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00000800 */
9497 #define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00001000 */
9498 #define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00002000 */
9499 #define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00004000 */
9500 #define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
9501 #define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
9502 #define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
9503 #define HRTIM_FLTINR1_FLT3E_Pos       (16U)
9504 #define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
9505 #define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
9506 #define HRTIM_FLTINR1_FLT3P_Pos       (17U)
9507 #define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
9508 #define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
9509 #define HRTIM_FLTINR1_FLT3SRC_0_Pos   (18U)
9510 #define HRTIM_FLTINR1_FLT3SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT3SRC_0_Pos)   /*!< 0x00040000 */
9511 #define HRTIM_FLTINR1_FLT3SRC_0       HRTIM_FLTINR1_FLT3SRC_0_Msk              /*!< Fault 3 source bit 0 */
9512 #define HRTIM_FLTINR1_FLT3F_Pos       (19U)
9513 #define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
9514 #define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
9515 #define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00080000 */
9516 #define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00100000 */
9517 #define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00200000 */
9518 #define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00400000 */
9519 #define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
9520 #define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
9521 #define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
9522 #define HRTIM_FLTINR1_FLT4E_Pos       (24U)
9523 #define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
9524 #define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
9525 #define HRTIM_FLTINR1_FLT4P_Pos       (25U)
9526 #define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
9527 #define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
9528 #define HRTIM_FLTINR1_FLT4SRC_0_Pos   (26U)
9529 #define HRTIM_FLTINR1_FLT4SRC_0_Msk   (0x1UL << HRTIM_FLTINR1_FLT4SRC_0_Pos)    /*!< 0x04000000 */
9530 #define HRTIM_FLTINR1_FLT4SRC_0       HRTIM_FLTINR1_FLT4SRC_0_Msk               /*!< Fault 4 source bit 0 */
9531 #define HRTIM_FLTINR1_FLT4F_Pos       (27U)
9532 #define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
9533 #define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
9534 #define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x08000000 */
9535 #define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x10000000 */
9536 #define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x20000000 */
9537 #define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x40000000 */
9538 #define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
9539 #define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
9540 #define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
9541 
9542 /*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
9543 #define HRTIM_FLTINR2_FLT5E_Pos       (0U)
9544 #define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
9545 #define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
9546 #define HRTIM_FLTINR2_FLT5P_Pos       (1U)
9547 #define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
9548 #define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
9549 #define HRTIM_FLTINR2_FLT5SRC_0_Pos   (2U)
9550 #define HRTIM_FLTINR2_FLT5SRC_0_Msk   (0x1UL << HRTIM_FLTINR2_FLT5SRC_0_Pos)   /*!< 0x00000004 */
9551 #define HRTIM_FLTINR2_FLT5SRC_0       HRTIM_FLTINR2_FLT5SRC_0_Msk              /*!< Fault 5 source bit 0 */
9552 #define HRTIM_FLTINR2_FLT5F_Pos       (3U)
9553 #define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
9554 #define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
9555 #define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000008 */
9556 #define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000010 */
9557 #define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000020 */
9558 #define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000040 */
9559 #define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
9560 #define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
9561 #define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
9562 #define HRTIM_FLTINR2_FLT6E_Pos       (8U)
9563 #define HRTIM_FLTINR2_FLT6E_Msk       (0x1UL << HRTIM_FLTINR2_FLT6E_Pos)       /*!< 0x00000100 */
9564 #define HRTIM_FLTINR2_FLT6E           HRTIM_FLTINR2_FLT6E_Msk                  /*!< Fault 6 enable */
9565 #define HRTIM_FLTINR2_FLT6P_Pos       (9U)
9566 #define HRTIM_FLTINR2_FLT6P_Msk       (0x1UL << HRTIM_FLTINR2_FLT6P_Pos)       /*!< 0x00000200 */
9567 #define HRTIM_FLTINR2_FLT6P           HRTIM_FLTINR2_FLT6P_Msk                  /*!< Fault 6 polarity */
9568 #define HRTIM_FLTINR2_FLT6SRC_0_Pos   (10U)
9569 #define HRTIM_FLTINR2_FLT6SRC_0_Msk   (0x1UL << HRTIM_FLTINR2_FLT6SRC_0_Pos)   /*!< 0x00000400 */
9570 #define HRTIM_FLTINR2_FLT6SRC_0       HRTIM_FLTINR2_FLT6SRC_0_Msk              /*!< Fault 6 source bit 0 */
9571 #define HRTIM_FLTINR2_FLT6F_Pos       (11U)
9572 #define HRTIM_FLTINR2_FLT6F_Msk       (0xFUL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00007800 */
9573 #define HRTIM_FLTINR2_FLT6F           HRTIM_FLTINR2_FLT6F_Msk                  /*!< Fault 6 filter */
9574 #define HRTIM_FLTINR2_FLT6F_0         (0x1UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000008 */
9575 #define HRTIM_FLTINR2_FLT6F_1         (0x2UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000010 */
9576 #define HRTIM_FLTINR2_FLT6F_2         (0x4UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000020 */
9577 #define HRTIM_FLTINR2_FLT6F_3         (0x8UL << HRTIM_FLTINR2_FLT6F_Pos)       /*!< 0x00000040 */
9578 #define HRTIM_FLTINR2_FLT6LCK_Pos     (15U)
9579 #define HRTIM_FLTINR2_FLT6LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT6LCK_Pos)     /*!< 0x00008000 */
9580 #define HRTIM_FLTINR2_FLT6LCK         HRTIM_FLTINR2_FLT6LCK_Msk                /*!< Fault 6 lock */
9581 #define HRTIM_FLTINR2_FLT1SRC_1_Pos   (16U)
9582 #define HRTIM_FLTINR2_FLT1SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT1SRC_1_Pos)   /*!< 0x00010000 */
9583 #define HRTIM_FLTINR2_FLT1SRC_1       HRTIM_FLTINR2_FLT1SRC_1_Msk              /*!< Fault 1 source bit 1 */
9584 #define HRTIM_FLTINR2_FLT2SRC_1_Pos   (17U)
9585 #define HRTIM_FLTINR2_FLT2SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT2SRC_1_Pos)   /*!< 0x00020000 */
9586 #define HRTIM_FLTINR2_FLT2SRC_1       HRTIM_FLTINR2_FLT2SRC_1_Msk              /*!< Fault 2 source bit1 */
9587 #define HRTIM_FLTINR2_FLT3SRC_1_Pos   (18U)
9588 #define HRTIM_FLTINR2_FLT3SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT3SRC_1_Pos)   /*!< 0x00040000 */
9589 #define HRTIM_FLTINR2_FLT3SRC_1       HRTIM_FLTINR2_FLT3SRC_1_Msk              /*!< Fault 3 source bit 1 */
9590 #define HRTIM_FLTINR2_FLT4SRC_1_Pos   (19U)
9591 #define HRTIM_FLTINR2_FLT4SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT4SRC_1_Pos)   /*!< 0x00080000 */
9592 #define HRTIM_FLTINR2_FLT4SRC_1       HRTIM_FLTINR2_FLT4SRC_1_Msk              /*!< Fault 4 source bit 1 */
9593 #define HRTIM_FLTINR2_FLT5SRC_1_Pos   (20U)
9594 #define HRTIM_FLTINR2_FLT5SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT5SRC_1_Pos)   /*!< 0x00100000 */
9595 #define HRTIM_FLTINR2_FLT5SRC_1       HRTIM_FLTINR2_FLT5SRC_1_Msk              /*!< Fault 5 source bit 1 */
9596 #define HRTIM_FLTINR2_FLT6SRC_1_Pos   (21U)
9597 #define HRTIM_FLTINR2_FLT6SRC_1_Msk   (0x1UL << HRTIM_FLTINR2_FLT6SRC_1_Pos)   /*!< 0x00200000 */
9598 #define HRTIM_FLTINR2_FLT6SRC_1       HRTIM_FLTINR2_FLT6SRC_1_Msk              /*!< Fault 6 source bit 1 */
9599 #define HRTIM_FLTINR2_FLTSD_Pos       (24U)
9600 #define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
9601 #define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
9602 #define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x01000000 */
9603 #define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x02000000 */
9604 
9605 /*******************  Bit definition for HRTIM_FLTINR3 register  ***************/
9606 #define HRTIM_FLTINR3_FLT1BLKE_Pos     (0U)
9607 #define HRTIM_FLTINR3_FLT1BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT1BLKE_Pos)   /*!< 0x00000001 */
9608 #define HRTIM_FLTINR3_FLT1BLKE         HRTIM_FLTINR3_FLT1BLKE_Msk              /*!< Fault 1 Blanking Enable */
9609 #define HRTIM_FLTINR3_FLT1BLKS_Pos     (1U)
9610 #define HRTIM_FLTINR3_FLT1BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT1BLKS_Pos)   /*!< 0x00000002 */
9611 #define HRTIM_FLTINR3_FLT1BLKS         HRTIM_FLTINR3_FLT1BLKS_Msk              /*!< Fault 1 Blanking Source */
9612 #define HRTIM_FLTINR3_FLT1CNT_Pos      (2U)
9613 #define HRTIM_FLTINR3_FLT1CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x0000003C */
9614 #define HRTIM_FLTINR3_FLT1CNT          HRTIM_FLTINR3_FLT1CNT_Msk               /*!< Fault 1 Counter */
9615 #define HRTIM_FLTINR3_FLT1CNT_0        (0x1UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000004 */
9616 #define HRTIM_FLTINR3_FLT1CNT_1        (0x2UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000008 */
9617 #define HRTIM_FLTINR3_FLT1CNT_2        (0x4UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000010 */
9618 #define HRTIM_FLTINR3_FLT1CNT_3        (0x8UL << HRTIM_FLTINR3_FLT1CNT_Pos)    /*!< 0x00000020 */
9619 #define HRTIM_FLTINR3_FLT1CRES_Pos     (6U)
9620 #define HRTIM_FLTINR3_FLT1CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT1CRES_Pos)   /*!< 0x00000040 */
9621 #define HRTIM_FLTINR3_FLT1CRES         HRTIM_FLTINR3_FLT1CRES_Msk              /*!< Fault 1 Counter Reset  */
9622 #define HRTIM_FLTINR3_FLT1RSTM_Pos     (7U)
9623 #define HRTIM_FLTINR3_FLT1RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT1RSTM_Pos)   /*!< 0x00000080 */
9624 #define HRTIM_FLTINR3_FLT1RSTM         HRTIM_FLTINR3_FLT1RSTM_Msk              /*!< Fault 1 Counter Reset Mode */
9625 #define HRTIM_FLTINR3_FLT2BLKE_Pos     (8U)
9626 #define HRTIM_FLTINR3_FLT2BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT2BLKE_Pos)   /*!< 0x00000100 */
9627 #define HRTIM_FLTINR3_FLT2BLKE         HRTIM_FLTINR3_FLT2BLKE_Msk              /*!< Fault 2 Blanking Enable */
9628 #define HRTIM_FLTINR3_FLT2BLKS_Pos     (9U)
9629 #define HRTIM_FLTINR3_FLT2BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT2BLKS_Pos)   /*!< 0x00000200 */
9630 #define HRTIM_FLTINR3_FLT2BLKS         HRTIM_FLTINR3_FLT2BLKS_Msk              /*!< Fault 2 Blanking Source */
9631 #define HRTIM_FLTINR3_FLT2CNT_Pos      (10U)
9632 #define HRTIM_FLTINR3_FLT2CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00003C00 */
9633 #define HRTIM_FLTINR3_FLT2CNT          HRTIM_FLTINR3_FLT2CNT_Msk               /*!< Fault 2 Counter */
9634 #define HRTIM_FLTINR3_FLT2CNT_0        (0x1UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00000400 */
9635 #define HRTIM_FLTINR3_FLT2CNT_1        (0x2UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00000800 */
9636 #define HRTIM_FLTINR3_FLT2CNT_2        (0x4UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00001000 */
9637 #define HRTIM_FLTINR3_FLT2CNT_3        (0x8UL << HRTIM_FLTINR3_FLT2CNT_Pos)    /*!< 0x00002000 */
9638 #define HRTIM_FLTINR3_FLT2CRES_Pos     (14U)
9639 #define HRTIM_FLTINR3_FLT2CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT2CRES_Pos)   /*!< 0x00004000 */
9640 #define HRTIM_FLTINR3_FLT2CRES         HRTIM_FLTINR3_FLT2CRES_Msk              /*!< Fault 2 Counter Reset  */
9641 #define HRTIM_FLTINR3_FLT2RSTM_Pos     (15U)
9642 #define HRTIM_FLTINR3_FLT2RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT2RSTM_Pos)   /*!< 0x00008000 */
9643 #define HRTIM_FLTINR3_FLT2RSTM         HRTIM_FLTINR3_FLT2RSTM_Msk              /*!< Fault 2 Counter Reset Mode */
9644 #define HRTIM_FLTINR3_FLT3BLKE_Pos     (16U)
9645 #define HRTIM_FLTINR3_FLT3BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT3BLKE_Pos)   /*!< 0x00010000 */
9646 #define HRTIM_FLTINR3_FLT3BLKE         HRTIM_FLTINR3_FLT3BLKE_Msk              /*!< Fault 3 Blanking Enable */
9647 #define HRTIM_FLTINR3_FLT3BLKS_Pos     (17U)
9648 #define HRTIM_FLTINR3_FLT3BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT3BLKS_Pos)   /*!< 0x00020000 */
9649 #define HRTIM_FLTINR3_FLT3BLKS         HRTIM_FLTINR3_FLT3BLKS_Msk              /*!< Fault 3 Blanking Source */
9650 #define HRTIM_FLTINR3_FLT3CNT_Pos      (18U)
9651 #define HRTIM_FLTINR3_FLT3CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x003C0000 */
9652 #define HRTIM_FLTINR3_FLT3CNT          HRTIM_FLTINR3_FLT3CNT_Msk               /*!< Fault 3 Counter */
9653 #define HRTIM_FLTINR3_FLT3CNT_0        (0x1UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00040000 */
9654 #define HRTIM_FLTINR3_FLT3CNT_1        (0x2UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00080000 */
9655 #define HRTIM_FLTINR3_FLT3CNT_2        (0x4UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00100000 */
9656 #define HRTIM_FLTINR3_FLT3CNT_3        (0x8UL << HRTIM_FLTINR3_FLT3CNT_Pos)    /*!< 0x00200000 */
9657 #define HRTIM_FLTINR3_FLT3CRES_Pos     (22U)
9658 #define HRTIM_FLTINR3_FLT3CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT3CRES_Pos)   /*!< 0x00400000 */
9659 #define HRTIM_FLTINR3_FLT3CRES         HRTIM_FLTINR3_FLT3CRES_Msk              /*!< Fault 3 Counter Reset  */
9660 #define HRTIM_FLTINR3_FLT3RSTM_Pos     (23U)
9661 #define HRTIM_FLTINR3_FLT3RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT3RSTM_Pos)   /*!< 0x00800000 */
9662 #define HRTIM_FLTINR3_FLT3RSTM         HRTIM_FLTINR3_FLT3RSTM_Msk              /*!< Fault 3 Counter Reset Mode */
9663 #define HRTIM_FLTINR3_FLT4BLKE_Pos     (24U)
9664 #define HRTIM_FLTINR3_FLT4BLKE_Msk     (0x1UL << HRTIM_FLTINR3_FLT4BLKE_Pos)   /*!< 0x01000000 */
9665 #define HRTIM_FLTINR3_FLT4BLKE         HRTIM_FLTINR3_FLT4BLKE_Msk              /*!< Fault 4 Blanking Enable */
9666 #define HRTIM_FLTINR3_FLT4BLKS_Pos     (25U)
9667 #define HRTIM_FLTINR3_FLT4BLKS_Msk     (0x1UL << HRTIM_FLTINR3_FLT4BLKS_Pos)   /*!< 0x02000000 */
9668 #define HRTIM_FLTINR3_FLT4BLKS         HRTIM_FLTINR3_FLT4BLKS_Msk              /*!< Fault 4 Blanking Source */
9669 #define HRTIM_FLTINR3_FLT4CNT_Pos      (26U)
9670 #define HRTIM_FLTINR3_FLT4CNT_Msk      (0xFUL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x003C0000 */
9671 #define HRTIM_FLTINR3_FLT4CNT          HRTIM_FLTINR3_FLT4CNT_Msk               /*!< Fault 4 Counter */
9672 #define HRTIM_FLTINR3_FLT4CNT_0        (0x1UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00040000 */
9673 #define HRTIM_FLTINR3_FLT4CNT_1        (0x2UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00080000 */
9674 #define HRTIM_FLTINR3_FLT4CNT_2        (0x4UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00100000 */
9675 #define HRTIM_FLTINR3_FLT4CNT_3        (0x8UL << HRTIM_FLTINR3_FLT4CNT_Pos)    /*!< 0x00200000 */
9676 #define HRTIM_FLTINR3_FLT4CRES_Pos     (30U)
9677 #define HRTIM_FLTINR3_FLT4CRES_Msk     (0x1UL << HRTIM_FLTINR3_FLT4CRES_Pos)   /*!< 0x40000000 */
9678 #define HRTIM_FLTINR3_FLT4CRES         HRTIM_FLTINR3_FLT4CRES_Msk              /*!< Fault 4 Counter Reset  */
9679 #define HRTIM_FLTINR3_FLT4RSTM_Pos     (31U)
9680 #define HRTIM_FLTINR3_FLT4RSTM_Msk     (0x1UL << HRTIM_FLTINR3_FLT4RSTM_Pos)   /*!< 0x80000000 */
9681 #define HRTIM_FLTINR3_FLT4RSTM         HRTIM_FLTINR3_FLT4RSTM_Msk              /*!< Fault 4 Counter Reset Mode */
9682 
9683 /*******************  Bit definition for HRTIM_FLTINR4 register  ***************/
9684 #define HRTIM_FLTINR4_FLT5BLKE_Pos     (0U)
9685 #define HRTIM_FLTINR4_FLT5BLKE_Msk     (0x1UL << HRTIM_FLTINR4_FLT5BLKE_Pos)   /*!< 0x00000001 */
9686 #define HRTIM_FLTINR4_FLT5BLKE         HRTIM_FLTINR4_FLT5BLKE_Msk              /*!< Fault 5 Blanking Enable */
9687 #define HRTIM_FLTINR4_FLT5BLKS_Pos     (1U)
9688 #define HRTIM_FLTINR4_FLT5BLKS_Msk     (0x1UL << HRTIM_FLTINR4_FLT5BLKS_Pos)   /*!< 0x00000002 */
9689 #define HRTIM_FLTINR4_FLT5BLKS         HRTIM_FLTINR4_FLT5BLKS_Msk              /*!< Fault 5 Blanking Source */
9690 #define HRTIM_FLTINR4_FLT5CNT_Pos      (2U)
9691 #define HRTIM_FLTINR4_FLT5CNT_Msk      (0xFUL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x0000003C */
9692 #define HRTIM_FLTINR4_FLT5CNT          HRTIM_FLTINR4_FLT5CNT_Msk               /*!< Fault 5 Counter */
9693 #define HRTIM_FLTINR4_FLT5CNT_0        (0x1UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000004 */
9694 #define HRTIM_FLTINR4_FLT5CNT_1        (0x2UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000008 */
9695 #define HRTIM_FLTINR4_FLT5CNT_2        (0x4UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000010 */
9696 #define HRTIM_FLTINR4_FLT5CNT_3        (0x8UL << HRTIM_FLTINR4_FLT5CNT_Pos)    /*!< 0x00000020 */
9697 #define HRTIM_FLTINR4_FLT5CRES_Pos     (6U)
9698 #define HRTIM_FLTINR4_FLT5CRES_Msk     (0x1UL << HRTIM_FLTINR4_FLT5CRES_Pos)   /*!< 0x00000040 */
9699 #define HRTIM_FLTINR4_FLT5CRES         HRTIM_FLTINR4_FLT5CRES_Msk              /*!< Fault 5 Counter Reset  */
9700 #define HRTIM_FLTINR4_FLT5RSTM_Pos     (7U)
9701 #define HRTIM_FLTINR4_FLT5RSTM_Msk     (0x1UL << HRTIM_FLTINR4_FLT5RSTM_Pos)   /*!< 0x00000080 */
9702 #define HRTIM_FLTINR4_FLT5RSTM         HRTIM_FLTINR4_FLT5RSTM_Msk              /*!< Fault 5 Counter Reset Mode */
9703 #define HRTIM_FLTINR4_FLT6BLKE_Pos     (8U)
9704 #define HRTIM_FLTINR4_FLT6BLKE_Msk     (0x1UL << HRTIM_FLTINR4_FLT6BLKE_Pos)   /*!< 0x00000100 */
9705 #define HRTIM_FLTINR4_FLT6BLKE         HRTIM_FLTINR4_FLT6BLKE_Msk              /*!< Fault 6 Blanking Enable */
9706 #define HRTIM_FLTINR4_FLT6BLKS_Pos     (9U)
9707 #define HRTIM_FLTINR4_FLT6BLKS_Msk     (0x1UL << HRTIM_FLTINR4_FLT6BLKS_Pos)   /*!< 0x00000200 */
9708 #define HRTIM_FLTINR4_FLT6BLKS         HRTIM_FLTINR4_FLT6BLKS_Msk              /*!< Fault 6 Blanking Source */
9709 #define HRTIM_FLTINR4_FLT6CNT_Pos      (10U)
9710 #define HRTIM_FLTINR4_FLT6CNT_Msk      (0xFUL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00003C00 */
9711 #define HRTIM_FLTINR4_FLT6CNT          HRTIM_FLTINR4_FLT6CNT_Msk               /*!< Fault 6 Counter */
9712 #define HRTIM_FLTINR4_FLT6CNT_0        (0x1UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00000400 */
9713 #define HRTIM_FLTINR4_FLT6CNT_1        (0x2UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00000800 */
9714 #define HRTIM_FLTINR4_FLT6CNT_2        (0x4UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00001000 */
9715 #define HRTIM_FLTINR4_FLT6CNT_3        (0x8UL << HRTIM_FLTINR4_FLT6CNT_Pos)    /*!< 0x00002000 */
9716 #define HRTIM_FLTINR4_FLT6CRES_Pos     (14U)
9717 #define HRTIM_FLTINR4_FLT6CRES_Msk     (0x1UL << HRTIM_FLTINR4_FLT6CRES_Pos)   /*!< 0x00004000 */
9718 #define HRTIM_FLTINR4_FLT6CRES         HRTIM_FLTINR4_FLT6CRES_Msk              /*!< Fault 6 Counter Reset  */
9719 #define HRTIM_FLTINR4_FLT6RSTM_Pos     (15U)
9720 #define HRTIM_FLTINR4_FLT6RSTM_Msk     (0x1UL << HRTIM_FLTINR4_FLT6RSTM_Pos)   /*!< 0x00008000 */
9721 #define HRTIM_FLTINR4_FLT6RSTM         HRTIM_FLTINR4_FLT6RSTM_Msk              /*!< Fault 6 Counter Reset Mode */
9722 
9723 /*******************  Bit definition for HRTIM_BDMUPR register  ***************/
9724 #define HRTIM_BDMUPR_MCR_Pos          (0U)
9725 #define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
9726 #define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
9727 #define HRTIM_BDMUPR_MICR_Pos         (1U)
9728 #define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
9729 #define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
9730 #define HRTIM_BDMUPR_MDIER_Pos        (2U)
9731 #define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
9732 #define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
9733 #define HRTIM_BDMUPR_MCNT_Pos         (3U)
9734 #define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
9735 #define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
9736 #define HRTIM_BDMUPR_MPER_Pos         (4U)
9737 #define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
9738 #define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
9739 #define HRTIM_BDMUPR_MREP_Pos         (5U)
9740 #define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
9741 #define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
9742 #define HRTIM_BDMUPR_MCMP1_Pos        (6U)
9743 #define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
9744 #define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
9745 #define HRTIM_BDMUPR_MCMP2_Pos        (7U)
9746 #define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
9747 #define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
9748 #define HRTIM_BDMUPR_MCMP3_Pos        (8U)
9749 #define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
9750 #define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
9751 #define HRTIM_BDMUPR_MCMP4_Pos        (9U)
9752 #define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
9753 #define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
9754 
9755 /*******************  Bit definition for HRTIM_BDTUPR register  ***************/
9756 #define HRTIM_BDTUPR_TIMCR_Pos        (0U)
9757 #define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
9758 #define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
9759 #define HRTIM_BDTUPR_TIMICR_Pos       (1U)
9760 #define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
9761 #define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
9762 #define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
9763 #define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
9764 #define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
9765 #define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
9766 #define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
9767 #define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
9768 #define HRTIM_BDTUPR_TIMPER_Pos       (4U)
9769 #define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
9770 #define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
9771 #define HRTIM_BDTUPR_TIMREP_Pos       (5U)
9772 #define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
9773 #define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
9774 #define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
9775 #define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
9776 #define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
9777 #define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
9778 #define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
9779 #define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
9780 #define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
9781 #define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
9782 #define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
9783 #define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
9784 #define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
9785 #define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
9786 #define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
9787 #define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
9788 #define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
9789 #define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
9790 #define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
9791 #define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
9792 #define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
9793 #define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
9794 #define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
9795 #define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
9796 #define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
9797 #define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
9798 #define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
9799 #define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
9800 #define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
9801 #define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
9802 #define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
9803 #define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
9804 #define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
9805 #define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
9806 #define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
9807 #define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
9808 #define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
9809 #define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
9810 #define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
9811 #define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
9812 #define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
9813 #define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
9814 #define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
9815 #define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
9816 #define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
9817 #define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
9818 #define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
9819 #define HRTIM_BDTUPR_TIMCR2_Pos       (21U)
9820 #define HRTIM_BDTUPR_TIMCR2_Msk       (0x1UL << HRTIM_BDTUPR_TIMCR2_Pos)       /*!< 0x00200000 */
9821 #define HRTIM_BDTUPR_TIMCR2           HRTIM_BDTUPR_TIMCR2_Msk                  /*!<  TIMCR2 register update enable */
9822 #define HRTIM_BDTUPR_TIMEEFR3_Pos     (22U)
9823 #define HRTIM_BDTUPR_TIMEEFR3_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR3_Pos)     /*!< 0x00400000 */
9824 #define HRTIM_BDTUPR_TIMEEFR3         HRTIM_BDTUPR_TIMEEFR3_Msk                /*!<  TIMEEFR3 register update enable */
9825 
9826 /*******************  Bit definition for HRTIM_BDMADR register  ***************/
9827 #define HRTIM_BDMADR_BDMADR_Pos       (0U)
9828 #define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)/*!< 0xFFFFFFFF */
9829 #define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
9830 
9831 /*******************  Bit definition for HRTIM_ADC Extended Trigger register  ***************/
9832 #define HRTIM_ADCER_AD5TRG_Pos       (0U)
9833 #define HRTIM_ADCER_AD5TRG_Msk       (0x1FUL << HRTIM_ADCER_AD5TRG_Pos)    /*!< 0x0000001F */
9834 #define HRTIM_ADCER_AD5TRG           HRTIM_ADCER_AD5TRG_Msk                /*!< ADC5 trigger */
9835 #define HRTIM_ADCER_AD6TRG_Pos       (5U)
9836 #define HRTIM_ADCER_AD6TRG_Msk       (0x1FUL << HRTIM_ADCER_AD6TRG_Pos)    /*!< 0x000003E0 */
9837 #define HRTIM_ADCER_AD6TRG           HRTIM_ADCER_AD6TRG_Msk                /*!< ADC6 trigger */
9838 #define HRTIM_ADCER_AD7TRG_Pos       (10U)
9839 #define HRTIM_ADCER_AD7TRG_Msk       (0x1FUL << HRTIM_ADCER_AD7TRG_Pos)    /*!< 0x00007C00 */
9840 #define HRTIM_ADCER_AD7TRG           HRTIM_ADCER_AD7TRG_Msk                /*!< ADC7 trigger */
9841 #define HRTIM_ADCER_AD8TRG_Pos       (16U)
9842 #define HRTIM_ADCER_AD8TRG_Msk       (0x1FUL << HRTIM_ADCER_AD8TRG_Pos)    /*!< 0x001F0000 */
9843 #define HRTIM_ADCER_AD8TRG           HRTIM_ADCER_AD8TRG_Msk                /*!< ADC8 trigger */
9844 #define HRTIM_ADCER_AD9TRG_Pos       (21U)
9845 #define HRTIM_ADCER_AD9TRG_Msk       (0x1FUL << HRTIM_ADCER_AD9TRG_Pos)    /*!< 0x003E00000 */
9846 #define HRTIM_ADCER_AD9TRG           HRTIM_ADCER_AD9TRG_Msk                /*!< ADC9 trigger */
9847 #define HRTIM_ADCER_AD10TRG_Pos      (26U)
9848 #define HRTIM_ADCER_AD10TRG_Msk      (0x1FUL << HRTIM_ADCER_AD10TRG_Pos)    /*!< 0x7C000000 */
9849 #define HRTIM_ADCER_AD10TRG           HRTIM_ADCER_AD10TRG_Msk                /*!< ADC10 trigger */
9850 
9851 /*******************  Bit definition for HRTIM_ADC Trigger Update register  ***************/
9852 #define HRTIM_ADCUR_AD5USRC_Pos       (0U)
9853 #define HRTIM_ADCUR_AD5USRC_Msk       (0x7UL << HRTIM_ADCUR_AD5USRC_Pos)     /*!< 0x00000007 */
9854 #define HRTIM_ADCUR_AD5USRC           HRTIM_ADCUR_AD5USRC_Msk                /*!< ADC5 trigger Update Source */
9855 #define HRTIM_ADCUR_AD6USRC_Pos       (4U)
9856 #define HRTIM_ADCUR_AD6USRC_Msk       (0x7UL << HRTIM_ADCUR_AD6USRC_Pos)     /*!< 0x00000070 */
9857 #define HRTIM_ADCUR_AD6USRC           HRTIM_ADCUR_AD6USRC_Msk                /*!< ADC6 trigger Update Source */
9858 #define HRTIM_ADCUR_AD7USRC_Pos       (8U)
9859 #define HRTIM_ADCUR_AD7USRC_Msk       (0x7UL << HRTIM_ADCUR_AD7USRC_Pos)     /*!< 0x00000700 */
9860 #define HRTIM_ADCUR_AD7USRC           HRTIM_ADCUR_AD7USRC_Msk                /*!< ADC7 trigger Update Source */
9861 #define HRTIM_ADCUR_AD8USRC_Pos       (12U)
9862 #define HRTIM_ADCUR_AD8USRC_Msk       (0x7UL << HRTIM_ADCUR_AD8USRC_Pos)     /*!< 0x00007000 */
9863 #define HRTIM_ADCUR_AD8USRC           HRTIM_ADCUR_AD8USRC_Msk                /*!< ADC8 trigger Update Source */
9864 #define HRTIM_ADCUR_AD9USRC_Pos       (16U)
9865 #define HRTIM_ADCUR_AD9USRC_Msk       (0x7UL << HRTIM_ADCUR_AD9USRC_Pos)     /*!< 0x000070000 */
9866 #define HRTIM_ADCUR_AD9USRC           HRTIM_ADCUR_AD9USRC_Msk                /*!< ADC9 trigger Update Source */
9867 #define HRTIM_ADCUR_AD10USRC_Pos      (20U)
9868 #define HRTIM_ADCUR_AD10USRC_Msk      (0x7UL << HRTIM_ADCUR_AD10USRC_Pos)    /*!< 0x00700000 */
9869 #define HRTIM_ADCUR_AD10USRC          HRTIM_ADCUR_AD10USRC_Msk               /*!< ADC10 trigger Update Source */
9870 
9871 /*******************  Bit definition for HRTIM_ADCPS1 ADC Post Scaler register 1 ***************/
9872 #define HRTIM_ADCPS1_AD1PSC_Pos       (0U)
9873 #define HRTIM_ADCPS1_AD1PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD1PSC_Pos)    /*!< 0x0000001F */
9874 #define HRTIM_ADCPS1_AD1PSC           HRTIM_ADCPS1_AD1PSC_Msk                /*!< ADC1 post scaler */
9875 #define HRTIM_ADCPS1_AD2PSC_Pos       (6U)
9876 #define HRTIM_ADCPS1_AD2PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD2PSC_Pos)    /*!< 0x000007C0 */
9877 #define HRTIM_ADCPS1_AD2PSC           HRTIM_ADCPS1_AD2PSC_Msk                /*!< ADC2 post scaler */
9878 #define HRTIM_ADCPS1_AD3PSC_Pos       (12U)
9879 #define HRTIM_ADCPS1_AD3PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD3PSC_Pos)    /*!< 0x0001F000 */
9880 #define HRTIM_ADCPS1_AD3PSC           HRTIM_ADCPS1_AD3PSC_Msk                /*!< ADC3 post scaler */
9881 #define HRTIM_ADCPS1_AD4PSC_Pos       (18U)
9882 #define HRTIM_ADCPS1_AD4PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD4PSC_Pos)    /*!< 0x007C0000 */
9883 #define HRTIM_ADCPS1_AD4PSC           HRTIM_ADCPS1_AD4PSC_Msk                /*!< ADC4 post scaler */
9884 #define HRTIM_ADCPS1_AD5PSC_Pos       (24U)
9885 #define HRTIM_ADCPS1_AD5PSC_Msk       (0x1FUL << HRTIM_ADCPS1_AD5PSC_Pos)    /*!< 0x1F000000 */
9886 #define HRTIM_ADCPS1_AD5PSC           HRTIM_ADCPS1_AD5PSC_Msk                /*!< ADC5 post scaler */
9887 
9888 /*******************  Bit definition for HRTIM_ADCPS2 ADC Post Scaler register 2 ***************/
9889 #define HRTIM_ADCPS2_AD6PSC_Pos       (0U)
9890 #define HRTIM_ADCPS2_AD6PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD6PSC_Pos)    /*!< 0x0000001F */
9891 #define HRTIM_ADCPS2_AD6PSC           HRTIM_ADCPS2_AD6PSC_Msk                /*!< ADC6 post scaler */
9892 #define HRTIM_ADCPS2_AD7PSC_Pos       (6U)
9893 #define HRTIM_ADCPS2_AD7PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD7PSC_Pos)    /*!< 0x000007C0 */
9894 #define HRTIM_ADCPS2_AD7PSC           HRTIM_ADCPS2_AD7PSC_Msk                /*!< ADC7 post scaler */
9895 #define HRTIM_ADCPS2_AD8PSC_Pos       (12U)
9896 #define HRTIM_ADCPS2_AD8PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD8PSC_Pos)    /*!< 0x0001F000 */
9897 #define HRTIM_ADCPS2_AD8PSC           HRTIM_ADCPS2_AD8PSC_Msk                /*!< ADC8 post scaler */
9898 #define HRTIM_ADCPS2_AD9PSC_Pos       (18U)
9899 #define HRTIM_ADCPS2_AD9PSC_Msk       (0x1FUL << HRTIM_ADCPS2_AD9PSC_Pos)    /*!< 0x007C0000 */
9900 #define HRTIM_ADCPS2_AD9PSC           HRTIM_ADCPS2_AD9PSC_Msk                /*!< ADC9 post scaler */
9901 #define HRTIM_ADCPS2_AD10PSC_Pos      (24U)
9902 #define HRTIM_ADCPS2_AD10PSC_Msk      (0x1FUL << HRTIM_ADCPS2_AD10PSC_Pos)   /*!< 0x1F000000 */
9903 #define HRTIM_ADCPS2_AD10PSC          HRTIM_ADCPS2_AD10PSC_Msk               /*!< ADC10 post scaler */
9904 
9905 
9906 /******************************************************************************/
9907 /*                                                                            */
9908 /*                      Inter-integrated Circuit Interface (I2C)              */
9909 /*                                                                            */
9910 /******************************************************************************/
9911 /*******************  Bit definition for I2C_CR1 register  *******************/
9912 #define I2C_CR1_PE_Pos               (0U)
9913 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
9914 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
9915 #define I2C_CR1_TXIE_Pos             (1U)
9916 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
9917 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
9918 #define I2C_CR1_RXIE_Pos             (2U)
9919 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
9920 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
9921 #define I2C_CR1_ADDRIE_Pos           (3U)
9922 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
9923 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
9924 #define I2C_CR1_NACKIE_Pos           (4U)
9925 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
9926 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
9927 #define I2C_CR1_STOPIE_Pos           (5U)
9928 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
9929 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
9930 #define I2C_CR1_TCIE_Pos             (6U)
9931 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
9932 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
9933 #define I2C_CR1_ERRIE_Pos            (7U)
9934 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
9935 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
9936 #define I2C_CR1_DNF_Pos              (8U)
9937 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
9938 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
9939 #define I2C_CR1_ANFOFF_Pos           (12U)
9940 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
9941 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
9942 #define I2C_CR1_SWRST_Pos            (13U)
9943 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
9944 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
9945 #define I2C_CR1_TXDMAEN_Pos          (14U)
9946 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
9947 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
9948 #define I2C_CR1_RXDMAEN_Pos          (15U)
9949 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
9950 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
9951 #define I2C_CR1_SBC_Pos              (16U)
9952 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
9953 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
9954 #define I2C_CR1_NOSTRETCH_Pos        (17U)
9955 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
9956 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
9957 #define I2C_CR1_WUPEN_Pos            (18U)
9958 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
9959 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
9960 #define I2C_CR1_GCEN_Pos             (19U)
9961 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
9962 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
9963 #define I2C_CR1_SMBHEN_Pos           (20U)
9964 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
9965 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
9966 #define I2C_CR1_SMBDEN_Pos           (21U)
9967 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
9968 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
9969 #define I2C_CR1_ALERTEN_Pos          (22U)
9970 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
9971 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
9972 #define I2C_CR1_PECEN_Pos            (23U)
9973 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
9974 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
9975 
9976 /******************  Bit definition for I2C_CR2 register  ********************/
9977 #define I2C_CR2_SADD_Pos             (0U)
9978 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
9979 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
9980 #define I2C_CR2_RD_WRN_Pos           (10U)
9981 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
9982 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
9983 #define I2C_CR2_ADD10_Pos            (11U)
9984 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
9985 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
9986 #define I2C_CR2_HEAD10R_Pos          (12U)
9987 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
9988 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
9989 #define I2C_CR2_START_Pos            (13U)
9990 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
9991 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
9992 #define I2C_CR2_STOP_Pos             (14U)
9993 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
9994 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
9995 #define I2C_CR2_NACK_Pos             (15U)
9996 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
9997 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
9998 #define I2C_CR2_NBYTES_Pos           (16U)
9999 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
10000 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
10001 #define I2C_CR2_RELOAD_Pos           (24U)
10002 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
10003 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
10004 #define I2C_CR2_AUTOEND_Pos          (25U)
10005 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
10006 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
10007 #define I2C_CR2_PECBYTE_Pos          (26U)
10008 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
10009 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
10010 
10011 /*******************  Bit definition for I2C_OAR1 register  ******************/
10012 #define I2C_OAR1_OA1_Pos             (0U)
10013 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
10014 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
10015 #define I2C_OAR1_OA1MODE_Pos         (10U)
10016 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
10017 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
10018 #define I2C_OAR1_OA1EN_Pos           (15U)
10019 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
10020 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
10021 
10022 /*******************  Bit definition for I2C_OAR2 register  ******************/
10023 #define I2C_OAR2_OA2_Pos             (1U)
10024 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
10025 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
10026 #define I2C_OAR2_OA2MSK_Pos          (8U)
10027 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
10028 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
10029 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
10030 #define I2C_OAR2_OA2MASK01_Pos       (8U)
10031 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
10032 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
10033 #define I2C_OAR2_OA2MASK02_Pos       (9U)
10034 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
10035 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10036 #define I2C_OAR2_OA2MASK03_Pos       (8U)
10037 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
10038 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10039 #define I2C_OAR2_OA2MASK04_Pos       (10U)
10040 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
10041 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10042 #define I2C_OAR2_OA2MASK05_Pos       (8U)
10043 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
10044 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10045 #define I2C_OAR2_OA2MASK06_Pos       (9U)
10046 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
10047 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
10048 #define I2C_OAR2_OA2MASK07_Pos       (8U)
10049 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
10050 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
10051 #define I2C_OAR2_OA2EN_Pos           (15U)
10052 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
10053 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
10054 
10055 /*******************  Bit definition for I2C_TIMINGR register *******************/
10056 #define I2C_TIMINGR_SCLL_Pos         (0U)
10057 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
10058 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
10059 #define I2C_TIMINGR_SCLH_Pos         (8U)
10060 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
10061 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
10062 #define I2C_TIMINGR_SDADEL_Pos       (16U)
10063 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
10064 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
10065 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
10066 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
10067 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
10068 #define I2C_TIMINGR_PRESC_Pos        (28U)
10069 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
10070 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
10071 
10072 /******************* Bit definition for I2C_TIMEOUTR register *******************/
10073 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
10074 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
10075 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
10076 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
10077 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
10078 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
10079 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
10080 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
10081 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
10082 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
10083 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
10084 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
10085 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
10086 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
10087 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
10088 
10089 /******************  Bit definition for I2C_ISR register  *********************/
10090 #define I2C_ISR_TXE_Pos              (0U)
10091 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
10092 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
10093 #define I2C_ISR_TXIS_Pos             (1U)
10094 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
10095 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
10096 #define I2C_ISR_RXNE_Pos             (2U)
10097 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
10098 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
10099 #define I2C_ISR_ADDR_Pos             (3U)
10100 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
10101 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
10102 #define I2C_ISR_NACKF_Pos            (4U)
10103 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
10104 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
10105 #define I2C_ISR_STOPF_Pos            (5U)
10106 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
10107 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
10108 #define I2C_ISR_TC_Pos               (6U)
10109 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
10110 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
10111 #define I2C_ISR_TCR_Pos              (7U)
10112 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
10113 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
10114 #define I2C_ISR_BERR_Pos             (8U)
10115 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
10116 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
10117 #define I2C_ISR_ARLO_Pos             (9U)
10118 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
10119 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
10120 #define I2C_ISR_OVR_Pos              (10U)
10121 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
10122 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
10123 #define I2C_ISR_PECERR_Pos           (11U)
10124 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
10125 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
10126 #define I2C_ISR_TIMEOUT_Pos          (12U)
10127 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
10128 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
10129 #define I2C_ISR_ALERT_Pos            (13U)
10130 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
10131 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
10132 #define I2C_ISR_BUSY_Pos             (15U)
10133 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
10134 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
10135 #define I2C_ISR_DIR_Pos              (16U)
10136 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
10137 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
10138 #define I2C_ISR_ADDCODE_Pos          (17U)
10139 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
10140 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
10141 
10142 /******************  Bit definition for I2C_ICR register  *********************/
10143 #define I2C_ICR_ADDRCF_Pos           (3U)
10144 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
10145 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
10146 #define I2C_ICR_NACKCF_Pos           (4U)
10147 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
10148 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
10149 #define I2C_ICR_STOPCF_Pos           (5U)
10150 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
10151 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
10152 #define I2C_ICR_BERRCF_Pos           (8U)
10153 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
10154 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
10155 #define I2C_ICR_ARLOCF_Pos           (9U)
10156 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
10157 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
10158 #define I2C_ICR_OVRCF_Pos            (10U)
10159 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
10160 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
10161 #define I2C_ICR_PECCF_Pos            (11U)
10162 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
10163 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
10164 #define I2C_ICR_TIMOUTCF_Pos         (12U)
10165 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
10166 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
10167 #define I2C_ICR_ALERTCF_Pos          (13U)
10168 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
10169 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
10170 
10171 /******************  Bit definition for I2C_PECR register  *********************/
10172 #define I2C_PECR_PEC_Pos             (0U)
10173 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
10174 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
10175 
10176 /******************  Bit definition for I2C_RXDR register  *********************/
10177 #define I2C_RXDR_RXDATA_Pos          (0U)
10178 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
10179 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
10180 
10181 /******************  Bit definition for I2C_TXDR register  *********************/
10182 #define I2C_TXDR_TXDATA_Pos          (0U)
10183 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
10184 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
10185 
10186 /******************************************************************************/
10187 /*                                                                            */
10188 /*                           Independent WATCHDOG                             */
10189 /*                                                                            */
10190 /******************************************************************************/
10191 /*******************  Bit definition for IWDG_KR register  ********************/
10192 #define IWDG_KR_KEY_Pos      (0U)
10193 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
10194 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
10195 
10196 /*******************  Bit definition for IWDG_PR register  ********************/
10197 #define IWDG_PR_PR_Pos       (0U)
10198 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
10199 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
10200 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
10201 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
10202 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
10203 
10204 /*******************  Bit definition for IWDG_RLR register  *******************/
10205 #define IWDG_RLR_RL_Pos      (0U)
10206 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
10207 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
10208 
10209 /*******************  Bit definition for IWDG_SR register  ********************/
10210 #define IWDG_SR_PVU_Pos      (0U)
10211 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
10212 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
10213 #define IWDG_SR_RVU_Pos      (1U)
10214 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
10215 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
10216 #define IWDG_SR_WVU_Pos      (2U)
10217 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
10218 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
10219 
10220 /*******************  Bit definition for IWDG_KR register  ********************/
10221 #define IWDG_WINR_WIN_Pos    (0U)
10222 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
10223 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
10224 
10225 
10226 
10227 /******************************************************************************/
10228 /*                                                                            */
10229 /*                             Power Control                                  */
10230 /*                                                                            */
10231 /******************************************************************************/
10232 
10233 /********************  Bit definition for PWR_CR1 register  ********************/
10234 
10235 #define PWR_CR1_LPR_Pos              (14U)
10236 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
10237 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
10238 #define PWR_CR1_VOS_Pos              (9U)
10239 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
10240 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10241 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
10242 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
10243 #define PWR_CR1_DBP_Pos              (8U)
10244 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
10245 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
10246 #define PWR_CR1_LPMS_Pos             (0U)
10247 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
10248 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
10249 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
10250 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
10251 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
10252 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
10253 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
10254 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
10255 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
10256 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
10257 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
10258 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
10259 
10260 
10261 /********************  Bit definition for PWR_CR2 register  ********************/
10262 
10263 /*!< PVME  Peripheral Voltage Monitor Enable */
10264 #define PWR_CR2_PVME_Pos             (4U)
10265 #define PWR_CR2_PVME_Msk             (0xFUL << PWR_CR2_PVME_Pos)               /*!< 0x000000F0 */
10266 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
10267 #define PWR_CR2_PVME4_Pos            (7U)
10268 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
10269 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
10270 #define PWR_CR2_PVME3_Pos            (6U)
10271 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
10272 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
10273 #define PWR_CR2_PVME2_Pos            (5U)
10274 #define PWR_CR2_PVME2_Msk            (0x1UL << PWR_CR2_PVME2_Pos)              /*!< 0x00000020 */
10275 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
10276 #define PWR_CR2_PVME1_Pos            (4U)
10277 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
10278 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
10279 
10280 /*!< PVD level configuration */
10281 #define PWR_CR2_PLS_Pos              (1U)
10282 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
10283 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
10284 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
10285 #define PWR_CR2_PLS_LEV1_Pos         (1U)
10286 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
10287 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
10288 #define PWR_CR2_PLS_LEV2_Pos         (2U)
10289 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
10290 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
10291 #define PWR_CR2_PLS_LEV3_Pos         (1U)
10292 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
10293 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
10294 #define PWR_CR2_PLS_LEV4_Pos         (3U)
10295 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
10296 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
10297 #define PWR_CR2_PLS_LEV5_Pos         (1U)
10298 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
10299 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
10300 #define PWR_CR2_PLS_LEV6_Pos         (2U)
10301 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
10302 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
10303 #define PWR_CR2_PLS_LEV7_Pos         (1U)
10304 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
10305 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
10306 #define PWR_CR2_PVDE_Pos             (0U)
10307 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
10308 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
10309 
10310 /********************  Bit definition for PWR_CR3 register  ********************/
10311 #define PWR_CR3_EIWF_Pos             (15U)
10312 #define PWR_CR3_EIWF_Msk             (0x1UL << PWR_CR3_EIWF_Pos)               /*!< 0x00008000 */
10313 #define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
10314 #define PWR_CR3_APC_Pos              (10U)
10315 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
10316 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
10317 #define PWR_CR3_EWUP5_Pos            (4U)
10318 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
10319 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
10320 #define PWR_CR3_EWUP4_Pos            (3U)
10321 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
10322 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
10323 #define PWR_CR3_EWUP3_Pos            (2U)
10324 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
10325 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
10326 #define PWR_CR3_EWUP2_Pos            (1U)
10327 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
10328 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
10329 #define PWR_CR3_EWUP1_Pos            (0U)
10330 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
10331 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
10332 #define PWR_CR3_EWUP_Pos             (0U)
10333 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
10334 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
10335 
10336 /********************  Bit definition for PWR_CR4 register  ********************/
10337 #define PWR_CR4_VBRS_Pos             (9U)
10338 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
10339 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
10340 #define PWR_CR4_VBE_Pos              (8U)
10341 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
10342 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
10343 #define PWR_CR4_WP5_Pos              (4U)
10344 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
10345 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
10346 #define PWR_CR4_WP4_Pos              (3U)
10347 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
10348 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
10349 #define PWR_CR4_WP3_Pos              (2U)
10350 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
10351 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
10352 #define PWR_CR4_WP2_Pos              (1U)
10353 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
10354 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
10355 #define PWR_CR4_WP1_Pos              (0U)
10356 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
10357 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
10358 
10359 /********************  Bit definition for PWR_SR1 register  ********************/
10360 #define PWR_SR1_WUFI_Pos             (15U)
10361 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
10362 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
10363 #define PWR_SR1_SBF_Pos              (8U)
10364 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
10365 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
10366 #define PWR_SR1_WUF_Pos              (0U)
10367 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
10368 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
10369 #define PWR_SR1_WUF5_Pos             (4U)
10370 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
10371 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
10372 #define PWR_SR1_WUF4_Pos             (3U)
10373 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
10374 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
10375 #define PWR_SR1_WUF3_Pos             (2U)
10376 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
10377 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
10378 #define PWR_SR1_WUF2_Pos             (1U)
10379 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
10380 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
10381 #define PWR_SR1_WUF1_Pos             (0U)
10382 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
10383 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
10384 
10385 /********************  Bit definition for PWR_SR2 register  ********************/
10386 #define PWR_SR2_PVMO4_Pos            (15U)
10387 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
10388 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
10389 #define PWR_SR2_PVMO3_Pos            (14U)
10390 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
10391 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
10392 #define PWR_SR2_PVMO2_Pos            (13U)
10393 #define PWR_SR2_PVMO2_Msk            (0x1UL << PWR_SR2_PVMO2_Pos)              /*!< 0x00002000 */
10394 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
10395 #define PWR_SR2_PVMO1_Pos            (12U)
10396 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
10397 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
10398 #define PWR_SR2_PVDO_Pos             (11U)
10399 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
10400 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
10401 #define PWR_SR2_VOSF_Pos             (10U)
10402 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
10403 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
10404 #define PWR_SR2_REGLPF_Pos           (9U)
10405 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
10406 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
10407 #define PWR_SR2_REGLPS_Pos           (8U)
10408 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
10409 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
10410 
10411 /********************  Bit definition for PWR_SCR register  ********************/
10412 #define PWR_SCR_CSBF_Pos             (8U)
10413 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
10414 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
10415 #define PWR_SCR_CWUF_Pos             (0U)
10416 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
10417 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
10418 #define PWR_SCR_CWUF5_Pos            (4U)
10419 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
10420 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
10421 #define PWR_SCR_CWUF4_Pos            (3U)
10422 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
10423 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
10424 #define PWR_SCR_CWUF3_Pos            (2U)
10425 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
10426 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
10427 #define PWR_SCR_CWUF2_Pos            (1U)
10428 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
10429 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
10430 #define PWR_SCR_CWUF1_Pos            (0U)
10431 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
10432 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
10433 
10434 /********************  Bit definition for PWR_PUCRA register  ********************/
10435 #define PWR_PUCRA_PA15_Pos           (15U)
10436 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
10437 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
10438 #define PWR_PUCRA_PA13_Pos           (13U)
10439 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
10440 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
10441 #define PWR_PUCRA_PA12_Pos           (12U)
10442 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
10443 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
10444 #define PWR_PUCRA_PA11_Pos           (11U)
10445 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
10446 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
10447 #define PWR_PUCRA_PA10_Pos           (10U)
10448 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
10449 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
10450 #define PWR_PUCRA_PA9_Pos            (9U)
10451 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
10452 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
10453 #define PWR_PUCRA_PA8_Pos            (8U)
10454 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
10455 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
10456 #define PWR_PUCRA_PA7_Pos            (7U)
10457 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
10458 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
10459 #define PWR_PUCRA_PA6_Pos            (6U)
10460 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
10461 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
10462 #define PWR_PUCRA_PA5_Pos            (5U)
10463 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
10464 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
10465 #define PWR_PUCRA_PA4_Pos            (4U)
10466 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
10467 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
10468 #define PWR_PUCRA_PA3_Pos            (3U)
10469 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
10470 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
10471 #define PWR_PUCRA_PA2_Pos            (2U)
10472 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
10473 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
10474 #define PWR_PUCRA_PA1_Pos            (1U)
10475 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
10476 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
10477 #define PWR_PUCRA_PA0_Pos            (0U)
10478 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
10479 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
10480 
10481 /********************  Bit definition for PWR_PDCRA register  ********************/
10482 #define PWR_PDCRA_PA14_Pos           (14U)
10483 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
10484 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
10485 #define PWR_PDCRA_PA12_Pos           (12U)
10486 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
10487 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
10488 #define PWR_PDCRA_PA11_Pos           (11U)
10489 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
10490 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
10491 #define PWR_PDCRA_PA10_Pos           (10U)
10492 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
10493 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
10494 #define PWR_PDCRA_PA9_Pos            (9U)
10495 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
10496 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
10497 #define PWR_PDCRA_PA8_Pos            (8U)
10498 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
10499 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
10500 #define PWR_PDCRA_PA7_Pos            (7U)
10501 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
10502 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
10503 #define PWR_PDCRA_PA6_Pos            (6U)
10504 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
10505 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
10506 #define PWR_PDCRA_PA5_Pos            (5U)
10507 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
10508 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
10509 #define PWR_PDCRA_PA4_Pos            (4U)
10510 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
10511 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
10512 #define PWR_PDCRA_PA3_Pos            (3U)
10513 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
10514 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
10515 #define PWR_PDCRA_PA2_Pos            (2U)
10516 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
10517 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
10518 #define PWR_PDCRA_PA1_Pos            (1U)
10519 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
10520 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
10521 #define PWR_PDCRA_PA0_Pos            (0U)
10522 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
10523 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
10524 
10525 /********************  Bit definition for PWR_PUCRB register  ********************/
10526 
10527 #define PWR_PUCRB_PB15_Pos           (15U)
10528 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
10529 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
10530 #define PWR_PUCRB_PB14_Pos           (14U)
10531 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
10532 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
10533 #define PWR_PUCRB_PB13_Pos           (13U)
10534 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
10535 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
10536 #define PWR_PUCRB_PB12_Pos           (12U)
10537 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
10538 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
10539 #define PWR_PUCRB_PB11_Pos           (11U)
10540 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
10541 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
10542 #define PWR_PUCRB_PB10_Pos           (10U)
10543 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
10544 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
10545 #define PWR_PUCRB_PB9_Pos            (9U)
10546 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
10547 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
10548 #define PWR_PUCRB_PB8_Pos            (8U)
10549 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
10550 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
10551 #define PWR_PUCRB_PB7_Pos            (7U)
10552 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
10553 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
10554 #define PWR_PUCRB_PB6_Pos            (6U)
10555 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
10556 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
10557 #define PWR_PUCRB_PB5_Pos            (5U)
10558 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
10559 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
10560 #define PWR_PUCRB_PB4_Pos            (4U)
10561 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
10562 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
10563 #define PWR_PUCRB_PB3_Pos            (3U)
10564 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
10565 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
10566 #define PWR_PUCRB_PB2_Pos            (2U)
10567 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
10568 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
10569 #define PWR_PUCRB_PB1_Pos            (1U)
10570 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
10571 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
10572 #define PWR_PUCRB_PB0_Pos            (0U)
10573 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
10574 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
10575 
10576 /********************  Bit definition for PWR_PDCRB register  ********************/
10577 #define PWR_PDCRB_PB15_Pos           (15U)
10578 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
10579 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
10580 #define PWR_PDCRB_PB14_Pos           (14U)
10581 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
10582 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
10583 #define PWR_PDCRB_PB13_Pos           (13U)
10584 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
10585 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
10586 #define PWR_PDCRB_PB12_Pos           (12U)
10587 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
10588 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
10589 #define PWR_PDCRB_PB11_Pos           (11U)
10590 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
10591 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
10592 #define PWR_PDCRB_PB10_Pos           (10U)
10593 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
10594 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
10595 #define PWR_PDCRB_PB9_Pos            (9U)
10596 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
10597 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
10598 #define PWR_PDCRB_PB8_Pos            (8U)
10599 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
10600 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
10601 #define PWR_PDCRB_PB7_Pos            (7U)
10602 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
10603 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
10604 #define PWR_PDCRB_PB6_Pos            (6U)
10605 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
10606 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
10607 #define PWR_PDCRB_PB5_Pos            (5U)
10608 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
10609 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
10610 #define PWR_PDCRB_PB3_Pos            (3U)
10611 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
10612 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
10613 #define PWR_PDCRB_PB2_Pos            (2U)
10614 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
10615 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
10616 #define PWR_PDCRB_PB1_Pos            (1U)
10617 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
10618 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
10619 #define PWR_PDCRB_PB0_Pos            (0U)
10620 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
10621 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
10622 
10623 /********************  Bit definition for PWR_PUCRC register  ********************/
10624 #define PWR_PUCRC_PC15_Pos           (15U)
10625 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
10626 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
10627 #define PWR_PUCRC_PC14_Pos           (14U)
10628 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
10629 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
10630 #define PWR_PUCRC_PC13_Pos           (13U)
10631 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
10632 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
10633 #define PWR_PUCRC_PC12_Pos           (12U)
10634 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
10635 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
10636 #define PWR_PUCRC_PC11_Pos           (11U)
10637 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
10638 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
10639 #define PWR_PUCRC_PC10_Pos           (10U)
10640 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
10641 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
10642 #define PWR_PUCRC_PC9_Pos            (9U)
10643 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
10644 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
10645 #define PWR_PUCRC_PC8_Pos            (8U)
10646 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
10647 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
10648 #define PWR_PUCRC_PC7_Pos            (7U)
10649 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
10650 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
10651 #define PWR_PUCRC_PC6_Pos            (6U)
10652 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
10653 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
10654 #define PWR_PUCRC_PC5_Pos            (5U)
10655 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
10656 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
10657 #define PWR_PUCRC_PC4_Pos            (4U)
10658 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
10659 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
10660 #define PWR_PUCRC_PC3_Pos            (3U)
10661 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
10662 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
10663 #define PWR_PUCRC_PC2_Pos            (2U)
10664 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
10665 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
10666 #define PWR_PUCRC_PC1_Pos            (1U)
10667 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
10668 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
10669 #define PWR_PUCRC_PC0_Pos            (0U)
10670 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
10671 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
10672 
10673 /********************  Bit definition for PWR_PDCRC register  ********************/
10674 #define PWR_PDCRC_PC15_Pos           (15U)
10675 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
10676 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
10677 #define PWR_PDCRC_PC14_Pos           (14U)
10678 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
10679 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
10680 #define PWR_PDCRC_PC13_Pos           (13U)
10681 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
10682 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
10683 #define PWR_PDCRC_PC12_Pos           (12U)
10684 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
10685 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
10686 #define PWR_PDCRC_PC11_Pos           (11U)
10687 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
10688 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
10689 #define PWR_PDCRC_PC10_Pos           (10U)
10690 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
10691 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
10692 #define PWR_PDCRC_PC9_Pos            (9U)
10693 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
10694 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
10695 #define PWR_PDCRC_PC8_Pos            (8U)
10696 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
10697 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
10698 #define PWR_PDCRC_PC7_Pos            (7U)
10699 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
10700 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
10701 #define PWR_PDCRC_PC6_Pos            (6U)
10702 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
10703 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
10704 #define PWR_PDCRC_PC5_Pos            (5U)
10705 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
10706 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
10707 #define PWR_PDCRC_PC4_Pos            (4U)
10708 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
10709 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
10710 #define PWR_PDCRC_PC3_Pos            (3U)
10711 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
10712 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
10713 #define PWR_PDCRC_PC2_Pos            (2U)
10714 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
10715 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
10716 #define PWR_PDCRC_PC1_Pos            (1U)
10717 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
10718 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
10719 #define PWR_PDCRC_PC0_Pos            (0U)
10720 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
10721 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
10722 
10723 /********************  Bit definition for PWR_PUCRD register  ********************/
10724 #define PWR_PUCRD_PD15_Pos           (15U)
10725 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
10726 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
10727 #define PWR_PUCRD_PD14_Pos           (14U)
10728 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
10729 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
10730 #define PWR_PUCRD_PD13_Pos           (13U)
10731 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
10732 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
10733 #define PWR_PUCRD_PD12_Pos           (12U)
10734 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
10735 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
10736 #define PWR_PUCRD_PD11_Pos           (11U)
10737 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
10738 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
10739 #define PWR_PUCRD_PD10_Pos           (10U)
10740 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
10741 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
10742 #define PWR_PUCRD_PD9_Pos            (9U)
10743 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
10744 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
10745 #define PWR_PUCRD_PD8_Pos            (8U)
10746 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
10747 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
10748 #define PWR_PUCRD_PD7_Pos            (7U)
10749 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
10750 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
10751 #define PWR_PUCRD_PD6_Pos            (6U)
10752 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
10753 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
10754 #define PWR_PUCRD_PD5_Pos            (5U)
10755 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
10756 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
10757 #define PWR_PUCRD_PD4_Pos            (4U)
10758 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
10759 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
10760 #define PWR_PUCRD_PD3_Pos            (3U)
10761 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
10762 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
10763 #define PWR_PUCRD_PD2_Pos            (2U)
10764 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
10765 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
10766 #define PWR_PUCRD_PD1_Pos            (1U)
10767 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
10768 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
10769 #define PWR_PUCRD_PD0_Pos            (0U)
10770 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
10771 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
10772 
10773 /********************  Bit definition for PWR_PDCRD register  ********************/
10774 #define PWR_PDCRD_PD15_Pos           (15U)
10775 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
10776 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
10777 #define PWR_PDCRD_PD14_Pos           (14U)
10778 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
10779 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
10780 #define PWR_PDCRD_PD13_Pos           (13U)
10781 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
10782 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
10783 #define PWR_PDCRD_PD12_Pos           (12U)
10784 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
10785 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
10786 #define PWR_PDCRD_PD11_Pos           (11U)
10787 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
10788 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
10789 #define PWR_PDCRD_PD10_Pos           (10U)
10790 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
10791 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
10792 #define PWR_PDCRD_PD9_Pos            (9U)
10793 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
10794 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
10795 #define PWR_PDCRD_PD8_Pos            (8U)
10796 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
10797 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
10798 #define PWR_PDCRD_PD7_Pos            (7U)
10799 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
10800 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
10801 #define PWR_PDCRD_PD6_Pos            (6U)
10802 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
10803 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
10804 #define PWR_PDCRD_PD5_Pos            (5U)
10805 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
10806 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
10807 #define PWR_PDCRD_PD4_Pos            (4U)
10808 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
10809 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
10810 #define PWR_PDCRD_PD3_Pos            (3U)
10811 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
10812 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
10813 #define PWR_PDCRD_PD2_Pos            (2U)
10814 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
10815 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
10816 #define PWR_PDCRD_PD1_Pos            (1U)
10817 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
10818 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
10819 #define PWR_PDCRD_PD0_Pos            (0U)
10820 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
10821 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
10822 
10823 /********************  Bit definition for PWR_PUCRE register  ********************/
10824 #define PWR_PUCRE_PE15_Pos           (15U)
10825 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
10826 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
10827 #define PWR_PUCRE_PE14_Pos           (14U)
10828 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
10829 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
10830 #define PWR_PUCRE_PE13_Pos           (13U)
10831 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
10832 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
10833 #define PWR_PUCRE_PE12_Pos           (12U)
10834 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
10835 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
10836 #define PWR_PUCRE_PE11_Pos           (11U)
10837 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
10838 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
10839 #define PWR_PUCRE_PE10_Pos           (10U)
10840 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
10841 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
10842 #define PWR_PUCRE_PE9_Pos            (9U)
10843 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
10844 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
10845 #define PWR_PUCRE_PE8_Pos            (8U)
10846 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
10847 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
10848 #define PWR_PUCRE_PE7_Pos            (7U)
10849 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
10850 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
10851 #define PWR_PUCRE_PE6_Pos            (6U)
10852 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
10853 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
10854 #define PWR_PUCRE_PE5_Pos            (5U)
10855 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
10856 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
10857 #define PWR_PUCRE_PE4_Pos            (4U)
10858 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
10859 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
10860 #define PWR_PUCRE_PE3_Pos            (3U)
10861 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
10862 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
10863 #define PWR_PUCRE_PE2_Pos            (2U)
10864 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
10865 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
10866 #define PWR_PUCRE_PE1_Pos            (1U)
10867 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
10868 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
10869 #define PWR_PUCRE_PE0_Pos            (0U)
10870 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
10871 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
10872 
10873 /********************  Bit definition for PWR_PDCRE register  ********************/
10874 #define PWR_PDCRE_PE15_Pos           (15U)
10875 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
10876 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
10877 #define PWR_PDCRE_PE14_Pos           (14U)
10878 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
10879 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
10880 #define PWR_PDCRE_PE13_Pos           (13U)
10881 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
10882 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
10883 #define PWR_PDCRE_PE12_Pos           (12U)
10884 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
10885 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
10886 #define PWR_PDCRE_PE11_Pos           (11U)
10887 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
10888 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
10889 #define PWR_PDCRE_PE10_Pos           (10U)
10890 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
10891 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
10892 #define PWR_PDCRE_PE9_Pos            (9U)
10893 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
10894 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
10895 #define PWR_PDCRE_PE8_Pos            (8U)
10896 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
10897 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
10898 #define PWR_PDCRE_PE7_Pos            (7U)
10899 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
10900 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
10901 #define PWR_PDCRE_PE6_Pos            (6U)
10902 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
10903 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
10904 #define PWR_PDCRE_PE5_Pos            (5U)
10905 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
10906 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
10907 #define PWR_PDCRE_PE4_Pos            (4U)
10908 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
10909 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
10910 #define PWR_PDCRE_PE3_Pos            (3U)
10911 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
10912 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
10913 #define PWR_PDCRE_PE2_Pos            (2U)
10914 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
10915 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
10916 #define PWR_PDCRE_PE1_Pos            (1U)
10917 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
10918 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
10919 #define PWR_PDCRE_PE0_Pos            (0U)
10920 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
10921 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
10922 
10923 /********************  Bit definition for PWR_PUCRF register  ********************/
10924 #define PWR_PUCRF_PF15_Pos           (15U)
10925 #define PWR_PUCRF_PF15_Msk           (0x1UL << PWR_PUCRF_PF15_Pos)             /*!< 0x00008000 */
10926 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
10927 #define PWR_PUCRF_PF14_Pos           (14U)
10928 #define PWR_PUCRF_PF14_Msk           (0x1UL << PWR_PUCRF_PF14_Pos)             /*!< 0x00004000 */
10929 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
10930 #define PWR_PUCRF_PF13_Pos           (13U)
10931 #define PWR_PUCRF_PF13_Msk           (0x1UL << PWR_PUCRF_PF13_Pos)             /*!< 0x00002000 */
10932 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
10933 #define PWR_PUCRF_PF12_Pos           (12U)
10934 #define PWR_PUCRF_PF12_Msk           (0x1UL << PWR_PUCRF_PF12_Pos)             /*!< 0x00001000 */
10935 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
10936 #define PWR_PUCRF_PF11_Pos           (11U)
10937 #define PWR_PUCRF_PF11_Msk           (0x1UL << PWR_PUCRF_PF11_Pos)             /*!< 0x00000800 */
10938 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
10939 #define PWR_PUCRF_PF10_Pos           (10U)
10940 #define PWR_PUCRF_PF10_Msk           (0x1UL << PWR_PUCRF_PF10_Pos)             /*!< 0x00000400 */
10941 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
10942 #define PWR_PUCRF_PF9_Pos            (9U)
10943 #define PWR_PUCRF_PF9_Msk            (0x1UL << PWR_PUCRF_PF9_Pos)              /*!< 0x00000200 */
10944 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
10945 #define PWR_PUCRF_PF8_Pos            (8U)
10946 #define PWR_PUCRF_PF8_Msk            (0x1UL << PWR_PUCRF_PF8_Pos)              /*!< 0x00000100 */
10947 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
10948 #define PWR_PUCRF_PF7_Pos            (7U)
10949 #define PWR_PUCRF_PF7_Msk            (0x1UL << PWR_PUCRF_PF7_Pos)              /*!< 0x00000080 */
10950 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
10951 #define PWR_PUCRF_PF6_Pos            (6U)
10952 #define PWR_PUCRF_PF6_Msk            (0x1UL << PWR_PUCRF_PF6_Pos)              /*!< 0x00000040 */
10953 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
10954 #define PWR_PUCRF_PF5_Pos            (5U)
10955 #define PWR_PUCRF_PF5_Msk            (0x1UL << PWR_PUCRF_PF5_Pos)              /*!< 0x00000020 */
10956 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
10957 #define PWR_PUCRF_PF4_Pos            (4U)
10958 #define PWR_PUCRF_PF4_Msk            (0x1UL << PWR_PUCRF_PF4_Pos)              /*!< 0x00000010 */
10959 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
10960 #define PWR_PUCRF_PF3_Pos            (3U)
10961 #define PWR_PUCRF_PF3_Msk            (0x1UL << PWR_PUCRF_PF3_Pos)              /*!< 0x00000008 */
10962 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
10963 #define PWR_PUCRF_PF2_Pos            (2U)
10964 #define PWR_PUCRF_PF2_Msk            (0x1UL << PWR_PUCRF_PF2_Pos)              /*!< 0x00000004 */
10965 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
10966 #define PWR_PUCRF_PF1_Pos            (1U)
10967 #define PWR_PUCRF_PF1_Msk            (0x1UL << PWR_PUCRF_PF1_Pos)              /*!< 0x00000002 */
10968 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
10969 #define PWR_PUCRF_PF0_Pos            (0U)
10970 #define PWR_PUCRF_PF0_Msk            (0x1UL << PWR_PUCRF_PF0_Pos)              /*!< 0x00000001 */
10971 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
10972 
10973 /********************  Bit definition for PWR_PDCRF register  ********************/
10974 #define PWR_PDCRF_PF15_Pos           (15U)
10975 #define PWR_PDCRF_PF15_Msk           (0x1UL << PWR_PDCRF_PF15_Pos)             /*!< 0x00008000 */
10976 #define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
10977 #define PWR_PDCRF_PF14_Pos           (14U)
10978 #define PWR_PDCRF_PF14_Msk           (0x1UL << PWR_PDCRF_PF14_Pos)             /*!< 0x00004000 */
10979 #define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
10980 #define PWR_PDCRF_PF13_Pos           (13U)
10981 #define PWR_PDCRF_PF13_Msk           (0x1UL << PWR_PDCRF_PF13_Pos)             /*!< 0x00002000 */
10982 #define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
10983 #define PWR_PDCRF_PF12_Pos           (12U)
10984 #define PWR_PDCRF_PF12_Msk           (0x1UL << PWR_PDCRF_PF12_Pos)             /*!< 0x00001000 */
10985 #define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
10986 #define PWR_PDCRF_PF11_Pos           (11U)
10987 #define PWR_PDCRF_PF11_Msk           (0x1UL << PWR_PDCRF_PF11_Pos)             /*!< 0x00000800 */
10988 #define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
10989 #define PWR_PDCRF_PF10_Pos           (10U)
10990 #define PWR_PDCRF_PF10_Msk           (0x1UL << PWR_PDCRF_PF10_Pos)             /*!< 0x00000400 */
10991 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
10992 #define PWR_PDCRF_PF9_Pos            (9U)
10993 #define PWR_PDCRF_PF9_Msk            (0x1UL << PWR_PDCRF_PF9_Pos)              /*!< 0x00000200 */
10994 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
10995 #define PWR_PDCRF_PF8_Pos            (8U)
10996 #define PWR_PDCRF_PF8_Msk            (0x1UL << PWR_PDCRF_PF8_Pos)              /*!< 0x00000100 */
10997 #define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
10998 #define PWR_PDCRF_PF7_Pos            (7U)
10999 #define PWR_PDCRF_PF7_Msk            (0x1UL << PWR_PDCRF_PF7_Pos)              /*!< 0x00000080 */
11000 #define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
11001 #define PWR_PDCRF_PF6_Pos            (6U)
11002 #define PWR_PDCRF_PF6_Msk            (0x1UL << PWR_PDCRF_PF6_Pos)              /*!< 0x00000040 */
11003 #define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
11004 #define PWR_PDCRF_PF5_Pos            (5U)
11005 #define PWR_PDCRF_PF5_Msk            (0x1UL << PWR_PDCRF_PF5_Pos)              /*!< 0x00000020 */
11006 #define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
11007 #define PWR_PDCRF_PF4_Pos            (4U)
11008 #define PWR_PDCRF_PF4_Msk            (0x1UL << PWR_PDCRF_PF4_Pos)              /*!< 0x00000010 */
11009 #define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
11010 #define PWR_PDCRF_PF3_Pos            (3U)
11011 #define PWR_PDCRF_PF3_Msk            (0x1UL << PWR_PDCRF_PF3_Pos)              /*!< 0x00000008 */
11012 #define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
11013 #define PWR_PDCRF_PF2_Pos            (2U)
11014 #define PWR_PDCRF_PF2_Msk            (0x1UL << PWR_PDCRF_PF2_Pos)              /*!< 0x00000004 */
11015 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
11016 #define PWR_PDCRF_PF1_Pos            (1U)
11017 #define PWR_PDCRF_PF1_Msk            (0x1UL << PWR_PDCRF_PF1_Pos)              /*!< 0x00000002 */
11018 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
11019 #define PWR_PDCRF_PF0_Pos            (0U)
11020 #define PWR_PDCRF_PF0_Msk            (0x1UL << PWR_PDCRF_PF0_Pos)              /*!< 0x00000001 */
11021 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
11022 
11023 /********************  Bit definition for PWR_PUCRG register  ********************/
11024 #define PWR_PUCRG_PG15_Pos           (15U)
11025 #define PWR_PUCRG_PG15_Msk           (0x1UL << PWR_PUCRG_PG15_Pos)             /*!< 0x00008000 */
11026 #define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
11027 #define PWR_PUCRG_PG14_Pos           (14U)
11028 #define PWR_PUCRG_PG14_Msk           (0x1UL << PWR_PUCRG_PG14_Pos)             /*!< 0x00004000 */
11029 #define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
11030 #define PWR_PUCRG_PG13_Pos           (13U)
11031 #define PWR_PUCRG_PG13_Msk           (0x1UL << PWR_PUCRG_PG13_Pos)             /*!< 0x00002000 */
11032 #define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
11033 #define PWR_PUCRG_PG12_Pos           (12U)
11034 #define PWR_PUCRG_PG12_Msk           (0x1UL << PWR_PUCRG_PG12_Pos)             /*!< 0x00001000 */
11035 #define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
11036 #define PWR_PUCRG_PG11_Pos           (11U)
11037 #define PWR_PUCRG_PG11_Msk           (0x1UL << PWR_PUCRG_PG11_Pos)             /*!< 0x00000800 */
11038 #define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
11039 #define PWR_PUCRG_PG10_Pos           (10U)
11040 #define PWR_PUCRG_PG10_Msk           (0x1UL << PWR_PUCRG_PG10_Pos)             /*!< 0x00000400 */
11041 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
11042 #define PWR_PUCRG_PG9_Pos            (9U)
11043 #define PWR_PUCRG_PG9_Msk            (0x1UL << PWR_PUCRG_PG9_Pos)              /*!< 0x00000200 */
11044 #define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
11045 #define PWR_PUCRG_PG8_Pos            (8U)
11046 #define PWR_PUCRG_PG8_Msk            (0x1UL << PWR_PUCRG_PG8_Pos)              /*!< 0x00000100 */
11047 #define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
11048 #define PWR_PUCRG_PG7_Pos            (7U)
11049 #define PWR_PUCRG_PG7_Msk            (0x1UL << PWR_PUCRG_PG7_Pos)              /*!< 0x00000080 */
11050 #define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
11051 #define PWR_PUCRG_PG6_Pos            (6U)
11052 #define PWR_PUCRG_PG6_Msk            (0x1UL << PWR_PUCRG_PG6_Pos)              /*!< 0x00000040 */
11053 #define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
11054 #define PWR_PUCRG_PG5_Pos            (5U)
11055 #define PWR_PUCRG_PG5_Msk            (0x1UL << PWR_PUCRG_PG5_Pos)              /*!< 0x00000020 */
11056 #define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
11057 #define PWR_PUCRG_PG4_Pos            (4U)
11058 #define PWR_PUCRG_PG4_Msk            (0x1UL << PWR_PUCRG_PG4_Pos)              /*!< 0x00000010 */
11059 #define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
11060 #define PWR_PUCRG_PG3_Pos            (3U)
11061 #define PWR_PUCRG_PG3_Msk            (0x1UL << PWR_PUCRG_PG3_Pos)              /*!< 0x00000008 */
11062 #define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
11063 #define PWR_PUCRG_PG2_Pos            (2U)
11064 #define PWR_PUCRG_PG2_Msk            (0x1UL << PWR_PUCRG_PG2_Pos)              /*!< 0x00000004 */
11065 #define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
11066 #define PWR_PUCRG_PG1_Pos            (1U)
11067 #define PWR_PUCRG_PG1_Msk            (0x1UL << PWR_PUCRG_PG1_Pos)              /*!< 0x00000002 */
11068 #define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
11069 #define PWR_PUCRG_PG0_Pos            (0U)
11070 #define PWR_PUCRG_PG0_Msk            (0x1UL << PWR_PUCRG_PG0_Pos)              /*!< 0x00000001 */
11071 #define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
11072 
11073 /********************  Bit definition for PWR_PDCRG register  ********************/
11074 #define PWR_PDCRG_PG10_Pos           (10U)
11075 #define PWR_PDCRG_PG10_Msk           (0x1UL << PWR_PDCRG_PG10_Pos)             /*!< 0x00000400 */
11076 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
11077 #define PWR_PDCRG_PG9_Pos            (9U)
11078 #define PWR_PDCRG_PG9_Msk            (0x1UL << PWR_PDCRG_PG9_Pos)              /*!< 0x00000200 */
11079 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
11080 #define PWR_PDCRG_PG8_Pos            (8U)
11081 #define PWR_PDCRG_PG8_Msk            (0x1UL << PWR_PDCRG_PG8_Pos)              /*!< 0x00000100 */
11082 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
11083 #define PWR_PDCRG_PG7_Pos            (7U)
11084 #define PWR_PDCRG_PG7_Msk            (0x1UL << PWR_PDCRG_PG7_Pos)              /*!< 0x00000080 */
11085 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
11086 #define PWR_PDCRG_PG6_Pos            (6U)
11087 #define PWR_PDCRG_PG6_Msk            (0x1UL << PWR_PDCRG_PG6_Pos)              /*!< 0x00000040 */
11088 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
11089 #define PWR_PDCRG_PG5_Pos            (5U)
11090 #define PWR_PDCRG_PG5_Msk            (0x1UL << PWR_PDCRG_PG5_Pos)              /*!< 0x00000020 */
11091 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
11092 #define PWR_PDCRG_PG4_Pos            (4U)
11093 #define PWR_PDCRG_PG4_Msk            (0x1UL << PWR_PDCRG_PG4_Pos)              /*!< 0x00000010 */
11094 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
11095 #define PWR_PDCRG_PG3_Pos            (3U)
11096 #define PWR_PDCRG_PG3_Msk            (0x1UL << PWR_PDCRG_PG3_Pos)              /*!< 0x00000008 */
11097 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
11098 #define PWR_PDCRG_PG2_Pos            (2U)
11099 #define PWR_PDCRG_PG2_Msk            (0x1UL << PWR_PDCRG_PG2_Pos)              /*!< 0x00000004 */
11100 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
11101 #define PWR_PDCRG_PG1_Pos            (1U)
11102 #define PWR_PDCRG_PG1_Msk            (0x1UL << PWR_PDCRG_PG1_Pos)              /*!< 0x00000002 */
11103 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
11104 #define PWR_PDCRG_PG0_Pos            (0U)
11105 #define PWR_PDCRG_PG0_Msk            (0x1UL << PWR_PDCRG_PG0_Pos)              /*!< 0x00000001 */
11106 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
11107 
11108 /********************  Bit definition for PWR_CR5 register  ********************/
11109 #define PWR_CR5_R1MODE_Pos           (8U)
11110 #define PWR_CR5_R1MODE_Msk           (0x1U << PWR_CR5_R1MODE_Pos)              /*!< 0x00000100 */
11111 #define PWR_CR5_R1MODE               PWR_CR5_R1MODE_Msk                        /*!< selection for Main Regulator in Range1 */
11112 
11113 
11114 /******************************************************************************/
11115 /*                                                                            */
11116 /*                         Reset and Clock Control                            */
11117 /*                                                                            */
11118 /******************************************************************************/
11119 /*
11120 * @brief Specific device feature definitions  (not present on all devices in the STM32G4 series)
11121 */
11122 
11123 #define RCC_HSI48_SUPPORT
11124 #define RCC_PLLP_DIV_2_31_SUPPORT
11125 
11126 /********************  Bit definition for RCC_CR register  ********************/
11127 #define RCC_CR_HSION_Pos                     (8U)
11128 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
11129 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
11130 #define RCC_CR_HSIKERON_Pos                  (9U)
11131 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
11132 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
11133 #define RCC_CR_HSIRDY_Pos                    (10U)
11134 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
11135 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
11136 
11137 #define RCC_CR_HSEON_Pos                     (16U)
11138 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
11139 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
11140 #define RCC_CR_HSERDY_Pos                    (17U)
11141 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
11142 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
11143 #define RCC_CR_HSEBYP_Pos                    (18U)
11144 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
11145 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
11146 #define RCC_CR_CSSON_Pos                     (19U)
11147 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
11148 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
11149 
11150 #define RCC_CR_PLLON_Pos                     (24U)
11151 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
11152 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
11153 #define RCC_CR_PLLRDY_Pos                    (25U)
11154 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
11155 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
11156 
11157 /********************  Bit definition for RCC_ICSCR register  ***************/
11158 /*!< HSICAL configuration */
11159 #define RCC_ICSCR_HSICAL_Pos                 (16U)
11160 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
11161 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
11162 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
11163 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
11164 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
11165 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
11166 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
11167 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
11168 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
11169 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
11170 
11171 /*!< HSITRIM configuration */
11172 #define RCC_ICSCR_HSITRIM_Pos                (24U)
11173 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
11174 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
11175 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
11176 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
11177 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
11178 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
11179 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
11180 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
11181 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
11182 
11183 /********************  Bit definition for RCC_CFGR register  ******************/
11184 /*!< SW configuration */
11185 #define RCC_CFGR_SW_Pos                      (0U)
11186 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
11187 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
11188 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
11189 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
11190 
11191 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
11192 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
11193 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
11194 
11195 /*!< SWS configuration */
11196 #define RCC_CFGR_SWS_Pos                     (2U)
11197 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
11198 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
11199 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
11200 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
11201 
11202 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
11203 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
11204 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
11205 
11206 /*!< HPRE configuration */
11207 #define RCC_CFGR_HPRE_Pos                    (4U)
11208 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
11209 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
11210 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
11211 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
11212 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
11213 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
11214 
11215 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
11216 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
11217 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
11218 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
11219 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
11220 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
11221 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
11222 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
11223 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
11224 
11225 /*!< PPRE1 configuration */
11226 #define RCC_CFGR_PPRE1_Pos                   (8U)
11227 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
11228 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
11229 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
11230 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
11231 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
11232 
11233 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11234 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
11235 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
11236 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
11237 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
11238 
11239 /*!< PPRE2 configuration */
11240 #define RCC_CFGR_PPRE2_Pos                   (11U)
11241 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
11242 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
11243 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
11244 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
11245 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
11246 
11247 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11248 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
11249 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
11250 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
11251 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
11252 
11253 /*!< MCOSEL configuration */
11254 #define RCC_CFGR_MCOSEL_Pos                  (24U)
11255 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
11256 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
11257 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
11258 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
11259 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
11260 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
11261 
11262 #define RCC_CFGR_MCOPRE_Pos                  (28U)
11263 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
11264 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
11265 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
11266 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
11267 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
11268 
11269 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
11270 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
11271 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
11272 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
11273 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
11274 
11275 /* Legacy aliases */
11276 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
11277 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
11278 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
11279 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
11280 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
11281 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
11282 
11283 /********************  Bit definition for RCC_PLLCFGR register  ***************/
11284 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
11285 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
11286 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
11287 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
11288 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
11289 
11290 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
11291 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
11292 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
11293 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
11294 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
11295 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
11296 
11297 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
11298 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
11299 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
11300 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
11301 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
11302 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
11303 #define RCC_PLLCFGR_PLLM_3                   (0x8UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000080 */
11304 
11305 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
11306 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
11307 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
11308 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
11309 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
11310 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
11311 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
11312 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
11313 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
11314 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
11315 
11316 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
11317 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
11318 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
11319 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
11320 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
11321 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
11322 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
11323 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
11324 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
11325 
11326 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
11327 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
11328 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
11329 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
11330 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
11331 
11332 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
11333 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
11334 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
11335 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
11336 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
11337 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
11338 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
11339 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
11340 
11341 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
11342 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
11343 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
11344 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
11345 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
11346 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
11347 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
11348 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
11349 
11350 /********************  Bit definition for RCC_CIER register  ******************/
11351 #define RCC_CIER_LSIRDYIE_Pos                (0U)
11352 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
11353 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
11354 #define RCC_CIER_LSERDYIE_Pos                (1U)
11355 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
11356 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
11357 #define RCC_CIER_HSIRDYIE_Pos                (3U)
11358 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
11359 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
11360 #define RCC_CIER_HSERDYIE_Pos                (4U)
11361 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
11362 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
11363 #define RCC_CIER_PLLRDYIE_Pos                (5U)
11364 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
11365 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
11366 #define RCC_CIER_LSECSSIE_Pos                (9U)
11367 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
11368 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
11369 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
11370 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
11371 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
11372 
11373 /********************  Bit definition for RCC_CIFR register  ******************/
11374 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
11375 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
11376 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
11377 #define RCC_CIFR_LSERDYF_Pos                 (1U)
11378 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
11379 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
11380 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
11381 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
11382 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
11383 #define RCC_CIFR_HSERDYF_Pos                 (4U)
11384 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
11385 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
11386 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
11387 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
11388 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
11389 #define RCC_CIFR_CSSF_Pos                    (8U)
11390 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
11391 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
11392 #define RCC_CIFR_LSECSSF_Pos                 (9U)
11393 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
11394 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
11395 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
11396 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
11397 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
11398 
11399 /********************  Bit definition for RCC_CICR register  ******************/
11400 #define RCC_CICR_LSIRDYC_Pos                 (0U)
11401 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
11402 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
11403 #define RCC_CICR_LSERDYC_Pos                 (1U)
11404 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
11405 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
11406 #define RCC_CICR_HSIRDYC_Pos                 (3U)
11407 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
11408 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
11409 #define RCC_CICR_HSERDYC_Pos                 (4U)
11410 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
11411 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
11412 #define RCC_CICR_PLLRDYC_Pos                 (5U)
11413 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
11414 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
11415 #define RCC_CICR_CSSC_Pos                    (8U)
11416 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
11417 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
11418 #define RCC_CICR_LSECSSC_Pos                 (9U)
11419 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
11420 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
11421 #define RCC_CICR_HSI48RDYC_Pos               (10U)
11422 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
11423 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
11424 
11425 /********************  Bit definition for RCC_AHB1RSTR register  **************/
11426 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
11427 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
11428 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
11429 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
11430 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
11431 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
11432 #define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
11433 #define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
11434 #define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
11435 #define RCC_AHB1RSTR_CORDICRST_Pos           (3U)
11436 #define RCC_AHB1RSTR_CORDICRST_Msk           (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
11437 #define RCC_AHB1RSTR_CORDICRST               RCC_AHB1RSTR_CORDICRST_Msk
11438 #define RCC_AHB1RSTR_FMACRST_Pos             (4U)
11439 #define RCC_AHB1RSTR_FMACRST_Msk             (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)  /*!< 0x00000010 */
11440 #define RCC_AHB1RSTR_FMACRST                 RCC_AHB1RSTR_FMACRST_Msk
11441 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
11442 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
11443 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
11444 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
11445 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
11446 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
11447 
11448 /********************  Bit definition for RCC_AHB2RSTR register  **************/
11449 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
11450 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
11451 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
11452 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
11453 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
11454 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
11455 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
11456 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
11457 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
11458 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
11459 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
11460 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
11461 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
11462 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
11463 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
11464 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
11465 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
11466 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
11467 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
11468 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
11469 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
11470 #define RCC_AHB2RSTR_ADC12RST_Pos            (13U)
11471 #define RCC_AHB2RSTR_ADC12RST_Msk            (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
11472 #define RCC_AHB2RSTR_ADC12RST                RCC_AHB2RSTR_ADC12RST_Msk
11473 #define RCC_AHB2RSTR_DAC1RST_Pos             (16U)
11474 #define RCC_AHB2RSTR_DAC1RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
11475 #define RCC_AHB2RSTR_DAC1RST                 RCC_AHB2RSTR_DAC1RST_Msk
11476 #define RCC_AHB2RSTR_DAC2RST_Pos             (17U)
11477 #define RCC_AHB2RSTR_DAC2RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
11478 #define RCC_AHB2RSTR_DAC2RST                 RCC_AHB2RSTR_DAC2RST_Msk
11479 #define RCC_AHB2RSTR_DAC3RST_Pos             (18U)
11480 #define RCC_AHB2RSTR_DAC3RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
11481 #define RCC_AHB2RSTR_DAC3RST                 RCC_AHB2RSTR_DAC3RST_Msk
11482 #define RCC_AHB2RSTR_DAC4RST_Pos             (19U)
11483 #define RCC_AHB2RSTR_DAC4RST_Msk             (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
11484 #define RCC_AHB2RSTR_DAC4RST                 RCC_AHB2RSTR_DAC4RST_Msk
11485 #define RCC_AHB2RSTR_AESRST_Pos              (24U)
11486 #define RCC_AHB2RSTR_AESRST_Msk              (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x01000000 */
11487 #define RCC_AHB2RSTR_AESRST                  RCC_AHB2RSTR_AESRST_Msk
11488 #define RCC_AHB2RSTR_RNGRST_Pos              (26U)
11489 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
11490 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
11491 
11492 /********************  Bit definition for RCC_AHB3RSTR register  **************/
11493 
11494 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
11495 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
11496 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
11497 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
11498 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
11499 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
11500 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
11501 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
11502 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
11503 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
11504 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
11505 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
11506 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
11507 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
11508 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
11509 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
11510 #define RCC_APB1RSTR1_CRSRST_Pos             (8U)
11511 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
11512 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
11513 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
11514 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
11515 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
11516 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
11517 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
11518 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
11519 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
11520 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
11521 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
11522 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
11523 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
11524 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
11525 #define RCC_APB1RSTR1_UART5RST_Pos           (20U)
11526 #define RCC_APB1RSTR1_UART5RST_Msk           (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
11527 #define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk
11528 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
11529 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
11530 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
11531 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
11532 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
11533 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
11534 #define RCC_APB1RSTR1_FDCANRST_Pos           (25U)
11535 #define RCC_APB1RSTR1_FDCANRST_Msk           (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
11536 #define RCC_APB1RSTR1_FDCANRST               RCC_APB1RSTR1_FDCANRST_Msk
11537 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
11538 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
11539 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
11540 #define RCC_APB1RSTR1_I2C3RST_Pos            (30U)
11541 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
11542 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
11543 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
11544 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
11545 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
11546 
11547 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
11548 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
11549 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
11550 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
11551 
11552 /********************  Bit definition for RCC_APB2RSTR register  **************/
11553 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
11554 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
11555 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
11556 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
11557 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
11558 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
11559 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
11560 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
11561 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
11562 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
11563 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
11564 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
11565 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
11566 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
11567 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
11568 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
11569 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
11570 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
11571 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
11572 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
11573 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
11574 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
11575 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
11576 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
11577 #define RCC_APB2RSTR_HRTIM1RST_Pos           (26U)
11578 #define RCC_APB2RSTR_HRTIM1RST_Msk           (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)/*!< 0x04000000 */
11579 #define RCC_APB2RSTR_HRTIM1RST               RCC_APB2RSTR_HRTIM1RST_Msk
11580 
11581 /********************  Bit definition for RCC_AHB1ENR register  ***************/
11582 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
11583 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
11584 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
11585 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
11586 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
11587 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
11588 #define RCC_AHB1ENR_DMAMUX1EN_Pos            (2U)
11589 #define RCC_AHB1ENR_DMAMUX1EN_Msk            (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
11590 #define RCC_AHB1ENR_DMAMUX1EN                RCC_AHB1ENR_DMAMUX1EN_Msk
11591 #define RCC_AHB1ENR_CORDICEN_Pos             (3U)
11592 #define RCC_AHB1ENR_CORDICEN_Msk             (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
11593 #define RCC_AHB1ENR_CORDICEN                 RCC_AHB1ENR_CORDICEN_Msk
11594 #define RCC_AHB1ENR_FMACEN_Pos               (4U)
11595 #define RCC_AHB1ENR_FMACEN_Msk               (0x1UL << RCC_AHB1ENR_FMACEN_Pos)  /*!< 0x00000010 */
11596 #define RCC_AHB1ENR_FMACEN                   RCC_AHB1ENR_FMACEN_Msk
11597 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
11598 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
11599 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
11600 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
11601 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
11602 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
11603 
11604 /********************  Bit definition for RCC_AHB2ENR register  ***************/
11605 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
11606 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
11607 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
11608 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
11609 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
11610 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
11611 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
11612 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
11613 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
11614 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
11615 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
11616 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
11617 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
11618 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
11619 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
11620 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
11621 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
11622 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
11623 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
11624 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
11625 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
11626 #define RCC_AHB2ENR_ADC12EN_Pos              (13U)
11627 #define RCC_AHB2ENR_ADC12EN_Msk              (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)  /*!< 0x00002000 */
11628 #define RCC_AHB2ENR_ADC12EN                  RCC_AHB2ENR_ADC12EN_Msk
11629 #define RCC_AHB2ENR_DAC1EN_Pos               (16U)
11630 #define RCC_AHB2ENR_DAC1EN_Msk               (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)  /*!< 0x00010000 */
11631 #define RCC_AHB2ENR_DAC1EN                   RCC_AHB2ENR_DAC1EN_Msk
11632 #define RCC_AHB2ENR_DAC2EN_Pos               (17U)
11633 #define RCC_AHB2ENR_DAC2EN_Msk               (0x1UL << RCC_AHB2ENR_DAC2EN_Pos)  /*!< 0x00020000 */
11634 #define RCC_AHB2ENR_DAC2EN                   RCC_AHB2ENR_DAC2EN_Msk
11635 #define RCC_AHB2ENR_DAC3EN_Pos               (18U)
11636 #define RCC_AHB2ENR_DAC3EN_Msk               (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)  /*!< 0x00040000 */
11637 #define RCC_AHB2ENR_DAC3EN                   RCC_AHB2ENR_DAC3EN_Msk
11638 #define RCC_AHB2ENR_DAC4EN_Pos               (19U)
11639 #define RCC_AHB2ENR_DAC4EN_Msk               (0x1UL << RCC_AHB2ENR_DAC4EN_Pos)  /*!< 0x00080000 */
11640 #define RCC_AHB2ENR_DAC4EN                   RCC_AHB2ENR_DAC4EN_Msk
11641 #define RCC_AHB2ENR_AESEN_Pos                (24U)
11642 #define RCC_AHB2ENR_AESEN_Msk                (0x1UL << RCC_AHB2ENR_AESEN_Pos)  /*!< 0x01000000 */
11643 #define RCC_AHB2ENR_AESEN                    RCC_AHB2ENR_AESEN_Msk
11644 #define RCC_AHB2ENR_RNGEN_Pos                (26U)
11645 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x04000000 */
11646 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
11647 
11648 /********************  Bit definition for RCC_AHB3ENR register  ***************/
11649 
11650 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
11651 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
11652 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
11653 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
11654 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
11655 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
11656 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
11657 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
11658 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
11659 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
11660 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
11661 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
11662 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
11663 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
11664 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
11665 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
11666 #define RCC_APB1ENR1_CRSEN_Pos               (8U)
11667 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
11668 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
11669 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
11670 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
11671 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
11672 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
11673 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
11674 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
11675 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
11676 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
11677 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
11678 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
11679 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
11680 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
11681 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
11682 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
11683 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
11684 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
11685 #define RCC_APB1ENR1_UART4EN_Msk             (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
11686 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
11687 #define RCC_APB1ENR1_UART5EN_Pos             (20U)
11688 #define RCC_APB1ENR1_UART5EN_Msk             (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
11689 #define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk
11690 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
11691 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
11692 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
11693 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
11694 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
11695 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
11696 #define RCC_APB1ENR1_FDCANEN_Pos             (25U)
11697 #define RCC_APB1ENR1_FDCANEN_Msk             (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
11698 #define RCC_APB1ENR1_FDCANEN                 RCC_APB1ENR1_FDCANEN_Msk
11699 #define RCC_APB1ENR1_PWREN_Pos               (28U)
11700 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
11701 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
11702 #define RCC_APB1ENR1_I2C3EN_Pos              (30U)
11703 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
11704 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
11705 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
11706 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
11707 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
11708 
11709 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
11710 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
11711 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
11712 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
11713 
11714 /********************  Bit definition for RCC_APB2ENR register  ***************/
11715 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
11716 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
11717 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
11718 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
11719 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
11720 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
11721 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
11722 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
11723 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
11724 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
11725 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
11726 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
11727 #define RCC_APB2ENR_USART1EN_Pos             (14U)
11728 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
11729 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
11730 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
11731 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
11732 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
11733 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
11734 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
11735 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
11736 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
11737 #define RCC_APB2ENR_TIM17EN_Msk              (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
11738 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
11739 #define RCC_APB2ENR_HRTIM1EN_Pos              (26U)
11740 #define RCC_APB2ENR_HRTIM1EN_Msk              (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)/*!< 0x04000000 */
11741 #define RCC_APB2ENR_HRTIM1EN                  RCC_APB2ENR_HRTIM1EN_Msk
11742 
11743 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
11744 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
11745 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
11746 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
11747 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
11748 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
11749 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
11750 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos        (2U)
11751 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk        (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
11752 #define RCC_AHB1SMENR_DMAMUX1SMEN            RCC_AHB1SMENR_DMAMUX1SMEN_Msk
11753 #define RCC_AHB1SMENR_CORDICSMEN_Pos         (3U)
11754 #define RCC_AHB1SMENR_CORDICSMEN_Msk         (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
11755 #define RCC_AHB1SMENR_CORDICSMEN             RCC_AHB1SMENR_CORDICSMEN_Msk
11756 #define RCC_AHB1SMENR_FMACSMEN_Pos           (4U)
11757 #define RCC_AHB1SMENR_FMACSMEN_Msk           (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)  /*!< 0x00000010 */
11758 #define RCC_AHB1SMENR_FMACSMEN               RCC_AHB1SMENR_FMACSMEN_Msk
11759 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
11760 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
11761 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
11762 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
11763 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
11764 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
11765 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
11766 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
11767 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
11768 
11769 /********************  Bit definition for RCC_AHB2SMENR register  *************/
11770 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
11771 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
11772 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
11773 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
11774 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
11775 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
11776 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
11777 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
11778 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
11779 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
11780 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
11781 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
11782 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
11783 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
11784 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
11785 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
11786 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
11787 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
11788 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
11789 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
11790 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
11791 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos        (9U)
11792 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk        (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)  /*!< 0x00000200 */
11793 #define RCC_AHB2SMENR_CCMSRAMSMEN            RCC_AHB2SMENR_CCMSRAMSMEN_Msk
11794 #define RCC_AHB2SMENR_ADC12SMEN_Pos          (13U)
11795 #define RCC_AHB2SMENR_ADC12SMEN_Msk          (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
11796 #define RCC_AHB2SMENR_ADC12SMEN              RCC_AHB2SMENR_ADC12SMEN_Msk
11797 #define RCC_AHB2SMENR_DAC1SMEN_Pos           (16U)
11798 #define RCC_AHB2SMENR_DAC1SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
11799 #define RCC_AHB2SMENR_DAC1SMEN               RCC_AHB2SMENR_DAC1SMEN_Msk
11800 #define RCC_AHB2SMENR_DAC2SMEN_Pos           (17U)
11801 #define RCC_AHB2SMENR_DAC2SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
11802 #define RCC_AHB2SMENR_DAC2SMEN               RCC_AHB2SMENR_DAC2SMEN_Msk
11803 #define RCC_AHB2SMENR_DAC3SMEN_Pos           (18U)
11804 #define RCC_AHB2SMENR_DAC3SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
11805 #define RCC_AHB2SMENR_DAC3SMEN               RCC_AHB2SMENR_DAC3SMEN_Msk
11806 #define RCC_AHB2SMENR_DAC4SMEN_Pos           (19U)
11807 #define RCC_AHB2SMENR_DAC4SMEN_Msk           (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
11808 #define RCC_AHB2SMENR_DAC4SMEN               RCC_AHB2SMENR_DAC4SMEN_Msk
11809 #define RCC_AHB2SMENR_AESSMEN_Pos            (24U)
11810 #define RCC_AHB2SMENR_AESSMEN_Msk            (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x01000000 */
11811 #define RCC_AHB2SMENR_AESSMEN                RCC_AHB2SMENR_AESSMEN_Msk
11812 #define RCC_AHB2SMENR_RNGSMEN_Pos            (26U)
11813 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
11814 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
11815 
11816 /********************  Bit definition for RCC_AHB3SMENR register  *************/
11817 
11818 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
11819 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
11820 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
11821 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
11822 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
11823 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
11824 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
11825 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
11826 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
11827 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
11828 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
11829 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
11830 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
11831 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
11832 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
11833 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
11834 #define RCC_APB1SMENR1_CRSSMEN_Pos           (8U)
11835 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
11836 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
11837 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
11838 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
11839 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
11840 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
11841 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
11842 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
11843 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
11844 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
11845 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
11846 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
11847 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
11848 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
11849 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
11850 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
11851 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
11852 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
11853 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
11854 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
11855 #define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)
11856 #define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
11857 #define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk
11858 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
11859 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
11860 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
11861 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
11862 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
11863 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
11864 #define RCC_APB1SMENR1_FDCANSMEN_Pos         (25U)
11865 #define RCC_APB1SMENR1_FDCANSMEN_Msk         (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
11866 #define RCC_APB1SMENR1_FDCANSMEN             RCC_APB1SMENR1_FDCANSMEN_Msk
11867 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
11868 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
11869 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
11870 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (30U)
11871 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
11872 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
11873 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
11874 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
11875 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
11876 
11877 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
11878 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
11879 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
11880 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
11881 
11882 /********************  Bit definition for RCC_APB2SMENR register  *************/
11883 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
11884 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
11885 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
11886 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
11887 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
11888 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
11889 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
11890 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
11891 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
11892 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
11893 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
11894 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
11895 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
11896 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
11897 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
11898 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
11899 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
11900 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
11901 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
11902 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
11903 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
11904 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
11905 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
11906 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
11907 #define RCC_APB2SMENR_HRTIM1SMEN_Pos          (26U)
11908 #define RCC_APB2SMENR_HRTIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_HRTIM1SMEN_Pos)/*!< 0x04000000 */
11909 #define RCC_APB2SMENR_HRTIM1SMEN              RCC_APB2SMENR_HRTIM1SMEN_Msk
11910 
11911 /********************  Bit definition for RCC_CCIPR register  ******************/
11912 #define RCC_CCIPR_USART1SEL_Pos              (0U)
11913 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
11914 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
11915 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
11916 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
11917 
11918 #define RCC_CCIPR_USART2SEL_Pos              (2U)
11919 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
11920 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
11921 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
11922 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
11923 
11924 
11925 #define RCC_CCIPR_UART4SEL_Pos               (6U)
11926 #define RCC_CCIPR_UART4SEL_Msk               (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
11927 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
11928 #define RCC_CCIPR_UART4SEL_0                 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
11929 #define RCC_CCIPR_UART4SEL_1                 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
11930 
11931 #define RCC_CCIPR_UART5SEL_Pos               (8U)
11932 #define RCC_CCIPR_UART5SEL_Msk               (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
11933 #define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk
11934 #define RCC_CCIPR_UART5SEL_0                 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
11935 #define RCC_CCIPR_UART5SEL_1                 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
11936 
11937 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
11938 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
11939 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
11940 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
11941 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
11942 
11943 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
11944 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
11945 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
11946 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
11947 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
11948 
11949 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
11950 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
11951 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
11952 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
11953 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
11954 
11955 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
11956 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
11957 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
11958 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
11959 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
11960 
11961 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
11962 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
11963 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
11964 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
11965 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
11966 
11967 
11968 
11969 #define RCC_CCIPR_FDCANSEL_Pos               (24U)
11970 #define RCC_CCIPR_FDCANSEL_Msk               (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
11971 #define RCC_CCIPR_FDCANSEL                   RCC_CCIPR_FDCANSEL_Msk
11972 #define RCC_CCIPR_FDCANSEL_0                 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
11973 #define RCC_CCIPR_FDCANSEL_1                 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
11974 
11975 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
11976 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
11977 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
11978 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
11979 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
11980 
11981 #define RCC_CCIPR_ADC12SEL_Pos               (28U)
11982 #define RCC_CCIPR_ADC12SEL_Msk               (0x3UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x30000000 */
11983 #define RCC_CCIPR_ADC12SEL                   RCC_CCIPR_ADC12SEL_Msk
11984 #define RCC_CCIPR_ADC12SEL_0                 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x10000000 */
11985 #define RCC_CCIPR_ADC12SEL_1                 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)   /*!< 0x20000000 */
11986 
11987 
11988 /********************  Bit definition for RCC_BDCR register  ******************/
11989 #define RCC_BDCR_LSEON_Pos                   (0U)
11990 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
11991 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
11992 #define RCC_BDCR_LSERDY_Pos                  (1U)
11993 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
11994 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
11995 #define RCC_BDCR_LSEBYP_Pos                  (2U)
11996 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
11997 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
11998 
11999 #define RCC_BDCR_LSEDRV_Pos                  (3U)
12000 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
12001 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
12002 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
12003 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
12004 
12005 #define RCC_BDCR_LSECSSON_Pos                (5U)
12006 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
12007 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
12008 #define RCC_BDCR_LSECSSD_Pos                 (6U)
12009 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
12010 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
12011 
12012 #define RCC_BDCR_RTCSEL_Pos                  (8U)
12013 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
12014 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
12015 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
12016 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
12017 
12018 #define RCC_BDCR_RTCEN_Pos                   (15U)
12019 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
12020 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
12021 #define RCC_BDCR_BDRST_Pos                   (16U)
12022 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
12023 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
12024 #define RCC_BDCR_LSCOEN_Pos                  (24U)
12025 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
12026 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
12027 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
12028 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
12029 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
12030 
12031 /********************  Bit definition for RCC_CSR register  *******************/
12032 #define RCC_CSR_LSION_Pos                    (0U)
12033 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
12034 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
12035 #define RCC_CSR_LSIRDY_Pos                   (1U)
12036 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
12037 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
12038 
12039 #define RCC_CSR_RMVF_Pos                     (23U)
12040 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
12041 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
12042 #define RCC_CSR_OBLRSTF_Pos                  (25U)
12043 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
12044 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
12045 #define RCC_CSR_PINRSTF_Pos                  (26U)
12046 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
12047 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
12048 #define RCC_CSR_BORRSTF_Pos                  (27U)
12049 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
12050 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
12051 #define RCC_CSR_SFTRSTF_Pos                  (28U)
12052 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
12053 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
12054 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
12055 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
12056 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
12057 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
12058 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
12059 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
12060 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
12061 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
12062 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
12063 
12064 /********************  Bit definition for RCC_CRRCR register  *****************/
12065 #define RCC_CRRCR_HSI48ON_Pos                (0U)
12066 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
12067 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
12068 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
12069 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
12070 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
12071 
12072 /*!< HSI48CAL configuration */
12073 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
12074 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
12075 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
12076 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
12077 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
12078 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
12079 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
12080 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
12081 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
12082 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
12083 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
12084 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
12085 
12086 /********************  Bit definition for RCC_CCIPR2 register  ******************/
12087 
12088 
12089 /******************************************************************************/
12090 /*                                                                            */
12091 /*                                    RNG                                     */
12092 /*                                                                            */
12093 /******************************************************************************/
12094 /********************  Bits definition for RNG_CR register  *******************/
12095 #define RNG_CR_RNGEN_Pos    (2U)
12096 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
12097 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
12098 #define RNG_CR_IE_Pos       (3U)
12099 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
12100 #define RNG_CR_IE           RNG_CR_IE_Msk
12101 #define RNG_CR_CED_Pos      (5U)
12102 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000020 */
12103 #define RNG_CR_CED          RNG_CR_IE_Msk
12104 
12105 /********************  Bits definition for RNG_SR register  *******************/
12106 #define RNG_SR_DRDY_Pos     (0U)
12107 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
12108 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
12109 #define RNG_SR_CECS_Pos     (1U)
12110 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
12111 #define RNG_SR_CECS         RNG_SR_CECS_Msk
12112 #define RNG_SR_SECS_Pos     (2U)
12113 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
12114 #define RNG_SR_SECS         RNG_SR_SECS_Msk
12115 #define RNG_SR_CEIS_Pos     (5U)
12116 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
12117 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
12118 #define RNG_SR_SEIS_Pos     (6U)
12119 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
12120 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
12121 
12122 /******************************************************************************/
12123 /*                                                                            */
12124 /*                           Real-Time Clock (RTC)                            */
12125 /*                                                                            */
12126 /******************************************************************************/
12127 
12128 /********************  Bits definition for RTC_TR register  *******************/
12129 #define RTC_TR_PM_Pos                (22U)
12130 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
12131 #define RTC_TR_PM                    RTC_TR_PM_Msk
12132 #define RTC_TR_HT_Pos                (20U)
12133 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
12134 #define RTC_TR_HT                    RTC_TR_HT_Msk
12135 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
12136 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
12137 #define RTC_TR_HU_Pos                (16U)
12138 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
12139 #define RTC_TR_HU                    RTC_TR_HU_Msk
12140 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
12141 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
12142 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
12143 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
12144 #define RTC_TR_MNT_Pos               (12U)
12145 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
12146 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
12147 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
12148 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
12149 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
12150 #define RTC_TR_MNU_Pos               (8U)
12151 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
12152 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
12153 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
12154 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
12155 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
12156 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
12157 #define RTC_TR_ST_Pos                (4U)
12158 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
12159 #define RTC_TR_ST                    RTC_TR_ST_Msk
12160 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
12161 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
12162 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
12163 #define RTC_TR_SU_Pos                (0U)
12164 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
12165 #define RTC_TR_SU                    RTC_TR_SU_Msk
12166 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
12167 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
12168 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
12169 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
12170 
12171 /********************  Bits definition for RTC_DR register  *******************/
12172 #define RTC_DR_YT_Pos                (20U)
12173 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
12174 #define RTC_DR_YT                    RTC_DR_YT_Msk
12175 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
12176 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
12177 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
12178 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
12179 #define RTC_DR_YU_Pos                (16U)
12180 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
12181 #define RTC_DR_YU                    RTC_DR_YU_Msk
12182 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
12183 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
12184 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
12185 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
12186 #define RTC_DR_WDU_Pos               (13U)
12187 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
12188 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
12189 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
12190 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
12191 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
12192 #define RTC_DR_MT_Pos                (12U)
12193 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
12194 #define RTC_DR_MT                    RTC_DR_MT_Msk
12195 #define RTC_DR_MU_Pos                (8U)
12196 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
12197 #define RTC_DR_MU                    RTC_DR_MU_Msk
12198 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
12199 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
12200 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
12201 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
12202 #define RTC_DR_DT_Pos                (4U)
12203 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
12204 #define RTC_DR_DT                    RTC_DR_DT_Msk
12205 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
12206 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
12207 #define RTC_DR_DU_Pos                (0U)
12208 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
12209 #define RTC_DR_DU                    RTC_DR_DU_Msk
12210 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
12211 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
12212 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
12213 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
12214 
12215 /********************  Bits definition for RTC_SSR register  ******************/
12216 #define RTC_SSR_SS_Pos               (0U)
12217 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
12218 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
12219 
12220 /********************  Bits definition for RTC_ICSR register  ******************/
12221 #define RTC_ICSR_RECALPF_Pos         (16U)
12222 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
12223 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
12224 #define RTC_ICSR_INIT_Pos            (7U)
12225 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
12226 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
12227 #define RTC_ICSR_INITF_Pos           (6U)
12228 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
12229 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
12230 #define RTC_ICSR_RSF_Pos             (5U)
12231 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
12232 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
12233 #define RTC_ICSR_INITS_Pos           (4U)
12234 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
12235 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
12236 #define RTC_ICSR_SHPF_Pos            (3U)
12237 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
12238 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
12239 #define RTC_ICSR_WUTWF_Pos           (2U)
12240 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
12241 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
12242 #define RTC_ICSR_ALRBWF_Pos          (1U)
12243 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */
12244 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
12245 #define RTC_ICSR_ALRAWF_Pos          (0U)
12246 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */
12247 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
12248 
12249 /********************  Bits definition for RTC_PRER register  *****************/
12250 #define RTC_PRER_PREDIV_A_Pos        (16U)
12251 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
12252 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
12253 #define RTC_PRER_PREDIV_S_Pos        (0U)
12254 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
12255 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
12256 
12257 /********************  Bits definition for RTC_WUTR register  *****************/
12258 #define RTC_WUTR_WUT_Pos             (0U)
12259 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
12260 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
12261 
12262 /********************  Bits definition for RTC_CR register  *******************/
12263 #define RTC_CR_OUT2EN_Pos            (31U)
12264 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
12265 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
12266 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
12267 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
12268 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
12269 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
12270 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
12271 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
12272 #define RTC_CR_TAMPOE_Pos            (26U)
12273 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
12274 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
12275 #define RTC_CR_TAMPTS_Pos            (25U)
12276 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
12277 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
12278 #define RTC_CR_ITSE_Pos              (24U)
12279 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
12280 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
12281 #define RTC_CR_COE_Pos               (23U)
12282 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
12283 #define RTC_CR_COE                   RTC_CR_COE_Msk
12284 #define RTC_CR_OSEL_Pos              (21U)
12285 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
12286 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
12287 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
12288 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
12289 #define RTC_CR_POL_Pos               (20U)
12290 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
12291 #define RTC_CR_POL                   RTC_CR_POL_Msk
12292 #define RTC_CR_COSEL_Pos             (19U)
12293 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
12294 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
12295 #define RTC_CR_BKP_Pos               (18U)
12296 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
12297 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
12298 #define RTC_CR_SUB1H_Pos             (17U)
12299 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
12300 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
12301 #define RTC_CR_ADD1H_Pos             (16U)
12302 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
12303 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
12304 #define RTC_CR_TSIE_Pos              (15U)
12305 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
12306 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
12307 #define RTC_CR_WUTIE_Pos             (14U)
12308 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
12309 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
12310 #define RTC_CR_ALRBIE_Pos            (13U)
12311 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
12312 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
12313 #define RTC_CR_ALRAIE_Pos            (12U)
12314 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
12315 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
12316 #define RTC_CR_TSE_Pos               (11U)
12317 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
12318 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
12319 #define RTC_CR_WUTE_Pos              (10U)
12320 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
12321 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
12322 #define RTC_CR_ALRBE_Pos             (9U)
12323 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
12324 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
12325 #define RTC_CR_ALRAE_Pos             (8U)
12326 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
12327 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
12328 #define RTC_CR_FMT_Pos               (6U)
12329 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
12330 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
12331 #define RTC_CR_BYPSHAD_Pos           (5U)
12332 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
12333 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
12334 #define RTC_CR_REFCKON_Pos           (4U)
12335 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
12336 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
12337 #define RTC_CR_TSEDGE_Pos            (3U)
12338 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
12339 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
12340 #define RTC_CR_WUCKSEL_Pos           (0U)
12341 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
12342 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
12343 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
12344 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
12345 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
12346 
12347 /********************  Bits definition for RTC_WPR register  ******************/
12348 #define RTC_WPR_KEY_Pos              (0U)
12349 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
12350 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
12351 
12352 /********************  Bits definition for RTC_CALR register  *****************/
12353 #define RTC_CALR_CALP_Pos            (15U)
12354 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
12355 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
12356 #define RTC_CALR_CALW8_Pos           (14U)
12357 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
12358 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
12359 #define RTC_CALR_CALW16_Pos          (13U)
12360 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
12361 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
12362 #define RTC_CALR_CALM_Pos            (0U)
12363 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
12364 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
12365 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
12366 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
12367 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
12368 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
12369 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
12370 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
12371 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
12372 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
12373 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
12374 
12375 /********************  Bits definition for RTC_SHIFTR register  ***************/
12376 #define RTC_SHIFTR_SUBFS_Pos         (0U)
12377 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
12378 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
12379 #define RTC_SHIFTR_ADD1S_Pos         (31U)
12380 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
12381 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
12382 
12383 /********************  Bits definition for RTC_TSTR register  *****************/
12384 #define RTC_TSTR_PM_Pos              (22U)
12385 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
12386 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
12387 #define RTC_TSTR_HT_Pos              (20U)
12388 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
12389 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
12390 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
12391 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
12392 #define RTC_TSTR_HU_Pos              (16U)
12393 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
12394 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
12395 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
12396 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
12397 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
12398 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
12399 #define RTC_TSTR_MNT_Pos             (12U)
12400 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
12401 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
12402 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
12403 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
12404 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
12405 #define RTC_TSTR_MNU_Pos             (8U)
12406 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
12407 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
12408 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
12409 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
12410 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
12411 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
12412 #define RTC_TSTR_ST_Pos              (4U)
12413 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
12414 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
12415 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
12416 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
12417 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
12418 #define RTC_TSTR_SU_Pos              (0U)
12419 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
12420 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
12421 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
12422 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
12423 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
12424 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
12425 
12426 /********************  Bits definition for RTC_TSDR register  *****************/
12427 #define RTC_TSDR_WDU_Pos             (13U)
12428 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
12429 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
12430 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
12431 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
12432 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
12433 #define RTC_TSDR_MT_Pos              (12U)
12434 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
12435 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
12436 #define RTC_TSDR_MU_Pos              (8U)
12437 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
12438 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
12439 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
12440 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
12441 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
12442 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
12443 #define RTC_TSDR_DT_Pos              (4U)
12444 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
12445 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
12446 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
12447 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
12448 #define RTC_TSDR_DU_Pos              (0U)
12449 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
12450 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
12451 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
12452 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
12453 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
12454 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
12455 
12456 /********************  Bits definition for RTC_TSSSR register  ****************/
12457 #define RTC_TSSSR_SS_Pos             (0U)
12458 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
12459 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
12460 
12461 /********************  Bits definition for RTC_ALRMAR register  ***************/
12462 #define RTC_ALRMAR_MSK4_Pos          (31U)
12463 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
12464 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
12465 #define RTC_ALRMAR_WDSEL_Pos         (30U)
12466 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
12467 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
12468 #define RTC_ALRMAR_DT_Pos            (28U)
12469 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
12470 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
12471 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
12472 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
12473 #define RTC_ALRMAR_DU_Pos            (24U)
12474 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
12475 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
12476 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
12477 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
12478 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
12479 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
12480 #define RTC_ALRMAR_MSK3_Pos          (23U)
12481 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
12482 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
12483 #define RTC_ALRMAR_PM_Pos            (22U)
12484 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
12485 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
12486 #define RTC_ALRMAR_HT_Pos            (20U)
12487 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
12488 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
12489 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
12490 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
12491 #define RTC_ALRMAR_HU_Pos            (16U)
12492 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
12493 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
12494 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
12495 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
12496 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
12497 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
12498 #define RTC_ALRMAR_MSK2_Pos          (15U)
12499 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
12500 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
12501 #define RTC_ALRMAR_MNT_Pos           (12U)
12502 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
12503 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
12504 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
12505 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
12506 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
12507 #define RTC_ALRMAR_MNU_Pos           (8U)
12508 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
12509 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
12510 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
12511 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
12512 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
12513 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
12514 #define RTC_ALRMAR_MSK1_Pos          (7U)
12515 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
12516 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
12517 #define RTC_ALRMAR_ST_Pos            (4U)
12518 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
12519 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
12520 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
12521 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
12522 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
12523 #define RTC_ALRMAR_SU_Pos            (0U)
12524 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
12525 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
12526 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
12527 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
12528 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
12529 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
12530 
12531 /********************  Bits definition for RTC_ALRMASSR register  *************/
12532 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
12533 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
12534 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
12535 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
12536 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
12537 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
12538 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
12539 #define RTC_ALRMASSR_SS_Pos          (0U)
12540 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
12541 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
12542 
12543 /********************  Bits definition for RTC_ALRMBR register  ***************/
12544 #define RTC_ALRMBR_MSK4_Pos          (31U)
12545 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
12546 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
12547 #define RTC_ALRMBR_WDSEL_Pos         (30U)
12548 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
12549 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
12550 #define RTC_ALRMBR_DT_Pos            (28U)
12551 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
12552 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
12553 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
12554 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
12555 #define RTC_ALRMBR_DU_Pos            (24U)
12556 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
12557 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
12558 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
12559 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
12560 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
12561 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
12562 #define RTC_ALRMBR_MSK3_Pos          (23U)
12563 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
12564 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
12565 #define RTC_ALRMBR_PM_Pos            (22U)
12566 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
12567 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
12568 #define RTC_ALRMBR_HT_Pos            (20U)
12569 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
12570 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
12571 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
12572 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
12573 #define RTC_ALRMBR_HU_Pos            (16U)
12574 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
12575 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
12576 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
12577 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
12578 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
12579 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
12580 #define RTC_ALRMBR_MSK2_Pos          (15U)
12581 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
12582 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
12583 #define RTC_ALRMBR_MNT_Pos           (12U)
12584 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
12585 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
12586 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
12587 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
12588 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
12589 #define RTC_ALRMBR_MNU_Pos           (8U)
12590 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
12591 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
12592 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
12593 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
12594 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
12595 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
12596 #define RTC_ALRMBR_MSK1_Pos          (7U)
12597 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
12598 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
12599 #define RTC_ALRMBR_ST_Pos            (4U)
12600 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
12601 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
12602 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
12603 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
12604 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
12605 #define RTC_ALRMBR_SU_Pos            (0U)
12606 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
12607 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
12608 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
12609 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
12610 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
12611 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
12612 
12613 /********************  Bits definition for RTC_ALRMASSR register  *************/
12614 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
12615 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
12616 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
12617 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
12618 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
12619 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
12620 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
12621 #define RTC_ALRMBSSR_SS_Pos          (0U)
12622 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
12623 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
12624 
12625 /********************  Bits definition for RTC_SR register  *******************/
12626 #define RTC_SR_ITSF_Pos              (5U)
12627 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
12628 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
12629 #define RTC_SR_TSOVF_Pos             (4U)
12630 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
12631 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
12632 #define RTC_SR_TSF_Pos               (3U)
12633 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
12634 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
12635 #define RTC_SR_WUTF_Pos              (2U)
12636 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
12637 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
12638 #define RTC_SR_ALRBF_Pos             (1U)
12639 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
12640 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
12641 #define RTC_SR_ALRAF_Pos             (0U)
12642 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
12643 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
12644 
12645 /********************  Bits definition for RTC_MISR register  *****************/
12646 #define RTC_MISR_ITSMF_Pos           (5U)
12647 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
12648 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
12649 #define RTC_MISR_TSOVMF_Pos          (4U)
12650 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
12651 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
12652 #define RTC_MISR_TSMF_Pos            (3U)
12653 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
12654 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
12655 #define RTC_MISR_WUTMF_Pos           (2U)
12656 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
12657 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
12658 #define RTC_MISR_ALRBMF_Pos          (1U)
12659 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
12660 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
12661 #define RTC_MISR_ALRAMF_Pos          (0U)
12662 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
12663 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
12664 
12665 /********************  Bits definition for RTC_SCR register  ******************/
12666 #define RTC_SCR_CITSF_Pos            (5U)
12667 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
12668 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
12669 #define RTC_SCR_CTSOVF_Pos           (4U)
12670 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
12671 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
12672 #define RTC_SCR_CTSF_Pos             (3U)
12673 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
12674 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
12675 #define RTC_SCR_CWUTF_Pos            (2U)
12676 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
12677 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
12678 #define RTC_SCR_CALRBF_Pos           (1U)
12679 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
12680 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
12681 #define RTC_SCR_CALRAF_Pos           (0U)
12682 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
12683 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
12684 
12685 /******************************************************************************/
12686 /*                                                                            */
12687 /*                     Tamper and backup register (TAMP)                      */
12688 /*                                                                            */
12689 /******************************************************************************/
12690 /********************  Bits definition for TAMP_CR1 register  *****************/
12691 #define TAMP_CR1_TAMP1E_Pos          (0U)
12692 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
12693 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
12694 #define TAMP_CR1_TAMP2E_Pos          (1U)
12695 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
12696 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
12697 #define TAMP_CR1_TAMP3E_Pos          (2U)
12698 #define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
12699 #define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
12700 #define TAMP_CR1_ITAMP3E_Pos         (18U)
12701 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
12702 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
12703 #define TAMP_CR1_ITAMP4E_Pos         (19U)
12704 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */
12705 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
12706 #define TAMP_CR1_ITAMP5E_Pos         (20U)
12707 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
12708 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
12709 #define TAMP_CR1_ITAMP6E_Pos         (21U)
12710 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */
12711 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
12712 
12713 /********************  Bits definition for TAMP_CR2 register  *****************/
12714 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
12715 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
12716 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
12717 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
12718 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
12719 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
12720 #define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
12721 #define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
12722 #define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
12723 #define TAMP_CR2_TAMP1MSK_Pos         (16U)
12724 #define TAMP_CR2_TAMP1MSK_Msk         (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
12725 #define TAMP_CR2_TAMP1MSK             TAMP_CR2_TAMP1MSK_Msk
12726 #define TAMP_CR2_TAMP2MSK_Pos         (17U)
12727 #define TAMP_CR2_TAMP2MSK_Msk         (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
12728 #define TAMP_CR2_TAMP2MSK             TAMP_CR2_TAMP2MSK_Msk
12729 #define TAMP_CR2_TAMP3MSK_Pos         (18U)
12730 #define TAMP_CR2_TAMP3MSK_Msk         (0x1UL << TAMP_CR2_TAMP3MSK_Pos)           /*!< 0x00040000 */
12731 #define TAMP_CR2_TAMP3MSK             TAMP_CR2_TAMP3MSK_Msk
12732 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
12733 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
12734 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
12735 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
12736 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
12737 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
12738 #define TAMP_CR2_TAMP3TRG_Pos        (26U)
12739 #define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */
12740 #define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
12741 
12742 /* Legacy aliases */
12743 #define TAMP_CR2_TAMP1MF_Pos            TAMP_CR2_TAMP1MSK_Pos
12744 #define TAMP_CR2_TAMP1MF_Msk            TAMP_CR2_TAMP1MSK_Msk
12745 #define TAMP_CR2_TAMP1MF                TAMP_CR2_TAMP1MSK
12746 #define TAMP_CR2_TAMP2MF_Pos            TAMP_CR2_TAMP2MSK_Pos
12747 #define TAMP_CR2_TAMP2MF_Msk            TAMP_CR2_TAMP2MSK_Msk
12748 #define TAMP_CR2_TAMP2MF                TAMP_CR2_TAMP2MSK
12749 #define TAMP_CR2_TAMP3MF_Pos            TAMP_CR2_TAMP3MSK_Pos
12750 #define TAMP_CR2_TAMP3MF_Msk            TAMP_CR2_TAMP3MSK_Msk
12751 #define TAMP_CR2_TAMP3MF                TAMP_CR2_TAMP3MSK
12752 
12753 /********************  Bits definition for TAMP_FLTCR register  ***************/
12754 #define TAMP_FLTCR_TAMPFREQ_0        (0x00000001UL)
12755 #define TAMP_FLTCR_TAMPFREQ_1        (0x00000002UL)
12756 #define TAMP_FLTCR_TAMPFREQ_2        (0x00000004UL)
12757 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
12758 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
12759 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
12760 #define TAMP_FLTCR_TAMPFLT_0         (0x00000008UL)
12761 #define TAMP_FLTCR_TAMPFLT_1         (0x00000010UL)
12762 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
12763 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
12764 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
12765 #define TAMP_FLTCR_TAMPPRCH_0        (0x00000020UL)
12766 #define TAMP_FLTCR_TAMPPRCH_1        (0x00000040UL)
12767 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
12768 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
12769 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
12770 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
12771 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
12772 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
12773 
12774 /********************  Bits definition for TAMP_IER register  *****************/
12775 #define TAMP_IER_TAMP1IE_Pos         (0U)
12776 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
12777 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
12778 #define TAMP_IER_TAMP2IE_Pos         (1U)
12779 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
12780 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
12781 #define TAMP_IER_TAMP3IE_Pos         (2U)
12782 #define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
12783 #define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
12784 #define TAMP_IER_ITAMP3IE_Pos        (18U)
12785 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
12786 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
12787 #define TAMP_IER_ITAMP4IE_Pos        (19U)
12788 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */
12789 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
12790 #define TAMP_IER_ITAMP5IE_Pos        (20U)
12791 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
12792 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
12793 #define TAMP_IER_ITAMP6IE_Pos        (21U)
12794 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */
12795 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
12796 
12797 /********************  Bits definition for TAMP_SR register  ******************/
12798 #define TAMP_SR_TAMP1F_Pos           (0U)
12799 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)       /*!< 0x00000001 */
12800 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
12801 #define TAMP_SR_TAMP2F_Pos           (1U)
12802 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)       /*!< 0x00000002 */
12803 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
12804 #define TAMP_SR_TAMP3F_Pos           (2U)
12805 #define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)       /*!< 0x00000004 */
12806 #define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
12807 #define TAMP_SR_ITAMP3F_Pos          (18U)
12808 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)      /*!< 0x00040000 */
12809 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
12810 #define TAMP_SR_ITAMP4F_Pos          (19U)
12811 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)      /*!< 0x00080000 */
12812 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
12813 #define TAMP_SR_ITAMP5F_Pos          (20U)
12814 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)      /*!< 0x00100000 */
12815 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
12816 #define TAMP_SR_ITAMP6F_Pos          (21U)
12817 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)      /*!< 0x00200000 */
12818 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
12819 
12820 /********************  Bits definition for TAMP_MISR register  ****************/
12821 #define TAMP_MISR_TAMP1MF_Pos        (0U)
12822 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)       /*!< 0x00000001 */
12823 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
12824 #define TAMP_MISR_TAMP2MF_Pos        (1U)
12825 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)       /*!< 0x00000002 */
12826 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
12827 #define TAMP_MISR_TAMP3MF_Pos        (2U)
12828 #define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)       /*!< 0x00000004 */
12829 #define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
12830 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
12831 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)      /*!< 0x00040000 */
12832 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
12833 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
12834 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)      /*!< 0x00080000 */
12835 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
12836 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
12837 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)      /*!< 0x00100000 */
12838 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
12839 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
12840 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)      /*!< 0x00200000 */
12841 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
12842 
12843 /********************  Bits definition for TAMP_SCR register  *****************/
12844 #define TAMP_SCR_CTAMP1F_Pos         (0U)
12845 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)       /*!< 0x00000001 */
12846 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
12847 #define TAMP_SCR_CTAMP2F_Pos         (1U)
12848 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)       /*!< 0x00000002 */
12849 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
12850 #define TAMP_SCR_CTAMP3F_Pos         (2U)
12851 #define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)       /*!< 0x00000004 */
12852 #define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
12853 #define TAMP_SCR_CITAMP3F_Pos        (18U)
12854 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)      /*!< 0x00040000 */
12855 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
12856 #define TAMP_SCR_CITAMP4F_Pos        (19U)
12857 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)      /*!< 0x00080000 */
12858 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
12859 #define TAMP_SCR_CITAMP5F_Pos        (20U)
12860 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)      /*!< 0x00100000 */
12861 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
12862 #define TAMP_SCR_CITAMP6F_Pos        (21U)
12863 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)      /*!< 0x00200000 */
12864 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
12865 
12866 /********************  Bits definition for TAMP_BKP0R register  ***************/
12867 #define TAMP_BKP0R_Pos               (0U)
12868 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)         /*!< 0xFFFFFFFF */
12869 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
12870 
12871 /********************  Bits definition for TAMP_BKP1R register  ***************/
12872 #define TAMP_BKP1R_Pos               (0U)
12873 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
12874 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
12875 
12876 /********************  Bits definition for TAMP_BKP2R register  ***************/
12877 #define TAMP_BKP2R_Pos               (0U)
12878 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
12879 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
12880 
12881 /********************  Bits definition for TAMP_BKP3R register  ***************/
12882 #define TAMP_BKP3R_Pos               (0U)
12883 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
12884 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
12885 
12886 /********************  Bits definition for TAMP_BKP4R register  ***************/
12887 #define TAMP_BKP4R_Pos               (0U)
12888 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
12889 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
12890 
12891 /********************  Bits definition for TAMP_BKP5R register  ***************/
12892 #define TAMP_BKP5R_Pos               (0U)
12893 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
12894 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
12895 
12896 /********************  Bits definition for TAMP_BKP6R register  ***************/
12897 #define TAMP_BKP6R_Pos               (0U)
12898 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
12899 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
12900 
12901 /********************  Bits definition for TAMP_BKP7R register  ***************/
12902 #define TAMP_BKP7R_Pos               (0U)
12903 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
12904 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
12905 
12906 /********************  Bits definition for TAMP_BKP8R register  ***************/
12907 #define TAMP_BKP8R_Pos               (0U)
12908 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
12909 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
12910 
12911 /********************  Bits definition for TAMP_BKP9R register  ***************/
12912 #define TAMP_BKP9R_Pos               (0U)
12913 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
12914 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
12915 
12916 /********************  Bits definition for TAMP_BKP10R register  ***************/
12917 #define TAMP_BKP10R_Pos               (0U)
12918 #define TAMP_BKP10R_Msk               (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
12919 #define TAMP_BKP10R                   TAMP_BKP10R_Msk
12920 
12921 /********************  Bits definition for TAMP_BKP11R register  ***************/
12922 #define TAMP_BKP11R_Pos               (0U)
12923 #define TAMP_BKP11R_Msk               (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
12924 #define TAMP_BKP11R                   TAMP_BKP11R_Msk
12925 
12926 /********************  Bits definition for TAMP_BKP12R register  ***************/
12927 #define TAMP_BKP12R_Pos               (0U)
12928 #define TAMP_BKP12R_Msk               (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
12929 #define TAMP_BKP12R                   TAMP_BKP12R_Msk
12930 
12931 /********************  Bits definition for TAMP_BKP13R register  ***************/
12932 #define TAMP_BKP13R_Pos               (0U)
12933 #define TAMP_BKP13R_Msk               (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
12934 #define TAMP_BKP13R                   TAMP_BKP13R_Msk
12935 
12936 /********************  Bits definition for TAMP_BKP14R register  ***************/
12937 #define TAMP_BKP14R_Pos               (0U)
12938 #define TAMP_BKP14R_Msk               (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
12939 #define TAMP_BKP14R                   TAMP_BKP14R_Msk
12940 
12941 /********************  Bits definition for TAMP_BKP15R register  ***************/
12942 #define TAMP_BKP15R_Pos               (0U)
12943 #define TAMP_BKP15R_Msk               (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
12944 #define TAMP_BKP15R                   TAMP_BKP15R_Msk
12945 
12946 /********************  Bits definition for TAMP_BKP16R register  ***************/
12947 #define TAMP_BKP16R_Pos               (0U)
12948 #define TAMP_BKP16R_Msk               (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
12949 #define TAMP_BKP16R                   TAMP_BKP16R_Msk
12950 
12951 /********************  Bits definition for TAMP_BKP17R register  ***************/
12952 #define TAMP_BKP17R_Pos               (0U)
12953 #define TAMP_BKP17R_Msk               (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
12954 #define TAMP_BKP17R                   TAMP_BKP17R_Msk
12955 
12956 /********************  Bits definition for TAMP_BKP18R register  ***************/
12957 #define TAMP_BKP18R_Pos               (0U)
12958 #define TAMP_BKP18R_Msk               (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
12959 #define TAMP_BKP18R                   TAMP_BKP18R_Msk
12960 
12961 /********************  Bits definition for TAMP_BKP19R register  ***************/
12962 #define TAMP_BKP19R_Pos               (0U)
12963 #define TAMP_BKP19R_Msk               (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
12964 #define TAMP_BKP19R                   TAMP_BKP19R_Msk
12965 
12966 /********************  Bits definition for TAMP_BKP20R register  ***************/
12967 #define TAMP_BKP20R_Pos               (0U)
12968 #define TAMP_BKP20R_Msk               (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
12969 #define TAMP_BKP20R                   TAMP_BKP20R_Msk
12970 
12971 /********************  Bits definition for TAMP_BKP21R register  ***************/
12972 #define TAMP_BKP21R_Pos               (0U)
12973 #define TAMP_BKP21R_Msk               (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
12974 #define TAMP_BKP21R                   TAMP_BKP21R_Msk
12975 
12976 /********************  Bits definition for TAMP_BKP22R register  ***************/
12977 #define TAMP_BKP22R_Pos               (0U)
12978 #define TAMP_BKP22R_Msk               (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
12979 #define TAMP_BKP22R                   TAMP_BKP22R_Msk
12980 
12981 /********************  Bits definition for TAMP_BKP23R register  ***************/
12982 #define TAMP_BKP23R_Pos               (0U)
12983 #define TAMP_BKP23R_Msk               (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
12984 #define TAMP_BKP23R                   TAMP_BKP23R_Msk
12985 
12986 /********************  Bits definition for TAMP_BKP24R register  ***************/
12987 #define TAMP_BKP24R_Pos               (0U)
12988 #define TAMP_BKP24R_Msk               (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
12989 #define TAMP_BKP24R                   TAMP_BKP24R_Msk
12990 
12991 /********************  Bits definition for TAMP_BKP25R register  ***************/
12992 #define TAMP_BKP25R_Pos               (0U)
12993 #define TAMP_BKP25R_Msk               (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
12994 #define TAMP_BKP25R                   TAMP_BKP25R_Msk
12995 
12996 /********************  Bits definition for TAMP_BKP26R register  ***************/
12997 #define TAMP_BKP26R_Pos               (0U)
12998 #define TAMP_BKP26R_Msk               (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
12999 #define TAMP_BKP26R                   TAMP_BKP26R_Msk
13000 
13001 /********************  Bits definition for TAMP_BKP27R register  ***************/
13002 #define TAMP_BKP27R_Pos               (0U)
13003 #define TAMP_BKP27R_Msk               (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
13004 #define TAMP_BKP27R                   TAMP_BKP27R_Msk
13005 
13006 /********************  Bits definition for TAMP_BKP28R register  ***************/
13007 #define TAMP_BKP28R_Pos               (0U)
13008 #define TAMP_BKP28R_Msk               (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
13009 #define TAMP_BKP28R                   TAMP_BKP28R_Msk
13010 
13011 /********************  Bits definition for TAMP_BKP29R register  ***************/
13012 #define TAMP_BKP29R_Pos               (0U)
13013 #define TAMP_BKP29R_Msk               (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
13014 #define TAMP_BKP29R                   TAMP_BKP29R_Msk
13015 
13016 /********************  Bits definition for TAMP_BKP30R register  ***************/
13017 #define TAMP_BKP30R_Pos               (0U)
13018 #define TAMP_BKP30R_Msk               (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
13019 #define TAMP_BKP30R                   TAMP_BKP30R_Msk
13020 
13021 /********************  Bits definition for TAMP_BKP31R register  ***************/
13022 #define TAMP_BKP31R_Pos               (0U)
13023 #define TAMP_BKP31R_Msk               (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
13024 #define TAMP_BKP31R                   TAMP_BKP31R_Msk
13025 
13026 
13027 
13028 
13029 /******************************************************************************/
13030 /*                                                                            */
13031 /*                        Serial Peripheral Interface (SPI)                   */
13032 /*                                                                            */
13033 /******************************************************************************/
13034 
13035 /*******************  Bit definition for SPI_CR1 register  ********************/
13036 #define SPI_CR1_CPHA_Pos            (0U)
13037 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
13038 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
13039 #define SPI_CR1_CPOL_Pos            (1U)
13040 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
13041 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
13042 #define SPI_CR1_MSTR_Pos            (2U)
13043 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
13044 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
13045 
13046 #define SPI_CR1_BR_Pos              (3U)
13047 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
13048 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
13049 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
13050 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
13051 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
13052 
13053 #define SPI_CR1_SPE_Pos             (6U)
13054 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
13055 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
13056 #define SPI_CR1_LSBFIRST_Pos        (7U)
13057 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
13058 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
13059 #define SPI_CR1_SSI_Pos             (8U)
13060 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
13061 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
13062 #define SPI_CR1_SSM_Pos             (9U)
13063 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
13064 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
13065 #define SPI_CR1_RXONLY_Pos          (10U)
13066 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
13067 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
13068 #define SPI_CR1_CRCL_Pos            (11U)
13069 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
13070 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
13071 #define SPI_CR1_CRCNEXT_Pos         (12U)
13072 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
13073 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
13074 #define SPI_CR1_CRCEN_Pos           (13U)
13075 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
13076 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
13077 #define SPI_CR1_BIDIOE_Pos          (14U)
13078 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
13079 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
13080 #define SPI_CR1_BIDIMODE_Pos        (15U)
13081 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
13082 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
13083 
13084 /*******************  Bit definition for SPI_CR2 register  ********************/
13085 #define SPI_CR2_RXDMAEN_Pos         (0U)
13086 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
13087 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
13088 #define SPI_CR2_TXDMAEN_Pos         (1U)
13089 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
13090 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
13091 #define SPI_CR2_SSOE_Pos            (2U)
13092 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
13093 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
13094 #define SPI_CR2_NSSP_Pos            (3U)
13095 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
13096 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
13097 #define SPI_CR2_FRF_Pos             (4U)
13098 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
13099 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
13100 #define SPI_CR2_ERRIE_Pos           (5U)
13101 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
13102 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
13103 #define SPI_CR2_RXNEIE_Pos          (6U)
13104 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
13105 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
13106 #define SPI_CR2_TXEIE_Pos           (7U)
13107 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
13108 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
13109 #define SPI_CR2_DS_Pos              (8U)
13110 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
13111 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
13112 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
13113 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
13114 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
13115 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
13116 #define SPI_CR2_FRXTH_Pos           (12U)
13117 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
13118 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
13119 #define SPI_CR2_LDMARX_Pos          (13U)
13120 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
13121 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
13122 #define SPI_CR2_LDMATX_Pos          (14U)
13123 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
13124 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
13125 
13126 /********************  Bit definition for SPI_SR register  ********************/
13127 #define SPI_SR_RXNE_Pos             (0U)
13128 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
13129 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
13130 #define SPI_SR_TXE_Pos              (1U)
13131 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
13132 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
13133 #define SPI_SR_CHSIDE_Pos           (2U)
13134 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
13135 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
13136 #define SPI_SR_UDR_Pos              (3U)
13137 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
13138 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
13139 #define SPI_SR_CRCERR_Pos           (4U)
13140 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
13141 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
13142 #define SPI_SR_MODF_Pos             (5U)
13143 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
13144 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
13145 #define SPI_SR_OVR_Pos              (6U)
13146 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
13147 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
13148 #define SPI_SR_BSY_Pos              (7U)
13149 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
13150 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
13151 #define SPI_SR_FRE_Pos              (8U)
13152 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
13153 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
13154 #define SPI_SR_FRLVL_Pos            (9U)
13155 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
13156 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
13157 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
13158 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
13159 #define SPI_SR_FTLVL_Pos            (11U)
13160 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
13161 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
13162 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
13163 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
13164 
13165 /********************  Bit definition for SPI_DR register  ********************/
13166 #define SPI_DR_DR_Pos               (0U)
13167 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
13168 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
13169 
13170 /*******************  Bit definition for SPI_CRCPR register  ******************/
13171 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
13172 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
13173 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
13174 
13175 /******************  Bit definition for SPI_RXCRCR register  ******************/
13176 #define SPI_RXCRCR_RXCRC_Pos        (0U)
13177 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
13178 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
13179 
13180 /******************  Bit definition for SPI_TXCRCR register  ******************/
13181 #define SPI_TXCRCR_TXCRC_Pos        (0U)
13182 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
13183 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
13184 
13185 /******************  Bit definition for SPI_I2SCFGR register  *****************/
13186 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
13187 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
13188 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
13189 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
13190 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
13191 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
13192 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
13193 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
13194 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
13195 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
13196 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
13197 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
13198 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
13199 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
13200 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
13201 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
13202 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
13203 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
13204 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
13205 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
13206 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
13207 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
13208 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
13209 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
13210 #define SPI_I2SCFGR_I2SE_Pos        (10U)
13211 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
13212 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
13213 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
13214 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
13215 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
13216 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
13217 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
13218 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
13219 
13220 /******************  Bit definition for SPI_I2SPR register  *******************/
13221 #define SPI_I2SPR_I2SDIV_Pos        (0U)
13222 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
13223 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
13224 #define SPI_I2SPR_ODD_Pos           (8U)
13225 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
13226 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
13227 #define SPI_I2SPR_MCKOE_Pos         (9U)
13228 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
13229 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
13230 
13231 /******************************************************************************/
13232 /*                                                                            */
13233 /*                                 SYSCFG                                     */
13234 /*                                                                            */
13235 /******************************************************************************/
13236 /******************  Bit definition for SYSCFG_MEMRMP register ***************/
13237 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
13238 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
13239 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
13240 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
13241 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
13242 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
13243 
13244 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
13245 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)   /*!< 0x00000100 */
13246 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< User Flash Bank mode selection */
13247 
13248 /******************  Bit definition for SYSCFG_CFGR1 register ******************/
13249 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
13250 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
13251 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
13252 #define SYSCFG_CFGR1_ANASWVDD_Pos       (9U)
13253 #define SYSCFG_CFGR1_ANASWVDD_Msk       (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)    /*!< 0x00000200 */
13254 #define SYSCFG_CFGR1_ANASWVDD           SYSCFG_CFGR1_ANASWVDD_Msk               /*!< GPIO analog switch control voltage selection */
13255 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
13256 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
13257 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
13258 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
13259 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
13260 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
13261 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
13262 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
13263 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
13264 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
13265 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
13266 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
13267 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
13268 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
13269 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
13270 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
13271 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
13272 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
13273 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
13274 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
13275 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
13276 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
13277 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
13278 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
13279 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
13280 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
13281 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
13282 
13283 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
13284 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
13285 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
13286 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
13287 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
13288 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
13289 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
13290 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
13291 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
13292 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
13293 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
13294 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
13295 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
13296 
13297 /**
13298   * @brief   EXTI0 configuration
13299   */
13300 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
13301 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
13302 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
13303 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
13304 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
13305 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
13306 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
13307 
13308 /**
13309   * @brief   EXTI1 configuration
13310   */
13311 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
13312 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
13313 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
13314 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
13315 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
13316 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
13317 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
13318 
13319 /**
13320   * @brief   EXTI2 configuration
13321   */
13322 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
13323 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
13324 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
13325 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
13326 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
13327 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
13328 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
13329 
13330 /**
13331   * @brief   EXTI3 configuration
13332   */
13333 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
13334 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
13335 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
13336 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
13337 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
13338 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
13339 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
13340 
13341 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
13342 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
13343 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
13344 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
13345 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
13346 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
13347 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
13348 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
13349 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
13350 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
13351 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
13352 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
13353 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
13354 
13355 /**
13356   * @brief   EXTI4 configuration
13357   */
13358 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
13359 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
13360 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
13361 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
13362 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
13363 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
13364 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
13365 
13366 /**
13367   * @brief   EXTI5 configuration
13368   */
13369 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
13370 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
13371 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
13372 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
13373 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
13374 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
13375 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
13376 
13377 /**
13378   * @brief   EXTI6 configuration
13379   */
13380 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
13381 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
13382 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
13383 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
13384 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
13385 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
13386 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
13387 
13388 /**
13389   * @brief   EXTI7 configuration
13390   */
13391 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
13392 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
13393 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
13394 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
13395 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
13396 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
13397 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
13398 
13399 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
13400 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
13401 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
13402 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
13403 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
13404 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
13405 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
13406 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
13407 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
13408 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
13409 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
13410 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
13411 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
13412 
13413 /**
13414   * @brief   EXTI8 configuration
13415   */
13416 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
13417 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
13418 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
13419 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
13420 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
13421 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
13422 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
13423 
13424 /**
13425   * @brief   EXTI9 configuration
13426   */
13427 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
13428 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
13429 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
13430 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
13431 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
13432 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
13433 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
13434 
13435 /**
13436   * @brief   EXTI10 configuration
13437   */
13438 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
13439 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
13440 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
13441 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
13442 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
13443 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
13444 
13445 /**
13446   * @brief   EXTI11 configuration
13447   */
13448 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
13449 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
13450 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
13451 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
13452 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
13453 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
13454 
13455 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
13456 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
13457 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
13458 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
13459 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
13460 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
13461 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
13462 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
13463 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
13464 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
13465 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
13466 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
13467 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
13468 
13469 /**
13470   * @brief   EXTI12 configuration
13471   */
13472 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
13473 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
13474 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
13475 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
13476 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
13477 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
13478 
13479 /**
13480   * @brief   EXTI13 configuration
13481   */
13482 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
13483 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
13484 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
13485 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
13486 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
13487 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
13488 
13489 /**
13490   * @brief   EXTI14 configuration
13491   */
13492 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
13493 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
13494 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
13495 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
13496 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
13497 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
13498 
13499 /**
13500   * @brief   EXTI15 configuration
13501   */
13502 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
13503 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
13504 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
13505 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
13506 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
13507 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
13508 
13509 /******************  Bit definition for SYSCFG_SCSR register  ****************/
13510 #define SYSCFG_SCSR_CCMER_Pos         (0U)
13511 #define SYSCFG_SCSR_CCMER_Msk         (0x1UL << SYSCFG_SCSR_CCMER_Pos)      /*!< 0x00000001 */
13512 #define SYSCFG_SCSR_CCMER             SYSCFG_SCSR_CCMER_Msk                 /*!< CCMSRAM  Erase Request */
13513 #define SYSCFG_SCSR_CCMBSY_Pos        (1U)
13514 #define SYSCFG_SCSR_CCMBSY_Msk        (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)     /*!< 0x00000002 */
13515 #define SYSCFG_SCSR_CCMBSY            SYSCFG_SCSR_CCMBSY_Msk                /*!< CCMSRAM  Erase Ongoing */
13516 
13517 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
13518 #define SYSCFG_CFGR2_CLL_Pos            (0U)
13519 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
13520 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
13521 #define SYSCFG_CFGR2_SPL_Pos            (1U)
13522 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
13523 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
13524 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
13525 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
13526 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
13527 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
13528 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
13529 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
13530 #define SYSCFG_CFGR2_SPF_Pos            (8U)
13531 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
13532 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
13533 
13534 /******************  Bit definition for SYSCFG_SWPR register  ****************/
13535 #define SYSCFG_SWPR_PAGE0_Pos          (0U)
13536 #define SYSCFG_SWPR_PAGE0_Msk          (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
13537 #define SYSCFG_SWPR_PAGE0              (SYSCFG_SWPR_PAGE0_Msk)                /*!< CCMSRAM  Write protection page 0 */
13538 #define SYSCFG_SWPR_PAGE1_Pos          (1U)
13539 #define SYSCFG_SWPR_PAGE1_Msk          (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
13540 #define SYSCFG_SWPR_PAGE1              (SYSCFG_SWPR_PAGE1_Msk)                /*!< CCMSRAM  Write protection page 1 */
13541 #define SYSCFG_SWPR_PAGE2_Pos          (2U)
13542 #define SYSCFG_SWPR_PAGE2_Msk          (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
13543 #define SYSCFG_SWPR_PAGE2              (SYSCFG_SWPR_PAGE2_Msk)                /*!< CCMSRAM  Write protection page 2 */
13544 #define SYSCFG_SWPR_PAGE3_Pos          (3U)
13545 #define SYSCFG_SWPR_PAGE3_Msk          (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
13546 #define SYSCFG_SWPR_PAGE3              (SYSCFG_SWPR_PAGE3_Msk)                /*!< CCMSRAM  Write protection page 3 */
13547 #define SYSCFG_SWPR_PAGE4_Pos          (4U)
13548 #define SYSCFG_SWPR_PAGE4_Msk          (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
13549 #define SYSCFG_SWPR_PAGE4              (SYSCFG_SWPR_PAGE4_Msk)                /*!< CCMSRAM  Write protection page 4 */
13550 #define SYSCFG_SWPR_PAGE5_Pos          (5U)
13551 #define SYSCFG_SWPR_PAGE5_Msk          (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
13552 #define SYSCFG_SWPR_PAGE5              (SYSCFG_SWPR_PAGE5_Msk)                /*!< CCMSRAM  Write protection page 5 */
13553 #define SYSCFG_SWPR_PAGE6_Pos          (6U)
13554 #define SYSCFG_SWPR_PAGE6_Msk          (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
13555 #define SYSCFG_SWPR_PAGE6              (SYSCFG_SWPR_PAGE6_Msk)                /*!< CCMSRAM  Write protection page 6 */
13556 #define SYSCFG_SWPR_PAGE7_Pos          (7U)
13557 #define SYSCFG_SWPR_PAGE7_Msk          (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
13558 #define SYSCFG_SWPR_PAGE7              (SYSCFG_SWPR_PAGE7_Msk)                /*!< CCMSRAM  Write protection page 7 */
13559 #define SYSCFG_SWPR_PAGE8_Pos          (8U)
13560 #define SYSCFG_SWPR_PAGE8_Msk          (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
13561 #define SYSCFG_SWPR_PAGE8              (SYSCFG_SWPR_PAGE8_Msk)                /*!< CCMSRAM  Write protection page 8 */
13562 #define SYSCFG_SWPR_PAGE9_Pos          (9U)
13563 #define SYSCFG_SWPR_PAGE9_Msk          (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
13564 #define SYSCFG_SWPR_PAGE9              (SYSCFG_SWPR_PAGE9_Msk)                /*!< CCMSRAM  Write protection page 9 */
13565 #define SYSCFG_SWPR_PAGE10_Pos         (10U)
13566 #define SYSCFG_SWPR_PAGE10_Msk         (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
13567 #define SYSCFG_SWPR_PAGE10             (SYSCFG_SWPR_PAGE10_Msk)               /*!< CCMSRAM  Write protection page 10*/
13568 #define SYSCFG_SWPR_PAGE11_Pos         (11U)
13569 #define SYSCFG_SWPR_PAGE11_Msk         (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
13570 #define SYSCFG_SWPR_PAGE11             (SYSCFG_SWPR_PAGE11_Msk)               /*!< CCMSRAM  Write protection page 11*/
13571 #define SYSCFG_SWPR_PAGE12_Pos         (12U)
13572 #define SYSCFG_SWPR_PAGE12_Msk         (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
13573 #define SYSCFG_SWPR_PAGE12             (SYSCFG_SWPR_PAGE12_Msk)               /*!< CCMSRAM  Write protection page 12*/
13574 #define SYSCFG_SWPR_PAGE13_Pos         (13U)
13575 #define SYSCFG_SWPR_PAGE13_Msk         (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
13576 #define SYSCFG_SWPR_PAGE13             (SYSCFG_SWPR_PAGE13_Msk)               /*!< CCMSRAM  Write protection page 13*/
13577 #define SYSCFG_SWPR_PAGE14_Pos         (14U)
13578 #define SYSCFG_SWPR_PAGE14_Msk         (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
13579 #define SYSCFG_SWPR_PAGE14             (SYSCFG_SWPR_PAGE14_Msk)               /*!< CCMSRAM  Write protection page 14*/
13580 #define SYSCFG_SWPR_PAGE15_Pos         (15U)
13581 #define SYSCFG_SWPR_PAGE15_Msk         (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
13582 #define SYSCFG_SWPR_PAGE15             (SYSCFG_SWPR_PAGE15_Msk)               /*!< CCMSRAM  Write protection page 15*/
13583 #define SYSCFG_SWPR_PAGE16_Pos         (16U)
13584 #define SYSCFG_SWPR_PAGE16_Msk         (0x1UL << SYSCFG_SWPR_PAGE16_Pos)      /*!< 0x00010000 */
13585 #define SYSCFG_SWPR_PAGE16             (SYSCFG_SWPR_PAGE16_Msk)               /*!< CCMSRAM  Write protection page 16*/
13586 #define SYSCFG_SWPR_PAGE17_Pos         (17U)
13587 #define SYSCFG_SWPR_PAGE17_Msk         (0x1UL << SYSCFG_SWPR_PAGE17_Pos)      /*!< 0x00020000 */
13588 #define SYSCFG_SWPR_PAGE17             (SYSCFG_SWPR_PAGE17_Msk)               /*!< CCMSRAM  Write protection page 17*/
13589 #define SYSCFG_SWPR_PAGE18_Pos         (18U)
13590 #define SYSCFG_SWPR_PAGE18_Msk         (0x1UL << SYSCFG_SWPR_PAGE18_Pos)      /*!< 0x00040000 */
13591 #define SYSCFG_SWPR_PAGE18             (SYSCFG_SWPR_PAGE18_Msk)               /*!< CCMSRAM  Write protection page 18*/
13592 #define SYSCFG_SWPR_PAGE19_Pos         (19U)
13593 #define SYSCFG_SWPR_PAGE19_Msk         (0x1UL << SYSCFG_SWPR_PAGE19_Pos)      /*!< 0x00080000 */
13594 #define SYSCFG_SWPR_PAGE19             (SYSCFG_SWPR_PAGE19_Msk)               /*!< CCMSRAM  Write protection page 19*/
13595 #define SYSCFG_SWPR_PAGE20_Pos         (20U)
13596 #define SYSCFG_SWPR_PAGE20_Msk         (0x1UL << SYSCFG_SWPR_PAGE20_Pos)      /*!< 0x00100000 */
13597 #define SYSCFG_SWPR_PAGE20             (SYSCFG_SWPR_PAGE20_Msk)               /*!< CCMSRAM  Write protection page 20*/
13598 #define SYSCFG_SWPR_PAGE21_Pos         (21U)
13599 #define SYSCFG_SWPR_PAGE21_Msk         (0x1UL << SYSCFG_SWPR_PAGE21_Pos)      /*!< 0x00200000 */
13600 #define SYSCFG_SWPR_PAGE21             (SYSCFG_SWPR_PAGE21_Msk)               /*!< CCMSRAM  Write protection page 21*/
13601 #define SYSCFG_SWPR_PAGE22_Pos         (22U)
13602 #define SYSCFG_SWPR_PAGE22_Msk         (0x1UL << SYSCFG_SWPR_PAGE22_Pos)      /*!< 0x00400000 */
13603 #define SYSCFG_SWPR_PAGE22             (SYSCFG_SWPR_PAGE22_Msk)               /*!< CCMSRAM  Write protection page 22*/
13604 #define SYSCFG_SWPR_PAGE23_Pos         (23U)
13605 #define SYSCFG_SWPR_PAGE23_Msk         (0x1UL << SYSCFG_SWPR_PAGE23_Pos)      /*!< 0x00800000 */
13606 #define SYSCFG_SWPR_PAGE23             (SYSCFG_SWPR_PAGE23_Msk)               /*!< CCMSRAM  Write protection page 23*/
13607 #define SYSCFG_SWPR_PAGE24_Pos         (24U)
13608 #define SYSCFG_SWPR_PAGE24_Msk         (0x1UL << SYSCFG_SWPR_PAGE24_Pos)      /*!< 0x01000000 */
13609 #define SYSCFG_SWPR_PAGE24             (SYSCFG_SWPR_PAGE24_Msk)               /*!< CCMSRAM  Write protection page 24*/
13610 #define SYSCFG_SWPR_PAGE25_Pos         (25U)
13611 #define SYSCFG_SWPR_PAGE25_Msk         (0x1UL << SYSCFG_SWPR_PAGE25_Pos)      /*!< 0x02000000 */
13612 #define SYSCFG_SWPR_PAGE25             (SYSCFG_SWPR_PAGE25_Msk)               /*!< CCMSRAM  Write protection page 25*/
13613 #define SYSCFG_SWPR_PAGE26_Pos         (26U)
13614 #define SYSCFG_SWPR_PAGE26_Msk         (0x1UL << SYSCFG_SWPR_PAGE26_Pos)      /*!< 0x04000000 */
13615 #define SYSCFG_SWPR_PAGE26             (SYSCFG_SWPR_PAGE26_Msk)               /*!< CCMSRAM  Write protection page 26*/
13616 #define SYSCFG_SWPR_PAGE27_Pos         (27U)
13617 #define SYSCFG_SWPR_PAGE27_Msk         (0x1UL << SYSCFG_SWPR_PAGE27_Pos)      /*!< 0x08000000 */
13618 #define SYSCFG_SWPR_PAGE27             (SYSCFG_SWPR_PAGE27_Msk)               /*!< CCMSRAM  Write protection page 27*/
13619 #define SYSCFG_SWPR_PAGE28_Pos         (28U)
13620 #define SYSCFG_SWPR_PAGE28_Msk         (0x1UL << SYSCFG_SWPR_PAGE28_Pos)      /*!< 0x10000000 */
13621 #define SYSCFG_SWPR_PAGE28             (SYSCFG_SWPR_PAGE28_Msk)               /*!< CCMSRAM  Write protection page 28*/
13622 #define SYSCFG_SWPR_PAGE29_Pos         (29U)
13623 #define SYSCFG_SWPR_PAGE29_Msk         (0x1UL << SYSCFG_SWPR_PAGE29_Pos)      /*!< 0x20000000 */
13624 #define SYSCFG_SWPR_PAGE29             (SYSCFG_SWPR_PAGE29_Msk)               /*!< CCMSRAM  Write protection page 29*/
13625 #define SYSCFG_SWPR_PAGE30_Pos         (30U)
13626 #define SYSCFG_SWPR_PAGE30_Msk         (0x1UL << SYSCFG_SWPR_PAGE30_Pos)      /*!< 0x40000000 */
13627 #define SYSCFG_SWPR_PAGE30             (SYSCFG_SWPR_PAGE30_Msk)               /*!< CCMSRAM  Write protection page 30*/
13628 #define SYSCFG_SWPR_PAGE31_Pos         (31U)
13629 #define SYSCFG_SWPR_PAGE31_Msk         (0x1UL << SYSCFG_SWPR_PAGE31_Pos)      /*!< 0x80000000 */
13630 #define SYSCFG_SWPR_PAGE31             (SYSCFG_SWPR_PAGE31_Msk)               /*!< CCMSRAM  Write protection page 31*/
13631 
13632 /******************  Bit definition for SYSCFG_SKR register  ****************/
13633 #define SYSCFG_SKR_KEY_Pos              (0U)
13634 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
13635 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!< CCMSRAM  write protection key for software erase  */
13636 
13637 /******************************************************************************/
13638 /*                                                                            */
13639 /*                                    TIM                                     */
13640 /*                                                                            */
13641 /******************************************************************************/
13642 /*******************  Bit definition for TIM_CR1 register  ********************/
13643 #define TIM_CR1_CEN_Pos           (0U)
13644 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
13645 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
13646 #define TIM_CR1_UDIS_Pos          (1U)
13647 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
13648 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
13649 #define TIM_CR1_URS_Pos           (2U)
13650 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
13651 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
13652 #define TIM_CR1_OPM_Pos           (3U)
13653 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
13654 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
13655 #define TIM_CR1_DIR_Pos           (4U)
13656 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
13657 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
13658 
13659 #define TIM_CR1_CMS_Pos           (5U)
13660 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
13661 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
13662 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
13663 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
13664 
13665 #define TIM_CR1_ARPE_Pos          (7U)
13666 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
13667 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
13668 
13669 #define TIM_CR1_CKD_Pos           (8U)
13670 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
13671 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
13672 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
13673 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
13674 
13675 #define TIM_CR1_UIFREMAP_Pos      (11U)
13676 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
13677 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
13678 
13679 #define TIM_CR1_DITHEN_Pos      (12U)
13680 #define TIM_CR1_DITHEN_Msk      (0x1UL << TIM_CR1_DITHEN_Pos)                  /*!< 0x00001000 */
13681 #define TIM_CR1_DITHEN          TIM_CR1_DITHEN_Msk                             /*!<Dithering enable */
13682 
13683 /*******************  Bit definition for TIM_CR2 register  ********************/
13684 #define TIM_CR2_CCPC_Pos          (0U)
13685 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
13686 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
13687 #define TIM_CR2_CCUS_Pos          (2U)
13688 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
13689 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
13690 #define TIM_CR2_CCDS_Pos          (3U)
13691 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
13692 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
13693 
13694 #define TIM_CR2_MMS_Pos           (4U)
13695 #define TIM_CR2_MMS_Msk           (0x200007UL << TIM_CR2_MMS_Pos)              /*!< 0x02000070 */
13696 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[3:0] bits (Master Mode Selection) */
13697 #define TIM_CR2_MMS_0             (0x000001UL << TIM_CR2_MMS_Pos)              /*!< 0x00000010 */
13698 #define TIM_CR2_MMS_1             (0x000002UL << TIM_CR2_MMS_Pos)              /*!< 0x00000020 */
13699 #define TIM_CR2_MMS_2             (0x000004UL << TIM_CR2_MMS_Pos)              /*!< 0x00000040 */
13700 #define TIM_CR2_MMS_3             (0x200000UL << TIM_CR2_MMS_Pos)              /*!< 0x02000000 */
13701 
13702 #define TIM_CR2_TI1S_Pos          (7U)
13703 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
13704 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
13705 #define TIM_CR2_OIS1_Pos          (8U)
13706 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
13707 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
13708 #define TIM_CR2_OIS1N_Pos         (9U)
13709 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
13710 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
13711 #define TIM_CR2_OIS2_Pos          (10U)
13712 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
13713 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
13714 #define TIM_CR2_OIS2N_Pos         (11U)
13715 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
13716 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
13717 #define TIM_CR2_OIS3_Pos          (12U)
13718 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
13719 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
13720 #define TIM_CR2_OIS3N_Pos         (13U)
13721 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
13722 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
13723 #define TIM_CR2_OIS4_Pos          (14U)
13724 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
13725 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
13726 #define TIM_CR2_OIS4N_Pos         (15U)
13727 #define TIM_CR2_OIS4N_Msk         (0x1UL << TIM_CR2_OIS4N_Pos)                 /*!< 0x00008000 */
13728 #define TIM_CR2_OIS4N             TIM_CR2_OIS4N_Msk                            /*!<Output Idle state 4 (OC4N output) */
13729 #define TIM_CR2_OIS5_Pos          (16U)
13730 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
13731 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
13732 #define TIM_CR2_OIS6_Pos          (18U)
13733 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
13734 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
13735 
13736 #define TIM_CR2_MMS2_Pos          (20U)
13737 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
13738 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
13739 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
13740 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
13741 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
13742 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
13743 
13744 /*******************  Bit definition for TIM_SMCR register  *******************/
13745 #define TIM_SMCR_SMS_Pos          (0U)
13746 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
13747 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
13748 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
13749 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
13750 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
13751 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
13752 
13753 #define TIM_SMCR_OCCS_Pos         (3U)
13754 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
13755 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
13756 
13757 #define TIM_SMCR_TS_Pos           (4U)
13758 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
13759 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
13760 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
13761 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
13762 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
13763 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
13764 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
13765 
13766 #define TIM_SMCR_MSM_Pos          (7U)
13767 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
13768 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
13769 
13770 #define TIM_SMCR_ETF_Pos          (8U)
13771 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
13772 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
13773 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
13774 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
13775 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
13776 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
13777 
13778 #define TIM_SMCR_ETPS_Pos         (12U)
13779 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
13780 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
13781 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
13782 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
13783 
13784 #define TIM_SMCR_ECE_Pos          (14U)
13785 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
13786 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
13787 #define TIM_SMCR_ETP_Pos          (15U)
13788 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
13789 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
13790 
13791 #define TIM_SMCR_SMSPE_Pos        (24U)
13792 #define TIM_SMCR_SMSPE_Msk        (0x1UL << TIM_SMCR_SMSPE_Pos)                /*!< 0x02000000 */
13793 #define TIM_SMCR_SMSPE            TIM_SMCR_SMSPE_Msk                           /*!<SMS preload enable */
13794 
13795 #define TIM_SMCR_SMSPS_Pos        (25U)
13796 #define TIM_SMCR_SMSPS_Msk        (0x1UL << TIM_SMCR_SMSPS_Pos)                /*!< 0x04000000 */
13797 #define TIM_SMCR_SMSPS            TIM_SMCR_SMSPS_Msk                           /*!<SMS preload source */
13798 
13799 /*******************  Bit definition for TIM_DIER register  *******************/
13800 #define TIM_DIER_UIE_Pos          (0U)
13801 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
13802 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
13803 #define TIM_DIER_CC1IE_Pos        (1U)
13804 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
13805 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
13806 #define TIM_DIER_CC2IE_Pos        (2U)
13807 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
13808 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
13809 #define TIM_DIER_CC3IE_Pos        (3U)
13810 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
13811 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
13812 #define TIM_DIER_CC4IE_Pos        (4U)
13813 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
13814 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
13815 #define TIM_DIER_COMIE_Pos        (5U)
13816 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
13817 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
13818 #define TIM_DIER_TIE_Pos          (6U)
13819 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
13820 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
13821 #define TIM_DIER_BIE_Pos          (7U)
13822 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
13823 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
13824 #define TIM_DIER_UDE_Pos          (8U)
13825 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
13826 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
13827 #define TIM_DIER_CC1DE_Pos        (9U)
13828 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
13829 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
13830 #define TIM_DIER_CC2DE_Pos        (10U)
13831 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
13832 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
13833 #define TIM_DIER_CC3DE_Pos        (11U)
13834 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
13835 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
13836 #define TIM_DIER_CC4DE_Pos        (12U)
13837 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
13838 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
13839 #define TIM_DIER_COMDE_Pos        (13U)
13840 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
13841 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
13842 #define TIM_DIER_TDE_Pos          (14U)
13843 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
13844 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
13845 #define TIM_DIER_IDXIE_Pos        (20U)
13846 #define TIM_DIER_IDXIE_Msk        (0x1UL << TIM_DIER_IDXIE_Pos)                /*!< 0x00100000 */
13847 #define TIM_DIER_IDXIE            TIM_DIER_IDXIE_Msk                           /*!<Encoder index interrupt enable */
13848 #define TIM_DIER_DIRIE_Pos        (21U)
13849 #define TIM_DIER_DIRIE_Msk        (0x1UL << TIM_DIER_DIRIE_Pos)                /*!< 0x00200000 */
13850 #define TIM_DIER_DIRIE            TIM_DIER_DIRIE_Msk                           /*!<Encoder direction change interrupt enable */
13851 #define TIM_DIER_IERRIE_Pos       (22U)
13852 #define TIM_DIER_IERRIE_Msk       (0x1UL << TIM_DIER_IERRIE_Pos)               /*!< 0x00400000 */
13853 #define TIM_DIER_IERRIE           TIM_DIER_IERRIE_Msk                          /*!<Encoder index error enable */
13854 #define TIM_DIER_TERRIE_Pos       (23U)
13855 #define TIM_DIER_TERRIE_Msk       (0x1UL << TIM_DIER_TERRIE_Pos)               /*!< 0x00800000 */
13856 #define TIM_DIER_TERRIE           TIM_DIER_TERRIE_Msk                          /*!<Encoder transition error enable */
13857 
13858 /********************  Bit definition for TIM_SR register  ********************/
13859 #define TIM_SR_UIF_Pos            (0U)
13860 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
13861 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
13862 #define TIM_SR_CC1IF_Pos          (1U)
13863 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
13864 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
13865 #define TIM_SR_CC2IF_Pos          (2U)
13866 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
13867 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
13868 #define TIM_SR_CC3IF_Pos          (3U)
13869 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
13870 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
13871 #define TIM_SR_CC4IF_Pos          (4U)
13872 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
13873 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
13874 #define TIM_SR_COMIF_Pos          (5U)
13875 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
13876 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
13877 #define TIM_SR_TIF_Pos            (6U)
13878 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
13879 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
13880 #define TIM_SR_BIF_Pos            (7U)
13881 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
13882 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
13883 #define TIM_SR_B2IF_Pos           (8U)
13884 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
13885 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
13886 #define TIM_SR_CC1OF_Pos          (9U)
13887 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
13888 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
13889 #define TIM_SR_CC2OF_Pos          (10U)
13890 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
13891 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
13892 #define TIM_SR_CC3OF_Pos          (11U)
13893 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
13894 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
13895 #define TIM_SR_CC4OF_Pos          (12U)
13896 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
13897 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
13898 #define TIM_SR_SBIF_Pos           (13U)
13899 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
13900 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
13901 #define TIM_SR_CC5IF_Pos          (16U)
13902 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
13903 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
13904 #define TIM_SR_CC6IF_Pos          (17U)
13905 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
13906 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
13907 #define TIM_SR_IDXF_Pos           (20U)
13908 #define TIM_SR_IDXF_Msk           (0x1UL << TIM_SR_IDXF_Pos)                   /*!< 0x00100000 */
13909 #define TIM_SR_IDXF               TIM_SR_IDXF_Msk                              /*!<Encoder index interrupt flag */
13910 #define TIM_SR_DIRF_Pos           (21U)
13911 #define TIM_SR_DIRF_Msk           (0x1UL << TIM_SR_DIRF_Pos)                   /*!< 0x00200000 */
13912 #define TIM_SR_DIRF               TIM_SR_DIRF_Msk                              /*!<Encoder direction change interrupt flag */
13913 #define TIM_SR_IERRF_Pos          (22U)
13914 #define TIM_SR_IERRF_Msk          (0x1UL << TIM_SR_IERRF_Pos)                  /*!< 0x00400000 */
13915 #define TIM_SR_IERRF              TIM_SR_IERRF_Msk                             /*!<Encoder index error flag */
13916 #define TIM_SR_TERRF_Pos          (23U)
13917 #define TIM_SR_TERRF_Msk          (0x1UL << TIM_SR_TERRF_Pos)                  /*!< 0x00800000 */
13918 #define TIM_SR_TERRF              TIM_SR_TERRF_Msk                             /*!<Encoder transition error flag */
13919 
13920 /*******************  Bit definition for TIM_EGR register  ********************/
13921 #define TIM_EGR_UG_Pos            (0U)
13922 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
13923 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
13924 #define TIM_EGR_CC1G_Pos          (1U)
13925 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
13926 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
13927 #define TIM_EGR_CC2G_Pos          (2U)
13928 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
13929 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
13930 #define TIM_EGR_CC3G_Pos          (3U)
13931 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
13932 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
13933 #define TIM_EGR_CC4G_Pos          (4U)
13934 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
13935 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
13936 #define TIM_EGR_COMG_Pos          (5U)
13937 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
13938 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
13939 #define TIM_EGR_TG_Pos            (6U)
13940 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
13941 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
13942 #define TIM_EGR_BG_Pos            (7U)
13943 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
13944 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
13945 #define TIM_EGR_B2G_Pos           (8U)
13946 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
13947 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
13948 
13949 
13950 /******************  Bit definition for TIM_CCMR1 register  *******************/
13951 #define TIM_CCMR1_CC1S_Pos        (0U)
13952 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
13953 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13954 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
13955 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
13956 
13957 #define TIM_CCMR1_OC1FE_Pos       (2U)
13958 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
13959 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
13960 #define TIM_CCMR1_OC1PE_Pos       (3U)
13961 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
13962 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
13963 
13964 #define TIM_CCMR1_OC1M_Pos        (4U)
13965 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
13966 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13967 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
13968 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
13969 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
13970 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
13971 
13972 #define TIM_CCMR1_OC1CE_Pos       (7U)
13973 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
13974 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
13975 
13976 #define TIM_CCMR1_CC2S_Pos        (8U)
13977 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
13978 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13979 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
13980 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
13981 
13982 #define TIM_CCMR1_OC2FE_Pos       (10U)
13983 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
13984 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
13985 #define TIM_CCMR1_OC2PE_Pos       (11U)
13986 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
13987 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
13988 
13989 #define TIM_CCMR1_OC2M_Pos        (12U)
13990 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
13991 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13992 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
13993 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
13994 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
13995 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
13996 
13997 #define TIM_CCMR1_OC2CE_Pos       (15U)
13998 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
13999 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
14000 
14001 /*----------------------------------------------------------------------------*/
14002 #define TIM_CCMR1_IC1PSC_Pos      (2U)
14003 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
14004 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
14005 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
14006 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
14007 
14008 #define TIM_CCMR1_IC1F_Pos        (4U)
14009 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
14010 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
14011 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
14012 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
14013 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
14014 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
14015 
14016 #define TIM_CCMR1_IC2PSC_Pos      (10U)
14017 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
14018 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
14019 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
14020 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
14021 
14022 #define TIM_CCMR1_IC2F_Pos        (12U)
14023 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
14024 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
14025 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
14026 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
14027 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
14028 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
14029 
14030 /******************  Bit definition for TIM_CCMR2 register  *******************/
14031 #define TIM_CCMR2_CC3S_Pos        (0U)
14032 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
14033 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
14034 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
14035 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
14036 
14037 #define TIM_CCMR2_OC3FE_Pos       (2U)
14038 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
14039 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
14040 #define TIM_CCMR2_OC3PE_Pos       (3U)
14041 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
14042 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
14043 
14044 #define TIM_CCMR2_OC3M_Pos        (4U)
14045 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
14046 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
14047 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
14048 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
14049 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
14050 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
14051 
14052 #define TIM_CCMR2_OC3CE_Pos       (7U)
14053 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
14054 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
14055 
14056 #define TIM_CCMR2_CC4S_Pos        (8U)
14057 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
14058 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
14059 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
14060 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
14061 
14062 #define TIM_CCMR2_OC4FE_Pos       (10U)
14063 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
14064 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
14065 #define TIM_CCMR2_OC4PE_Pos       (11U)
14066 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
14067 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
14068 
14069 #define TIM_CCMR2_OC4M_Pos        (12U)
14070 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
14071 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
14072 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
14073 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
14074 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
14075 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
14076 
14077 #define TIM_CCMR2_OC4CE_Pos       (15U)
14078 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
14079 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
14080 
14081 /*----------------------------------------------------------------------------*/
14082 #define TIM_CCMR2_IC3PSC_Pos      (2U)
14083 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
14084 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
14085 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
14086 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
14087 
14088 #define TIM_CCMR2_IC3F_Pos        (4U)
14089 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
14090 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
14091 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
14092 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
14093 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
14094 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
14095 
14096 #define TIM_CCMR2_IC4PSC_Pos      (10U)
14097 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
14098 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
14099 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
14100 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
14101 
14102 #define TIM_CCMR2_IC4F_Pos        (12U)
14103 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
14104 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
14105 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
14106 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
14107 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
14108 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
14109 
14110 /******************  Bit definition for TIM_CCMR3 register  *******************/
14111 #define TIM_CCMR3_OC5FE_Pos       (2U)
14112 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
14113 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
14114 #define TIM_CCMR3_OC5PE_Pos       (3U)
14115 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
14116 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
14117 
14118 #define TIM_CCMR3_OC5M_Pos        (4U)
14119 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
14120 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
14121 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
14122 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
14123 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
14124 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
14125 
14126 #define TIM_CCMR3_OC5CE_Pos       (7U)
14127 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
14128 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
14129 
14130 #define TIM_CCMR3_OC6FE_Pos       (10U)
14131 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
14132 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
14133 #define TIM_CCMR3_OC6PE_Pos       (11U)
14134 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
14135 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
14136 
14137 #define TIM_CCMR3_OC6M_Pos        (12U)
14138 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
14139 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
14140 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
14141 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
14142 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
14143 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
14144 
14145 #define TIM_CCMR3_OC6CE_Pos       (15U)
14146 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
14147 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
14148 
14149 /*******************  Bit definition for TIM_CCER register  *******************/
14150 #define TIM_CCER_CC1E_Pos         (0U)
14151 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
14152 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
14153 #define TIM_CCER_CC1P_Pos         (1U)
14154 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
14155 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
14156 #define TIM_CCER_CC1NE_Pos        (2U)
14157 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
14158 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
14159 #define TIM_CCER_CC1NP_Pos        (3U)
14160 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
14161 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
14162 #define TIM_CCER_CC2E_Pos         (4U)
14163 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
14164 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
14165 #define TIM_CCER_CC2P_Pos         (5U)
14166 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
14167 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
14168 #define TIM_CCER_CC2NE_Pos        (6U)
14169 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
14170 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
14171 #define TIM_CCER_CC2NP_Pos        (7U)
14172 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
14173 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
14174 #define TIM_CCER_CC3E_Pos         (8U)
14175 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
14176 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
14177 #define TIM_CCER_CC3P_Pos         (9U)
14178 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
14179 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
14180 #define TIM_CCER_CC3NE_Pos        (10U)
14181 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
14182 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
14183 #define TIM_CCER_CC3NP_Pos        (11U)
14184 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
14185 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
14186 #define TIM_CCER_CC4E_Pos         (12U)
14187 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
14188 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
14189 #define TIM_CCER_CC4P_Pos         (13U)
14190 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
14191 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
14192 #define TIM_CCER_CC4NE_Pos        (14U)
14193 #define TIM_CCER_CC4NE_Msk        (0x1UL << TIM_CCER_CC4NE_Pos)                /*!< 0x00004000 */
14194 #define TIM_CCER_CC4NE            TIM_CCER_CC4NE_Msk                           /*!<Capture/Compare 4 Complementary output enable */
14195 #define TIM_CCER_CC4NP_Pos        (15U)
14196 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
14197 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
14198 #define TIM_CCER_CC5E_Pos         (16U)
14199 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
14200 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
14201 #define TIM_CCER_CC5P_Pos         (17U)
14202 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
14203 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
14204 #define TIM_CCER_CC6E_Pos         (20U)
14205 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
14206 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
14207 #define TIM_CCER_CC6P_Pos         (21U)
14208 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
14209 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
14210 
14211 /*******************  Bit definition for TIM_CNT register  ********************/
14212 #define TIM_CNT_CNT_Pos           (0U)
14213 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
14214 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
14215 #define TIM_CNT_UIFCPY_Pos        (31U)
14216 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
14217 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
14218 
14219 /*******************  Bit definition for TIM_PSC register  ********************/
14220 #define TIM_PSC_PSC_Pos           (0U)
14221 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
14222 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
14223 
14224 /*******************  Bit definition for TIM_ARR register  ********************/
14225 #define TIM_ARR_ARR_Pos           (0U)
14226 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
14227 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
14228 
14229 /*******************  Bit definition for TIM_RCR register  ********************/
14230 #define TIM_RCR_REP_Pos           (0U)
14231 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
14232 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
14233 
14234 /*******************  Bit definition for TIM_CCR1 register  *******************/
14235 #define TIM_CCR1_CCR1_Pos         (0U)
14236 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
14237 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
14238 
14239 /*******************  Bit definition for TIM_CCR2 register  *******************/
14240 #define TIM_CCR2_CCR2_Pos         (0U)
14241 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
14242 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
14243 
14244 /*******************  Bit definition for TIM_CCR3 register  *******************/
14245 #define TIM_CCR3_CCR3_Pos         (0U)
14246 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
14247 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
14248 
14249 /*******************  Bit definition for TIM_CCR4 register  *******************/
14250 #define TIM_CCR4_CCR4_Pos         (0U)
14251 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
14252 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
14253 
14254 /*******************  Bit definition for TIM_CCR5 register  *******************/
14255 #define TIM_CCR5_CCR5_Pos         (0U)
14256 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
14257 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
14258 #define TIM_CCR5_GC5C1_Pos        (29U)
14259 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
14260 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
14261 #define TIM_CCR5_GC5C2_Pos        (30U)
14262 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
14263 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
14264 #define TIM_CCR5_GC5C3_Pos        (31U)
14265 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
14266 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
14267 
14268 /*******************  Bit definition for TIM_CCR6 register  *******************/
14269 #define TIM_CCR6_CCR6_Pos         (0U)
14270 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
14271 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
14272 
14273 /*******************  Bit definition for TIM_BDTR register  *******************/
14274 #define TIM_BDTR_DTG_Pos          (0U)
14275 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
14276 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
14277 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
14278 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
14279 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
14280 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
14281 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
14282 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
14283 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
14284 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
14285 
14286 #define TIM_BDTR_LOCK_Pos         (8U)
14287 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
14288 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
14289 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
14290 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
14291 
14292 #define TIM_BDTR_OSSI_Pos         (10U)
14293 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
14294 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
14295 #define TIM_BDTR_OSSR_Pos         (11U)
14296 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
14297 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
14298 #define TIM_BDTR_BKE_Pos          (12U)
14299 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
14300 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
14301 #define TIM_BDTR_BKP_Pos          (13U)
14302 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
14303 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
14304 #define TIM_BDTR_AOE_Pos          (14U)
14305 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
14306 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
14307 #define TIM_BDTR_MOE_Pos          (15U)
14308 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
14309 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
14310 
14311 #define TIM_BDTR_BKF_Pos          (16U)
14312 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
14313 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
14314 #define TIM_BDTR_BK2F_Pos         (20U)
14315 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
14316 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
14317 
14318 #define TIM_BDTR_BK2E_Pos         (24U)
14319 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
14320 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
14321 #define TIM_BDTR_BK2P_Pos         (25U)
14322 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
14323 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
14324 
14325 #define TIM_BDTR_BKDSRM_Pos       (26U)
14326 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
14327 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
14328 #define TIM_BDTR_BK2DSRM_Pos      (27U)
14329 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
14330 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
14331 
14332 #define TIM_BDTR_BKBID_Pos        (28U)
14333 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
14334 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
14335 #define TIM_BDTR_BK2BID_Pos       (29U)
14336 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
14337 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
14338 
14339 /*******************  Bit definition for TIM_DCR register  ********************/
14340 #define TIM_DCR_DBA_Pos           (0U)
14341 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
14342 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
14343 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
14344 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
14345 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
14346 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
14347 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
14348 
14349 #define TIM_DCR_DBL_Pos           (8U)
14350 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
14351 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
14352 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
14353 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
14354 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
14355 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
14356 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
14357 
14358 /*******************  Bit definition for TIM1_AF1 register  *******************/
14359 #define TIM1_AF1_BKINE_Pos        (0U)
14360 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
14361 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
14362 #define TIM1_AF1_BKCMP1E_Pos      (1U)
14363 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
14364 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
14365 #define TIM1_AF1_BKCMP2E_Pos      (2U)
14366 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
14367 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
14368 #define TIM1_AF1_BKCMP3E_Pos      (3U)
14369 #define TIM1_AF1_BKCMP3E_Msk      (0x1UL << TIM1_AF1_BKCMP3E_Pos)              /*!< 0x00000008 */
14370 #define TIM1_AF1_BKCMP3E          TIM1_AF1_BKCMP3E_Msk                         /*!<BRK COMP3 enable */
14371 #define TIM1_AF1_BKCMP4E_Pos      (4U)
14372 #define TIM1_AF1_BKCMP4E_Msk      (0x1UL << TIM1_AF1_BKCMP4E_Pos)              /*!< 0x00000010 */
14373 #define TIM1_AF1_BKCMP4E          TIM1_AF1_BKCMP4E_Msk                         /*!<BRK COMP4 enable */
14374 #define TIM1_AF1_BKCMP5E_Pos      (5U)
14375 #define TIM1_AF1_BKCMP5E_Msk      (0x1UL << TIM1_AF1_BKCMP5E_Pos)              /*!< 0x00000020 */
14376 #define TIM1_AF1_BKCMP5E          TIM1_AF1_BKCMP5E_Msk                         /*!<BRK COMP5 enable */
14377 #define TIM1_AF1_BKCMP6E_Pos      (6U)
14378 #define TIM1_AF1_BKCMP6E_Msk      (0x1UL << TIM1_AF1_BKCMP6E_Pos)              /*!< 0x00000040 */
14379 #define TIM1_AF1_BKCMP6E          TIM1_AF1_BKCMP6E_Msk                         /*!<BRK COMP6 enable */
14380 #define TIM1_AF1_BKCMP7E_Pos      (7U)
14381 #define TIM1_AF1_BKCMP7E_Msk      (0x1UL << TIM1_AF1_BKCMP7E_Pos)              /*!< 0x00000080 */
14382 #define TIM1_AF1_BKCMP7E          TIM1_AF1_BKCMP7E_Msk                         /*!<BRK COMP7 enable */
14383 #define TIM1_AF1_BKINP_Pos        (9U)
14384 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
14385 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
14386 #define TIM1_AF1_BKCMP1P_Pos      (10U)
14387 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
14388 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
14389 #define TIM1_AF1_BKCMP2P_Pos      (11U)
14390 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
14391 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
14392 #define TIM1_AF1_BKCMP3P_Pos      (12U)
14393 #define TIM1_AF1_BKCMP3P_Msk      (0x1UL << TIM1_AF1_BKCMP3P_Pos)              /*!< 0x00001000 */
14394 #define TIM1_AF1_BKCMP3P          TIM1_AF1_BKCMP3P_Msk                         /*!<BRK COMP3 input polarity */
14395 #define TIM1_AF1_BKCMP4P_Pos      (13U)
14396 #define TIM1_AF1_BKCMP4P_Msk      (0x1UL << TIM1_AF1_BKCMP4P_Pos)              /*!< 0x00002000 */
14397 #define TIM1_AF1_BKCMP4P          TIM1_AF1_BKCMP4P_Msk                         /*!<BRK COMP4 input polarity */
14398 #define TIM1_AF1_ETRSEL_Pos       (14U)
14399 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
14400 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
14401 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
14402 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
14403 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
14404 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
14405 
14406 /*******************  Bit definition for TIM1_AF2 register  *********************/
14407 #define TIM1_AF2_BK2INE_Pos        (0U)
14408 #define TIM1_AF2_BK2INE_Msk        (0x1UL << TIM1_AF2_BK2INE_Pos)                /*!< 0x00000001 */
14409 #define TIM1_AF2_BK2INE            TIM1_AF2_BK2INE_Msk                           /*!<BRK2 BKIN input enable */
14410 #define TIM1_AF2_BK2CMP1E_Pos      (1U)
14411 #define TIM1_AF2_BK2CMP1E_Msk      (0x1UL << TIM1_AF2_BK2CMP1E_Pos)              /*!< 0x00000002 */
14412 #define TIM1_AF2_BK2CMP1E          TIM1_AF2_BK2CMP1E_Msk                         /*!<BRK2 COMP1 enable */
14413 #define TIM1_AF2_BK2CMP2E_Pos      (2U)
14414 #define TIM1_AF2_BK2CMP2E_Msk      (0x1UL << TIM1_AF2_BK2CMP2E_Pos)              /*!< 0x00000004 */
14415 #define TIM1_AF2_BK2CMP2E          TIM1_AF2_BK2CMP2E_Msk                         /*!<BRK2 COMP2 enable */
14416 #define TIM1_AF2_BK2CMP3E_Pos      (3U)
14417 #define TIM1_AF2_BK2CMP3E_Msk      (0x1UL << TIM1_AF2_BK2CMP3E_Pos)              /*!< 0x00000008 */
14418 #define TIM1_AF2_BK2CMP3E          TIM1_AF2_BK2CMP3E_Msk                         /*!<BRK2 COMP3 enable */
14419 #define TIM1_AF2_BK2CMP4E_Pos      (4U)
14420 #define TIM1_AF2_BK2CMP4E_Msk      (0x1UL << TIM1_AF2_BK2CMP4E_Pos)              /*!< 0x00000010 */
14421 #define TIM1_AF2_BK2CMP4E          TIM1_AF2_BK2CMP4E_Msk                         /*!<BRK2 COMP4 enable */
14422 #define TIM1_AF2_BK2CMP5E_Pos      (5U)
14423 #define TIM1_AF2_BK2CMP5E_Msk      (0x1UL << TIM1_AF2_BK2CMP5E_Pos)              /*!< 0x00000020 */
14424 #define TIM1_AF2_BK2CMP5E          TIM1_AF2_BK2CMP5E_Msk                         /*!<BRK2 COMP5 enable */
14425 #define TIM1_AF2_BK2CMP6E_Pos      (6U)
14426 #define TIM1_AF2_BK2CMP6E_Msk      (0x1UL << TIM1_AF2_BK2CMP6E_Pos)              /*!< 0x00000040 */
14427 #define TIM1_AF2_BK2CMP6E          TIM1_AF2_BK2CMP6E_Msk                         /*!<BRK2 COMP6 enable */
14428 #define TIM1_AF2_BK2CMP7E_Pos      (7U)
14429 #define TIM1_AF2_BK2CMP7E_Msk      (0x1UL << TIM1_AF2_BK2CMP7E_Pos)              /*!< 0x00000080 */
14430 #define TIM1_AF2_BK2CMP7E          TIM1_AF2_BK2CMP7E_Msk                         /*!<BRK2 COMP7 enable */
14431 #define TIM1_AF2_BK2INP_Pos        (9U)
14432 #define TIM1_AF2_BK2INP_Msk        (0x1UL << TIM1_AF2_BK2INP_Pos)                /*!< 0x00000200 */
14433 #define TIM1_AF2_BK2INP            TIM1_AF2_BK2INP_Msk                           /*!<BRK2 BKIN input polarity */
14434 #define TIM1_AF2_BK2CMP1P_Pos      (10U)
14435 #define TIM1_AF2_BK2CMP1P_Msk      (0x1UL << TIM1_AF2_BK2CMP1P_Pos)              /*!< 0x00000400 */
14436 #define TIM1_AF2_BK2CMP1P          TIM1_AF2_BK2CMP1P_Msk                         /*!<BRK2 COMP1 input polarity */
14437 #define TIM1_AF2_BK2CMP2P_Pos      (11U)
14438 #define TIM1_AF2_BK2CMP2P_Msk      (0x1UL << TIM1_AF2_BK2CMP2P_Pos)              /*!< 0x00000800 */
14439 #define TIM1_AF2_BK2CMP2P          TIM1_AF2_BK2CMP2P_Msk                         /*!<BRK2 COMP2 input polarity */
14440 #define TIM1_AF2_BK2CMP3P_Pos      (12U)
14441 #define TIM1_AF2_BK2CMP3P_Msk      (0x1UL << TIM1_AF2_BK2CMP3P_Pos)              /*!< 0x00000400 */
14442 #define TIM1_AF2_BK2CMP3P          TIM1_AF2_BK2CMP3P_Msk                         /*!<BRK2 COMP3 input polarity */
14443 #define TIM1_AF2_BK2CMP4P_Pos      (13U)
14444 #define TIM1_AF2_BK2CMP4P_Msk      (0x1UL << TIM1_AF2_BK2CMP4P_Pos)              /*!< 0x00000800 */
14445 #define TIM1_AF2_BK2CMP4P          TIM1_AF2_BK2CMP4P_Msk                         /*!<BRK2 COMP4 input polarity */
14446 #define TIM1_AF2_OCRSEL_Pos        (16U)
14447 #define TIM1_AF2_OCRSEL_Msk        (0x7UL << TIM1_AF2_OCRSEL_Pos)                /*!< 0x00070000 */
14448 #define TIM1_AF2_OCRSEL            TIM1_AF2_OCRSEL_Msk                           /*!<BRK2 COMP2 input polarity */
14449 #define TIM1_AF2_OCRSEL_0         (0x1UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00010000 */
14450 #define TIM1_AF2_OCRSEL_1         (0x2UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00020000 */
14451 #define TIM1_AF2_OCRSEL_2         (0x4UL << TIM1_AF2_OCRSEL_Pos)                 /*!< 0x00040000 */
14452 
14453 /*******************  Bit definition for TIM_OR register  *********************/
14454 #define TIM_OR_HSE32EN_Pos       (0U)
14455 #define TIM_OR_HSE32EN_Msk       (0x1UL << TIM_OR_HSE32EN_Pos)                  /*!< 0x00000001 */
14456 #define TIM_OR_HSE32EN           TIM_OR_HSE32EN_Msk                             /*!< HSE/32 clock enable */
14457 
14458 /*******************  Bit definition for TIM_TISEL register  *********************/
14459 #define TIM_TISEL_TI1SEL_Pos      (0U)
14460 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
14461 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
14462 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
14463 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
14464 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
14465 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
14466 
14467 #define TIM_TISEL_TI2SEL_Pos      (8U)
14468 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
14469 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
14470 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
14471 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
14472 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
14473 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
14474 
14475 #define TIM_TISEL_TI3SEL_Pos      (16U)
14476 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
14477 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
14478 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
14479 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
14480 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
14481 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
14482 
14483 #define TIM_TISEL_TI4SEL_Pos      (24U)
14484 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
14485 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
14486 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
14487 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
14488 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
14489 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
14490 
14491 /*******************  Bit definition for TIM_DTR2 register  *********************/
14492 #define TIM_DTR2_DTGF_Pos      (0U)
14493 #define TIM_DTR2_DTGF_Msk      (0xFFUL << TIM_DTR2_DTGF_Pos)                /*!< 0x0000000F */
14494 #define TIM_DTR2_DTGF          TIM_DTR2_DTGF_Msk                            /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
14495 #define TIM_DTR2_DTGF_0        (0x01UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000001 */
14496 #define TIM_DTR2_DTGF_1        (0x02UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000002 */
14497 #define TIM_DTR2_DTGF_2        (0x04UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000004 */
14498 #define TIM_DTR2_DTGF_3        (0x08UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000008 */
14499 #define TIM_DTR2_DTGF_4        (0x10UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000010 */
14500 #define TIM_DTR2_DTGF_5        (0x20UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000020 */
14501 #define TIM_DTR2_DTGF_6        (0x40UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000040 */
14502 #define TIM_DTR2_DTGF_7        (0x80UL << TIM_DTR2_DTGF_Pos)                /*!< 0x00000080 */
14503 
14504 #define TIM_DTR2_DTAE_Pos      (16U)
14505 #define TIM_DTR2_DTAE_Msk      (0x1UL << TIM_DTR2_DTAE_Pos)                 /*!< 0x00004000 */
14506 #define TIM_DTR2_DTAE          TIM_DTR2_DTAE_Msk                            /*!<Deadtime asymmetric enable */
14507 #define TIM_DTR2_DTPE_Pos      (17U)
14508 #define TIM_DTR2_DTPE_Msk      (0x1UL << TIM_DTR2_DTPE_Pos)                 /*!< 0x00008000 */
14509 #define TIM_DTR2_DTPE          TIM_DTR2_DTPE_Msk                            /*!<Deadtime prelaod enable */
14510 
14511 /*******************  Bit definition for TIM_ECR register  *********************/
14512 #define TIM_ECR_IE_Pos       (0U)
14513 #define TIM_ECR_IE_Msk       (0x1UL << TIM_ECR_IE_Pos)                   /*!< 0x00000001 */
14514 #define TIM_ECR_IE           TIM_ECR_IE_Msk                              /*!<Index enable */
14515 
14516 #define TIM_ECR_IDIR_Pos      (1U)
14517 #define TIM_ECR_IDIR_Msk      (0x3UL << TIM_ECR_IDIR_Pos)                 /*!< 0x00000006 */
14518 #define TIM_ECR_IDIR          TIM_ECR_IDIR_Msk                            /*!<IDIR[1:0] bits (Index direction)*/
14519 #define TIM_ECR_IDIR_0        (0x01UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000001 */
14520 #define TIM_ECR_IDIR_1        (0x02UL << TIM_ECR_IDIR_Pos)                /*!< 0x00000002 */
14521 
14522 #define TIM_ECR_FIDX_Pos      (5U)
14523 #define TIM_ECR_FIDX_Msk      (0x1UL << TIM_ECR_FIDX_Pos)                 /*!< 0x00000020 */
14524 #define TIM_ECR_FIDX          TIM_ECR_FIDX_Msk                            /*!<First index enable */
14525 
14526 #define TIM_ECR_IPOS_Pos      (6U)
14527 #define TIM_ECR_IPOS_Msk      (0x3UL << TIM_ECR_IPOS_Pos)                 /*!< 0x0000000C0 */
14528 #define TIM_ECR_IPOS          TIM_ECR_IPOS_Msk                            /*!<IPOS[1:0] bits (Index positioning)*/
14529 #define TIM_ECR_IPOS_0        (0x01UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000001 */
14530 #define TIM_ECR_IPOS_1        (0x02UL << TIM_ECR_IPOS_Pos)                /*!< 0x00000002 */
14531 
14532 #define TIM_ECR_PW_Pos        (16U)
14533 #define TIM_ECR_PW_Msk        (0xFFUL << TIM_ECR_PW_Pos)                  /*!< 0x00FF0000 */
14534 #define TIM_ECR_PW            TIM_ECR_PW_Msk                              /*!<PW[7:0] bits (Pulse width)*/
14535 #define TIM_ECR_PW_0          (0x01UL << TIM_ECR_PW_Pos)                  /*!< 0x00010000 */
14536 #define TIM_ECR_PW_1          (0x02UL << TIM_ECR_PW_Pos)                  /*!< 0x00020000 */
14537 #define TIM_ECR_PW_2          (0x04UL << TIM_ECR_PW_Pos)                  /*!< 0x00040000 */
14538 #define TIM_ECR_PW_3          (0x08UL << TIM_ECR_PW_Pos)                  /*!< 0x00080000 */
14539 #define TIM_ECR_PW_4          (0x10UL << TIM_ECR_PW_Pos)                  /*!< 0x00100000 */
14540 #define TIM_ECR_PW_5          (0x20UL << TIM_ECR_PW_Pos)                  /*!< 0x00200000 */
14541 #define TIM_ECR_PW_6          (0x40UL << TIM_ECR_PW_Pos)                  /*!< 0x00400000 */
14542 #define TIM_ECR_PW_7          (0x80UL << TIM_ECR_PW_Pos)                  /*!< 0x00800000 */
14543 
14544 #define TIM_ECR_PWPRSC_Pos    (24U)
14545 #define TIM_ECR_PWPRSC_Msk    (0x7UL << TIM_ECR_PWPRSC_Pos)               /*!< 0x07000000 */
14546 #define TIM_ECR_PWPRSC        TIM_ECR_PWPRSC_Msk                          /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
14547 #define TIM_ECR_PWPRSC_0      (0x01UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x01000000 */
14548 #define TIM_ECR_PWPRSC_1      (0x02UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x02000000 */
14549 #define TIM_ECR_PWPRSC_2      (0x04UL << TIM_ECR_PWPRSC_Pos)              /*!< 0x04000000 */
14550 
14551 /*******************  Bit definition for TIM_DMAR register  *******************/
14552 #define TIM_DMAR_DMAB_Pos         (0U)
14553 #define TIM_DMAR_DMAB_Msk         (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
14554 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
14555 
14556 /******************************************************************************/
14557 /*                                                                            */
14558 /*                         Low Power Timer (LPTIM)                           */
14559 /*                                                                            */
14560 /******************************************************************************/
14561 /******************  Bit definition for LPTIM_ISR register  *******************/
14562 #define LPTIM_ISR_CMPM_Pos          (0U)
14563 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
14564 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
14565 #define LPTIM_ISR_ARRM_Pos          (1U)
14566 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
14567 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
14568 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
14569 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
14570 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
14571 #define LPTIM_ISR_CMPOK_Pos         (3U)
14572 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
14573 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
14574 #define LPTIM_ISR_ARROK_Pos         (4U)
14575 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
14576 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
14577 #define LPTIM_ISR_UP_Pos            (5U)
14578 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
14579 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
14580 #define LPTIM_ISR_DOWN_Pos          (6U)
14581 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
14582 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
14583 
14584 /******************  Bit definition for LPTIM_ICR register  *******************/
14585 #define LPTIM_ICR_CMPMCF_Pos        (0U)
14586 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
14587 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
14588 #define LPTIM_ICR_ARRMCF_Pos        (1U)
14589 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
14590 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
14591 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
14592 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
14593 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
14594 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
14595 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
14596 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
14597 #define LPTIM_ICR_ARROKCF_Pos       (4U)
14598 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
14599 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
14600 #define LPTIM_ICR_UPCF_Pos          (5U)
14601 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
14602 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
14603 #define LPTIM_ICR_DOWNCF_Pos        (6U)
14604 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
14605 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
14606 
14607 /******************  Bit definition for LPTIM_IER register ********************/
14608 #define LPTIM_IER_CMPMIE_Pos        (0U)
14609 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
14610 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
14611 #define LPTIM_IER_ARRMIE_Pos        (1U)
14612 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
14613 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
14614 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
14615 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
14616 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
14617 #define LPTIM_IER_CMPOKIE_Pos       (3U)
14618 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
14619 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
14620 #define LPTIM_IER_ARROKIE_Pos       (4U)
14621 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
14622 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
14623 #define LPTIM_IER_UPIE_Pos          (5U)
14624 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
14625 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
14626 #define LPTIM_IER_DOWNIE_Pos        (6U)
14627 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
14628 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
14629 
14630 /******************  Bit definition for LPTIM_CFGR register *******************/
14631 #define LPTIM_CFGR_CKSEL_Pos        (0U)
14632 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
14633 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
14634 
14635 #define LPTIM_CFGR_CKPOL_Pos        (1U)
14636 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
14637 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
14638 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
14639 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
14640 
14641 #define LPTIM_CFGR_CKFLT_Pos        (3U)
14642 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
14643 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
14644 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
14645 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
14646 
14647 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
14648 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
14649 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
14650 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
14651 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
14652 
14653 #define LPTIM_CFGR_PRESC_Pos        (9U)
14654 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
14655 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
14656 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
14657 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
14658 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
14659 
14660 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
14661 #define LPTIM_CFGR_TRIGSEL_Msk      (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x0200E000 */
14662 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
14663 #define LPTIM_CFGR_TRIGSEL_0        (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00002000 */
14664 #define LPTIM_CFGR_TRIGSEL_1        (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00004000 */
14665 #define LPTIM_CFGR_TRIGSEL_2        (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x00008000 */
14666 #define LPTIM_CFGR_TRIGSEL_3        (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)      /*!< 0x02000000 */
14667 
14668 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
14669 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
14670 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
14671 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
14672 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
14673 
14674 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
14675 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
14676 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
14677 #define LPTIM_CFGR_WAVE_Pos         (20U)
14678 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
14679 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
14680 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
14681 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
14682 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
14683 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
14684 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
14685 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
14686 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
14687 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
14688 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
14689 #define LPTIM_CFGR_ENC_Pos          (24U)
14690 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
14691 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
14692 
14693 /******************  Bit definition for LPTIM_CR register  ********************/
14694 #define LPTIM_CR_ENABLE_Pos         (0U)
14695 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
14696 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
14697 #define LPTIM_CR_SNGSTRT_Pos        (1U)
14698 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
14699 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
14700 #define LPTIM_CR_CNTSTRT_Pos        (2U)
14701 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
14702 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
14703 #define LPTIM_CR_COUNTRST_Pos       (3U)
14704 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
14705 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
14706 #define LPTIM_CR_RSTARE_Pos         (4U)
14707 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
14708 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
14709 
14710 /******************  Bit definition for LPTIM_CMP register  *******************/
14711 #define LPTIM_CMP_CMP_Pos           (0U)
14712 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
14713 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
14714 
14715 /******************  Bit definition for LPTIM_ARR register  *******************/
14716 #define LPTIM_ARR_ARR_Pos           (0U)
14717 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
14718 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
14719 
14720 /******************  Bit definition for LPTIM_CNT register  *******************/
14721 #define LPTIM_CNT_CNT_Pos           (0U)
14722 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
14723 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
14724 
14725 /******************  Bit definition for LPTIM_OR register  *******************/
14726 #define LPTIM_OR_IN1_Pos             (0U)
14727 #define LPTIM_OR_IN1_Msk             (0xDUL << LPTIM_OR_IN1_Pos)                 /*!< 0x0000000D */
14728 #define LPTIM_OR_IN1                 LPTIM_OR_IN1_Msk                            /*!< IN1[2:0] bits (Remap selection) */
14729 #define LPTIM_OR_IN1_0               (0x1UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000001 */
14730 #define LPTIM_OR_IN1_1               (0x4UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000004 */
14731 #define LPTIM_OR_IN1_2               (0x8UL << LPTIM_OR_IN1_Pos)                 /*!< 0x00000008 */
14732 
14733 #define LPTIM_OR_IN2_Pos             (1U)
14734 #define LPTIM_OR_IN2_Msk             (0x19UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000032 */
14735 #define LPTIM_OR_IN2                 LPTIM_OR_IN2_Msk                            /*!< IN2[2:0] bits (Remap selection) */
14736 #define LPTIM_OR_IN2_0               (0x1UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000002 */
14737 #define LPTIM_OR_IN2_1               (0x8UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000010 */
14738 #define LPTIM_OR_IN2_2               (0x10UL << LPTIM_OR_IN2_Pos)                 /*!< 0x00000020 */
14739 /******************************************************************************/
14740 /*                                                                            */
14741 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
14742 /*                                                                            */
14743 /******************************************************************************/
14744 /******************  Bit definition for USART_CR1 register  *******************/
14745 #define USART_CR1_UE_Pos             (0U)
14746 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
14747 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
14748 #define USART_CR1_UESM_Pos           (1U)
14749 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
14750 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
14751 #define USART_CR1_RE_Pos             (2U)
14752 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
14753 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
14754 #define USART_CR1_TE_Pos             (3U)
14755 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
14756 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
14757 #define USART_CR1_IDLEIE_Pos         (4U)
14758 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
14759 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
14760 #define USART_CR1_RXNEIE_Pos         (5U)
14761 #define USART_CR1_RXNEIE_Msk         (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
14762 #define USART_CR1_RXNEIE             USART_CR1_RXNEIE_Msk                      /*!< RXNE Interrupt Enable */
14763 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
14764 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk                      /*!< 0x00000020 */
14765 #define USART_CR1_RXNEIE_RXFNEIE     USART_CR1_RXNEIE_Msk                      /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
14766 #define USART_CR1_TCIE_Pos           (6U)
14767 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
14768 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
14769 #define USART_CR1_TXEIE_Pos          (7U)
14770 #define USART_CR1_TXEIE_Msk          (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
14771 #define USART_CR1_TXEIE              USART_CR1_TXEIE_Msk                       /*!< TXE Interrupt Enable */
14772 #define USART_CR1_TXEIE_TXFNFIE_Pos  USART_CR1_TXEIE_Pos
14773 #define USART_CR1_TXEIE_TXFNFIE_Msk  USART_CR1_TXEIE_Msk                       /*!< 0x00000080 */
14774 #define USART_CR1_TXEIE_TXFNFIE      USART_CR1_TXEIE_Msk                       /*!< TXE and TX FIFO Not Full Interrupt Enable */
14775 #define USART_CR1_PEIE_Pos           (8U)
14776 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
14777 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
14778 #define USART_CR1_PS_Pos             (9U)
14779 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
14780 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
14781 #define USART_CR1_PCE_Pos            (10U)
14782 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
14783 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
14784 #define USART_CR1_WAKE_Pos           (11U)
14785 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
14786 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
14787 #define USART_CR1_M_Pos              (12U)
14788 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
14789 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
14790 #define USART_CR1_M0_Pos             (12U)
14791 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
14792 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
14793 #define USART_CR1_MME_Pos            (13U)
14794 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
14795 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
14796 #define USART_CR1_CMIE_Pos           (14U)
14797 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
14798 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
14799 #define USART_CR1_OVER8_Pos          (15U)
14800 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
14801 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
14802 #define USART_CR1_DEDT_Pos           (16U)
14803 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
14804 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14805 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
14806 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
14807 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
14808 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
14809 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
14810 #define USART_CR1_DEAT_Pos           (21U)
14811 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
14812 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
14813 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
14814 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
14815 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
14816 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
14817 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
14818 #define USART_CR1_RTOIE_Pos          (26U)
14819 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
14820 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
14821 #define USART_CR1_EOBIE_Pos          (27U)
14822 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
14823 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
14824 #define USART_CR1_M1_Pos             (28U)
14825 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
14826 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
14827 #define USART_CR1_FIFOEN_Pos         (29U)
14828 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
14829 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
14830 #define USART_CR1_TXFEIE_Pos         (30U)
14831 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
14832 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
14833 #define USART_CR1_RXFFIE_Pos         (31U)
14834 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
14835 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
14836 
14837 /******************  Bit definition for USART_CR2 register  *******************/
14838 #define USART_CR2_SLVEN_Pos          (0U)
14839 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
14840 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
14841 #define USART_CR2_DIS_NSS_Pos        (3U)
14842 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
14843 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< Slave Select (NSS) pin management */
14844 #define USART_CR2_ADDM7_Pos          (4U)
14845 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
14846 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
14847 #define USART_CR2_LBDL_Pos           (5U)
14848 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
14849 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
14850 #define USART_CR2_LBDIE_Pos          (6U)
14851 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
14852 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
14853 #define USART_CR2_LBCL_Pos           (8U)
14854 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
14855 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
14856 #define USART_CR2_CPHA_Pos           (9U)
14857 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
14858 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
14859 #define USART_CR2_CPOL_Pos           (10U)
14860 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
14861 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
14862 #define USART_CR2_CLKEN_Pos          (11U)
14863 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
14864 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
14865 #define USART_CR2_STOP_Pos           (12U)
14866 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
14867 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
14868 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
14869 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
14870 #define USART_CR2_LINEN_Pos          (14U)
14871 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
14872 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
14873 #define USART_CR2_SWAP_Pos           (15U)
14874 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
14875 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
14876 #define USART_CR2_RXINV_Pos          (16U)
14877 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
14878 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
14879 #define USART_CR2_TXINV_Pos          (17U)
14880 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
14881 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
14882 #define USART_CR2_DATAINV_Pos        (18U)
14883 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
14884 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
14885 #define USART_CR2_MSBFIRST_Pos       (19U)
14886 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
14887 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
14888 #define USART_CR2_ABREN_Pos          (20U)
14889 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
14890 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
14891 #define USART_CR2_ABRMODE_Pos        (21U)
14892 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
14893 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14894 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
14895 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
14896 #define USART_CR2_RTOEN_Pos          (23U)
14897 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
14898 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
14899 #define USART_CR2_ADD_Pos            (24U)
14900 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
14901 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
14902 
14903 /******************  Bit definition for USART_CR3 register  *******************/
14904 #define USART_CR3_EIE_Pos            (0U)
14905 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
14906 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
14907 #define USART_CR3_IREN_Pos           (1U)
14908 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
14909 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
14910 #define USART_CR3_IRLP_Pos           (2U)
14911 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
14912 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
14913 #define USART_CR3_HDSEL_Pos          (3U)
14914 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
14915 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
14916 #define USART_CR3_NACK_Pos           (4U)
14917 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
14918 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
14919 #define USART_CR3_SCEN_Pos           (5U)
14920 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
14921 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
14922 #define USART_CR3_DMAR_Pos           (6U)
14923 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
14924 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
14925 #define USART_CR3_DMAT_Pos           (7U)
14926 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
14927 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
14928 #define USART_CR3_RTSE_Pos           (8U)
14929 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
14930 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
14931 #define USART_CR3_CTSE_Pos           (9U)
14932 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
14933 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
14934 #define USART_CR3_CTSIE_Pos          (10U)
14935 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
14936 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
14937 #define USART_CR3_ONEBIT_Pos         (11U)
14938 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
14939 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
14940 #define USART_CR3_OVRDIS_Pos         (12U)
14941 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
14942 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
14943 #define USART_CR3_DDRE_Pos           (13U)
14944 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
14945 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
14946 #define USART_CR3_DEM_Pos            (14U)
14947 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
14948 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
14949 #define USART_CR3_DEP_Pos            (15U)
14950 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
14951 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
14952 #define USART_CR3_SCARCNT_Pos        (17U)
14953 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
14954 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14955 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
14956 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
14957 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
14958 #define USART_CR3_WUS_Pos            (20U)
14959 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
14960 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
14961 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
14962 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
14963 #define USART_CR3_WUFIE_Pos          (22U)
14964 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
14965 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
14966 #define USART_CR3_TXFTIE_Pos         (23U)
14967 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
14968 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
14969 #define USART_CR3_TCBGTIE_Pos        (24U)
14970 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
14971 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
14972 #define USART_CR3_RXFTCFG_Pos        (25U)
14973 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
14974 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
14975 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
14976 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
14977 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
14978 #define USART_CR3_RXFTIE_Pos         (28U)
14979 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
14980 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
14981 #define USART_CR3_TXFTCFG_Pos        (29U)
14982 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
14983 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
14984 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
14985 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
14986 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
14987 
14988 /******************  Bit definition for USART_BRR register  *******************/
14989 #define USART_BRR_LPUART_Pos         (0U)
14990 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
14991 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
14992 #define USART_BRR_BRR_Pos            (0U)
14993 #define USART_BRR_BRR_Msk            (0xFFFFUL << USART_BRR_BRR_Pos)           /*!< 0x0000FFFF */
14994 #define USART_BRR_BRR                USART_BRR_BRR_Msk                         /*!< USART Baud rate register [15:0] */
14995 
14996 /******************  Bit definition for USART_GTPR register  ******************/
14997 #define USART_GTPR_PSC_Pos           (0U)
14998 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
14999 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
15000 #define USART_GTPR_GT_Pos            (8U)
15001 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
15002 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
15003 
15004 /*******************  Bit definition for USART_RTOR register  *****************/
15005 #define USART_RTOR_RTO_Pos           (0U)
15006 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
15007 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
15008 #define USART_RTOR_BLEN_Pos          (24U)
15009 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
15010 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
15011 
15012 /*******************  Bit definition for USART_RQR register  ******************/
15013 #define USART_RQR_ABRRQ_Pos          (0U)
15014 #define USART_RQR_ABRRQ_Msk          (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
15015 #define USART_RQR_ABRRQ              USART_RQR_ABRRQ_Msk                       /*!< Auto-Baud Rate Request */
15016 #define USART_RQR_SBKRQ_Pos          (1U)
15017 #define USART_RQR_SBKRQ_Msk          (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
15018 #define USART_RQR_SBKRQ              USART_RQR_SBKRQ_Msk                       /*!< Send Break Request */
15019 #define USART_RQR_MMRQ_Pos           (2U)
15020 #define USART_RQR_MMRQ_Msk           (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
15021 #define USART_RQR_MMRQ               USART_RQR_MMRQ_Msk                        /*!< Mute Mode Request */
15022 #define USART_RQR_RXFRQ_Pos          (3U)
15023 #define USART_RQR_RXFRQ_Msk          (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
15024 #define USART_RQR_RXFRQ              USART_RQR_RXFRQ_Msk                       /*!< Receive Data flush Request */
15025 #define USART_RQR_TXFRQ_Pos          (4U)
15026 #define USART_RQR_TXFRQ_Msk          (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
15027 #define USART_RQR_TXFRQ              USART_RQR_TXFRQ_Msk                       /*!< Transmit data flush Request */
15028 
15029 /*******************  Bit definition for USART_ISR register  ******************/
15030 #define USART_ISR_PE_Pos             (0U)
15031 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
15032 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
15033 #define USART_ISR_FE_Pos             (1U)
15034 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
15035 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
15036 #define USART_ISR_NE_Pos             (2U)
15037 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
15038 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
15039 #define USART_ISR_ORE_Pos            (3U)
15040 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
15041 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
15042 #define USART_ISR_IDLE_Pos           (4U)
15043 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
15044 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
15045 #define USART_ISR_RXNE_Pos           (5U)
15046 #define USART_ISR_RXNE_Msk           (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
15047 #define USART_ISR_RXNE               USART_ISR_RXNE_Msk                        /*!< Read Data Register Not Empty */
15048 #define USART_ISR_RXNE_RXFNE_Pos     USART_ISR_RXNE_Pos
15049 #define USART_ISR_RXNE_RXFNE_Msk     USART_ISR_RXNE_Msk                        /*!< 0x00000020 */
15050 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_Msk                        /*!< Read Data Register or RX FIFO Not Empty */
15051 #define USART_ISR_TC_Pos             (6U)
15052 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
15053 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
15054 #define USART_ISR_TXE_Pos            (7U)
15055 #define USART_ISR_TXE_Msk            (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
15056 #define USART_ISR_TXE                USART_ISR_TXE_Msk                         /*!< Transmit Data Register Empty */
15057 #define USART_ISR_TXE_TXFNF_Pos      USART_ISR_TXE_Pos
15058 #define USART_ISR_TXE_TXFNF_Msk      USART_ISR_TXE_Msk                       /*!< 0x00000080 */
15059 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
15060 #define USART_ISR_LBDF_Pos           (8U)
15061 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
15062 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
15063 #define USART_ISR_CTSIF_Pos          (9U)
15064 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
15065 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
15066 #define USART_ISR_CTS_Pos            (10U)
15067 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
15068 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
15069 #define USART_ISR_RTOF_Pos           (11U)
15070 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
15071 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
15072 #define USART_ISR_EOBF_Pos           (12U)
15073 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
15074 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
15075 #define USART_ISR_UDR_Pos            (13U)
15076 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
15077 #define USART_ISR_UDR                USART_ISR_UDR_Msk                         /*!< SPI slave underrun error flag */
15078 #define USART_ISR_ABRE_Pos           (14U)
15079 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
15080 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
15081 #define USART_ISR_ABRF_Pos           (15U)
15082 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
15083 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
15084 #define USART_ISR_BUSY_Pos           (16U)
15085 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
15086 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
15087 #define USART_ISR_CMF_Pos            (17U)
15088 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
15089 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
15090 #define USART_ISR_SBKF_Pos           (18U)
15091 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
15092 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
15093 #define USART_ISR_RWU_Pos            (19U)
15094 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
15095 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
15096 #define USART_ISR_WUF_Pos            (20U)
15097 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
15098 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
15099 #define USART_ISR_TEACK_Pos          (21U)
15100 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
15101 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
15102 #define USART_ISR_REACK_Pos          (22U)
15103 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
15104 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
15105 #define USART_ISR_TXFE_Pos           (23U)
15106 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
15107 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty */
15108 #define USART_ISR_RXFF_Pos           (24U)
15109 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
15110 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full */
15111 #define USART_ISR_TCBGT_Pos          (25U)
15112 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
15113 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time completion */
15114 #define USART_ISR_RXFT_Pos           (26U)
15115 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
15116 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO threshold flag */
15117 #define USART_ISR_TXFT_Pos           (27U)
15118 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
15119 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO threshold flag */
15120 
15121 /*******************  Bit definition for USART_ICR register  ******************/
15122 #define USART_ICR_PECF_Pos           (0U)
15123 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
15124 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
15125 #define USART_ICR_FECF_Pos           (1U)
15126 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
15127 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
15128 #define USART_ICR_NECF_Pos           (2U)
15129 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
15130 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise detected Clear Flag */
15131 #define USART_ICR_ORECF_Pos          (3U)
15132 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
15133 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
15134 #define USART_ICR_IDLECF_Pos         (4U)
15135 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
15136 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
15137 #define USART_ICR_TXFECF_Pos         (5U)
15138 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
15139 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO empty Clear flag */
15140 #define USART_ICR_TCCF_Pos           (6U)
15141 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
15142 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
15143 #define USART_ICR_TCBGTCF_Pos        (7U)
15144 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
15145 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
15146 #define USART_ICR_LBDCF_Pos          (8U)
15147 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
15148 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
15149 #define USART_ICR_CTSCF_Pos          (9U)
15150 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
15151 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
15152 #define USART_ICR_RTOCF_Pos          (11U)
15153 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
15154 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
15155 #define USART_ICR_EOBCF_Pos          (12U)
15156 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
15157 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
15158 #define USART_ICR_UDRCF_Pos          (13U)
15159 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
15160 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
15161 #define USART_ICR_CMCF_Pos           (17U)
15162 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
15163 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
15164 #define USART_ICR_WUCF_Pos           (20U)
15165 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
15166 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
15167 
15168 /*******************  Bit definition for USART_RDR register  ******************/
15169 #define USART_RDR_RDR_Pos            (0U)
15170 #define USART_RDR_RDR_Msk            (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
15171 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
15172 
15173 /*******************  Bit definition for USART_TDR register  ******************/
15174 #define USART_TDR_TDR_Pos            (0U)
15175 #define USART_TDR_TDR_Msk            (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
15176 #define USART_TDR_TDR                USART_TDR_TDR_Msk                         /*!< TDR[8:0] bits (Transmit Data value) */
15177 
15178 /*******************  Bit definition for USART_PRESC register  ****************/
15179 #define USART_PRESC_PRESCALER_Pos    (0U)
15180 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
15181 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
15182 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
15183 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
15184 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
15185 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
15186 
15187 
15188 
15189 
15190 /******************************************************************************/
15191 /*                                                                            */
15192 /*                            Window WATCHDOG                                 */
15193 /*                                                                            */
15194 /******************************************************************************/
15195 /*******************  Bit definition for WWDG_CR register  ********************/
15196 #define WWDG_CR_T_Pos           (0U)
15197 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
15198 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
15199 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
15200 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
15201 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
15202 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
15203 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
15204 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
15205 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
15206 
15207 #define WWDG_CR_WDGA_Pos        (7U)
15208 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
15209 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
15210 
15211 /*******************  Bit definition for WWDG_CFR register  *******************/
15212 #define WWDG_CFR_W_Pos          (0U)
15213 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
15214 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
15215 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
15216 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
15217 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
15218 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
15219 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
15220 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
15221 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
15222 
15223 #define WWDG_CFR_WDGTB_Pos      (11U)
15224 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
15225 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
15226 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
15227 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
15228 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
15229 
15230 #define WWDG_CFR_EWI_Pos        (9U)
15231 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
15232 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
15233 
15234 /*******************  Bit definition for WWDG_SR register  ********************/
15235 #define WWDG_SR_EWIF_Pos        (0U)
15236 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
15237 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
15238 
15239 /**
15240   * @}
15241   */
15242 
15243 /**
15244   * @}
15245   */
15246 
15247 /** @addtogroup Exported_macros
15248   * @{
15249   */
15250 
15251 /******************************* ADC Instances ********************************/
15252 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15253                                        ((INSTANCE) == ADC2))
15254 
15255 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15256 
15257 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
15258 
15259 /******************************* AES Instances ********************************/
15260 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
15261 
15262 /******************************** FDCAN Instances ******************************/
15263 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
15264 
15265 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
15266 /******************************** COMP Instances ******************************/
15267 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
15268                                         ((INSTANCE) == COMP2) || \
15269                                         ((INSTANCE) == COMP3) || \
15270                                         ((INSTANCE) == COMP4) || \
15271                                         ((INSTANCE) == COMP5) || \
15272                                         ((INSTANCE) == COMP6) || \
15273                                         ((INSTANCE) == COMP7))
15274 
15275 /******************************* CORDIC Instances *****************************/
15276 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
15277 
15278 /******************************* CRC Instances ********************************/
15279 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15280 
15281 /******************************* DAC Instances ********************************/
15282 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
15283                                        ((INSTANCE) == DAC2) || \
15284                                        ((INSTANCE) == DAC3) || \
15285                                        ((INSTANCE) == DAC4))
15286 
15287 
15288 /******************************** DMA Instances *******************************/
15289 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
15290                                        ((INSTANCE) == DMA1_Channel2) || \
15291                                        ((INSTANCE) == DMA1_Channel3) || \
15292                                        ((INSTANCE) == DMA1_Channel4) || \
15293                                        ((INSTANCE) == DMA1_Channel5) || \
15294                                        ((INSTANCE) == DMA1_Channel6) || \
15295                                        ((INSTANCE) == DMA1_Channel7) || \
15296                                        ((INSTANCE) == DMA1_Channel8) || \
15297                                        ((INSTANCE) == DMA2_Channel1) || \
15298                                        ((INSTANCE) == DMA2_Channel2) || \
15299                                        ((INSTANCE) == DMA2_Channel3) || \
15300                                        ((INSTANCE) == DMA2_Channel4) || \
15301                                        ((INSTANCE) == DMA2_Channel5) || \
15302                                        ((INSTANCE) == DMA2_Channel6) || \
15303                                        ((INSTANCE) == DMA2_Channel7) || \
15304                                        ((INSTANCE) == DMA2_Channel8))
15305 
15306 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
15307                                                    ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
15308                                                    ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
15309                                                    ((INSTANCE) == DMAMUX1_RequestGenerator3))
15310 
15311 /******************************* FMAC Instances *******************************/
15312 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
15313 
15314 /******************************* GPIO Instances *******************************/
15315 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15316                                         ((INSTANCE) == GPIOB) || \
15317                                         ((INSTANCE) == GPIOC) || \
15318                                         ((INSTANCE) == GPIOD) || \
15319                                         ((INSTANCE) == GPIOE) || \
15320                                         ((INSTANCE) == GPIOF) || \
15321                                         ((INSTANCE) == GPIOG))
15322 
15323 /******************************* GPIO AF Instances ****************************/
15324 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
15325 
15326 /**************************** GPIO Lock Instances *****************************/
15327 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
15328 
15329 /******************************** I2C Instances *******************************/
15330 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15331                                        ((INSTANCE) == I2C2) || \
15332                                        ((INSTANCE) == I2C3))
15333 
15334 /****************** I2C Instances : wakeup capability from stop modes *********/
15335 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
15336 
15337 
15338 
15339 
15340 /******************************* RNG Instances ********************************/
15341 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
15342 
15343 /****************************** RTC Instances *********************************/
15344 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
15345 
15346 #define IS_TAMP_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == TAMP)
15347 
15348 /****************************** SMBUS Instances *******************************/
15349 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15350                                          ((INSTANCE) == I2C2) || \
15351                                          ((INSTANCE) == I2C3))
15352 
15353 
15354 /******************************** SPI Instances *******************************/
15355 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15356                                        ((INSTANCE) == SPI2) || \
15357                                        ((INSTANCE) == SPI3))
15358 
15359 /******************************** I2S Instances *******************************/
15360 #define IS_I2S_ALL_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == SPI2) || \
15361                                             ((__INSTANCE__) == SPI3))
15362 
15363 /****************** LPTIM Instances : All supported instances *****************/
15364 #define IS_LPTIM_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
15365 
15366 /****************** LPTIM Instances : supporting encoder interface **************/
15367 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     ((INSTANCE) == LPTIM1)
15368 
15369 /****************** LPTIM Instances : All supported instances *****************/
15370 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
15371 
15372 /****************** TIM Instances : All supported instances *******************/
15373 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
15374                                          ((INSTANCE) == TIM2)   || \
15375                                          ((INSTANCE) == TIM3)   || \
15376                                          ((INSTANCE) == TIM4)   || \
15377                                          ((INSTANCE) == TIM6)   || \
15378                                          ((INSTANCE) == TIM7)   || \
15379                                          ((INSTANCE) == TIM8)   || \
15380                                          ((INSTANCE) == TIM15)  || \
15381                                          ((INSTANCE) == TIM16)  || \
15382                                          ((INSTANCE) == TIM17))
15383 
15384 /****************** TIM Instances : supporting 32 bits counter ****************/
15385 
15386 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
15387 
15388 /****************** TIM Instances : supporting the break function *************/
15389 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
15390                                             ((INSTANCE) == TIM8)    || \
15391                                             ((INSTANCE) == TIM15)   || \
15392                                             ((INSTANCE) == TIM16)   || \
15393                                             ((INSTANCE) == TIM17))
15394 
15395 /************** TIM Instances : supporting Break source selection *************/
15396 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15397                                                ((INSTANCE) == TIM8)   || \
15398                                                ((INSTANCE) == TIM15)  || \
15399                                                ((INSTANCE) == TIM16)  || \
15400                                                ((INSTANCE) == TIM17))
15401 
15402 /****************** TIM Instances : supporting 2 break inputs *****************/
15403 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
15404                                             ((INSTANCE) == TIM8))
15405 
15406 /************* TIM Instances : at least 1 capture/compare channel *************/
15407 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15408                                          ((INSTANCE) == TIM2)   || \
15409                                          ((INSTANCE) == TIM3)   || \
15410                                          ((INSTANCE) == TIM4)   || \
15411                                          ((INSTANCE) == TIM8)   || \
15412                                          ((INSTANCE) == TIM15)  || \
15413                                          ((INSTANCE) == TIM16)  || \
15414                                          ((INSTANCE) == TIM17))
15415 
15416 /************ TIM Instances : at least 2 capture/compare channels *************/
15417 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15418                                          ((INSTANCE) == TIM2)   || \
15419                                          ((INSTANCE) == TIM3)   || \
15420                                          ((INSTANCE) == TIM4)   || \
15421                                          ((INSTANCE) == TIM8)   || \
15422                                          ((INSTANCE) == TIM15))
15423 
15424 /************ TIM Instances : at least 3 capture/compare channels *************/
15425 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15426                                          ((INSTANCE) == TIM2)   || \
15427                                          ((INSTANCE) == TIM3)   || \
15428                                          ((INSTANCE) == TIM4)   || \
15429                                          ((INSTANCE) == TIM8))
15430 
15431 /************ TIM Instances : at least 4 capture/compare channels *************/
15432 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15433                                          ((INSTANCE) == TIM2)   || \
15434                                          ((INSTANCE) == TIM3)   || \
15435                                          ((INSTANCE) == TIM4)   || \
15436                                          ((INSTANCE) == TIM8))
15437 
15438 /****************** TIM Instances : at least 5 capture/compare channels *******/
15439 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15440                                          ((INSTANCE) == TIM8))
15441 
15442 /****************** TIM Instances : at least 6 capture/compare channels *******/
15443 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15444                                          ((INSTANCE) == TIM8))
15445 
15446 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
15447 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
15448                                             ((INSTANCE) == TIM8)   || \
15449                                             ((INSTANCE) == TIM15)  || \
15450                                             ((INSTANCE) == TIM16)  || \
15451                                             ((INSTANCE) == TIM17))
15452 
15453 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
15454 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
15455                                             ((INSTANCE) == TIM2)   || \
15456                                             ((INSTANCE) == TIM3)   || \
15457                                             ((INSTANCE) == TIM4)   || \
15458                                             ((INSTANCE) == TIM6)   || \
15459                                             ((INSTANCE) == TIM7)   || \
15460                                             ((INSTANCE) == TIM8)   || \
15461                                             ((INSTANCE) == TIM15)  || \
15462                                             ((INSTANCE) == TIM16)  || \
15463                                             ((INSTANCE) == TIM17))
15464 
15465 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
15466 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
15467                                             ((INSTANCE) == TIM2)   || \
15468                                             ((INSTANCE) == TIM3)   || \
15469                                             ((INSTANCE) == TIM4)   || \
15470                                             ((INSTANCE) == TIM8)   || \
15471                                             ((INSTANCE) == TIM15)  || \
15472                                             ((INSTANCE) == TIM16)  || \
15473                                             ((INSTANCE) == TIM17))
15474 
15475 /******************** TIM Instances : DMA burst feature ***********************/
15476 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15477                                             ((INSTANCE) == TIM2)   || \
15478                                             ((INSTANCE) == TIM3)   || \
15479                                             ((INSTANCE) == TIM4)   || \
15480                                             ((INSTANCE) == TIM8)   || \
15481                                             ((INSTANCE) == TIM15)  || \
15482                                             ((INSTANCE) == TIM16)  || \
15483                                             ((INSTANCE) == TIM17))
15484 
15485 /******************* TIM Instances : output(s) available **********************/
15486 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15487     ((((INSTANCE) == TIM1) &&                  \
15488      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15489       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15490       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15491       ((CHANNEL) == TIM_CHANNEL_4) ||          \
15492       ((CHANNEL) == TIM_CHANNEL_5) ||          \
15493       ((CHANNEL) == TIM_CHANNEL_6)))           \
15494      ||                                        \
15495      (((INSTANCE) == TIM2) &&                  \
15496      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15497       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15498       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15499       ((CHANNEL) == TIM_CHANNEL_4)))           \
15500      ||                                        \
15501      (((INSTANCE) == TIM3) &&                  \
15502      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15503       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15504       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15505       ((CHANNEL) == TIM_CHANNEL_4)))           \
15506      ||                                        \
15507      (((INSTANCE) == TIM4) &&                  \
15508      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15509       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15510       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15511       ((CHANNEL) == TIM_CHANNEL_4)))           \
15512      ||                                        \
15513      (((INSTANCE) == TIM8) &&                  \
15514      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15515       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15516       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15517       ((CHANNEL) == TIM_CHANNEL_4) ||          \
15518       ((CHANNEL) == TIM_CHANNEL_5) ||          \
15519       ((CHANNEL) == TIM_CHANNEL_6)))           \
15520      ||                                        \
15521      (((INSTANCE) == TIM15) &&                 \
15522      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15523       ((CHANNEL) == TIM_CHANNEL_2)))           \
15524      ||                                        \
15525      (((INSTANCE) == TIM16) &&                 \
15526      (((CHANNEL) == TIM_CHANNEL_1)))           \
15527      ||                                        \
15528      (((INSTANCE) == TIM17) &&                 \
15529       (((CHANNEL) == TIM_CHANNEL_1))))
15530 
15531 /****************** TIM Instances : supporting complementary output(s) ********/
15532 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15533    ((((INSTANCE) == TIM1) &&                    \
15534      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15535       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15536       ((CHANNEL) == TIM_CHANNEL_3) ||           \
15537       ((CHANNEL) == TIM_CHANNEL_4)))            \
15538     ||                                          \
15539     (((INSTANCE) == TIM8) &&                    \
15540      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15541       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15542       ((CHANNEL) == TIM_CHANNEL_3) ||           \
15543       ((CHANNEL) == TIM_CHANNEL_4)))            \
15544     ||                                          \
15545     (((INSTANCE) == TIM15) &&                   \
15546      ((CHANNEL) == TIM_CHANNEL_1))              \
15547     ||                                          \
15548     (((INSTANCE) == TIM16) &&                   \
15549      ((CHANNEL) == TIM_CHANNEL_1))              \
15550     ||                                          \
15551     (((INSTANCE) == TIM17) &&                   \
15552      ((CHANNEL) == TIM_CHANNEL_1)))
15553 
15554 /****************** TIM Instances : supporting clock division *****************/
15555 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
15556                                                     ((INSTANCE) == TIM2)    || \
15557                                                     ((INSTANCE) == TIM3)    || \
15558                                                     ((INSTANCE) == TIM4)    || \
15559                                                     ((INSTANCE) == TIM8)    || \
15560                                                     ((INSTANCE) == TIM15)   || \
15561                                                     ((INSTANCE) == TIM16)   || \
15562                                                     ((INSTANCE) == TIM17))
15563 
15564 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15565 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15566                                                         ((INSTANCE) == TIM2) || \
15567                                                         ((INSTANCE) == TIM3) || \
15568                                                         ((INSTANCE) == TIM4) || \
15569                                                         ((INSTANCE) == TIM8))
15570 
15571 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15572 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15573                                                         ((INSTANCE) == TIM2) || \
15574                                                         ((INSTANCE) == TIM3) || \
15575                                                         ((INSTANCE) == TIM4) || \
15576                                                         ((INSTANCE) == TIM8))
15577 
15578 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
15579 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
15580                                                         ((INSTANCE) == TIM2) || \
15581                                                         ((INSTANCE) == TIM3) || \
15582                                                         ((INSTANCE) == TIM4) || \
15583                                                         ((INSTANCE) == TIM8) || \
15584                                                         ((INSTANCE) == TIM15))
15585 
15586 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
15587 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
15588                                                         ((INSTANCE) == TIM2) || \
15589                                                         ((INSTANCE) == TIM3) || \
15590                                                         ((INSTANCE) == TIM4) || \
15591                                                         ((INSTANCE) == TIM8) || \
15592                                                         ((INSTANCE) == TIM15))
15593 
15594 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15595 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15596                                                      ((INSTANCE) == TIM8))
15597 
15598 /****************** TIM Instances : supporting commutation event generation ***/
15599 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15600                                                      ((INSTANCE) == TIM8)   || \
15601                                                      ((INSTANCE) == TIM15)  || \
15602                                                      ((INSTANCE) == TIM16)  || \
15603                                                      ((INSTANCE) == TIM17))
15604 
15605 /****************** TIM Instances : supporting counting mode selection ********/
15606 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15607                                                         ((INSTANCE) == TIM2) || \
15608                                                         ((INSTANCE) == TIM3) || \
15609                                                         ((INSTANCE) == TIM4) || \
15610                                                         ((INSTANCE) == TIM8))
15611 
15612 /****************** TIM Instances : supporting encoder interface **************/
15613 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
15614                                                       ((INSTANCE) == TIM2)  || \
15615                                                       ((INSTANCE) == TIM3)  || \
15616                                                       ((INSTANCE) == TIM4)  || \
15617                                                       ((INSTANCE) == TIM8))
15618 
15619 /****************** TIM Instances : supporting Hall sensor interface **********/
15620 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15621                                                          ((INSTANCE) == TIM2)   || \
15622                                                          ((INSTANCE) == TIM3)   || \
15623                                                          ((INSTANCE) == TIM4)   || \
15624                                                          ((INSTANCE) == TIM8)   || \
15625                                                          ((INSTANCE) == TIM15))
15626 
15627 /**************** TIM Instances : external trigger input available ************/
15628 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
15629                                             ((INSTANCE) == TIM2)  || \
15630                                             ((INSTANCE) == TIM3)  || \
15631                                             ((INSTANCE) == TIM4)  || \
15632                                             ((INSTANCE) == TIM8))
15633 
15634 /************* TIM Instances : supporting ETR source selection ***************/
15635 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
15636                                              ((INSTANCE) == TIM2)  || \
15637                                              ((INSTANCE) == TIM3)  || \
15638                                              ((INSTANCE) == TIM4)  || \
15639                                              ((INSTANCE) == TIM8))
15640 
15641 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
15642 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
15643                                             ((INSTANCE) == TIM2)  || \
15644                                             ((INSTANCE) == TIM3)  || \
15645                                             ((INSTANCE) == TIM4)  || \
15646                                             ((INSTANCE) == TIM6)  || \
15647                                             ((INSTANCE) == TIM7)  || \
15648                                             ((INSTANCE) == TIM8)  || \
15649                                             ((INSTANCE) == TIM15))
15650 
15651 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15652 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
15653                                             ((INSTANCE) == TIM2)  || \
15654                                             ((INSTANCE) == TIM3)  || \
15655                                             ((INSTANCE) == TIM4)  || \
15656                                             ((INSTANCE) == TIM8)  || \
15657                                             ((INSTANCE) == TIM15))
15658 
15659 /****************** TIM Instances : supporting OCxREF clear *******************/
15660 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
15661                                                        ((INSTANCE) == TIM2) || \
15662                                                        ((INSTANCE) == TIM3) || \
15663                                                        ((INSTANCE) == TIM4)  || \
15664                                                        ((INSTANCE) == TIM8)  || \
15665                                                        ((INSTANCE) == TIM15) || \
15666                                                        ((INSTANCE) == TIM16) || \
15667                                                        ((INSTANCE) == TIM17))
15668 
15669 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
15670 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
15671                                                        ((INSTANCE) == TIM2)  || \
15672                                                        ((INSTANCE) == TIM3)  || \
15673                                                        ((INSTANCE) == TIM8)  || \
15674                                                        ((INSTANCE) == TIM15) || \
15675                                                        ((INSTANCE) == TIM16) || \
15676                                                        ((INSTANCE) == TIM17))
15677 
15678 /****************** TIM Instances : remapping capability **********************/
15679 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
15680                                             ((INSTANCE) == TIM2)  || \
15681                                             ((INSTANCE) == TIM3)  || \
15682                                             ((INSTANCE) == TIM4)  || \
15683                                             ((INSTANCE) == TIM8))
15684 
15685 /****************** TIM Instances : supporting repetition counter *************/
15686 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
15687                                                        ((INSTANCE) == TIM8)  || \
15688                                                        ((INSTANCE) == TIM15) || \
15689                                                        ((INSTANCE) == TIM16) || \
15690                                                        ((INSTANCE) == TIM17))
15691 
15692 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15693 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
15694                                             ((INSTANCE) == TIM8))
15695 
15696 /******************* TIM Instances : Timer input XOR function *****************/
15697 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
15698                                             ((INSTANCE) == TIM2)   || \
15699                                             ((INSTANCE) == TIM3)   || \
15700                                             ((INSTANCE) == TIM4)   || \
15701                                             ((INSTANCE) == TIM8)   || \
15702                                             ((INSTANCE) == TIM15))
15703 
15704 /******************* TIM Instances : Timer input selection ********************/
15705 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
15706                                          ((INSTANCE) == TIM2)   || \
15707                                          ((INSTANCE) == TIM3)   || \
15708                                          ((INSTANCE) == TIM4)   || \
15709                                          ((INSTANCE) == TIM8)   || \
15710                                          ((INSTANCE) == TIM15)  || \
15711                                          ((INSTANCE) == TIM16)  || \
15712                                          ((INSTANCE) == TIM17))
15713 
15714 /****************** TIM Instances : Advanced timer instances *******************/
15715 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
15716                                                   ((INSTANCE) == TIM8))
15717 
15718 
15719 /****************** TIM Instances : supporting HSE/32 request instances *******************/
15720 #define IS_TIM_HSE32_INSTANCE(INSTANCE)         (((INSTANCE) == TIM16)   || \
15721                                                  ((INSTANCE) == TIM17))
15722 
15723 /****************************** HRTIM Instances *******************************/
15724 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
15725 
15726 /******************** USART Instances : Synchronous mode **********************/
15727 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15728                                      ((INSTANCE) == USART2))
15729 
15730 /******************** UART Instances : Asynchronous mode **********************/
15731 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15732                                     ((INSTANCE) == USART2) || \
15733                                     ((INSTANCE) == UART4))
15734 
15735 /*********************** UART Instances : FIFO mode ***************************/
15736 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15737                                          ((INSTANCE) == USART2) || \
15738                                          ((INSTANCE) == UART4) || \
15739                                          ((INSTANCE) == LPUART1))
15740 
15741 /*********************** UART Instances : SPI Slave mode **********************/
15742 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15743                                               ((INSTANCE) == USART2))
15744 
15745 /****************** UART Instances : Auto Baud Rate detection ****************/
15746 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15747                                                             ((INSTANCE) == USART2) || \
15748                                                             ((INSTANCE) == UART4))
15749 
15750 /****************** UART Instances : Driver Enable *****************/
15751 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
15752                                                       ((INSTANCE) == USART2) || \
15753                                                       ((INSTANCE) == UART4)  || \
15754                                                       ((INSTANCE) == LPUART1))
15755 
15756 /******************** UART Instances : Half-Duplex mode **********************/
15757 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15758                                                  ((INSTANCE) == USART2) || \
15759                                                  ((INSTANCE) == UART4)  || \
15760                                                  ((INSTANCE) == LPUART1))
15761 
15762 /****************** UART Instances : Hardware Flow control ********************/
15763 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15764                                            ((INSTANCE) == USART2) || \
15765                                            ((INSTANCE) == UART4)  || \
15766                                            ((INSTANCE) == LPUART1))
15767 
15768 /******************** UART Instances : LIN mode **********************/
15769 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15770                                           ((INSTANCE) == USART2) || \
15771                                           ((INSTANCE) == UART4))
15772 
15773 /******************** UART Instances : Wake-up from Stop mode **********************/
15774 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15775                                                       ((INSTANCE) == USART2) || \
15776                                                       ((INSTANCE) == UART4)  || \
15777                                                       ((INSTANCE) == LPUART1))
15778 
15779 /*********************** UART Instances : IRDA mode ***************************/
15780 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15781                                     ((INSTANCE) == USART2) || \
15782                                     ((INSTANCE) == UART4))
15783 
15784 /********************* USART Instances : Smard card mode ***********************/
15785 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15786                                          ((INSTANCE) == USART2))
15787 
15788 /******************** LPUART Instance *****************************************/
15789 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
15790 
15791 /****************************** IWDG Instances ********************************/
15792 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
15793 
15794 /****************************** WWDG Instances ********************************/
15795 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15796 
15797 
15798 
15799 /**
15800   * @}
15801   */
15802 
15803 
15804 /******************************************************************************/
15805 /*  For a painless codes migration between the STM32G4xx device product       */
15806 /*  lines, the aliases defined below are put in place to overcome the         */
15807 /*  differences in the interrupt handlers and IRQn definitions.               */
15808 /*  No need to update developed interrupt code when moving across             */
15809 /*  product lines within the same STM32G4 Family                              */
15810 /******************************************************************************/
15811 
15812 /* Aliases for __IRQn */
15813 
15814 /* Aliases for __IRQHandler */
15815 
15816 #ifdef __cplusplus
15817 }
15818 #endif /* __cplusplus */
15819 
15820 #endif /* __STM32G414xx_H */
15821 
15822 /**
15823   * @}
15824   */
15825 
15826   /**
15827   * @}
15828   */
15829