1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_tim_ex.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer Extended peripheral:
8 * + Time Hall Sensor Interface Initialization
9 * + Time Hall Sensor Interface Start
10 * + Time Complementary signal break and dead time configuration
11 * + Time Master and Slave synchronization configuration
12 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
13 * + Timer remapping capabilities configuration
14 * + Timer encoder index configuration
15 ******************************************************************************
16 * @attention
17 *
18 * Copyright (c) 2022 STMicroelectronics.
19 * All rights reserved.
20 *
21 * This software is licensed under terms that can be found in the LICENSE file
22 * in the root directory of this software component.
23 * If no LICENSE file comes with this software, it is provided AS-IS.
24 *
25 ******************************************************************************
26 @verbatim
27 ==============================================================================
28 ##### TIMER Extended features #####
29 ==============================================================================
30 [..]
31 The Timer Extended features include:
32 (#) Complementary outputs with programmable dead-time for :
33 (++) Output Compare
34 (++) PWM generation (Edge and Center-aligned Mode)
35 (++) One-pulse mode output
36 (#) Synchronization circuit to control the timer with external signals and to
37 interconnect several timers together.
38 (#) Break input to put the timer output signals in reset state or in a known state.
39 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
40 positioning purposes
41 (#) In case of Pulse on compare, configure pulse length and delay
42 (#) Encoder index configuration
43
44 ##### How to use this driver #####
45 ==============================================================================
46 [..]
47 (#) Initialize the TIM low level resources by implementing the following functions
48 depending on the selected feature:
49 (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
50
51 (#) Initialize the TIM low level resources :
52 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
53 (##) TIM pins configuration
54 (+++) Enable the clock for the TIM GPIOs using the following function:
55 __HAL_RCC_GPIOx_CLK_ENABLE();
56 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
57
58 (#) The external Clock can be configured, if needed (the default clock is the
59 internal clock from the APBx), using the following function:
60 HAL_TIM_ConfigClockSource, the clock configuration should be done before
61 any start function.
62
63 (#) Configure the TIM in the desired functioning mode using one of the
64 initialization function of this driver:
65 (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
66 Timer Hall Sensor Interface and the commutation event with the corresponding
67 Interrupt and DMA request if needed (Note that One Timer is used to interface
68 with the Hall sensor Interface and another Timer should be used to use
69 the commutation event).
70 (#) In case of Pulse On Compare:
71 (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler
72
73
74 (#) Activate the TIM peripheral using one of the start functions:
75 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
76 HAL_TIMEx_OCN_Start_IT()
77 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
78 HAL_TIMEx_PWMN_Start_IT()
79 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
80 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
81 HAL_TIMEx_HallSensor_Start_IT().
82
83 @endverbatim
84 ******************************************************************************
85 */
86
87 /* Includes ------------------------------------------------------------------*/
88 #include "stm32h7rsxx_hal.h"
89
90 /** @addtogroup STM32H7RSxx_HAL_Driver
91 * @{
92 */
93
94 /** @defgroup TIMEx TIMEx
95 * @brief TIM Extended HAL module driver
96 * @{
97 */
98
99 #ifdef HAL_TIM_MODULE_ENABLED
100
101 /* Private typedef -----------------------------------------------------------*/
102 /* Private define ------------------------------------------------------------*/
103 /* Private constants ---------------------------------------------------------*/
104 /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
105 * @{
106 */
107 /* Timeout for break input rearm */
108 #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */
109 /**
110 * @}
111 */
112 /* End of private constants --------------------------------------------------*/
113
114 /* Private macros ------------------------------------------------------------*/
115 /* Private variables ---------------------------------------------------------*/
116 /* Private function prototypes -----------------------------------------------*/
117 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
118 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
119 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
120
121 /* Exported functions --------------------------------------------------------*/
122 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
123 * @{
124 */
125
126 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
127 * @brief Timer Hall Sensor functions
128 *
129 @verbatim
130 ==============================================================================
131 ##### Timer Hall Sensor functions #####
132 ==============================================================================
133 [..]
134 This section provides functions allowing to:
135 (+) Initialize and configure TIM HAL Sensor.
136 (+) De-initialize TIM HAL Sensor.
137 (+) Start the Hall Sensor Interface.
138 (+) Stop the Hall Sensor Interface.
139 (+) Start the Hall Sensor Interface and enable interrupts.
140 (+) Stop the Hall Sensor Interface and disable interrupts.
141 (+) Start the Hall Sensor Interface and enable DMA transfers.
142 (+) Stop the Hall Sensor Interface and disable DMA transfers.
143
144 @endverbatim
145 * @{
146 */
147 /**
148 * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
149 * @note When the timer instance is initialized in Hall Sensor Interface mode,
150 * timer channels 1 and channel 2 are reserved and cannot be used for
151 * other purpose.
152 * @param htim TIM Hall Sensor Interface handle
153 * @param sConfig TIM Hall Sensor configuration structure
154 * @retval HAL status
155 */
HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef * htim,const TIM_HallSensor_InitTypeDef * sConfig)156 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
157 {
158 TIM_OC_InitTypeDef OC_Config;
159
160 /* Check the TIM handle allocation */
161 if (htim == NULL)
162 {
163 return HAL_ERROR;
164 }
165
166 /* Check the parameters */
167 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
168 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
169 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
170 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
171 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
172 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
173 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
174 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
175
176 if (htim->State == HAL_TIM_STATE_RESET)
177 {
178 /* Allocate lock resource and initialize it */
179 htim->Lock = HAL_UNLOCKED;
180
181 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
182 /* Reset interrupt callbacks to legacy week callbacks */
183 TIM_ResetCallback(htim);
184
185 if (htim->HallSensor_MspInitCallback == NULL)
186 {
187 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
188 }
189 /* Init the low level hardware : GPIO, CLOCK, NVIC */
190 htim->HallSensor_MspInitCallback(htim);
191 #else
192 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
193 HAL_TIMEx_HallSensor_MspInit(htim);
194 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
195 }
196
197 /* Set the TIM state */
198 htim->State = HAL_TIM_STATE_BUSY;
199
200 /* Configure the Time base in the Encoder Mode */
201 TIM_Base_SetConfig(htim->Instance, &htim->Init);
202
203 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
204 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
205
206 /* Reset the IC1PSC Bits */
207 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
208 /* Set the IC1PSC value */
209 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
210
211 /* Enable the Hall sensor interface (XOR function of the three inputs) */
212 htim->Instance->CR2 |= TIM_CR2_TI1S;
213
214 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
215 htim->Instance->SMCR &= ~TIM_SMCR_TS;
216 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
217
218 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
219 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
220 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
221
222 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
223 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
224 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
225 OC_Config.OCMode = TIM_OCMODE_PWM2;
226 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
227 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
228 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
229 OC_Config.Pulse = sConfig->Commutation_Delay;
230
231 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
232
233 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
234 register to 101 */
235 htim->Instance->CR2 &= ~TIM_CR2_MMS;
236 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
237
238 /* Initialize the DMA burst operation state */
239 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
240
241 /* Initialize the TIM channels state */
242 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
243 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
244 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
245 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
246
247 /* Initialize the TIM state*/
248 htim->State = HAL_TIM_STATE_READY;
249
250 return HAL_OK;
251 }
252
253 /**
254 * @brief DeInitializes the TIM Hall Sensor interface
255 * @param htim TIM Hall Sensor Interface handle
256 * @retval HAL status
257 */
HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef * htim)258 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
259 {
260 /* Check the parameters */
261 assert_param(IS_TIM_INSTANCE(htim->Instance));
262
263 htim->State = HAL_TIM_STATE_BUSY;
264
265 /* Disable the TIM Peripheral Clock */
266 __HAL_TIM_DISABLE(htim);
267
268 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
269 if (htim->HallSensor_MspDeInitCallback == NULL)
270 {
271 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
272 }
273 /* DeInit the low level hardware */
274 htim->HallSensor_MspDeInitCallback(htim);
275 #else
276 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
277 HAL_TIMEx_HallSensor_MspDeInit(htim);
278 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
279
280 /* Change the DMA burst operation state */
281 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
282
283 /* Change the TIM channels state */
284 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
286 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
288
289 /* Change TIM state */
290 htim->State = HAL_TIM_STATE_RESET;
291
292 /* Release Lock */
293 __HAL_UNLOCK(htim);
294
295 return HAL_OK;
296 }
297
298 /**
299 * @brief Initializes the TIM Hall Sensor MSP.
300 * @param htim TIM Hall Sensor Interface handle
301 * @retval None
302 */
HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef * htim)303 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
304 {
305 /* Prevent unused argument(s) compilation warning */
306 UNUSED(htim);
307
308 /* NOTE : This function should not be modified, when the callback is needed,
309 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
310 */
311 }
312
313 /**
314 * @brief DeInitializes TIM Hall Sensor MSP.
315 * @param htim TIM Hall Sensor Interface handle
316 * @retval None
317 */
HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef * htim)318 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
319 {
320 /* Prevent unused argument(s) compilation warning */
321 UNUSED(htim);
322
323 /* NOTE : This function should not be modified, when the callback is needed,
324 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
325 */
326 }
327
328 /**
329 * @brief Starts the TIM Hall Sensor Interface.
330 * @param htim TIM Hall Sensor Interface handle
331 * @retval HAL status
332 */
HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef * htim)333 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
334 {
335 uint32_t tmpsmcr;
336 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
337 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
338 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
339 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
340
341 /* Check the parameters */
342 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
343
344 /* Check the TIM channels state */
345 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
346 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
347 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
348 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
349 {
350 return HAL_ERROR;
351 }
352
353 /* Set the TIM channels state */
354 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
355 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
356 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
357 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
358
359 /* Enable the Input Capture channel 1
360 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
361 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
362 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
363
364 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
365 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
366 {
367 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
368 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
369 {
370 __HAL_TIM_ENABLE(htim);
371 }
372 }
373 else
374 {
375 __HAL_TIM_ENABLE(htim);
376 }
377
378 /* Return function status */
379 return HAL_OK;
380 }
381
382 /**
383 * @brief Stops the TIM Hall sensor Interface.
384 * @param htim TIM Hall Sensor Interface handle
385 * @retval HAL status
386 */
HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef * htim)387 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
388 {
389 /* Check the parameters */
390 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
391
392 /* Disable the Input Capture channels 1, 2 and 3
393 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
394 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
395 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
396
397 /* Disable the Peripheral */
398 __HAL_TIM_DISABLE(htim);
399
400 /* Set the TIM channels state */
401 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
402 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
403 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
404 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
405
406 /* Return function status */
407 return HAL_OK;
408 }
409
410 /**
411 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
412 * @param htim TIM Hall Sensor Interface handle
413 * @retval HAL status
414 */
HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef * htim)415 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
416 {
417 uint32_t tmpsmcr;
418 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
419 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
420 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
421 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
422
423 /* Check the parameters */
424 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
425
426 /* Check the TIM channels state */
427 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
428 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
429 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
430 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
431 {
432 return HAL_ERROR;
433 }
434
435 /* Set the TIM channels state */
436 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
437 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
438 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
439 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
440
441 /* Enable the capture compare Interrupts 1 event */
442 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
443
444 /* Enable the Input Capture channel 1
445 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
446 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
447 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
448
449 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
450 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
451 {
452 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
453 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
454 {
455 __HAL_TIM_ENABLE(htim);
456 }
457 }
458 else
459 {
460 __HAL_TIM_ENABLE(htim);
461 }
462
463 /* Return function status */
464 return HAL_OK;
465 }
466
467 /**
468 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
469 * @param htim TIM Hall Sensor Interface handle
470 * @retval HAL status
471 */
HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef * htim)472 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
473 {
474 /* Check the parameters */
475 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
476
477 /* Disable the Input Capture channel 1
478 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
479 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
480 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
481
482 /* Disable the capture compare Interrupts event */
483 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
484
485 /* Disable the Peripheral */
486 __HAL_TIM_DISABLE(htim);
487
488 /* Set the TIM channels state */
489 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
491 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
492 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
493
494 /* Return function status */
495 return HAL_OK;
496 }
497
498 /**
499 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
500 * @param htim TIM Hall Sensor Interface handle
501 * @param pData The destination Buffer address.
502 * @param Length The length of data to be transferred from TIM peripheral to memory.
503 * @retval HAL status
504 */
HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)505 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
506 {
507 uint32_t tmpsmcr;
508 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
509 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
510
511 /* Check the parameters */
512 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
513
514 /* Set the TIM channel state */
515 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
516 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
517 {
518 return HAL_BUSY;
519 }
520 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
521 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
522 {
523 if ((pData == NULL) || (Length == 0U))
524 {
525 return HAL_ERROR;
526 }
527 else
528 {
529 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
530 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
531 }
532 }
533 else
534 {
535 return HAL_ERROR;
536 }
537
538 /* Enable the Input Capture channel 1
539 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
540 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
541 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
542
543 /* Set the DMA Input Capture 1 Callbacks */
544 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
545 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
546 /* Set the DMA error callback */
547 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
548
549 /* Enable the DMA channel for Capture 1*/
550 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
551 {
552 /* Return error status */
553 return HAL_ERROR;
554 }
555 /* Enable the capture compare 1 Interrupt */
556 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
557
558 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
559 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
560 {
561 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
562 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
563 {
564 __HAL_TIM_ENABLE(htim);
565 }
566 }
567 else
568 {
569 __HAL_TIM_ENABLE(htim);
570 }
571
572 /* Return function status */
573 return HAL_OK;
574 }
575
576 /**
577 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
578 * @param htim TIM Hall Sensor Interface handle
579 * @retval HAL status
580 */
HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef * htim)581 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
582 {
583 /* Check the parameters */
584 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
585
586 /* Disable the Input Capture channel 1
587 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
588 TIM_CHANNEL_2 and TIM_CHANNEL_3) */
589 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
590
591
592 /* Disable the capture compare Interrupts 1 event */
593 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
594
595 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
596
597 /* Disable the Peripheral */
598 __HAL_TIM_DISABLE(htim);
599
600 /* Set the TIM channel state */
601 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
602 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
603
604 /* Return function status */
605 return HAL_OK;
606 }
607
608 /**
609 * @}
610 */
611
612 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
613 * @brief Timer Complementary Output Compare functions
614 *
615 @verbatim
616 ==============================================================================
617 ##### Timer Complementary Output Compare functions #####
618 ==============================================================================
619 [..]
620 This section provides functions allowing to:
621 (+) Start the Complementary Output Compare/PWM.
622 (+) Stop the Complementary Output Compare/PWM.
623 (+) Start the Complementary Output Compare/PWM and enable interrupts.
624 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
625 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
626 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
627
628 @endverbatim
629 * @{
630 */
631
632 /**
633 * @brief Starts the TIM Output Compare signal generation on the complementary
634 * output.
635 * @param htim TIM Output Compare handle
636 * @param Channel TIM Channel to be enabled
637 * This parameter can be one of the following values:
638 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
639 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
640 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
641 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
642 * @retval HAL status
643 */
HAL_TIMEx_OCN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)644 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
645 {
646 uint32_t tmpsmcr;
647
648 /* Check the parameters */
649 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
650
651 /* Check the TIM complementary channel state */
652 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
653 {
654 return HAL_ERROR;
655 }
656
657 /* Set the TIM complementary channel state */
658 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
659
660 /* Enable the Capture compare channel N */
661 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
662
663 /* Enable the Main Output */
664 __HAL_TIM_MOE_ENABLE(htim);
665
666 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
667 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
668 {
669 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
670 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
671 {
672 __HAL_TIM_ENABLE(htim);
673 }
674 }
675 else
676 {
677 __HAL_TIM_ENABLE(htim);
678 }
679
680 /* Return function status */
681 return HAL_OK;
682 }
683
684 /**
685 * @brief Stops the TIM Output Compare signal generation on the complementary
686 * output.
687 * @param htim TIM handle
688 * @param Channel TIM Channel to be disabled
689 * This parameter can be one of the following values:
690 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
691 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
692 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
693 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
694 * @retval HAL status
695 */
HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)696 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
697 {
698 /* Check the parameters */
699 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
700
701 /* Disable the Capture compare channel N */
702 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
703
704 /* Disable the Main Output */
705 __HAL_TIM_MOE_DISABLE(htim);
706
707 /* Disable the Peripheral */
708 __HAL_TIM_DISABLE(htim);
709
710 /* Set the TIM complementary channel state */
711 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
712
713 /* Return function status */
714 return HAL_OK;
715 }
716
717 /**
718 * @brief Starts the TIM Output Compare signal generation in interrupt mode
719 * on the complementary output.
720 * @param htim TIM OC handle
721 * @param Channel TIM Channel to be enabled
722 * This parameter can be one of the following values:
723 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
724 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
725 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
726 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
727 * @retval HAL status
728 */
HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)729 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
730 {
731 HAL_StatusTypeDef status = HAL_OK;
732 uint32_t tmpsmcr;
733
734 /* Check the parameters */
735 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
736
737 /* Check the TIM complementary channel state */
738 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
739 {
740 return HAL_ERROR;
741 }
742
743 /* Set the TIM complementary channel state */
744 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
745
746 switch (Channel)
747 {
748 case TIM_CHANNEL_1:
749 {
750 /* Enable the TIM Output Compare interrupt */
751 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
752 break;
753 }
754
755 case TIM_CHANNEL_2:
756 {
757 /* Enable the TIM Output Compare interrupt */
758 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
759 break;
760 }
761
762 case TIM_CHANNEL_3:
763 {
764 /* Enable the TIM Output Compare interrupt */
765 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
766 break;
767 }
768
769
770 case TIM_CHANNEL_4:
771 {
772 /* Enable the TIM Output Compare interrupt */
773 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
774 break;
775 }
776
777 default:
778 status = HAL_ERROR;
779 break;
780 }
781
782 if (status == HAL_OK)
783 {
784 /* Enable the TIM Break interrupt */
785 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
786
787 /* Enable the Capture compare channel N */
788 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
789
790 /* Enable the Main Output */
791 __HAL_TIM_MOE_ENABLE(htim);
792
793 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
794 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
795 {
796 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
797 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
798 {
799 __HAL_TIM_ENABLE(htim);
800 }
801 }
802 else
803 {
804 __HAL_TIM_ENABLE(htim);
805 }
806 }
807
808 /* Return function status */
809 return status;
810 }
811
812 /**
813 * @brief Stops the TIM Output Compare signal generation in interrupt mode
814 * on the complementary output.
815 * @param htim TIM Output Compare handle
816 * @param Channel TIM Channel to be disabled
817 * This parameter can be one of the following values:
818 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
819 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
820 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
821 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
822 * @retval HAL status
823 */
HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)824 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
825 {
826 HAL_StatusTypeDef status = HAL_OK;
827 uint32_t tmpccer;
828
829 /* Check the parameters */
830 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
831
832 switch (Channel)
833 {
834 case TIM_CHANNEL_1:
835 {
836 /* Disable the TIM Output Compare interrupt */
837 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
838 break;
839 }
840
841 case TIM_CHANNEL_2:
842 {
843 /* Disable the TIM Output Compare interrupt */
844 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
845 break;
846 }
847
848 case TIM_CHANNEL_3:
849 {
850 /* Disable the TIM Output Compare interrupt */
851 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
852 break;
853 }
854
855 case TIM_CHANNEL_4:
856 {
857 /* Disable the TIM Output Compare interrupt */
858 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
859 break;
860 }
861
862 default:
863 status = HAL_ERROR;
864 break;
865 }
866
867 if (status == HAL_OK)
868 {
869 /* Disable the Capture compare channel N */
870 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
871
872 /* Disable the TIM Break interrupt (only if no more channel is active) */
873 tmpccer = htim->Instance->CCER;
874 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
875 {
876 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
877 }
878
879 /* Disable the Main Output */
880 __HAL_TIM_MOE_DISABLE(htim);
881
882 /* Disable the Peripheral */
883 __HAL_TIM_DISABLE(htim);
884
885 /* Set the TIM complementary channel state */
886 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
887 }
888
889 /* Return function status */
890 return status;
891 }
892
893 /**
894 * @brief Starts the TIM Output Compare signal generation in DMA mode
895 * on the complementary output.
896 * @param htim TIM Output Compare handle
897 * @param Channel TIM Channel to be enabled
898 * This parameter can be one of the following values:
899 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
900 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
901 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
902 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
903 * @param pData The source Buffer address.
904 * @param Length The length of data to be transferred from memory to TIM peripheral
905 * @retval HAL status
906 */
HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)907 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
908 uint16_t Length)
909 {
910 HAL_StatusTypeDef status = HAL_OK;
911 uint32_t tmpsmcr;
912
913 /* Check the parameters */
914 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
915
916 /* Set the TIM complementary channel state */
917 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
918 {
919 return HAL_BUSY;
920 }
921 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
922 {
923 if ((pData == NULL) || (Length == 0U))
924 {
925 return HAL_ERROR;
926 }
927 else
928 {
929 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
930 }
931 }
932 else
933 {
934 return HAL_ERROR;
935 }
936
937 switch (Channel)
938 {
939 case TIM_CHANNEL_1:
940 {
941 /* Set the DMA compare callbacks */
942 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
943 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
944
945 /* Set the DMA error callback */
946 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
947
948 /* Enable the DMA channel */
949 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
950 Length) != HAL_OK)
951 {
952 /* Return error status */
953 return HAL_ERROR;
954 }
955 /* Enable the TIM Output Compare DMA request */
956 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
957 break;
958 }
959
960 case TIM_CHANNEL_2:
961 {
962 /* Set the DMA compare callbacks */
963 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
964 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
965
966 /* Set the DMA error callback */
967 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
968
969 /* Enable the DMA channel */
970 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
971 Length) != HAL_OK)
972 {
973 /* Return error status */
974 return HAL_ERROR;
975 }
976 /* Enable the TIM Output Compare DMA request */
977 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
978 break;
979 }
980
981 case TIM_CHANNEL_3:
982 {
983 /* Set the DMA compare callbacks */
984 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
985 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
986
987 /* Set the DMA error callback */
988 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
989
990 /* Enable the DMA channel */
991 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
992 Length) != HAL_OK)
993 {
994 /* Return error status */
995 return HAL_ERROR;
996 }
997 /* Enable the TIM Output Compare DMA request */
998 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
999 break;
1000 }
1001
1002 case TIM_CHANNEL_4:
1003 {
1004 /* Set the DMA compare callbacks */
1005 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1006 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1007
1008 /* Set the DMA error callback */
1009 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1010
1011 /* Enable the DMA channel */
1012 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1013 Length) != HAL_OK)
1014 {
1015 /* Return error status */
1016 return HAL_ERROR;
1017 }
1018 /* Enable the TIM Output Compare DMA request */
1019 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1020 break;
1021 }
1022
1023 default:
1024 status = HAL_ERROR;
1025 break;
1026 }
1027
1028 if (status == HAL_OK)
1029 {
1030 /* Enable the Capture compare channel N */
1031 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1032
1033 /* Enable the Main Output */
1034 __HAL_TIM_MOE_ENABLE(htim);
1035
1036 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1037 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1038 {
1039 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1040 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1041 {
1042 __HAL_TIM_ENABLE(htim);
1043 }
1044 }
1045 else
1046 {
1047 __HAL_TIM_ENABLE(htim);
1048 }
1049 }
1050
1051 /* Return function status */
1052 return status;
1053 }
1054
1055 /**
1056 * @brief Stops the TIM Output Compare signal generation in DMA mode
1057 * on the complementary output.
1058 * @param htim TIM Output Compare handle
1059 * @param Channel TIM Channel to be disabled
1060 * This parameter can be one of the following values:
1061 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1062 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1063 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1064 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1065 * @retval HAL status
1066 */
HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1067 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1068 {
1069 HAL_StatusTypeDef status = HAL_OK;
1070
1071 /* Check the parameters */
1072 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1073
1074 switch (Channel)
1075 {
1076 case TIM_CHANNEL_1:
1077 {
1078 /* Disable the TIM Output Compare DMA request */
1079 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1080 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1081 break;
1082 }
1083
1084 case TIM_CHANNEL_2:
1085 {
1086 /* Disable the TIM Output Compare DMA request */
1087 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1088 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1089 break;
1090 }
1091
1092 case TIM_CHANNEL_3:
1093 {
1094 /* Disable the TIM Output Compare DMA request */
1095 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1096 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1097 break;
1098 }
1099
1100 case TIM_CHANNEL_4:
1101 {
1102 /* Disable the TIM Output Compare interrupt */
1103 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1104 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1105 break;
1106 }
1107
1108 default:
1109 status = HAL_ERROR;
1110 break;
1111 }
1112
1113 if (status == HAL_OK)
1114 {
1115 /* Disable the Capture compare channel N */
1116 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1117
1118 /* Disable the Main Output */
1119 __HAL_TIM_MOE_DISABLE(htim);
1120
1121 /* Disable the Peripheral */
1122 __HAL_TIM_DISABLE(htim);
1123
1124 /* Set the TIM complementary channel state */
1125 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1126 }
1127
1128 /* Return function status */
1129 return status;
1130 }
1131
1132 /**
1133 * @}
1134 */
1135
1136 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
1137 * @brief Timer Complementary PWM functions
1138 *
1139 @verbatim
1140 ==============================================================================
1141 ##### Timer Complementary PWM functions #####
1142 ==============================================================================
1143 [..]
1144 This section provides functions allowing to:
1145 (+) Start the Complementary PWM.
1146 (+) Stop the Complementary PWM.
1147 (+) Start the Complementary PWM and enable interrupts.
1148 (+) Stop the Complementary PWM and disable interrupts.
1149 (+) Start the Complementary PWM and enable DMA transfers.
1150 (+) Stop the Complementary PWM and disable DMA transfers.
1151 @endverbatim
1152 * @{
1153 */
1154
1155 /**
1156 * @brief Starts the PWM signal generation on the complementary output.
1157 * @param htim TIM handle
1158 * @param Channel TIM Channel to be enabled
1159 * This parameter can be one of the following values:
1160 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1161 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1162 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1163 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1164 * @retval HAL status
1165 */
HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1166 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1167 {
1168 uint32_t tmpsmcr;
1169
1170 /* Check the parameters */
1171 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1172
1173 /* Check the TIM complementary channel state */
1174 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1175 {
1176 return HAL_ERROR;
1177 }
1178
1179 /* Set the TIM complementary channel state */
1180 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1181
1182 /* Enable the complementary PWM output */
1183 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1184
1185 /* Enable the Main Output */
1186 __HAL_TIM_MOE_ENABLE(htim);
1187
1188 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1189 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1190 {
1191 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1192 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1193 {
1194 __HAL_TIM_ENABLE(htim);
1195 }
1196 }
1197 else
1198 {
1199 __HAL_TIM_ENABLE(htim);
1200 }
1201
1202 /* Return function status */
1203 return HAL_OK;
1204 }
1205
1206 /**
1207 * @brief Stops the PWM signal generation on the complementary output.
1208 * @param htim TIM handle
1209 * @param Channel TIM Channel to be disabled
1210 * This parameter can be one of the following values:
1211 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1212 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1213 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1214 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1215 * @retval HAL status
1216 */
HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1217 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1218 {
1219 /* Check the parameters */
1220 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1221
1222 /* Disable the complementary PWM output */
1223 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1224
1225 /* Disable the Main Output */
1226 __HAL_TIM_MOE_DISABLE(htim);
1227
1228 /* Disable the Peripheral */
1229 __HAL_TIM_DISABLE(htim);
1230
1231 /* Set the TIM complementary channel state */
1232 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1233
1234 /* Return function status */
1235 return HAL_OK;
1236 }
1237
1238 /**
1239 * @brief Starts the PWM signal generation in interrupt mode on the
1240 * complementary output.
1241 * @param htim TIM handle
1242 * @param Channel TIM Channel to be disabled
1243 * This parameter can be one of the following values:
1244 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1245 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1246 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1247 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1248 * @retval HAL status
1249 */
HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1250 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1251 {
1252 HAL_StatusTypeDef status = HAL_OK;
1253 uint32_t tmpsmcr;
1254
1255 /* Check the parameters */
1256 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1257
1258 /* Check the TIM complementary channel state */
1259 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1260 {
1261 return HAL_ERROR;
1262 }
1263
1264 /* Set the TIM complementary channel state */
1265 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1266
1267 switch (Channel)
1268 {
1269 case TIM_CHANNEL_1:
1270 {
1271 /* Enable the TIM Capture/Compare 1 interrupt */
1272 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1273 break;
1274 }
1275
1276 case TIM_CHANNEL_2:
1277 {
1278 /* Enable the TIM Capture/Compare 2 interrupt */
1279 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1280 break;
1281 }
1282
1283 case TIM_CHANNEL_3:
1284 {
1285 /* Enable the TIM Capture/Compare 3 interrupt */
1286 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1287 break;
1288 }
1289
1290 case TIM_CHANNEL_4:
1291 {
1292 /* Enable the TIM Capture/Compare 4 interrupt */
1293 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1294 break;
1295 }
1296
1297 default:
1298 status = HAL_ERROR;
1299 break;
1300 }
1301
1302 if (status == HAL_OK)
1303 {
1304 /* Enable the TIM Break interrupt */
1305 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1306
1307 /* Enable the complementary PWM output */
1308 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1309
1310 /* Enable the Main Output */
1311 __HAL_TIM_MOE_ENABLE(htim);
1312
1313 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1314 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1315 {
1316 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1317 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1318 {
1319 __HAL_TIM_ENABLE(htim);
1320 }
1321 }
1322 else
1323 {
1324 __HAL_TIM_ENABLE(htim);
1325 }
1326 }
1327
1328 /* Return function status */
1329 return status;
1330 }
1331
1332 /**
1333 * @brief Stops the PWM signal generation in interrupt mode on the
1334 * complementary output.
1335 * @param htim TIM handle
1336 * @param Channel TIM Channel to be disabled
1337 * This parameter can be one of the following values:
1338 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1339 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1340 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1341 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1342 * @retval HAL status
1343 */
HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1344 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1345 {
1346 HAL_StatusTypeDef status = HAL_OK;
1347 uint32_t tmpccer;
1348
1349 /* Check the parameters */
1350 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1351
1352 switch (Channel)
1353 {
1354 case TIM_CHANNEL_1:
1355 {
1356 /* Disable the TIM Capture/Compare 1 interrupt */
1357 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1358 break;
1359 }
1360
1361 case TIM_CHANNEL_2:
1362 {
1363 /* Disable the TIM Capture/Compare 2 interrupt */
1364 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1365 break;
1366 }
1367
1368 case TIM_CHANNEL_3:
1369 {
1370 /* Disable the TIM Capture/Compare 3 interrupt */
1371 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1372 break;
1373 }
1374
1375 case TIM_CHANNEL_4:
1376 {
1377 /* Disable the TIM Capture/Compare 4 interrupt */
1378 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1379 break;
1380 }
1381
1382 default:
1383 status = HAL_ERROR;
1384 break;
1385 }
1386
1387 if (status == HAL_OK)
1388 {
1389 /* Disable the complementary PWM output */
1390 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1391
1392 /* Disable the TIM Break interrupt (only if no more channel is active) */
1393 tmpccer = htim->Instance->CCER;
1394 if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
1395 {
1396 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1397 }
1398
1399 /* Disable the Main Output */
1400 __HAL_TIM_MOE_DISABLE(htim);
1401
1402 /* Disable the Peripheral */
1403 __HAL_TIM_DISABLE(htim);
1404
1405 /* Set the TIM complementary channel state */
1406 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1407 }
1408
1409 /* Return function status */
1410 return status;
1411 }
1412
1413 /**
1414 * @brief Starts the TIM PWM signal generation in DMA mode on the
1415 * complementary output
1416 * @param htim TIM handle
1417 * @param Channel TIM Channel to be enabled
1418 * This parameter can be one of the following values:
1419 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1420 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1421 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1422 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1423 * @param pData The source Buffer address.
1424 * @param Length The length of data to be transferred from memory to TIM peripheral
1425 * @retval HAL status
1426 */
HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,const uint32_t * pData,uint16_t Length)1427 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
1428 uint16_t Length)
1429 {
1430 HAL_StatusTypeDef status = HAL_OK;
1431 uint32_t tmpsmcr;
1432
1433 /* Check the parameters */
1434 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1435
1436 /* Set the TIM complementary channel state */
1437 if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1438 {
1439 return HAL_BUSY;
1440 }
1441 else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1442 {
1443 if ((pData == NULL) || (Length == 0U))
1444 {
1445 return HAL_ERROR;
1446 }
1447 else
1448 {
1449 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1450 }
1451 }
1452 else
1453 {
1454 return HAL_ERROR;
1455 }
1456
1457 switch (Channel)
1458 {
1459 case TIM_CHANNEL_1:
1460 {
1461 /* Set the DMA compare callbacks */
1462 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1463 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1464
1465 /* Set the DMA error callback */
1466 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1467
1468 /* Enable the DMA channel */
1469 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
1470 Length) != HAL_OK)
1471 {
1472 /* Return error status */
1473 return HAL_ERROR;
1474 }
1475 /* Enable the TIM Capture/Compare 1 DMA request */
1476 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1477 break;
1478 }
1479
1480 case TIM_CHANNEL_2:
1481 {
1482 /* Set the DMA compare callbacks */
1483 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1484 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1485
1486 /* Set the DMA error callback */
1487 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1488
1489 /* Enable the DMA channel */
1490 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
1491 Length) != HAL_OK)
1492 {
1493 /* Return error status */
1494 return HAL_ERROR;
1495 }
1496 /* Enable the TIM Capture/Compare 2 DMA request */
1497 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1498 break;
1499 }
1500
1501 case TIM_CHANNEL_3:
1502 {
1503 /* Set the DMA compare callbacks */
1504 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1505 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1506
1507 /* Set the DMA error callback */
1508 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1509
1510 /* Enable the DMA channel */
1511 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
1512 Length) != HAL_OK)
1513 {
1514 /* Return error status */
1515 return HAL_ERROR;
1516 }
1517 /* Enable the TIM Capture/Compare 3 DMA request */
1518 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1519 break;
1520 }
1521
1522 case TIM_CHANNEL_4:
1523 {
1524 /* Set the DMA compare callbacks */
1525 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1526 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1527
1528 /* Set the DMA error callback */
1529 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ;
1530
1531 /* Enable the DMA channel */
1532 if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
1533 Length) != HAL_OK)
1534 {
1535 /* Return error status */
1536 return HAL_ERROR;
1537 }
1538 /* Enable the TIM Capture/Compare 4 DMA request */
1539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1540 break;
1541 }
1542
1543 default:
1544 status = HAL_ERROR;
1545 break;
1546 }
1547
1548 if (status == HAL_OK)
1549 {
1550 /* Enable the complementary PWM output */
1551 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1552
1553 /* Enable the Main Output */
1554 __HAL_TIM_MOE_ENABLE(htim);
1555
1556 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1557 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
1558 {
1559 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1560 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1561 {
1562 __HAL_TIM_ENABLE(htim);
1563 }
1564 }
1565 else
1566 {
1567 __HAL_TIM_ENABLE(htim);
1568 }
1569 }
1570
1571 /* Return function status */
1572 return status;
1573 }
1574
1575 /**
1576 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
1577 * output
1578 * @param htim TIM handle
1579 * @param Channel TIM Channel to be disabled
1580 * This parameter can be one of the following values:
1581 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1582 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1583 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1584 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1585 * @retval HAL status
1586 */
HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1587 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1588 {
1589 HAL_StatusTypeDef status = HAL_OK;
1590
1591 /* Check the parameters */
1592 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1593
1594 switch (Channel)
1595 {
1596 case TIM_CHANNEL_1:
1597 {
1598 /* Disable the TIM Capture/Compare 1 DMA request */
1599 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1600 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1601 break;
1602 }
1603
1604 case TIM_CHANNEL_2:
1605 {
1606 /* Disable the TIM Capture/Compare 2 DMA request */
1607 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1608 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1609 break;
1610 }
1611
1612 case TIM_CHANNEL_3:
1613 {
1614 /* Disable the TIM Capture/Compare 3 DMA request */
1615 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1616 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1617 break;
1618 }
1619
1620 case TIM_CHANNEL_4:
1621 {
1622 /* Disable the TIM Capture/Compare 4 DMA request */
1623 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1624 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1625 break;
1626 }
1627
1628 default:
1629 status = HAL_ERROR;
1630 break;
1631 }
1632
1633 if (status == HAL_OK)
1634 {
1635 /* Disable the complementary PWM output */
1636 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1637
1638 /* Disable the Main Output */
1639 __HAL_TIM_MOE_DISABLE(htim);
1640
1641 /* Disable the Peripheral */
1642 __HAL_TIM_DISABLE(htim);
1643
1644 /* Set the TIM complementary channel state */
1645 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1646 }
1647
1648 /* Return function status */
1649 return status;
1650 }
1651
1652 /**
1653 * @}
1654 */
1655
1656 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
1657 * @brief Timer Complementary One Pulse functions
1658 *
1659 @verbatim
1660 ==============================================================================
1661 ##### Timer Complementary One Pulse functions #####
1662 ==============================================================================
1663 [..]
1664 This section provides functions allowing to:
1665 (+) Start the Complementary One Pulse generation.
1666 (+) Stop the Complementary One Pulse.
1667 (+) Start the Complementary One Pulse and enable interrupts.
1668 (+) Stop the Complementary One Pulse and disable interrupts.
1669
1670 @endverbatim
1671 * @{
1672 */
1673
1674 /**
1675 * @brief Starts the TIM One Pulse signal generation on the complementary
1676 * output.
1677 * @note OutputChannel must match the pulse output channel chosen when calling
1678 * @ref HAL_TIM_OnePulse_ConfigChannel().
1679 * @param htim TIM One Pulse handle
1680 * @param OutputChannel pulse output channel to enable
1681 * This parameter can be one of the following values:
1682 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1683 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1684 * @retval HAL status
1685 */
HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1686 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1687 {
1688 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1689 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1690 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1691 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1692 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1693
1694 /* Check the parameters */
1695 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1696
1697 /* Check the TIM channels state */
1698 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1699 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1700 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1701 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1702 {
1703 return HAL_ERROR;
1704 }
1705
1706 /* Set the TIM channels state */
1707 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1708 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1709 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1710 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1711
1712 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1713 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1714 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1715
1716 /* Enable the Main Output */
1717 __HAL_TIM_MOE_ENABLE(htim);
1718
1719 /* Return function status */
1720 return HAL_OK;
1721 }
1722
1723 /**
1724 * @brief Stops the TIM One Pulse signal generation on the complementary
1725 * output.
1726 * @note OutputChannel must match the pulse output channel chosen when calling
1727 * @ref HAL_TIM_OnePulse_ConfigChannel().
1728 * @param htim TIM One Pulse handle
1729 * @param OutputChannel pulse output channel to disable
1730 * This parameter can be one of the following values:
1731 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1732 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1733 * @retval HAL status
1734 */
HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1735 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1736 {
1737 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1738
1739 /* Check the parameters */
1740 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1741
1742 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1743 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1744 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1745
1746 /* Disable the Main Output */
1747 __HAL_TIM_MOE_DISABLE(htim);
1748
1749 /* Disable the Peripheral */
1750 __HAL_TIM_DISABLE(htim);
1751
1752 /* Set the TIM channels state */
1753 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1754 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1755 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1756 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1757
1758 /* Return function status */
1759 return HAL_OK;
1760 }
1761
1762 /**
1763 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
1764 * complementary channel.
1765 * @note OutputChannel must match the pulse output channel chosen when calling
1766 * @ref HAL_TIM_OnePulse_ConfigChannel().
1767 * @param htim TIM One Pulse handle
1768 * @param OutputChannel pulse output channel to enable
1769 * This parameter can be one of the following values:
1770 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1771 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1772 * @retval HAL status
1773 */
HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1774 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1775 {
1776 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1777 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
1778 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
1779 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
1780 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
1781
1782 /* Check the parameters */
1783 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1784
1785 /* Check the TIM channels state */
1786 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1787 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
1788 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
1789 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
1790 {
1791 return HAL_ERROR;
1792 }
1793
1794 /* Set the TIM channels state */
1795 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1796 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1797 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
1798 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
1799
1800 /* Enable the TIM Capture/Compare 1 interrupt */
1801 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1802
1803 /* Enable the TIM Capture/Compare 2 interrupt */
1804 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1805
1806 /* Enable the complementary One Pulse output channel and the Input Capture channel */
1807 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1808 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1809
1810 /* Enable the Main Output */
1811 __HAL_TIM_MOE_ENABLE(htim);
1812
1813 /* Return function status */
1814 return HAL_OK;
1815 }
1816
1817 /**
1818 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
1819 * complementary channel.
1820 * @note OutputChannel must match the pulse output channel chosen when calling
1821 * @ref HAL_TIM_OnePulse_ConfigChannel().
1822 * @param htim TIM One Pulse handle
1823 * @param OutputChannel pulse output channel to disable
1824 * This parameter can be one of the following values:
1825 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1826 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1827 * @retval HAL status
1828 */
HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)1829 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1830 {
1831 uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1832
1833 /* Check the parameters */
1834 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1835
1836 /* Disable the TIM Capture/Compare 1 interrupt */
1837 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1838
1839 /* Disable the TIM Capture/Compare 2 interrupt */
1840 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1841
1842 /* Disable the complementary One Pulse output channel and the Input Capture channel */
1843 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1844 TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1845
1846 /* Disable the Main Output */
1847 __HAL_TIM_MOE_DISABLE(htim);
1848
1849 /* Disable the Peripheral */
1850 __HAL_TIM_DISABLE(htim);
1851
1852 /* Set the TIM channels state */
1853 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1854 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1855 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
1856 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
1857
1858 /* Return function status */
1859 return HAL_OK;
1860 }
1861
1862 /**
1863 * @}
1864 */
1865
1866 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
1867 * @brief Peripheral Control functions
1868 *
1869 @verbatim
1870 ==============================================================================
1871 ##### Peripheral Control functions #####
1872 ==============================================================================
1873 [..]
1874 This section provides functions allowing to:
1875 (+) Configure the commutation event in case of use of the Hall sensor interface.
1876 (+) Configure Output channels for OC and PWM mode.
1877
1878 (+) Configure Complementary channels, break features and dead time.
1879 (+) Configure Master synchronization.
1880 (+) Configure timer remapping capabilities.
1881 (+) Select timer input source.
1882 (+) Enable or disable channel grouping.
1883 (+) Configure Pulse on compare.
1884 (+) Configure Encoder index.
1885
1886 @endverbatim
1887 * @{
1888 */
1889
1890 /**
1891 * @brief Configure the TIM commutation event sequence.
1892 * @note This function is mandatory to use the commutation event in order to
1893 * update the configuration at each commutation detection on the TRGI input of the Timer,
1894 * the typical use of this feature is with the use of another Timer(interface Timer)
1895 * configured in Hall sensor interface, this interface Timer will generate the
1896 * commutation at its TRGO output (connected to Timer used in this function) each time
1897 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1898 * @param htim TIM handle
1899 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1900 * This parameter can be one of the following values:
1901 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1902 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1903 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1904 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1905 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1906 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1907 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1908 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1909 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1910 * @arg TIM_TS_ITR9: Internal trigger 9 selected
1911 * @arg TIM_TS_ITR10: Internal trigger 10 selected
1912 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1913 * @arg TIM_TS_ITR13: Internal trigger 13 selected
1914 * @arg TIM_TS_ITR14: Internal trigger 14 selected
1915 * @arg TIM_TS_NONE: No trigger is needed
1916 * @param CommutationSource the Commutation Event source
1917 * This parameter can be one of the following values:
1918 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1919 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1920 * @retval HAL status
1921 */
HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1922 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1923 uint32_t CommutationSource)
1924 {
1925 /* Check the parameters */
1926 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1927 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1928
1929 __HAL_LOCK(htim);
1930
1931 if (CommutationSource == TIM_COMMUTATION_TRGI)
1932 {
1933 /* Select the Input trigger */
1934 htim->Instance->SMCR &= ~TIM_SMCR_TS;
1935 htim->Instance->SMCR |= InputTrigger;
1936 }
1937
1938 /* Select the Capture Compare preload feature */
1939 htim->Instance->CR2 |= TIM_CR2_CCPC;
1940 /* Select the Commutation event source */
1941 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
1942 htim->Instance->CR2 |= CommutationSource;
1943
1944 /* Disable Commutation Interrupt */
1945 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
1946
1947 /* Disable Commutation DMA request */
1948 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
1949
1950 __HAL_UNLOCK(htim);
1951
1952 return HAL_OK;
1953 }
1954
1955 /**
1956 * @brief Configure the TIM commutation event sequence with interrupt.
1957 * @note This function is mandatory to use the commutation event in order to
1958 * update the configuration at each commutation detection on the TRGI input of the Timer,
1959 * the typical use of this feature is with the use of another Timer(interface Timer)
1960 * configured in Hall sensor interface, this interface Timer will generate the
1961 * commutation at its TRGO output (connected to Timer used in this function) each time
1962 * the TI1 of the Interface Timer detect a commutation at its input TI1.
1963 * @param htim TIM handle
1964 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
1965 * This parameter can be one of the following values:
1966 * @arg TIM_TS_ITR0: Internal trigger 0 selected
1967 * @arg TIM_TS_ITR1: Internal trigger 1 selected
1968 * @arg TIM_TS_ITR2: Internal trigger 2 selected
1969 * @arg TIM_TS_ITR3: Internal trigger 3 selected
1970 * @arg TIM_TS_ITR4: Internal trigger 4 selected
1971 * @arg TIM_TS_ITR5: Internal trigger 5 selected
1972 * @arg TIM_TS_ITR6: Internal trigger 6 selected
1973 * @arg TIM_TS_ITR7: Internal trigger 7 selected
1974 * @arg TIM_TS_ITR8: Internal trigger 8 selected
1975 * @arg TIM_TS_ITR9: Internal trigger 9 selected
1976 * @arg TIM_TS_ITR10: Internal trigger 10 selected
1977 * @arg TIM_TS_ITR11: Internal trigger 11 selected
1978 * @arg TIM_TS_ITR13: Internal trigger 13 selected
1979 * @arg TIM_TS_ITR14: Internal trigger 14 selected
1980 * @arg TIM_TS_NONE: No trigger is needed
1981 * @param CommutationSource the Commutation Event source
1982 * This parameter can be one of the following values:
1983 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
1984 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
1985 * @retval HAL status
1986 */
HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)1987 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
1988 uint32_t CommutationSource)
1989 {
1990 /* Check the parameters */
1991 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
1992 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
1993
1994 __HAL_LOCK(htim);
1995
1996 if (CommutationSource == TIM_COMMUTATION_TRGI)
1997 {
1998 /* Select the Input trigger */
1999 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2000 htim->Instance->SMCR |= InputTrigger;
2001 }
2002
2003 /* Select the Capture Compare preload feature */
2004 htim->Instance->CR2 |= TIM_CR2_CCPC;
2005 /* Select the Commutation event source */
2006 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2007 htim->Instance->CR2 |= CommutationSource;
2008
2009 /* Disable Commutation DMA request */
2010 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
2011
2012 /* Enable the Commutation Interrupt */
2013 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
2014
2015 __HAL_UNLOCK(htim);
2016
2017 return HAL_OK;
2018 }
2019
2020 /**
2021 * @brief Configure the TIM commutation event sequence with DMA.
2022 * @note This function is mandatory to use the commutation event in order to
2023 * update the configuration at each commutation detection on the TRGI input of the Timer,
2024 * the typical use of this feature is with the use of another Timer(interface Timer)
2025 * configured in Hall sensor interface, this interface Timer will generate the
2026 * commutation at its TRGO output (connected to Timer used in this function) each time
2027 * the TI1 of the Interface Timer detect a commutation at its input TI1.
2028 * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
2029 * @param htim TIM handle
2030 * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
2031 * This parameter can be one of the following values:
2032 * @arg TIM_TS_ITR0: Internal trigger 0 selected
2033 * @arg TIM_TS_ITR1: Internal trigger 1 selected
2034 * @arg TIM_TS_ITR2: Internal trigger 2 selected
2035 * @arg TIM_TS_ITR3: Internal trigger 3 selected
2036 * @arg TIM_TS_ITR4: Internal trigger 4 selected
2037 * @arg TIM_TS_ITR5: Internal trigger 5 selected
2038 * @arg TIM_TS_ITR6: Internal trigger 6 selected
2039 * @arg TIM_TS_ITR7: Internal trigger 7 selected
2040 * @arg TIM_TS_ITR8: Internal trigger 8 selected
2041 * @arg TIM_TS_ITR9: Internal trigger 9 selected
2042 * @arg TIM_TS_ITR10: Internal trigger 10 selected
2043 * @arg TIM_TS_ITR11: Internal trigger 11 selected
2044 * @arg TIM_TS_ITR13: Internal trigger 13 selected
2045 * @arg TIM_TS_ITR14: Internal trigger 14 selected
2046 * @arg TIM_TS_NONE: No trigger is needed
2047 * @param CommutationSource the Commutation Event source
2048 * This parameter can be one of the following values:
2049 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
2050 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
2051 * @retval HAL status
2052 */
HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef * htim,uint32_t InputTrigger,uint32_t CommutationSource)2053 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
2054 uint32_t CommutationSource)
2055 {
2056 /* Check the parameters */
2057 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
2058 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger));
2059
2060 __HAL_LOCK(htim);
2061
2062 if (CommutationSource == TIM_COMMUTATION_TRGI)
2063 {
2064 /* Select the Input trigger */
2065 htim->Instance->SMCR &= ~TIM_SMCR_TS;
2066 htim->Instance->SMCR |= InputTrigger;
2067 }
2068
2069 /* Select the Capture Compare preload feature */
2070 htim->Instance->CR2 |= TIM_CR2_CCPC;
2071 /* Select the Commutation event source */
2072 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
2073 htim->Instance->CR2 |= CommutationSource;
2074
2075 /* Enable the Commutation DMA Request */
2076 /* Set the DMA Commutation Callback */
2077 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
2078 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
2079 /* Set the DMA error callback */
2080 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
2081
2082 /* Disable Commutation Interrupt */
2083 __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
2084
2085 /* Enable the Commutation DMA Request */
2086 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
2087
2088 __HAL_UNLOCK(htim);
2089
2090 return HAL_OK;
2091 }
2092
2093 /**
2094 * @brief Configures the TIM in master mode.
2095 * @param htim TIM handle.
2096 * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
2097 * contains the selected trigger output (TRGO) and the Master/Slave
2098 * mode.
2099 * @retval HAL status
2100 */
HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef * htim,const TIM_MasterConfigTypeDef * sMasterConfig)2101 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
2102 const TIM_MasterConfigTypeDef *sMasterConfig)
2103 {
2104 uint32_t tmpcr2;
2105 uint32_t tmpsmcr;
2106
2107 /* Check the parameters */
2108 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
2109 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
2110 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
2111
2112 /* Check input state */
2113 __HAL_LOCK(htim);
2114
2115 /* Change the handler state */
2116 htim->State = HAL_TIM_STATE_BUSY;
2117
2118 /* Get the TIMx CR2 register value */
2119 tmpcr2 = htim->Instance->CR2;
2120
2121 /* Get the TIMx SMCR register value */
2122 tmpsmcr = htim->Instance->SMCR;
2123
2124 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
2125 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
2126 {
2127 /* Check the parameters */
2128 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
2129
2130 /* Clear the MMS2 bits */
2131 tmpcr2 &= ~TIM_CR2_MMS2;
2132 /* Select the TRGO2 source*/
2133 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
2134 }
2135
2136 /* Reset the MMS Bits */
2137 tmpcr2 &= ~TIM_CR2_MMS;
2138 /* Select the TRGO source */
2139 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
2140
2141 /* Update TIMx CR2 */
2142 htim->Instance->CR2 = tmpcr2;
2143
2144 if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
2145 {
2146 /* Reset the MSM Bit */
2147 tmpsmcr &= ~TIM_SMCR_MSM;
2148 /* Set master mode */
2149 tmpsmcr |= sMasterConfig->MasterSlaveMode;
2150
2151 /* Update TIMx SMCR */
2152 htim->Instance->SMCR = tmpsmcr;
2153 }
2154
2155 /* Change the htim state */
2156 htim->State = HAL_TIM_STATE_READY;
2157
2158 __HAL_UNLOCK(htim);
2159
2160 return HAL_OK;
2161 }
2162
2163 /**
2164 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
2165 * and the AOE(automatic output enable).
2166 * @param htim TIM handle
2167 * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
2168 * contains the BDTR Register configuration information for the TIM peripheral.
2169 * @note Interrupts can be generated when an active level is detected on the
2170 * break input, the break 2 input or the system break input. Break
2171 * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
2172 * @retval HAL status
2173 */
HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef * htim,const TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)2174 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
2175 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
2176 {
2177 /* Keep this variable initialized to 0 as it is used to configure BDTR register */
2178 uint32_t tmpbdtr = 0U;
2179
2180 /* Check the parameters */
2181 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2182 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
2183 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
2184 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
2185 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
2186 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
2187 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
2188 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
2189 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
2190 assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
2191
2192 /* Check input state */
2193 __HAL_LOCK(htim);
2194
2195 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
2196 the OSSI State, the dead time value and the Automatic Output Enable Bit */
2197
2198 /* Set the BDTR bits */
2199 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
2200 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
2201 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
2202 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
2203 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
2204 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
2205 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
2206 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
2207 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
2208
2209 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
2210 {
2211 /* Check the parameters */
2212 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
2213 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
2214 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
2215 assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
2216
2217 /* Set the BREAK2 input related BDTR bits */
2218 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
2219 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
2220 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
2221 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
2222 }
2223
2224 /* Set TIMx_BDTR */
2225 htim->Instance->BDTR = tmpbdtr;
2226
2227 __HAL_UNLOCK(htim);
2228
2229 return HAL_OK;
2230 }
2231
2232 /**
2233 * @brief Configures the break input source.
2234 * @param htim TIM handle.
2235 * @param BreakInput Break input to configure
2236 * This parameter can be one of the following values:
2237 * @arg TIM_BREAKINPUT_BRK: Timer break input
2238 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2239 * @param sBreakInputConfig Break input source configuration
2240 * @retval HAL status
2241 */
HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput,const TIMEx_BreakInputConfigTypeDef * sBreakInputConfig)2242 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
2243 uint32_t BreakInput,
2244 const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
2245 {
2246 HAL_StatusTypeDef status = HAL_OK;
2247 uint32_t tmporx;
2248 uint32_t bkin_enable_mask;
2249 uint32_t bkin_polarity_mask;
2250 uint32_t bkin_enable_bitpos;
2251 uint32_t bkin_polarity_bitpos;
2252
2253 /* Check the parameters */
2254 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2255 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2256 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
2257 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
2258 assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
2259
2260 /* Check input state */
2261 __HAL_LOCK(htim);
2262
2263 switch (sBreakInputConfig->Source)
2264 {
2265 case TIM_BREAKINPUTSOURCE_BKIN:
2266 {
2267 bkin_enable_mask = TIM_AF1_BKINE;
2268 bkin_enable_bitpos = TIM_AF1_BKINE_Pos;
2269 bkin_polarity_mask = TIM_AF1_BKINP;
2270 bkin_polarity_bitpos = TIM_AF1_BKINP_Pos;
2271 break;
2272 }
2273
2274 default:
2275 {
2276 bkin_enable_mask = 0U;
2277 bkin_polarity_mask = 0U;
2278 bkin_enable_bitpos = 0U;
2279 bkin_polarity_bitpos = 0U;
2280 break;
2281 }
2282 }
2283
2284 switch (BreakInput)
2285 {
2286 case TIM_BREAKINPUT_BRK:
2287 {
2288 /* Get the TIMx_AF1 register value */
2289 tmporx = htim->Instance->AF1;
2290
2291 /* Enable the break input */
2292 tmporx &= ~bkin_enable_mask;
2293 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2294
2295 /* Set the break input polarity */
2296 tmporx &= ~bkin_polarity_mask;
2297 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2298
2299 /* Set TIMx_AF1 */
2300 htim->Instance->AF1 = tmporx;
2301 break;
2302 }
2303 case TIM_BREAKINPUT_BRK2:
2304 {
2305 /* Get the TIMx_AF2 register value */
2306 tmporx = htim->Instance->AF2;
2307
2308 /* Enable the break input */
2309 tmporx &= ~bkin_enable_mask;
2310 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
2311
2312 /* Set the break input polarity */
2313 tmporx &= ~bkin_polarity_mask;
2314 tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
2315
2316 /* Set TIMx_AF2 */
2317 htim->Instance->AF2 = tmporx;
2318 break;
2319 }
2320 default:
2321 status = HAL_ERROR;
2322 break;
2323 }
2324
2325 __HAL_UNLOCK(htim);
2326
2327 return status;
2328 }
2329
2330 /**
2331 * @brief Configures the TIMx Remapping input capabilities.
2332 * @param htim TIM handle.
2333 * @param Remap specifies the TIM remapping source.
2334 * For TIM1, the parameter can take one of the following values:
2335 * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO
2336 * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1
2337 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2
2338 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3
2339 * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1 ETR is connected to ADC2 AWD1
2340 * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1 ETR is connected to ADC2 AWD2
2341 * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1 ETR is connected to ADC2 AWD3
2342 *
2343 * For TIM2, the parameter can take one of the following values:
2344 * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO
2345 * @arg TIM_TIM2_ETR_DCMIPP_HSYNC TIM2 ETR is connected to DCMIPP HSYNC pin
2346 * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2 ETR is connected to LTDC HSYNC pin
2347 * @arg TIM_TIM2_ETR_SAI1_FSA TIM2_ETR is connected to SAI1 FS_A
2348 * @arg TIM_TIM2_ETR_SAI1_FSB TIM2_ETR is connected to SAI1 FS_B
2349 * @arg TIM_TIM2_ETR_GFXTIM_TE TIM2_ETR is connected to GFXTIM TE
2350 * @arg TIM_TIM2_ETR_DCMIPP_HSYNC TIM2 ETR is connected to DCMIPP HSYNC pin
2351 * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2 ETR is connected to LTDC HSYNC pin
2352 * @arg TIM_TIM3_ETR_TIM3_ETR TIM3_ETR is connected to TIM3 ETR
2353 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR
2354 * @arg TIM_TIM3_ETR_TIM5_ETR TIM3_ETR is connected to TIM5 ETR
2355 * @arg TIM_TIM2_ETR_ETH_PPS TIM2_ETR is connected to ETH PPS
2356 *
2357 * For TIM3, the parameter can take one of the following values:
2358 * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is not connected to I/O
2359 * @arg TIM_TIM3_ETR_DCMIPP_HSYNC TIM3_ETR is connected to DCMIPP HSYNC
2360 * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC
2361 * @arg TIM_TIM3_ETR_GFXTIM_TE TIM3_ETR is connected to GFXTIM TE
2362 * @arg TIM_TIM3_ETR_DCMIPP_HSYNC TIM3_ETR is connected to DCMIPP VSYNC
2363 * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC VSYNC
2364 * @arg TIM_TIM3_ETR_TIM2_ETR TIM3_ETR is connected to TIM2 ETR
2365 * @arg TIM_TIM3_ETR_TIM4_ETR TIM3_ETR is connected to TIM4 ETR
2366 * @arg TIM_TIM3_ETR_TIM5_ETR TIM3_ETR is connected to TIM5 ETR
2367 * @arg TIM_TIM3_ETR_ETH_PPS TIM3_ETR is connected to ETH PPS
2368 *
2369 * For TIM4, the parameter can take one of the following values:
2370 * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO
2371 * @arg TIM_TIM4_ETR_DCMIPP_HSYNC TIM4_ETR is connected to DCMIPP HSYNC
2372 * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC
2373 * @arg TIM_TIM4_ETR_GFXTIM_TE TIM4_ETR is connected to GFXTIM TE
2374 * @arg TIM_TIM4_ETR_DCMIPP_HSYNC TIM4_ETR is connected to DCMIPP VSYNC
2375 * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC VSYNC
2376 * @arg TIM_TIM4_ETR_TIM2_ETR TIM4_ETR is connected to TIM2 ETR
2377 * @arg TIM_TIM4_ETR_TIM3_ETR TIM4_ETR is connected to TIM3 ETR
2378 * @arg TIM_TIM4_ETR_TIM5_ETR TIM4_ETR is connected to TIM5 ETR
2379 * @arg TIM_TIM4_ETR_ETH1_PPS TIM4_ETR is connected to ETH1 PPS
2380 *
2381 * For TIM5, the parameter can take one of the following values:
2382 * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO
2383 * @arg TIM_TIM5_ETR_SAI2_FSA TIM5_ETR is connected to SAI2 FS_A
2384 * @arg TIM_TIM5_ETR_SAI2_FSB TIM5_ETR is connected to SAI2 FS_B
2385 * @arg TIM_TIM5_ETR_DCMIPP_HSYNC TIM5_ETR is connected to DCMIPP HSYNC
2386 * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC
2387 * @arg TIM_TIM5_ETR_GFXTIM_TE TIM5_ETR is connected to GFXTIM TE
2388 * @arg TIM_TIM5_ETR_DCMIPP_HSYNC TIM5_ETR is connected to DCMIPP VSYNC
2389 * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC VSYNC
2390 * @arg TIM_TIM5_ETR_TIM2_ETR TIM5_ETR is connected to TIM2 ETR
2391 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5_ETR is connected to TIM3 ETR
2392 * @arg TIM_TIM5_ETR_TIM3_ETR TIM5_ETR is connected to TIM4 ETR
2393 *
2394 * @retval HAL status
2395 */
HAL_TIMEx_RemapConfig(TIM_HandleTypeDef * htim,uint32_t Remap)2396 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
2397 {
2398 /* Check parameters */
2399 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
2400 assert_param(IS_TIM_REMAP(htim->Instance, Remap));
2401
2402 __HAL_LOCK(htim);
2403
2404 MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap);
2405
2406 __HAL_UNLOCK(htim);
2407
2408 return HAL_OK;
2409 }
2410
2411 /**
2412 * @brief Select the timer input source
2413 * @param htim TIM handle.
2414 * @param Channel specifies the TIM Channel
2415 * This parameter can be one of the following values:
2416 * @arg TIM_CHANNEL_1: TI1 input channel
2417 * @arg TIM_CHANNEL_2: TI2 input channel
2418 * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows:
2419 * For TIM2, the parameter is one of the following values:
2420 * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO
2421 * @arg TIM_TIM2_TI1_ETH_PPS: TIM2 TI1 is connected to ETH PPS
2422 *
2423 * For TIM3, the parameter is one of the following values:
2424 * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO
2425 * @arg TIM_TIM3_TI1_ETH_PPS: TIM3 TI1 is connected to ETH PPS
2426 *
2427 * For TIM9, the parameter is one of the following values:
2428 * @arg TIM_TIM9_TI1_GPIO: TIM9 TI1 is connected to GPIO
2429 * @arg TIM_TIM9_TI1_MCO1: TIM9 TI1 is connected to MCO1
2430 * @arg TIM_TIM9_TI1_MCO2: TIM9 TI1 is connected to MCO2
2431 *
2432 * For TIM12, the parameter is one of the following values:
2433 * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
2434 * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
2435 * @arg TIM_TIM12_TI1_HSI_1024: TIM12 TI1 is connected to HSI/1024
2436 * @arg TIM_TIM12_TI1_CSI_128: TIM12_TI1 is connected to CSI/128
2437 * @arg TIM_TIM12_TI1_MCO1: TIM12 TI1 is connected to MCO1
2438 * @arg TIM_TIM12_TI1_MCO2: TIM12 TI1 is connected to MCO2
2439 *
2440 * For TIM15, the parameter is one of the following values:
2441 * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
2442 * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1
2443 * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1
2444 * @arg TIM_TIM15_TI1_TIM4_CH1: TIM15 TI1 is connected to TIM4 CH1
2445 * @arg TIM_TIM15_TI1_MCO1: TIM15 TI1 is connected to MCO1
2446 * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
2447 * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
2448 * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2
2449 * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2
2450 * @arg TIM_TIM15_TI2_TIM4_CH2: TIM15 TI2 is connected to TIM4 CH2
2451 *
2452 * For TIM16, the parameter is one of the following values:
2453 * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
2454 * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt
2455 *
2456 * For TIM17, the parameter is one of the following values:
2457 * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
2458 * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS
2459 * @retval HAL status
2460 */
HAL_TIMEx_TISelection(TIM_HandleTypeDef * htim,uint32_t TISelection,uint32_t Channel)2461 HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel)
2462 {
2463 HAL_StatusTypeDef status = HAL_OK;
2464
2465 /* Check parameters */
2466 assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel));
2467 assert_param(IS_TIM_TISEL(TISelection));
2468
2469 __HAL_LOCK(htim);
2470
2471 switch (Channel)
2472 {
2473 case TIM_CHANNEL_1:
2474 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection);
2475 break;
2476 case TIM_CHANNEL_2:
2477 MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection);
2478 break;
2479 default:
2480 status = HAL_ERROR;
2481 break;
2482 }
2483
2484 __HAL_UNLOCK(htim);
2485
2486 return status;
2487 }
2488
2489 /**
2490 * @brief Group channel 5 and channel 1, 2 or 3
2491 * @param htim TIM handle.
2492 * @param Channels specifies the reference signal(s) the OC5REF is combined with.
2493 * This parameter can be any combination of the following values:
2494 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
2495 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
2496 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
2497 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
2498 * @retval HAL status
2499 */
HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef * htim,uint32_t Channels)2500 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
2501 {
2502 /* Check parameters */
2503 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
2504 assert_param(IS_TIM_GROUPCH5(Channels));
2505
2506 /* Process Locked */
2507 __HAL_LOCK(htim);
2508
2509 htim->State = HAL_TIM_STATE_BUSY;
2510
2511 /* Clear GC5Cx bit fields */
2512 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1);
2513
2514 /* Set GC5Cx bit fields */
2515 htim->Instance->CCR5 |= Channels;
2516
2517 /* Change the htim state */
2518 htim->State = HAL_TIM_STATE_READY;
2519
2520 __HAL_UNLOCK(htim);
2521
2522 return HAL_OK;
2523 }
2524
2525 /**
2526 * @brief Disarm the designated break input (when it operates in bidirectional mode).
2527 * @param htim TIM handle.
2528 * @param BreakInput Break input to disarm
2529 * This parameter can be one of the following values:
2530 * @arg TIM_BREAKINPUT_BRK: Timer break input
2531 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2532 * @note The break input can be disarmed only when it is configured in
2533 * bidirectional mode and when when MOE is reset.
2534 * @note Purpose is to be able to have the input voltage back to high-state,
2535 * whatever the time constant on the output .
2536 * @retval HAL status
2537 */
HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef * htim,uint32_t BreakInput)2538 HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
2539 {
2540 HAL_StatusTypeDef status = HAL_OK;
2541 uint32_t tmpbdtr;
2542
2543 /* Check the parameters */
2544 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2545 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2546
2547 switch (BreakInput)
2548 {
2549 case TIM_BREAKINPUT_BRK:
2550 {
2551 /* Check initial conditions */
2552 tmpbdtr = READ_REG(htim->Instance->BDTR);
2553 if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
2554 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2555 {
2556 /* Break input BRK is disarmed */
2557 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
2558 }
2559 break;
2560 }
2561 case TIM_BREAKINPUT_BRK2:
2562 {
2563 /* Check initial conditions */
2564 tmpbdtr = READ_REG(htim->Instance->BDTR);
2565 if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
2566 (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
2567 {
2568 /* Break input BRK is disarmed */
2569 SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
2570 }
2571 break;
2572 }
2573 default:
2574 status = HAL_ERROR;
2575 break;
2576 }
2577
2578 return status;
2579 }
2580
2581 /**
2582 * @brief Arm the designated break input (when it operates in bidirectional mode).
2583 * @param htim TIM handle.
2584 * @param BreakInput Break input to arm
2585 * This parameter can be one of the following values:
2586 * @arg TIM_BREAKINPUT_BRK: Timer break input
2587 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
2588 * @note Arming is possible at anytime, even if fault is present.
2589 * @note Break input is automatically armed as soon as MOE bit is set.
2590 * @retval HAL status
2591 */
HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef * htim,uint32_t BreakInput)2592 HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
2593 {
2594 HAL_StatusTypeDef status = HAL_OK;
2595 uint32_t tickstart;
2596
2597 /* Check the parameters */
2598 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2599 assert_param(IS_TIM_BREAKINPUT(BreakInput));
2600
2601 switch (BreakInput)
2602 {
2603 case TIM_BREAKINPUT_BRK:
2604 {
2605 /* Check initial conditions */
2606 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
2607 {
2608 /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2609 /* Init tickstart for timeout management */
2610 tickstart = HAL_GetTick();
2611 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2612 {
2613 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2614 {
2615 /* New check to avoid false timeout detection in case of preemption */
2616 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
2617 {
2618 return HAL_TIMEOUT;
2619 }
2620 }
2621 }
2622 }
2623 break;
2624 }
2625
2626 case TIM_BREAKINPUT_BRK2:
2627 {
2628 /* Check initial conditions */
2629 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
2630 {
2631 /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
2632 /* Init tickstart for timeout management */
2633 tickstart = HAL_GetTick();
2634 while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2635 {
2636 if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
2637 {
2638 /* New check to avoid false timeout detection in case of preemption */
2639 if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
2640 {
2641 return HAL_TIMEOUT;
2642 }
2643 }
2644 }
2645 }
2646 break;
2647 }
2648 default:
2649 status = HAL_ERROR;
2650 break;
2651 }
2652
2653 return status;
2654 }
2655
2656 /**
2657 * @brief Enable dithering
2658 * @param htim TIM handle
2659 * @note Main usage is PWM mode
2660 * @note This function must be called when timer is stopped or disabled (CEN =0)
2661 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2662 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2663 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2664 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2665 * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers
2666 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2667 * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER()
2668 * can be used to calculate period (ARR) and delay (CCRx) value.
2669 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2670 * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2671 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2672 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2673 * @retval HAL status
2674 */
HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef * htim)2675 HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim)
2676 {
2677 /* Check the parameters */
2678 assert_param(IS_TIM_INSTANCE(htim->Instance));
2679
2680 SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2681 return HAL_OK;
2682 }
2683
2684 /**
2685 * @brief Disable dithering
2686 * @param htim TIM handle
2687 * @note This function must be called when timer is stopped or disabled (CEN =0)
2688 * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation:
2689 * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers)
2690 * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers
2691 * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers
2692 * - ARR and CCRx values are limited to 0xFFEF in dithering mode
2693 * (corresponds to 4094 for the integer part and 15 for the dithered part).
2694 * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part.
2695 * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD()
2696 * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period .
2697 * @retval HAL status
2698 */
HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef * htim)2699 HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim)
2700 {
2701 /* Check the parameters */
2702 assert_param(IS_TIM_INSTANCE(htim->Instance));
2703
2704 CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN);
2705 return HAL_OK;
2706 }
2707
2708 /**
2709 * @brief Initializes the pulse on compare pulse width and pulse prescaler
2710 * @param htim TIM Output Compare handle
2711 * @param PulseWidthPrescaler Pulse width prescaler
2712 * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7
2713 * @param PulseWidth Pulse width
2714 * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2715 * @retval HAL status
2716 */
HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef * htim,uint32_t PulseWidthPrescaler,uint32_t PulseWidth)2717 HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim,
2718 uint32_t PulseWidthPrescaler,
2719 uint32_t PulseWidth)
2720 {
2721 uint32_t tmpecr;
2722
2723 /* Check the parameters */
2724 assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance));
2725 assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth));
2726 assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler));
2727
2728 /* Process Locked */
2729 __HAL_LOCK(htim);
2730
2731 /* Set the TIM state */
2732 htim->State = HAL_TIM_STATE_BUSY;
2733
2734 /* Get the TIMx ECR register value */
2735 tmpecr = htim->Instance->ECR;
2736 /* Reset the Pulse width prescaler and the Pulse width */
2737 tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW);
2738 /* Set the Pulse width prescaler and Pulse width*/
2739 tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos;
2740 tmpecr |= PulseWidth << TIM_ECR_PW_Pos;
2741 /* Write to TIMx ECR */
2742 htim->Instance->ECR = tmpecr;
2743
2744 /* Change the TIM state */
2745 htim->State = HAL_TIM_STATE_READY;
2746
2747 /* Release Lock */
2748 __HAL_UNLOCK(htim);
2749
2750 return HAL_OK;
2751 }
2752
2753 /**
2754 * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register)
2755 * @param htim TIM handle
2756 * @param Source Source of slave mode selection preload
2757 * This parameter can be one of the following values:
2758 * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload
2759 * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload
2760 * @retval HAL status
2761 */
HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef * htim,uint32_t Source)2762 HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source)
2763 {
2764 /* Check the parameters */
2765 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2766 assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source));
2767
2768 MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source);
2769 return HAL_OK;
2770 }
2771
2772 /**
2773 * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2774 * @param htim TIM handle
2775 * @retval HAL status
2776 */
HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef * htim)2777 HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim)
2778 {
2779 /* Check the parameters */
2780 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2781
2782 SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2783 return HAL_OK;
2784 }
2785
2786 /**
2787 * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register)
2788 * @param htim TIM handle
2789 * @retval HAL status
2790 */
HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef * htim)2791 HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim)
2792 {
2793 /* Check the parameters */
2794 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
2795
2796 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE);
2797 return HAL_OK;
2798 }
2799
2800 /**
2801 * @brief Enable deadtime preload
2802 * @param htim TIM handle
2803 * @retval HAL status
2804 */
HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef * htim)2805 HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim)
2806 {
2807 /* Check the parameters */
2808 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2809
2810 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2811 return HAL_OK;
2812 }
2813
2814 /**
2815 * @brief Disable deadtime preload
2816 * @param htim TIM handle
2817 * @retval HAL status
2818 */
HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef * htim)2819 HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim)
2820 {
2821 /* Check the parameters */
2822 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2823
2824 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE);
2825 return HAL_OK;
2826 }
2827
2828 /**
2829 * @brief Configure deadtime
2830 * @param htim TIM handle
2831 * @param Deadtime Deadtime value
2832 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2833 * @retval HAL status
2834 */
HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef * htim,uint32_t Deadtime)2835 HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime)
2836 {
2837 /* Check the parameters */
2838 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2839 assert_param(IS_TIM_DEADTIME(Deadtime));
2840
2841 MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime);
2842 return HAL_OK;
2843 }
2844
2845 /**
2846 * @brief Configure asymmetrical deadtime
2847 * @param htim TIM handle
2848 * @param FallingDeadtime Falling edge deadtime value
2849 * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF
2850 * @retval HAL status
2851 */
HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef * htim,uint32_t FallingDeadtime)2852 HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime)
2853 {
2854 /* Check the parameters */
2855 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2856 assert_param(IS_TIM_DEADTIME(FallingDeadtime));
2857
2858 MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime);
2859 return HAL_OK;
2860 }
2861
2862 /**
2863 * @brief Enable asymmetrical deadtime
2864 * @param htim TIM handle
2865 * @retval HAL status
2866 */
HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)2867 HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
2868 {
2869 /* Check the parameters */
2870 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2871
2872 SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
2873 return HAL_OK;
2874 }
2875
2876 /**
2877 * @brief Disable asymmetrical deadtime
2878 * @param htim TIM handle
2879 * @retval HAL status
2880 */
HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef * htim)2881 HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim)
2882 {
2883 /* Check the parameters */
2884 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
2885
2886 CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE);
2887 return HAL_OK;
2888 }
2889
2890 /**
2891 * @brief Configures the encoder index.
2892 * @note warning in case of encoder mode clock plus direction
2893 * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
2894 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN
2895 * @param htim TIM handle.
2896 * @param sEncoderIndexConfig Encoder index configuration
2897 * @retval HAL status
2898 */
HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef * htim,TIMEx_EncoderIndexConfigTypeDef * sEncoderIndexConfig)2899 HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
2900 TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig)
2901 {
2902 /* Check the parameters */
2903 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2904 assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity));
2905 assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler));
2906 assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter));
2907 assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking));
2908 assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable));
2909 assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position));
2910 assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction));
2911
2912 /* Process Locked */
2913 __HAL_LOCK(htim);
2914
2915 /* Configures the TIMx External Trigger (ETR) which is used as Index input */
2916 TIM_ETR_SetConfig(htim->Instance,
2917 sEncoderIndexConfig->Prescaler,
2918 sEncoderIndexConfig->Polarity,
2919 sEncoderIndexConfig->Filter);
2920
2921 /* Configures the encoder index */
2922 MODIFY_REG(htim->Instance->ECR,
2923 TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk,
2924 (sEncoderIndexConfig->Direction |
2925 (sEncoderIndexConfig->Blanking) |
2926 ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) |
2927 sEncoderIndexConfig->Position |
2928 TIM_ECR_IE));
2929
2930 __HAL_UNLOCK(htim);
2931
2932 return HAL_OK;
2933 }
2934
2935 /**
2936 * @brief Enable encoder index
2937 * @param htim TIM handle
2938 * @retval HAL status
2939 */
HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef * htim)2940 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim)
2941 {
2942 /* Check the parameters */
2943 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2944
2945 SET_BIT(htim->Instance->ECR, TIM_ECR_IE);
2946 return HAL_OK;
2947 }
2948
2949 /**
2950 * @brief Disable encoder index
2951 * @param htim TIM handle
2952 * @retval HAL status
2953 */
HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef * htim)2954 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim)
2955 {
2956 /* Check the parameters */
2957 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2958
2959 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE);
2960 return HAL_OK;
2961 }
2962
2963 /**
2964 * @brief Enable encoder first index
2965 * @param htim TIM handle
2966 * @retval HAL status
2967 */
HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef * htim)2968 HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim)
2969 {
2970 /* Check the parameters */
2971 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2972
2973 SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
2974 return HAL_OK;
2975 }
2976
2977 /**
2978 * @brief Disable encoder first index
2979 * @param htim TIM handle
2980 * @retval HAL status
2981 */
HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef * htim)2982 HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim)
2983 {
2984 /* Check the parameters */
2985 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2986
2987 CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX);
2988 return HAL_OK;
2989 }
2990
2991 /**
2992 * @}
2993 */
2994
2995 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
2996 * @brief Extended Callbacks functions
2997 *
2998 @verbatim
2999 ==============================================================================
3000 ##### Extended Callbacks functions #####
3001 ==============================================================================
3002 [..]
3003 This section provides Extended TIM callback functions:
3004 (+) Timer Commutation callback
3005 (+) Timer Break callback
3006
3007 @endverbatim
3008 * @{
3009 */
3010
3011 /**
3012 * @brief Commutation callback in non-blocking mode
3013 * @param htim TIM handle
3014 * @retval None
3015 */
HAL_TIMEx_CommutCallback(TIM_HandleTypeDef * htim)3016 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
3017 {
3018 /* Prevent unused argument(s) compilation warning */
3019 UNUSED(htim);
3020
3021 /* NOTE : This function should not be modified, when the callback is needed,
3022 the HAL_TIMEx_CommutCallback could be implemented in the user file
3023 */
3024 }
3025 /**
3026 * @brief Commutation half complete callback in non-blocking mode
3027 * @param htim TIM handle
3028 * @retval None
3029 */
HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef * htim)3030 __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
3031 {
3032 /* Prevent unused argument(s) compilation warning */
3033 UNUSED(htim);
3034
3035 /* NOTE : This function should not be modified, when the callback is needed,
3036 the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
3037 */
3038 }
3039
3040 /**
3041 * @brief Break detection callback in non-blocking mode
3042 * @param htim TIM handle
3043 * @retval None
3044 */
HAL_TIMEx_BreakCallback(TIM_HandleTypeDef * htim)3045 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
3046 {
3047 /* Prevent unused argument(s) compilation warning */
3048 UNUSED(htim);
3049
3050 /* NOTE : This function should not be modified, when the callback is needed,
3051 the HAL_TIMEx_BreakCallback could be implemented in the user file
3052 */
3053 }
3054
3055 /**
3056 * @brief Break2 detection callback in non blocking mode
3057 * @param htim: TIM handle
3058 * @retval None
3059 */
HAL_TIMEx_Break2Callback(TIM_HandleTypeDef * htim)3060 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
3061 {
3062 /* Prevent unused argument(s) compilation warning */
3063 UNUSED(htim);
3064
3065 /* NOTE : This function Should not be modified, when the callback is needed,
3066 the HAL_TIMEx_Break2Callback could be implemented in the user file
3067 */
3068 }
3069
3070 /**
3071 * @brief Encoder index callback in non-blocking mode
3072 * @param htim TIM handle
3073 * @retval None
3074 */
HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef * htim)3075 __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
3076 {
3077 /* Prevent unused argument(s) compilation warning */
3078 UNUSED(htim);
3079
3080 /* NOTE : This function should not be modified, when the callback is needed,
3081 the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
3082 */
3083 }
3084
3085 /**
3086 * @brief Direction change callback in non-blocking mode
3087 * @param htim TIM handle
3088 * @retval None
3089 */
HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef * htim)3090 __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
3091 {
3092 /* Prevent unused argument(s) compilation warning */
3093 UNUSED(htim);
3094
3095 /* NOTE : This function should not be modified, when the callback is needed,
3096 the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
3097 */
3098 }
3099
3100 /**
3101 * @brief Index error callback in non-blocking mode
3102 * @param htim TIM handle
3103 * @retval None
3104 */
HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef * htim)3105 __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
3106 {
3107 /* Prevent unused argument(s) compilation warning */
3108 UNUSED(htim);
3109
3110 /* NOTE : This function should not be modified, when the callback is needed,
3111 the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
3112 */
3113 }
3114
3115 /**
3116 * @brief Transition error callback in non-blocking mode
3117 * @param htim TIM handle
3118 * @retval None
3119 */
HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef * htim)3120 __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
3121 {
3122 /* Prevent unused argument(s) compilation warning */
3123 UNUSED(htim);
3124
3125 /* NOTE : This function should not be modified, when the callback is needed,
3126 the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
3127 */
3128 }
3129
3130 /**
3131 * @}
3132 */
3133
3134 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
3135 * @brief Extended Peripheral State functions
3136 *
3137 @verbatim
3138 ==============================================================================
3139 ##### Extended Peripheral State functions #####
3140 ==============================================================================
3141 [..]
3142 This subsection permits to get in run-time the status of the peripheral
3143 and the data flow.
3144
3145 @endverbatim
3146 * @{
3147 */
3148
3149 /**
3150 * @brief Return the TIM Hall Sensor interface handle state.
3151 * @param htim TIM Hall Sensor handle
3152 * @retval HAL state
3153 */
HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef * htim)3154 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
3155 {
3156 return htim->State;
3157 }
3158
3159 /**
3160 * @brief Return actual state of the TIM complementary channel.
3161 * @param htim TIM handle
3162 * @param ChannelN TIM Complementary channel
3163 * This parameter can be one of the following values:
3164 * @arg TIM_CHANNEL_1: TIM Channel 1
3165 * @arg TIM_CHANNEL_2: TIM Channel 2
3166 * @arg TIM_CHANNEL_3: TIM Channel 3
3167 * @arg TIM_CHANNEL_4: TIM Channel 4
3168 * @retval TIM Complementary channel state
3169 */
HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef * htim,uint32_t ChannelN)3170 HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN)
3171 {
3172 HAL_TIM_ChannelStateTypeDef channel_state;
3173
3174 /* Check the parameters */
3175 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
3176
3177 channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
3178
3179 return channel_state;
3180 }
3181 /**
3182 * @}
3183 */
3184
3185 /**
3186 * @}
3187 */
3188
3189 /* Private functions ---------------------------------------------------------*/
3190 /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
3191 * @{
3192 */
3193
3194 /**
3195 * @brief TIM DMA Commutation callback.
3196 * @param hdma pointer to DMA handle.
3197 * @retval None
3198 */
TIMEx_DMACommutationCplt(DMA_HandleTypeDef * hdma)3199 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
3200 {
3201 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3202
3203 /* Change the htim state */
3204 htim->State = HAL_TIM_STATE_READY;
3205
3206 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3207 htim->CommutationCallback(htim);
3208 #else
3209 HAL_TIMEx_CommutCallback(htim);
3210 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3211 }
3212
3213 /**
3214 * @brief TIM DMA Commutation half complete callback.
3215 * @param hdma pointer to DMA handle.
3216 * @retval None
3217 */
TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef * hdma)3218 void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
3219 {
3220 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3221
3222 /* Change the htim state */
3223 htim->State = HAL_TIM_STATE_READY;
3224
3225 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3226 htim->CommutationHalfCpltCallback(htim);
3227 #else
3228 HAL_TIMEx_CommutHalfCpltCallback(htim);
3229 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3230 }
3231
3232
3233 /**
3234 * @brief TIM DMA Delay Pulse complete callback (complementary channel).
3235 * @param hdma pointer to DMA handle.
3236 * @retval None
3237 */
TIM_DMADelayPulseNCplt(DMA_HandleTypeDef * hdma)3238 static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
3239 {
3240 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3241
3242 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3243 {
3244 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3245 }
3246 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3247 {
3248 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3249 }
3250 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3251 {
3252 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3253 }
3254 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3255 {
3256 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3257 }
3258 else
3259 {
3260 /* nothing to do */
3261 }
3262
3263 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3264 htim->PWM_PulseFinishedCallback(htim);
3265 #else
3266 HAL_TIM_PWM_PulseFinishedCallback(htim);
3267 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3268
3269 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3270 }
3271
3272 /**
3273 * @brief TIM DMA error callback (complementary channel)
3274 * @param hdma pointer to DMA handle.
3275 * @retval None
3276 */
TIM_DMAErrorCCxN(DMA_HandleTypeDef * hdma)3277 static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
3278 {
3279 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3280
3281 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
3282 {
3283 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3284 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3285 }
3286 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
3287 {
3288 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3289 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3290 }
3291 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
3292 {
3293 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3294 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
3295 }
3296 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
3297 {
3298 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3299 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
3300 }
3301 else
3302 {
3303 /* nothing to do */
3304 }
3305
3306 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3307 htim->ErrorCallback(htim);
3308 #else
3309 HAL_TIM_ErrorCallback(htim);
3310 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3311
3312 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3313 }
3314
3315 /**
3316 * @brief Enables or disables the TIM Capture Compare Channel xN.
3317 * @param TIMx to select the TIM peripheral
3318 * @param Channel specifies the TIM Channel
3319 * This parameter can be one of the following values:
3320 * @arg TIM_CHANNEL_1: TIM Channel 1
3321 * @arg TIM_CHANNEL_2: TIM Channel 2
3322 * @arg TIM_CHANNEL_3: TIM Channel 3
3323 * @arg TIM_CHANNEL_4: TIM Channel 4
3324 * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
3325 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
3326 * @retval None
3327 */
TIM_CCxNChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelNState)3328 static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
3329 {
3330 uint32_t tmp;
3331
3332 tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
3333
3334 /* Reset the CCxNE Bit */
3335 TIMx->CCER &= ~tmp;
3336
3337 /* Set or reset the CCxNE Bit */
3338 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
3339 }
3340 /**
3341 * @}
3342 */
3343
3344 #endif /* HAL_TIM_MODULE_ENABLED */
3345 /**
3346 * @}
3347 */
3348
3349 /**
3350 * @}
3351 */
3352
