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Searched refs:MDIER (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_hrtim.h8596 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_EnableIT_SYNC()
8607 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_DisableIT_SYNC()
8618 …return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : … in LL_HRTIM_IsEnabledIT_SYNC()
8638 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_UPDATE()
8660 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_UPDATE()
8682 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_UPDATE()
8705 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_REP()
8727 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_REP()
8749 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_REP()
8772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_CMP1()
[all …]
Dstm32h7xx_hal_hrtim.h2856 …AL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \
2858 …HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \
2914 …_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\
3017 …M_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
3018 …M_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_hrtim.h8721 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_EnableIT_SYNC()
8732 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_DisableIT_SYNC()
8743 …return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : … in LL_HRTIM_IsEnabledIT_SYNC()
8763 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_UPDATE()
8785 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_UPDATE()
8807 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_UPDATE()
8830 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_REP()
8852 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_REP()
8874 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_REP()
8897 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_CMP1()
[all …]
Dstm32f3xx_hal_hrtim.h2889 …ABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
2890 …ISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__…
2945 …TUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__))…
3045 …M_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
3046 …M_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_hrtim.h11942 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_EnableIT_SYNC()
11953 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); in LL_HRTIM_DisableIT_SYNC()
11964 …return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : … in LL_HRTIM_IsEnabledIT_SYNC()
11985 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_UPDATE()
12008 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_UPDATE()
12031 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_UPDATE()
12055 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_REP()
12078 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_DisableIT_REP()
12101 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_IsEnabledIT_REP()
12125 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + in LL_HRTIM_EnableIT_CMP1()
[all …]
Dstm32g4xx_hal_hrtim.h4197 …AL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \
4199 …HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \
4257 …_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\
4362 …M_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
4363 …M_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_hrtim.c8651 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); in HRTIM_Master_ISR()
9034 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9042 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9050 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9058 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9066 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9074 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9082 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_hal_hrtim.c8820 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); in HRTIM_Master_ISR()
9225 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9233 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9241 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9249 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9257 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9265 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
9273 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_hrtim.c10430 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); in HRTIM_Master_ISR()
10836 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10844 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10852 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10860 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10868 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10876 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
10884 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET) in HRTIM_DMAMasterCplt()
/hal_stm32-latest/stm32cube/stm32f3xx/soc/
Dstm32f334x8.h427 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g414xx.h886 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32g474xx.h1029 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32g484xx.h1061 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h742xx.h1582 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h750xx.h1739 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h753xx.h1739 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h745xx.h1744 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h745xg.h1744 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h743xx.h1669 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h755xx.h1814 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h757xx.h1895 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h747xg.h1825 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member
Dstm32h747xx.h1825 …__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Addres… member