1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_HRTIM_H
21 #define STM32H7xx_LL_HRTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (HRTIM1)
35
36 /** @defgroup HRTIM_LL HRTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
43 * @{
44 */
45 static const uint16_t REG_OFFSET_TAB_TIMER[] =
46 {
47 0x00U, /* 0: MASTER */
48 0x80U, /* 1: TIMER A */
49 0x100U, /* 2: TIMER B */
50 0x180U, /* 3: TIMER C */
51 0x200U, /* 4: TIMER D */
52 0x280U /* 5: TIMER E */
53 };
54
55 static const uint8_t REG_OFFSET_TAB_ADCxR[] =
56 {
57 0x00U, /* 0: HRTIM_ADC1R */
58 0x04U, /* 1: HRTIM_ADC2R */
59 0x08U, /* 2: HRTIM_ADC3R */
60 0x0CU, /* 3: HRTIM_ADC4R */
61 };
62
63 static const uint16_t REG_OFFSET_TAB_SETxR[] =
64 {
65 0x00U, /* 0: TA1 */
66 0x08U, /* 1: TA2 */
67 0x80U, /* 2: TB1 */
68 0x88U, /* 3: TB2 */
69 0x100U, /* 4: TC1 */
70 0x108U, /* 5: TC2 */
71 0x180U, /* 6: TD1 */
72 0x188U, /* 7: TD2 */
73 0x200U, /* 8: TE1 */
74 0x208U /* 9: TE2 */
75 };
76
77 static const uint16_t REG_OFFSET_TAB_OUTxR[] =
78 {
79 0x00U, /* 0: TA1 */
80 0x00U, /* 1: TA2 */
81 0x80U, /* 2: TB1 */
82 0x80U, /* 3: TB2 */
83 0x100U, /* 4: TC1 */
84 0x100U, /* 5: TC2 */
85 0x180U, /* 6: TD1 */
86 0x180U, /* 7: TD2 */
87 0x200U, /* 8: TE1 */
88 0x200U /* 9: TE2 */
89 };
90
91 static const uint8_t REG_OFFSET_TAB_EECR[] =
92 {
93 0x00U, /* LL_HRTIM_EVENT_1 */
94 0x00U, /* LL_HRTIM_EVENT_2 */
95 0x00U, /* LL_HRTIM_EVENT_3 */
96 0x00U, /* LL_HRTIM_EVENT_4 */
97 0x00U, /* LL_HRTIM_EVENT_5 */
98 0x04U, /* LL_HRTIM_EVENT_6 */
99 0x04U, /* LL_HRTIM_EVENT_7 */
100 0x04U, /* LL_HRTIM_EVENT_8 */
101 0x04U, /* LL_HRTIM_EVENT_9 */
102 0x04U /* LL_HRTIM_EVENT_10 */
103 };
104
105 static const uint8_t REG_OFFSET_TAB_FLTINR[] =
106 {
107 0x00U, /* LL_HRTIM_FAULT_1 */
108 0x00U, /* LL_HRTIM_FAULT_2 */
109 0x00U, /* LL_HRTIM_FAULT_3 */
110 0x00U, /* LL_HRTIM_FAULT_4 */
111 0x04U /* LL_HRTIM_FAULT_5 */
112 };
113
114 static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
115 {
116 0x20000000U, /* 0: MASTER */
117 0x01FE0000U, /* 1: TIMER A */
118 0x01FE0000U, /* 2: TIMER B */
119 0x01FE0000U, /* 3: TIMER C */
120 0x01FE0000U, /* 4: TIMER D */
121 0x01FE0000U /* 5: TIMER E */
122 };
123
124 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
125 {
126 12U, /* 0: MASTER */
127 0U, /* 1: TIMER A */
128 0U, /* 2: TIMER B */
129 0U, /* 3: TIMER C */
130 0U, /* 4: TIMER D */
131 0U /* 5: TIMER E */
132 };
133
134 static const uint8_t REG_SHIFT_TAB_EExSRC[] =
135 {
136 0U, /* LL_HRTIM_EVENT_1 */
137 6U, /* LL_HRTIM_EVENT_2 */
138 12U, /* LL_HRTIM_EVENT_3 */
139 18U, /* LL_HRTIM_EVENT_4 */
140 24U, /* LL_HRTIM_EVENT_5 */
141 0U, /* LL_HRTIM_EVENT_6 */
142 6U, /* LL_HRTIM_EVENT_7 */
143 12U, /* LL_HRTIM_EVENT_8 */
144 18U, /* LL_HRTIM_EVENT_9 */
145 24U /* LL_HRTIM_EVENT_10 */
146 };
147
148 static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
149 {
150 HRTIM_MCR_BRSTDMA, /* 0: MASTER */
151 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
152 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
153 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
154 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
155 HRTIM_TIMCR_UPDGAT /* 5: TIMER E */
156 };
157
158 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
159 {
160 2U, /* 0: MASTER */
161 0U, /* 1: TIMER A */
162 0U, /* 2: TIMER B */
163 0U, /* 3: TIMER C */
164 0U, /* 4: TIMER D */
165 0U /* 5: TIMER E */
166 };
167
168 static const uint8_t REG_SHIFT_TAB_OUTxR[] =
169 {
170 0U, /* 0: TA1 */
171 16U, /* 1: TA2 */
172 0U, /* 2: TB1 */
173 16U, /* 3: TB2 */
174 0U, /* 4: TC1 */
175 16U, /* 5: TC2 */
176 0U, /* 6: TD1 */
177 16U, /* 7: TD2 */
178 0U, /* 8: TE1 */
179 16U /* 9: TE2 */
180 };
181
182 static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
183 {
184 0U, /* 0: TA1 */
185 1U, /* 1: TA2 */
186 0U, /* 2: TB1 */
187 1U, /* 3: TB2 */
188 0U, /* 4: TC1 */
189 1U, /* 5: TC2 */
190 0U, /* 6: TD1 */
191 1U, /* 7: TD2 */
192 0U, /* 8: TE1 */
193 1U /* 9: TE2 */
194 };
195
196 static const uint8_t REG_SHIFT_TAB_FLTxE[] =
197 {
198 0U, /* LL_HRTIM_FAULT_1 */
199 8U, /* LL_HRTIM_FAULT_2 */
200 16U, /* LL_HRTIM_FAULT_3 */
201 24U, /* LL_HRTIM_FAULT_4 */
202 0U /* LL_HRTIM_FAULT_5 */
203 };
204
205 /**
206 * @}
207 */
208
209
210 /* Private constants ---------------------------------------------------------*/
211 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
212 * @{
213 */
214 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
215 HRTIM_CR1_TAUDIS |\
216 HRTIM_CR1_TBUDIS |\
217 HRTIM_CR1_TCUDIS |\
218 HRTIM_CR1_TDUDIS |\
219 HRTIM_CR1_TEUDIS))
220
221 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
222 HRTIM_CR2_TASWU |\
223 HRTIM_CR2_TBSWU |\
224 HRTIM_CR2_TCSWU |\
225 HRTIM_CR2_TDSWU |\
226 HRTIM_CR2_TESWU))
227
228 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
229 HRTIM_CR2_TARST |\
230 HRTIM_CR2_TBRST |\
231 HRTIM_CR2_TCRST |\
232 HRTIM_CR2_TDRST |\
233 HRTIM_CR2_TERST))
234
235 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
236 HRTIM_OENR_TA2OEN |\
237 HRTIM_OENR_TB1OEN |\
238 HRTIM_OENR_TB2OEN |\
239 HRTIM_OENR_TC1OEN |\
240 HRTIM_OENR_TC2OEN |\
241 HRTIM_OENR_TD1OEN |\
242 HRTIM_OENR_TD2OEN |\
243 HRTIM_OENR_TE1OEN |\
244 HRTIM_OENR_TE2OEN))
245
246 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
247 HRTIM_ODISR_TA2ODIS |\
248 HRTIM_ODISR_TB1ODIS |\
249 HRTIM_ODISR_TB2ODIS |\
250 HRTIM_ODISR_TC1ODIS |\
251 HRTIM_ODISR_TC2ODIS |\
252 HRTIM_ODISR_TD1ODIS |\
253 HRTIM_ODISR_TD2ODIS |\
254 HRTIM_ODISR_TE1ODIS |\
255 HRTIM_ODISR_TE2ODIS))
256
257 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
258 HRTIM_OUTR_IDLM1 |\
259 HRTIM_OUTR_IDLES1 |\
260 HRTIM_OUTR_FAULT1 |\
261 HRTIM_OUTR_CHP1 |\
262 HRTIM_OUTR_DIDL1))
263
264 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
265 HRTIM_EECR1_EE1POL |\
266 HRTIM_EECR1_EE1SNS |\
267 HRTIM_EECR1_EE1FAST))
268
269 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
270 HRTIM_FLTINR1_FLT1SRC))
271
272 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
273 HRTIM_BMCR_BMCLK |\
274 HRTIM_BMCR_BMOM))
275
276 /**
277 * @}
278 */
279
280
281 /* Private macros ------------------------------------------------------------*/
282 /* Exported types ------------------------------------------------------------*/
283 /* Exported constants --------------------------------------------------------*/
284 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
285 * @{
286 */
287
288 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
289 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
290 * @{
291 */
292 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
293 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
294 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
295 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
296 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
297 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
298 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
299
300 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
301 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
302 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
303 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
304 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
305 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
306 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
307
308 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
309 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
310 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
311 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
312 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
313 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
314 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
315 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
316 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
317 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
318 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
319 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
320 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
321 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
322 /**
323 * @}
324 */
325
326 /** @defgroup HRTIM_LL_EC_IT IT Defines
327 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
328 * @{
329 */
330 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
331 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
332 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
333 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
334 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
335 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
336 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
337
338 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
339 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
340 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
341 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
342 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
343 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
344 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
345
346 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
347 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
348 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
349 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
350 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
351 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
352 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
353 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
354 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
355 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
356 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
357 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
358 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
359 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
360 /**
361 * @}
362 */
363
364 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
365 * @{
366 * @brief Constants defining defining the synchronization input source.
367 */
368 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
369 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
370 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
371 /**
372 * @}
373 */
374
375 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
376 * @{
377 * @brief Constants defining the source and event to be sent on the synchronization output.
378 */
379 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
380 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
381 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
382 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
383 /**
384 * @}
385 */
386
387 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
388 * @{
389 * @brief Constants defining the routing and conditioning of the synchronization output event.
390 */
391 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
392 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
393 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
394 /**
395 * @}
396 */
397
398 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
399 * @{
400 * @brief Constants identifying a timing unit.
401 */
402 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
403 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
404 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
405 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
406 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
407 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
408 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
409 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TACEN |\
410 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
411 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
412 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
413
414 /**
415 * @}
416 */
417
418 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
419 * @{
420 * @brief Constants identifying an HRTIM output.
421 */
422 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
423 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
424 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
425 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
426 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
427 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
428 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
429 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
430 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
431 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
432 /**
433 * @}
434 */
435
436 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
437 * @{
438 * @brief Constants identifying a compare unit.
439 */
440 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
441 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
442 /**
443 * @}
444 */
445
446 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
447 * @{
448 * @brief Constants identifying a capture unit.
449 */
450 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
451 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
452 /**
453 * @}
454 */
455
456 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
457 * @{
458 * @brief Constants identifying a fault channel.
459 */
460 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
461 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
462 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
463 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
464 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
465 /**
466 * @}
467 */
468
469 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
470 * @{
471 * @brief Constants identifying an external event channel.
472 */
473 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
474 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
475 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
476 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
477 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
478 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
479 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
480 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
481 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
482 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
483 /**
484 * @}
485 */
486
487 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
488 * @{
489 * @brief Constants defining the state of an HRTIM output.
490 */
491 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
492 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
493 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
494 /**
495 * @}
496 */
497
498 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
499 * @{
500 * @brief Constants identifying an ADC trigger.
501 */
502 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
503 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
504 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
505 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
506 /**
507 * @}
508 */
509
510 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
511 * @{
512 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
513 */
514 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
515 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
516 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
517 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
518 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
519 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
520 /**
521 * @}
522 */
523
524 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
525 * @{
526 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
527 */
528 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
529 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
530 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
531 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
532 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
533 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
534 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
535 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
536 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
537 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
538 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
539 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
540 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
541 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
542 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
543 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
544 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
545 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
546 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
547 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
548 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
549 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
550 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
551 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
552 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
553 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
554 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
555 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
556 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
557 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
558 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
559 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
560 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
561 /**
562 * @}
563 */
564
565 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
566 * @{
567 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
568 */
569 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
570 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
571 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
572 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
573 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
574 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
575 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
576 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
577 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
578 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
579 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
580 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
581 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
582 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
583 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
584 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
585 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
586 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
587 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
588 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
589 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
590 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
591 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
592 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
593 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
594 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
595 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
596 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
597 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
598 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
599 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
600 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
601 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
602 /**
603 * @}
604 */
605
606 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
607 * @{
608 * @brief Constants defining timer high-resolution clock prescaler ratio.
609 */
610 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
611 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
612 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
613 /**
614 * @}
615 */
616
617 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
618 * @{
619 * @brief Constants defining timer counter operating mode.
620 */
621 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
622 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
623 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
624 /**
625 * @}
626 */
627
628 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
629 * @{
630 * @brief Constants defining on which output the DAC synchronization event is sent.
631 */
632 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
633 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
634 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
635 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
636 /**
637 * @}
638 */
639
640 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
641 * @{
642 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
643 */
644 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
645 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
646 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
647 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
648 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
649 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
650 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
651 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
652 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
653 /**
654 * @}
655 */
656
657 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
658 * @{
659 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
660 */
661 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
662 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
663 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
664 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
665 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
666 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
667 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
668 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
669 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
670 /**
671 * @}
672 */
673
674 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
675 * @{
676 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
677 */
678 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
679 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
680 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
681 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
682 /**
683 * @}
684 */
685
686 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
687 * @{
688 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
689 */
690 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
691 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
692 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
693 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
694 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
695 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
696 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
697 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
698 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
699 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
700 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
701 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
702 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
703 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
704 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
705 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
706 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
707 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
708 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
709 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
710 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
711 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
712 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
713 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
714 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
715 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
716 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
717 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
718 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
719 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
720 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
721 /**
722 * @}
723 */
724
725 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
726 * @{
727 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
728 */
729 #define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
730 #define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
731 #define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
732 #define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
733 #define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
734 #define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
735 #define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
736 #define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
737 #define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
738 #define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
739 #define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
740 #define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
741 #define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */
742 #define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */
743 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */
744 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */
745 #define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */
746 #define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */
747 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */
748 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */
749 #define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */
750 #define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */
751 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */
752 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */
753 #define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */
754 #define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */
755 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */
756 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */
757 #define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */
758 #define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */
759 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */
760 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */
761 /**
762 * @}
763 */
764
765 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
766 * @{
767 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
768 */
769 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
770 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
771 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
772 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
773 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
774 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
775 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
776 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
777
778 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
779 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
780 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
781 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
782 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
783 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
784 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
785 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
786 /**
787 * @}
788 */
789
790 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
791 * @{
792 * @brief Constants defining how the timer behaves during a burst mode operation.
793 */
794 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
795 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
796 /**
797 * @}
798 */
799
800 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
801 * @{
802 * @brief Constants defining the registers that can be written during a burst DMA operation.
803 */
804 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
805 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
806 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
807 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
808 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
809 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
810 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
811 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
812 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
813 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
814 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
815 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
816 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
817 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
818 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
819 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
820 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
821 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
822 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
823 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
824 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
825 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
826 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
827 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
828 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
829 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
830 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
831 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
832 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
833 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
834 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
835 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
836 /**
837 * @}
838 */
839
840 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
841 * @{
842 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
843 */
844 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
845 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
846 /**
847 * @}
848 */
849
850 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
851 * @{
852 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
853 */
854 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
855 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
856 /**
857 * @}
858 */
859
860 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
861 * @{
862 * @brief Constants defining the event filtering applied to external events by a timer.
863 */
864 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
865 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
866 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
867 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
868 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
869 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
870 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
871 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
872 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
873 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
874 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
875 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
876 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
877 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
878 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
879 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
880 /**
881 * @}
882 */
883
884 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
885 * @{
886 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
887 */
888 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
889 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
890 /**
891 * @}
892 */
893
894 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
895 * @{
896 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
897 */
898 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
899 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
900 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
901 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
902 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
903 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
904 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
905 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
906 /**
907 * @}
908 */
909
910 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
911 * @{
912 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
913 */
914 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
915 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
916 /**
917 * @}
918 */
919
920 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
921 * @{
922 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
923 */
924 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
925 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
926 /**
927 * @}
928 */
929
930 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
931 * @{
932 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
933 */
934 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
935 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
936 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
937 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
938 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
939 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
940 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
941 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
942 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
943 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
944 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
945 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
946 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
947 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
948 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
949 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
950 /**
951 * @}
952 */
953
954 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
955 * @{
956 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
957 */
958 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
959 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
960 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
961 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
962 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
963 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
964 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
965 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
966 /**
967 * @}
968 */
969
970 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
971 * @{
972 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
973 */
974 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
975 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
976 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
977 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
978 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
979 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
980 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
981 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
982 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
983 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
984 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
985 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
986 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
987 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
988 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
989 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
990 /**
991 * @}
992 */
993
994 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT
995 * @{
996 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
997 */
998 #define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */
999 #define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
1000 #define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
1001 #define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
1002 #define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
1003 #define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
1004 #define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
1005 #define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
1006 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
1007 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
1008 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
1009 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
1010 #define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */
1011 #define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */
1012 #define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */
1013 #define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */
1014 #define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */
1015 #define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */
1016 #define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */
1017 #define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */
1018 #define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */
1019 #define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
1020 #define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
1021 #define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
1022 #define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
1023 #define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
1024 #define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
1025 #define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
1026 #define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
1027 #define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
1028 #define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
1029 #define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1035 * @{
1036 * @brief Constants defining the polarity of a timer output.
1037 */
1038 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
1039 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1045 * @{
1046 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1047 */
1048 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1049 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1050 /**
1051 * @}
1052 */
1053
1054 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1055 * @{
1056 * @brief Constants defining the half mode of an HRTIM Timer instance.
1057 */
1058 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
1059 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1065 * @{
1066 * @brief Constants defining the output level when output is in IDLE state
1067 */
1068 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1069 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1070 /**
1071 * @}
1072 */
1073
1074 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1075 * @{
1076 * @brief Constants defining the output level when output is in FAULT state.
1077 */
1078 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1079 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1080 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1081 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1087 * @{
1088 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1089 */
1090 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
1091 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1097 * @{
1098 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1099 during a programmable period before the output takes its idle state.
1100 */
1101 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1102 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1103 /**
1104 * @}
1105 */
1106 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1107 * @{
1108 * @brief Constants defining the level of a timer output.
1109 */
1110 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1111 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1112 /**
1113 * @}
1114 */
1115
1116 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1117 * @{
1118 * @brief Constants defining available sources associated to external events.
1119 */
1120 #define LL_HRTIM_EE_SRC_1 0x00000000U /*!< External event source 1 (EExSrc1)*/
1121 #define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */
1122 #define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */
1123 #define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */
1124 /**
1125 * @}
1126 */
1127 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1128 * @{
1129 * @brief Constants defining the polarity of an external event.
1130 */
1131 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
1132 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1133 /**
1134 * @}
1135 */
1136
1137 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1138 * @{
1139 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1140 */
1141 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
1142 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1143 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1144 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1145 /**
1146 * @}
1147 */
1148
1149 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1150 * @{
1151 * @brief Constants defining whether or not an external event is programmed in fast mode.
1152 */
1153 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1154 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1160 * @{
1161 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1162 */
1163 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
1164 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
1165 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
1166 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1167 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
1168 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1169 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1170 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1171 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
1172 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1173 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1174 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1175 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1176 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1177 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1178 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1179 /**
1180 * @}
1181 */
1182
1183 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1184 * @{
1185 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1186 */
1187 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
1188 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
1189 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
1190 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1196 * @{
1197 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1198 */
1199 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
1200 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1201 /**
1202 * @}
1203 */
1204
1205 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1206 * @{
1207 * @brief Constants defining the polarity of a fault event.
1208 */
1209 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
1210 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1216 * @{
1217 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1218 */
1219 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
1220 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1221 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1222 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1223 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1224 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1225 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1226 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1227 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1228 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1229 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1230 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1231 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1232 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1233 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1234 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1235 /**
1236 * @}
1237 */
1238
1239 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1240 * @{
1241 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1242 */
1243 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
1244 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
1245 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
1246 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1247 /**
1248 * @}
1249 */
1250
1251 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1252 * @{
1253 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1254 */
1255 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1256 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1257 /**
1258 * @}
1259 */
1260
1261 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1262 * @{
1263 * @brief Constants defining the clock source for the burst mode counter.
1264 */
1265 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1266 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1267 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1268 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1269 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1270 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1271 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1272 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1273 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1274 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1280 * @{
1281 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1282 */
1283 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
1284 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
1285 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
1286 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1287 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
1288 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1289 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1290 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1291 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
1292 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1293 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1294 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1295 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1296 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1297 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1298 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1304 * @{
1305 * @brief Constants defining the events that can be used to trig the burst mode operation.
1306 */
1307 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
1308 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1309 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1310 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1311 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1312 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1313 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1314 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1315 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1316 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1317 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1318 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1319 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1320 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1321 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1322 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1323 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1324 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1325 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
1326 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1327 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1328 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
1329 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1330 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
1331 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1332 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1333 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1334 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1335 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1336 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1337 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1338 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1344 * @{
1345 * @brief Constants defining the operating state of the burst mode controller.
1346 */
1347 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
1348 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
1349 /**
1350 * @}
1351 */
1352
1353 /**
1354 * @}
1355 */
1356
1357 /* Exported macro ------------------------------------------------------------*/
1358 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
1359 * @{
1360 */
1361
1362 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
1363 * @{
1364 */
1365
1366 /**
1367 * @brief Write a value in HRTIM register
1368 * @param __INSTANCE__ HRTIM Instance
1369 * @param __REG__ Register to be written
1370 * @param __VALUE__ Value to be written in the register
1371 * @retval None
1372 */
1373 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1374
1375 /**
1376 * @brief Read a value in HRTIM register
1377 * @param __INSTANCE__ HRTIM Instance
1378 * @param __REG__ Register to be read
1379 * @retval Register value
1380 */
1381 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1382 /**
1383 * @}
1384 */
1385
1386 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
1387 * @{
1388 */
1389 /**
1390 * @brief HELPER macro returning the output state from output enable/disable status
1391 * @param __OUTPUT_STATUS_EN__ output enable status
1392 * @param __OUTPUT_STATUS_DIS__ output Disable status
1393 * @retval Returned value can be one of the following values:
1394 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
1395 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
1396 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
1397 */
1398 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
1399 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
1400 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
1401 /**
1402 * @}
1403 */
1404
1405 /**
1406 * @}
1407 */
1408
1409 /* Exported functions --------------------------------------------------------*/
1410 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
1411 * @{
1412 */
1413 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
1414 * @{
1415 */
1416
1417 /**
1418 * @brief Select the HRTIM synchronization input source.
1419 * @note This function must not be called when the concerned timer(s) is (are) enabled .
1420 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1421 * @param HRTIMx High Resolution Timer instance
1422 * @param SyncInSrc This parameter can be one of the following values:
1423 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1424 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1425 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1426 * @retval None
1427 */
LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncInSrc)1428 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
1429 {
1430 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
1431 }
1432
1433 /**
1434 * @brief Get actual HRTIM synchronization input source.
1435 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
1436 * @param HRTIMx High Resolution Timer instance
1437 * @retval SyncInSrc Returned value can be one of the following values:
1438 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
1439 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
1440 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
1441 */
LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef * HRTIMx)1442 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
1443 {
1444 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
1445 }
1446
1447 /**
1448 * @brief Configure the HRTIM synchronization output.
1449 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
1450 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
1451 * @param HRTIMx High Resolution Timer instance
1452 * @param Config This parameter can be one of the following values:
1453 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1454 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1455 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1456 * @param Src This parameter can be one of the following values:
1457 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1458 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1459 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1460 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1461 * @retval None
1462 */
LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef * HRTIMx,uint32_t Config,uint32_t Src)1463 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
1464 {
1465 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
1466 }
1467
1468 /**
1469 * @brief Set the routing and conditioning of the synchronization output event.
1470 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
1471 * @note This function can be called only when the master timer is enabled.
1472 * @param HRTIMx High Resolution Timer instance
1473 * @param SyncOutConfig This parameter can be one of the following values:
1474 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1475 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1476 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1477 * @retval None
1478 */
LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutConfig)1479 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
1480 {
1481 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
1482 }
1483
1484 /**
1485 * @brief Get actual routing and conditioning of the synchronization output event.
1486 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
1487 * @param HRTIMx High Resolution Timer instance
1488 * @retval SyncOutConfig Returned value can be one of the following values:
1489 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
1490 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
1491 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
1492 */
LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef * HRTIMx)1493 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
1494 {
1495 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
1496 }
1497
1498 /**
1499 * @brief Set the source and event to be sent on the HRTIM synchronization output.
1500 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
1501 * @param HRTIMx High Resolution Timer instance
1502 * @param SyncOutSrc This parameter can be one of the following values:
1503 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1504 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1505 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1506 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1507 * @retval None
1508 */
LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef * HRTIMx,uint32_t SyncOutSrc)1509 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
1510 {
1511 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
1512 }
1513
1514 /**
1515 * @brief Get actual source and event sent on the HRTIM synchronization output.
1516 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
1517 * @param HRTIMx High Resolution Timer instance
1518 * @retval SyncOutSrc Returned value can be one of the following values:
1519 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
1520 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
1521 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
1522 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
1523 */
LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef * HRTIMx)1524 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
1525 {
1526 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
1527 }
1528
1529 /**
1530 * @brief Disable (temporarily) update event generation.
1531 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
1532 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
1533 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
1534 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
1535 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
1536 * CR1 TEUDIS LL_HRTIM_SuspendUpdate
1537 * @note Allow to temporarily disable the transfer from preload to active
1538 * registers, whatever the selected update event. This allows to modify
1539 * several registers in multiple timers.
1540 * @param HRTIMx High Resolution Timer instance
1541 * @param Timers This parameter can be a combination of the following values:
1542 * @arg @ref LL_HRTIM_TIMER_MASTER
1543 * @arg @ref LL_HRTIM_TIMER_A
1544 * @arg @ref LL_HRTIM_TIMER_B
1545 * @arg @ref LL_HRTIM_TIMER_C
1546 * @arg @ref LL_HRTIM_TIMER_D
1547 * @arg @ref LL_HRTIM_TIMER_E
1548 * @retval None
1549 */
LL_HRTIM_SuspendUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1550 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1551 {
1552 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
1553 }
1554
1555 /**
1556 * @brief Enable update event generation.
1557 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
1558 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
1559 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
1560 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
1561 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
1562 * CR1 TEUDIS LL_HRTIM_ResumeUpdate
1563 * @note The regular update event takes place.
1564 * @param HRTIMx High Resolution Timer instance
1565 * @param Timers This parameter can be a combination of the following values:
1566 * @arg @ref LL_HRTIM_TIMER_MASTER
1567 * @arg @ref LL_HRTIM_TIMER_A
1568 * @arg @ref LL_HRTIM_TIMER_B
1569 * @arg @ref LL_HRTIM_TIMER_C
1570 * @arg @ref LL_HRTIM_TIMER_D
1571 * @arg @ref LL_HRTIM_TIMER_E
1572 * @retval None
1573 */
LL_HRTIM_ResumeUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1574 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1575 {
1576 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
1577 }
1578
1579 /**
1580 * @brief Force an immediate transfer from the preload to the active register .
1581 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
1582 * CR2 TASWU LL_HRTIM_ForceUpdate\n
1583 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
1584 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
1585 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
1586 * CR2 TESWU LL_HRTIM_ForceUpdate
1587 * @note Any pending update request is cancelled.
1588 * @param HRTIMx High Resolution Timer instance
1589 * @param Timers This parameter can be a combination of the following values:
1590 * @arg @ref LL_HRTIM_TIMER_MASTER
1591 * @arg @ref LL_HRTIM_TIMER_A
1592 * @arg @ref LL_HRTIM_TIMER_B
1593 * @arg @ref LL_HRTIM_TIMER_C
1594 * @arg @ref LL_HRTIM_TIMER_D
1595 * @arg @ref LL_HRTIM_TIMER_E
1596 * @retval None
1597 */
LL_HRTIM_ForceUpdate(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1598 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1599 {
1600 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
1601 }
1602
1603 /**
1604 * @brief Reset the HRTIM timer(s) counter.
1605 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
1606 * CR2 TARST LL_HRTIM_CounterReset\n
1607 * CR2 TBRST LL_HRTIM_CounterReset\n
1608 * CR2 TCRST LL_HRTIM_CounterReset\n
1609 * CR2 TDRST LL_HRTIM_CounterReset\n
1610 * CR2 TERST LL_HRTIM_CounterReset
1611 * @param HRTIMx High Resolution Timer instance
1612 * @param Timers This parameter can be a combination of the following values:
1613 * @arg @ref LL_HRTIM_TIMER_MASTER
1614 * @arg @ref LL_HRTIM_TIMER_A
1615 * @arg @ref LL_HRTIM_TIMER_B
1616 * @arg @ref LL_HRTIM_TIMER_C
1617 * @arg @ref LL_HRTIM_TIMER_D
1618 * @arg @ref LL_HRTIM_TIMER_E
1619 * @retval None
1620 */
LL_HRTIM_CounterReset(HRTIM_TypeDef * HRTIMx,uint32_t Timers)1621 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
1622 {
1623 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
1624 }
1625
1626 /**
1627 * @brief Enable the HRTIM timer(s) output(s) .
1628 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
1629 * OENR TA2OEN LL_HRTIM_EnableOutput\n
1630 * OENR TB1OEN LL_HRTIM_EnableOutput\n
1631 * OENR TB2OEN LL_HRTIM_EnableOutput\n
1632 * OENR TC1OEN LL_HRTIM_EnableOutput\n
1633 * OENR TC2OEN LL_HRTIM_EnableOutput\n
1634 * OENR TD1OEN LL_HRTIM_EnableOutput\n
1635 * OENR TD2OEN LL_HRTIM_EnableOutput\n
1636 * OENR TE1OEN LL_HRTIM_EnableOutput\n
1637 * OENR TE2OEN LL_HRTIM_EnableOutput
1638 * @param HRTIMx High Resolution Timer instance
1639 * @param Outputs This parameter can be a combination of the following values:
1640 * @arg @ref LL_HRTIM_OUTPUT_TA1
1641 * @arg @ref LL_HRTIM_OUTPUT_TA2
1642 * @arg @ref LL_HRTIM_OUTPUT_TB1
1643 * @arg @ref LL_HRTIM_OUTPUT_TB2
1644 * @arg @ref LL_HRTIM_OUTPUT_TC1
1645 * @arg @ref LL_HRTIM_OUTPUT_TC2
1646 * @arg @ref LL_HRTIM_OUTPUT_TD1
1647 * @arg @ref LL_HRTIM_OUTPUT_TD2
1648 * @arg @ref LL_HRTIM_OUTPUT_TE1
1649 * @arg @ref LL_HRTIM_OUTPUT_TE2
1650 * @retval None
1651 */
LL_HRTIM_EnableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)1652 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
1653 {
1654 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
1655 }
1656
1657 /**
1658 * @brief Disable the HRTIM timer(s) output(s) .
1659 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
1660 * OENR TA2OEN LL_HRTIM_DisableOutput\n
1661 * OENR TB1OEN LL_HRTIM_DisableOutput\n
1662 * OENR TB2OEN LL_HRTIM_DisableOutput\n
1663 * OENR TC1OEN LL_HRTIM_DisableOutput\n
1664 * OENR TC2OEN LL_HRTIM_DisableOutput\n
1665 * OENR TD1OEN LL_HRTIM_DisableOutput\n
1666 * OENR TD2OEN LL_HRTIM_DisableOutput\n
1667 * OENR TE1OEN LL_HRTIM_DisableOutput\n
1668 * OENR TE2OEN LL_HRTIM_DisableOutput
1669 * @param HRTIMx High Resolution Timer instance
1670 * @param Outputs This parameter can be a combination of the following values:
1671 * @arg @ref LL_HRTIM_OUTPUT_TA1
1672 * @arg @ref LL_HRTIM_OUTPUT_TA2
1673 * @arg @ref LL_HRTIM_OUTPUT_TB1
1674 * @arg @ref LL_HRTIM_OUTPUT_TB2
1675 * @arg @ref LL_HRTIM_OUTPUT_TC1
1676 * @arg @ref LL_HRTIM_OUTPUT_TC2
1677 * @arg @ref LL_HRTIM_OUTPUT_TD1
1678 * @arg @ref LL_HRTIM_OUTPUT_TD2
1679 * @arg @ref LL_HRTIM_OUTPUT_TE1
1680 * @arg @ref LL_HRTIM_OUTPUT_TE2
1681 * @retval None
1682 */
LL_HRTIM_DisableOutput(HRTIM_TypeDef * HRTIMx,uint32_t Outputs)1683 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
1684 {
1685 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
1686 }
1687
1688 /**
1689 * @brief Indicates whether the HRTIM timer output is enabled.
1690 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
1691 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
1692 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
1693 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
1694 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
1695 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
1696 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
1697 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
1698 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
1699 * OENR TE2OEN LL_HRTIM_IsEnabledOutput
1700 * @param HRTIMx High Resolution Timer instance
1701 * @param Output This parameter can be one of the following values:
1702 * @arg @ref LL_HRTIM_OUTPUT_TA1
1703 * @arg @ref LL_HRTIM_OUTPUT_TA2
1704 * @arg @ref LL_HRTIM_OUTPUT_TB1
1705 * @arg @ref LL_HRTIM_OUTPUT_TB2
1706 * @arg @ref LL_HRTIM_OUTPUT_TC1
1707 * @arg @ref LL_HRTIM_OUTPUT_TC2
1708 * @arg @ref LL_HRTIM_OUTPUT_TD1
1709 * @arg @ref LL_HRTIM_OUTPUT_TD2
1710 * @arg @ref LL_HRTIM_OUTPUT_TE1
1711 * @arg @ref LL_HRTIM_OUTPUT_TE2
1712 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
1713 */
LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)1714 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
1715 {
1716 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
1717 }
1718
1719 /**
1720 * @brief Indicates whether the HRTIM timer output is disabled.
1721 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
1722 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
1723 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
1724 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
1725 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
1726 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
1727 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
1728 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
1729 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
1730 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
1731 * @param HRTIMx High Resolution Timer instance
1732 * @param Output This parameter can be one of the following values:
1733 * @arg @ref LL_HRTIM_OUTPUT_TA1
1734 * @arg @ref LL_HRTIM_OUTPUT_TA2
1735 * @arg @ref LL_HRTIM_OUTPUT_TB1
1736 * @arg @ref LL_HRTIM_OUTPUT_TB2
1737 * @arg @ref LL_HRTIM_OUTPUT_TC1
1738 * @arg @ref LL_HRTIM_OUTPUT_TC2
1739 * @arg @ref LL_HRTIM_OUTPUT_TD1
1740 * @arg @ref LL_HRTIM_OUTPUT_TD2
1741 * @arg @ref LL_HRTIM_OUTPUT_TE1
1742 * @arg @ref LL_HRTIM_OUTPUT_TE2
1743 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
1744 */
LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef * HRTIMx,uint32_t Output)1745 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
1746 {
1747 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
1748 }
1749
1750 /**
1751 * @brief Configure an ADC trigger.
1752 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
1753 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
1754 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
1755 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
1756 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
1757 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
1758 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
1759 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
1760 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
1761 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
1762 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
1763 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
1764 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
1765 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
1766 * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
1767 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
1768 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
1769 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
1770 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
1771 * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
1772 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
1773 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
1774 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
1775 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
1776 * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
1777 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
1778 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
1779 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
1780 * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
1781 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
1782 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
1783 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
1784 * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
1785 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
1786 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
1787 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
1788 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
1789 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
1790 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
1791 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
1792 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
1793 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
1794 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
1795 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
1796 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
1797 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
1798 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
1799 * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
1800 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
1801 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
1802 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
1803 * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
1804 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
1805 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
1806 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
1807 * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
1808 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
1809 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
1810 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
1811 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
1812 * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
1813 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
1814 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
1815 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
1816 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
1817 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
1818 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
1819 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
1820 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
1821 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
1822 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
1823 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
1824 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
1825 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
1826 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
1827 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
1828 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
1829 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
1830 * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
1831 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
1832 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
1833 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
1834 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
1835 * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
1836 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
1837 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
1838 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
1839 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
1840 * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
1841 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
1842 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
1843 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
1844 * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
1845 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
1846 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
1847 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
1848 * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
1849 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
1850 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
1851 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
1852 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
1853 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
1854 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
1855 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
1856 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
1857 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
1858 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
1859 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
1860 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
1861 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
1862 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
1863 * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
1864 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
1865 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
1866 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
1867 * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
1868 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
1869 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
1870 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
1871 * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
1872 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
1873 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
1874 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
1875 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
1876 * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
1877 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
1878 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
1879 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
1880 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
1881 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
1882 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
1883 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
1884 * @param HRTIMx High Resolution Timer instance
1885 * @param ADCTrig This parameter can be one of the following values:
1886 * @arg @ref LL_HRTIM_ADCTRIG_1
1887 * @arg @ref LL_HRTIM_ADCTRIG_2
1888 * @arg @ref LL_HRTIM_ADCTRIG_3
1889 * @arg @ref LL_HRTIM_ADCTRIG_4
1890 * @param Update This parameter can be one of the following values:
1891 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
1892 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
1893 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
1894 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
1895 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
1896 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
1897 * @param Src This parameter can be a combination of the following values:
1898 *
1899 * For ADC trigger 1 and ADC trigger 3:
1900 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
1901 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
1902 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
1903 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
1904 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
1905 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
1906 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
1907 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
1908 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
1909 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
1910 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
1911 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
1912 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
1913 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
1914 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
1915 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
1916 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
1917 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
1918 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
1919 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
1920 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
1921 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
1922 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
1923 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
1924 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
1925 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
1926 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
1927 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
1928 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
1929 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
1930 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
1931 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
1932 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
1933 *
1934 * For ADC trigger 2 and ADC trigger 4:
1935 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
1936 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
1937 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
1938 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
1939 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
1940 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
1941 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
1942 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
1943 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
1944 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
1945 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
1946 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
1947 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
1948 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
1949 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
1950 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
1951 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
1952 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
1953 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
1954 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
1955 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
1956 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
1957 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
1958 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
1959 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
1960 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
1961 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
1962 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
1963 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
1964 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
1965 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
1966 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
1967 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
1968 *
1969 * @retval None
1970 */
LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update,uint32_t Src)1971 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
1972 {
1973 uint32_t shift = ((3U * ADCTrig) & 0x1FU);
1974 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
1975 REG_OFFSET_TAB_ADCxR[ADCTrig]));
1976 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
1977 WRITE_REG(*pReg, Src);
1978 }
1979
1980 /**
1981 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
1982 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
1983 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
1984 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
1985 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
1986 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
1987 * registers are not preloaded either: a write access will result in an
1988 * immediate update of the trigger source.
1989 * @param HRTIMx High Resolution Timer instance
1990 * @param ADCTrig This parameter can be one of the following values:
1991 * @arg @ref LL_HRTIM_ADCTRIG_1
1992 * @arg @ref LL_HRTIM_ADCTRIG_2
1993 * @arg @ref LL_HRTIM_ADCTRIG_3
1994 * @arg @ref LL_HRTIM_ADCTRIG_4
1995 * @param Update This parameter can be one of the following values:
1996 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
1997 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
1998 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
1999 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2000 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2001 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2002 * @retval None
2003 */
LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Update)2004 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2005 {
2006 uint32_t shift = ((3U * ADCTrig) & 0x1FU);
2007 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
2008 }
2009
2010 /**
2011 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2012 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2013 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2014 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2015 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2016 * @param HRTIMx High Resolution Timer instance
2017 * @param ADCTrig This parameter can be one of the following values:
2018 * @arg @ref LL_HRTIM_ADCTRIG_1
2019 * @arg @ref LL_HRTIM_ADCTRIG_2
2020 * @arg @ref LL_HRTIM_ADCTRIG_3
2021 * @arg @ref LL_HRTIM_ADCTRIG_4
2022 * @retval Update Returned value can be one of the following values:
2023 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2024 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2025 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2026 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2027 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2028 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2029 */
LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2030 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2031 {
2032 const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
2033 return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
2034 }
2035
2036 /**
2037 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2038 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2039 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2040 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2041 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2042 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2043 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2044 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2045 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2046 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2047 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2048 * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
2049 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2050 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2051 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2052 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2053 * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
2054 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2055 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2056 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2057 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2058 * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
2059 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2060 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2061 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2062 * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
2063 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2064 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2065 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2066 * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
2067 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2068 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2069 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2070 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2071 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2072 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2073 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2074 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2075 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2076 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2077 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2078 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2079 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2080 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2081 * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
2082 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2083 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2084 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2085 * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
2086 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2087 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2088 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2089 * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
2090 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2091 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2092 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2093 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2094 * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
2095 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
2096 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
2097 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
2098 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
2099 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
2100 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
2101 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
2102 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
2103 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
2104 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
2105 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
2106 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
2107 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
2108 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
2109 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
2110 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
2111 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
2112 * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
2113 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
2114 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
2115 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
2116 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
2117 * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
2118 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
2119 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
2120 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
2121 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
2122 * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
2123 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
2124 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
2125 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
2126 * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
2127 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
2128 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
2129 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
2130 * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
2131 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
2132 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
2133 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
2134 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
2135 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
2136 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
2137 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
2138 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
2139 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
2140 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
2141 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
2142 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
2143 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
2144 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
2145 * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
2146 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
2147 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
2148 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
2149 * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
2150 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
2151 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
2152 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
2153 * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
2154 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
2155 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
2156 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
2157 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
2158 * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
2159 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
2160 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
2161 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
2162 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
2163 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
2164 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
2165 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
2166 * @param HRTIMx High Resolution Timer instance
2167 * @param ADCTrig This parameter can be one of the following values:
2168 * @arg @ref LL_HRTIM_ADCTRIG_1
2169 * @arg @ref LL_HRTIM_ADCTRIG_2
2170 * @arg @ref LL_HRTIM_ADCTRIG_3
2171 * @arg @ref LL_HRTIM_ADCTRIG_4
2172 * @param Src
2173 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2174 * combination of the following values:
2175 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2176 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2177 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2178 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2179 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2180 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2181 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2182 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2183 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2184 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2185 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2186 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2187 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2188 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2189 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2190 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2191 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2192 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2193 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2194 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2195 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2196 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2197 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2198 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2199 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2200 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2201 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2202 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2203 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2204 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2205 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2206 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2207 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2208 *
2209 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2210 * combination of the following values:
2211 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2212 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2213 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2214 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2215 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2216 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2217 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2218 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2219 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2220 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2221 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2222 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2223 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2224 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2225 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2226 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2227 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2228 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2229 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2230 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2231 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2232 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2233 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2234 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2235 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2236 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2237 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2238 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2239 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2240 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2241 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2242 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2243 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2244 *
2245 * @retval None
2246 */
LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig,uint32_t Src)2247 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
2248 {
2249 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2250 REG_OFFSET_TAB_ADCxR[ADCTrig]));
2251 WRITE_REG(*pReg, Src);
2252 }
2253
2254 /**
2255 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
2256 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
2257 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
2258 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
2259 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
2260 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
2261 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
2262 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
2263 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
2264 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
2265 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
2266 * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
2267 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
2268 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
2269 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
2270 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
2271 * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
2272 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
2273 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
2274 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
2275 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
2276 * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
2277 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
2278 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
2279 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
2280 * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
2281 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
2282 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
2283 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
2284 * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
2285 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
2286 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
2287 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
2288 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
2289 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
2290 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
2291 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
2292 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
2293 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
2294 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
2295 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
2296 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
2297 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
2298 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
2299 * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
2300 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
2301 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
2302 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
2303 * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
2304 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
2305 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
2306 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
2307 * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
2308 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
2309 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
2310 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
2311 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
2312 * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
2313 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
2314 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
2315 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
2316 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
2317 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
2318 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
2319 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
2320 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
2321 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
2322 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
2323 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
2324 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
2325 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
2326 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
2327 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
2328 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
2329 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
2330 * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
2331 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
2332 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
2333 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
2334 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
2335 * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
2336 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
2337 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
2338 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
2339 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
2340 * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
2341 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
2342 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
2343 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
2344 * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
2345 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
2346 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
2347 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
2348 * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
2349 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
2350 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
2351 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
2352 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
2353 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
2354 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
2355 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
2356 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
2357 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
2358 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
2359 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
2360 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
2361 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
2362 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
2363 * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
2364 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
2365 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
2366 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
2367 * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
2368 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
2369 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
2370 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
2371 * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
2372 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
2373 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
2374 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
2375 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
2376 * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
2377 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
2378 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
2379 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
2380 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
2381 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
2382 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
2383 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
2384 * @param HRTIMx High Resolution Timer instance
2385 * @param ADCTrig This parameter can be one of the following values:
2386 * @arg @ref LL_HRTIM_ADCTRIG_1
2387 * @arg @ref LL_HRTIM_ADCTRIG_2
2388 * @arg @ref LL_HRTIM_ADCTRIG_3
2389 * @arg @ref LL_HRTIM_ADCTRIG_4
2390 * @retval Src This parameter can be a combination of the following values:
2391 *
2392 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
2393 * combination of the following values:
2394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
2406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2409 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2410 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
2411 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2412 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2413 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2414 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2415 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
2416 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2417 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2418 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2419 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
2420 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2421 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2422 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2423 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
2424 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2425 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2426 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2427 *
2428 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
2429 * combination of the following values:
2430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
2443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2445 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2446 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
2447 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2448 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2449 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2450 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
2451 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2452 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2453 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2454 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2455 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
2456 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2457 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2458 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2459 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2460 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2461 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2462 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2463 */
LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef * HRTIMx,uint32_t ADCTrig)2464 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
2465 {
2466 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2467 REG_OFFSET_TAB_ADCxR[ADCTrig]));
2468 return (*pReg);
2469
2470 }
2471
2472
2473 /**
2474 * @}
2475 */
2476
2477 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
2478 * @{
2479 */
2480
2481 /**
2482 * @brief Enable timer(s) counter.
2483 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
2484 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
2485 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
2486 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
2487 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
2488 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
2489 * @param HRTIMx High Resolution Timer instance
2490 * @param Timers This parameter can be a combination of the following values:
2491 * @arg @ref LL_HRTIM_TIMER_MASTER
2492 * @arg @ref LL_HRTIM_TIMER_A
2493 * @arg @ref LL_HRTIM_TIMER_B
2494 * @arg @ref LL_HRTIM_TIMER_C
2495 * @arg @ref LL_HRTIM_TIMER_D
2496 * @arg @ref LL_HRTIM_TIMER_E
2497 * @retval None
2498 */
LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2499 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2500 {
2501 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
2502 }
2503
2504 /**
2505 * @brief Disable timer(s) counter.
2506 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
2507 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
2508 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
2509 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
2510 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
2511 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
2512 * @param HRTIMx High Resolution Timer instance
2513 * @param Timers This parameter can be a combination of the following values:
2514 * @arg @ref LL_HRTIM_TIMER_MASTER
2515 * @arg @ref LL_HRTIM_TIMER_A
2516 * @arg @ref LL_HRTIM_TIMER_B
2517 * @arg @ref LL_HRTIM_TIMER_C
2518 * @arg @ref LL_HRTIM_TIMER_D
2519 * @arg @ref LL_HRTIM_TIMER_E
2520 * @retval None
2521 */
LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef * HRTIMx,uint32_t Timers)2522 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
2523 {
2524 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
2525 }
2526
2527 /**
2528 * @brief Indicate whether the timer counter is enabled.
2529 * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
2530 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
2531 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
2532 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
2533 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
2534 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
2535 * @param HRTIMx High Resolution Timer instance
2536 * @param Timer This parameter can be one of the following values:
2537 * @arg @ref LL_HRTIM_TIMER_MASTER
2538 * @arg @ref LL_HRTIM_TIMER_A
2539 * @arg @ref LL_HRTIM_TIMER_B
2540 * @arg @ref LL_HRTIM_TIMER_C
2541 * @arg @ref LL_HRTIM_TIMER_D
2542 * @arg @ref LL_HRTIM_TIMER_E
2543 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
2544 */
LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2545 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2546 {
2547 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
2548 }
2549
2550 /**
2551 * @brief Set the timer clock prescaler ratio.
2552 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
2553 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
2554 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
2555 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
2556 * @param HRTIMx High Resolution Timer instance
2557 * @param Timer This parameter can be one of the following values:
2558 * @arg @ref LL_HRTIM_TIMER_MASTER
2559 * @arg @ref LL_HRTIM_TIMER_A
2560 * @arg @ref LL_HRTIM_TIMER_B
2561 * @arg @ref LL_HRTIM_TIMER_C
2562 * @arg @ref LL_HRTIM_TIMER_D
2563 * @arg @ref LL_HRTIM_TIMER_E
2564 * @param Prescaler This parameter can be one of the following values:
2565 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2566 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2567 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2568 * @retval None
2569 */
LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)2570 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
2571 {
2572 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2573 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2574 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
2575 }
2576
2577 /**
2578 * @brief Get the timer clock prescaler ratio
2579 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
2580 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
2581 * @param HRTIMx High Resolution Timer instance
2582 * @param Timer This parameter can be one of the following values:
2583 * @arg @ref LL_HRTIM_TIMER_MASTER
2584 * @arg @ref LL_HRTIM_TIMER_A
2585 * @arg @ref LL_HRTIM_TIMER_B
2586 * @arg @ref LL_HRTIM_TIMER_C
2587 * @arg @ref LL_HRTIM_TIMER_D
2588 * @arg @ref LL_HRTIM_TIMER_E
2589 * @retval Prescaler Returned value can be one of the following values:
2590 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
2591 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
2592 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
2593 */
LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2594 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2595 {
2596 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2597 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2598 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
2599 }
2600
2601 /**
2602 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
2603 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
2604 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
2605 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
2606 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
2607 * @param HRTIMx High Resolution Timer instance
2608 * @param Timer This parameter can be one of the following values:
2609 * @arg @ref LL_HRTIM_TIMER_MASTER
2610 * @arg @ref LL_HRTIM_TIMER_A
2611 * @arg @ref LL_HRTIM_TIMER_B
2612 * @arg @ref LL_HRTIM_TIMER_C
2613 * @arg @ref LL_HRTIM_TIMER_D
2614 * @arg @ref LL_HRTIM_TIMER_E
2615 * @param Mode This parameter can be one of the following values:
2616 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2617 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2618 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2619 * @retval None
2620 */
LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Mode)2621 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
2622 {
2623 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2624 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2625 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
2626 }
2627
2628 /**
2629 * @brief Get the counter operating mode mode
2630 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
2631 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
2632 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
2633 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
2634 * @param HRTIMx High Resolution Timer instance
2635 * @param Timer This parameter can be one of the following values:
2636 * @arg @ref LL_HRTIM_TIMER_MASTER
2637 * @arg @ref LL_HRTIM_TIMER_A
2638 * @arg @ref LL_HRTIM_TIMER_B
2639 * @arg @ref LL_HRTIM_TIMER_C
2640 * @arg @ref LL_HRTIM_TIMER_D
2641 * @arg @ref LL_HRTIM_TIMER_E
2642 * @retval Mode Returned value can be one of the following values:
2643 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
2644 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
2645 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
2646 */
LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2647 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2648 {
2649 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2650 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2651 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
2652 }
2653
2654 /**
2655 * @brief Enable the half duty-cycle mode.
2656 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
2657 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
2658 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
2659 * active register is automatically updated with HRTIM_MPER/2
2660 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
2661 * @param HRTIMx High Resolution Timer instance
2662 * @param Timer This parameter can be one of the following values:
2663 * @arg @ref LL_HRTIM_TIMER_MASTER
2664 * @arg @ref LL_HRTIM_TIMER_A
2665 * @arg @ref LL_HRTIM_TIMER_B
2666 * @arg @ref LL_HRTIM_TIMER_C
2667 * @arg @ref LL_HRTIM_TIMER_D
2668 * @arg @ref LL_HRTIM_TIMER_E
2669 * @retval None
2670 */
LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2671 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2672 {
2673 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2674 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2675 SET_BIT(*pReg, HRTIM_MCR_HALF);
2676 }
2677
2678 /**
2679 * @brief Disable the half duty-cycle mode.
2680 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
2681 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
2682 * @param HRTIMx High Resolution Timer instance
2683 * @param Timer This parameter can be one of the following values:
2684 * @arg @ref LL_HRTIM_TIMER_MASTER
2685 * @arg @ref LL_HRTIM_TIMER_A
2686 * @arg @ref LL_HRTIM_TIMER_B
2687 * @arg @ref LL_HRTIM_TIMER_C
2688 * @arg @ref LL_HRTIM_TIMER_D
2689 * @arg @ref LL_HRTIM_TIMER_E
2690 * @retval None
2691 */
LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2692 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2693 {
2694 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2695 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2696 CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
2697 }
2698
2699 /**
2700 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
2701 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
2702 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
2703 * @param HRTIMx High Resolution Timer instance
2704 * @param Timer This parameter can be one of the following values:
2705 * @arg @ref LL_HRTIM_TIMER_MASTER
2706 * @arg @ref LL_HRTIM_TIMER_A
2707 * @arg @ref LL_HRTIM_TIMER_B
2708 * @arg @ref LL_HRTIM_TIMER_C
2709 * @arg @ref LL_HRTIM_TIMER_D
2710 * @arg @ref LL_HRTIM_TIMER_E
2711 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2712 */
LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2713 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2714 {
2715 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2716 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2717
2718 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
2719 }
2720 /**
2721 * @brief Enable the timer start when receiving a synchronization input event.
2722 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
2723 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
2724 * @param HRTIMx High Resolution Timer instance
2725 * @param Timer This parameter can be one of the following values:
2726 * @arg @ref LL_HRTIM_TIMER_MASTER
2727 * @arg @ref LL_HRTIM_TIMER_A
2728 * @arg @ref LL_HRTIM_TIMER_B
2729 * @arg @ref LL_HRTIM_TIMER_C
2730 * @arg @ref LL_HRTIM_TIMER_D
2731 * @arg @ref LL_HRTIM_TIMER_E
2732 * @retval None
2733 */
LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2734 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2735 {
2736 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2737 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2738 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
2739 }
2740
2741 /**
2742 * @brief Disable the timer start when receiving a synchronization input event.
2743 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
2744 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
2745 * @param HRTIMx High Resolution Timer instance
2746 * @param Timer This parameter can be one of the following values:
2747 * @arg @ref LL_HRTIM_TIMER_MASTER
2748 * @arg @ref LL_HRTIM_TIMER_A
2749 * @arg @ref LL_HRTIM_TIMER_B
2750 * @arg @ref LL_HRTIM_TIMER_C
2751 * @arg @ref LL_HRTIM_TIMER_D
2752 * @arg @ref LL_HRTIM_TIMER_E
2753 * @retval None
2754 */
LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2755 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2756 {
2757 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2759 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
2760 }
2761
2762 /**
2763 * @brief Indicate whether the timer start when receiving a synchronization input event.
2764 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
2765 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
2766 * @param HRTIMx High Resolution Timer instance
2767 * @param Timer This parameter can be one of the following values:
2768 * @arg @ref LL_HRTIM_TIMER_MASTER
2769 * @arg @ref LL_HRTIM_TIMER_A
2770 * @arg @ref LL_HRTIM_TIMER_B
2771 * @arg @ref LL_HRTIM_TIMER_C
2772 * @arg @ref LL_HRTIM_TIMER_D
2773 * @arg @ref LL_HRTIM_TIMER_E
2774 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2775 */
LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2776 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2777 {
2778 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2779 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2780
2781 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
2782 }
2783
2784 /**
2785 * @brief Enable the timer reset when receiving a synchronization input event.
2786 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
2787 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
2788 * @param HRTIMx High Resolution Timer instance
2789 * @param Timer This parameter can be one of the following values:
2790 * @arg @ref LL_HRTIM_TIMER_MASTER
2791 * @arg @ref LL_HRTIM_TIMER_A
2792 * @arg @ref LL_HRTIM_TIMER_B
2793 * @arg @ref LL_HRTIM_TIMER_C
2794 * @arg @ref LL_HRTIM_TIMER_D
2795 * @arg @ref LL_HRTIM_TIMER_E
2796 * @retval None
2797 */
LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2798 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2799 {
2800 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2801 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2802 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
2803 }
2804
2805 /**
2806 * @brief Disable the timer reset when receiving a synchronization input event.
2807 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
2808 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
2809 * @param HRTIMx High Resolution Timer instance
2810 * @param Timer This parameter can be one of the following values:
2811 * @arg @ref LL_HRTIM_TIMER_MASTER
2812 * @arg @ref LL_HRTIM_TIMER_A
2813 * @arg @ref LL_HRTIM_TIMER_B
2814 * @arg @ref LL_HRTIM_TIMER_C
2815 * @arg @ref LL_HRTIM_TIMER_D
2816 * @arg @ref LL_HRTIM_TIMER_E
2817 * @retval None
2818 */
LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2819 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2820 {
2821 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2822 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2823 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
2824 }
2825
2826 /**
2827 * @brief Indicate whether the timer reset when receiving a synchronization input event.
2828 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
2829 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
2830 * @param HRTIMx High Resolution Timer instance
2831 * @param Timer This parameter can be one of the following values:
2832 * @arg @ref LL_HRTIM_TIMER_MASTER
2833 * @arg @ref LL_HRTIM_TIMER_A
2834 * @arg @ref LL_HRTIM_TIMER_B
2835 * @arg @ref LL_HRTIM_TIMER_C
2836 * @arg @ref LL_HRTIM_TIMER_D
2837 * @arg @ref LL_HRTIM_TIMER_E
2838 * @retval None
2839 */
LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2840 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2841 {
2842 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2843 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2844
2845 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
2846 }
2847
2848 /**
2849 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2850 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
2851 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
2852 * @param HRTIMx High Resolution Timer instance
2853 * @param Timer This parameter can be one of the following values:
2854 * @arg @ref LL_HRTIM_TIMER_MASTER
2855 * @arg @ref LL_HRTIM_TIMER_A
2856 * @arg @ref LL_HRTIM_TIMER_B
2857 * @arg @ref LL_HRTIM_TIMER_C
2858 * @arg @ref LL_HRTIM_TIMER_D
2859 * @arg @ref LL_HRTIM_TIMER_E
2860 * @param DACTrig This parameter can be one of the following values:
2861 * @arg @ref LL_HRTIM_DACTRIG_NONE
2862 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2863 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2864 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2865 * @retval None
2866 */
LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DACTrig)2867 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
2868 {
2869 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2870 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2871 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
2872 }
2873
2874 /**
2875 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
2876 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
2877 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
2878 * @param HRTIMx High Resolution Timer instance
2879 * @param Timer This parameter can be one of the following values:
2880 * @arg @ref LL_HRTIM_TIMER_MASTER
2881 * @arg @ref LL_HRTIM_TIMER_A
2882 * @arg @ref LL_HRTIM_TIMER_B
2883 * @arg @ref LL_HRTIM_TIMER_C
2884 * @arg @ref LL_HRTIM_TIMER_D
2885 * @arg @ref LL_HRTIM_TIMER_E
2886 * @retval DACTrig Returned value can be one of the following values:
2887 * @arg @ref LL_HRTIM_DACTRIG_NONE
2888 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
2889 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
2890 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
2891 */
LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2892 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2893 {
2894 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2895 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2896 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
2897 }
2898
2899 /**
2900 * @brief Enable the timer registers preload mechanism.
2901 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
2902 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
2903 * @note When the preload mode is enabled, accessed registers are shadow registers.
2904 * Their content is transferred into the active register after an update request,
2905 * either software or synchronized with an event.
2906 * @param HRTIMx High Resolution Timer instance
2907 * @param Timer This parameter can be one of the following values:
2908 * @arg @ref LL_HRTIM_TIMER_MASTER
2909 * @arg @ref LL_HRTIM_TIMER_A
2910 * @arg @ref LL_HRTIM_TIMER_B
2911 * @arg @ref LL_HRTIM_TIMER_C
2912 * @arg @ref LL_HRTIM_TIMER_D
2913 * @arg @ref LL_HRTIM_TIMER_E
2914 * @retval None
2915 */
LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2916 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2917 {
2918 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2919 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2920 SET_BIT(*pReg, HRTIM_MCR_PREEN);
2921 }
2922
2923 /**
2924 * @brief Disable the timer registers preload mechanism.
2925 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
2926 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
2927 * @param HRTIMx High Resolution Timer instance
2928 * @param Timer This parameter can be one of the following values:
2929 * @arg @ref LL_HRTIM_TIMER_MASTER
2930 * @arg @ref LL_HRTIM_TIMER_A
2931 * @arg @ref LL_HRTIM_TIMER_B
2932 * @arg @ref LL_HRTIM_TIMER_C
2933 * @arg @ref LL_HRTIM_TIMER_D
2934 * @arg @ref LL_HRTIM_TIMER_E
2935 * @retval None
2936 */
LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef * HRTIMx,uint32_t Timer)2937 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2938 {
2939 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2941 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
2942 }
2943
2944 /**
2945 * @brief Indicate whether the timer registers preload mechanism is enabled.
2946 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
2947 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
2948 * @param HRTIMx High Resolution Timer instance
2949 * @param Timer This parameter can be one of the following values:
2950 * @arg @ref LL_HRTIM_TIMER_MASTER
2951 * @arg @ref LL_HRTIM_TIMER_A
2952 * @arg @ref LL_HRTIM_TIMER_B
2953 * @arg @ref LL_HRTIM_TIMER_C
2954 * @arg @ref LL_HRTIM_TIMER_D
2955 * @arg @ref LL_HRTIM_TIMER_E
2956 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
2957 */
LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)2958 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
2959 {
2960 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
2961 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
2962
2963 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
2964 }
2965
2966 /**
2967 * @brief Set the timer register update trigger.
2968 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
2969 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
2970 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
2971 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
2972 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
2973 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
2974 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
2975 * @param HRTIMx High Resolution Timer instance
2976 * @param Timer This parameter can be one of the following values:
2977 * @arg @ref LL_HRTIM_TIMER_MASTER
2978 * @arg @ref LL_HRTIM_TIMER_A
2979 * @arg @ref LL_HRTIM_TIMER_B
2980 * @arg @ref LL_HRTIM_TIMER_C
2981 * @arg @ref LL_HRTIM_TIMER_D
2982 * @arg @ref LL_HRTIM_TIMER_E
2983 * @param UpdateTrig This parameter can be one of the following values:
2984 *
2985 * For the master timer this parameter can be one of the following values:
2986 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
2987 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
2988 *
2989 * For timer A..E this parameter can be:
2990 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
2991 * or a combination of the following values:
2992 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
2993 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
2994 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
2995 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
2996 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
2997 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
2998 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
2999 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3000 * @retval None
3001 */
LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateTrig)3002 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
3003 {
3004 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3005 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3006 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
3007 }
3008
3009 /**
3010 * @brief Get the timer register update trigger.
3011 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
3012 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
3013 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
3014 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
3015 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
3016 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
3017 * @param HRTIMx High Resolution Timer instance
3018 * @param Timer This parameter can be one of the following values:
3019 * @arg @ref LL_HRTIM_TIMER_MASTER
3020 * @arg @ref LL_HRTIM_TIMER_A
3021 * @arg @ref LL_HRTIM_TIMER_B
3022 * @arg @ref LL_HRTIM_TIMER_C
3023 * @arg @ref LL_HRTIM_TIMER_D
3024 * @arg @ref LL_HRTIM_TIMER_E
3025 * @retval UpdateTrig Returned value can be one of the following values:
3026 *
3027 * For the master timer this parameter can be one of the following values:
3028 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3029 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3030 *
3031 * For timer A..E this parameter can be:
3032 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
3033 * or a combination of the following values:
3034 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
3035 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
3036 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
3037 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
3038 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
3039 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
3040 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
3041 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
3042 */
LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3043 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3044 {
3045 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3046 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3047 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
3048 }
3049
3050 /**
3051 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
3052 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
3053 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
3054 * @param HRTIMx High Resolution Timer instance
3055 * @param Timer This parameter can be one of the following values:
3056 * @arg @ref LL_HRTIM_TIMER_MASTER
3057 * @arg @ref LL_HRTIM_TIMER_A
3058 * @arg @ref LL_HRTIM_TIMER_B
3059 * @arg @ref LL_HRTIM_TIMER_C
3060 * @arg @ref LL_HRTIM_TIMER_D
3061 * @arg @ref LL_HRTIM_TIMER_E
3062 * @param UpdateGating This parameter can be one of the following values:
3063 *
3064 * For the master timer this parameter can be one of the following values:
3065 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3066 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3067 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3068 *
3069 * For the timer A..E this parameter can be one of the following values:
3070 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3071 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3072 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3073 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3074 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3075 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3076 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3077 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3078 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3079 * @retval None
3080 */
LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t UpdateGating)3081 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
3082 {
3083 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3084 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3085 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
3086 }
3087
3088 /**
3089 * @brief Get the timer registers update condition.
3090 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
3091 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
3092 * @param HRTIMx High Resolution Timer instance
3093 * @param Timer This parameter can be one of the following values:
3094 * @arg @ref LL_HRTIM_TIMER_MASTER
3095 * @arg @ref LL_HRTIM_TIMER_A
3096 * @arg @ref LL_HRTIM_TIMER_B
3097 * @arg @ref LL_HRTIM_TIMER_C
3098 * @arg @ref LL_HRTIM_TIMER_D
3099 * @arg @ref LL_HRTIM_TIMER_E
3100 * @retval UpdateGating Returned value can be one of the following values:
3101 *
3102 * For the master timer this parameter can be one of the following values:
3103 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3104 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3105 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3106 *
3107 * For the timer A..E this parameter can be one of the following values:
3108 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
3109 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
3110 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
3111 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
3112 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
3113 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
3114 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
3115 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
3116 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
3117 */
LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3118 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3119 {
3120 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3121 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3122 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
3123 }
3124
3125 /**
3126 * @brief Enable the push-pull mode.
3127 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
3128 * @param HRTIMx High Resolution Timer instance
3129 * @param Timer This parameter can be one of the following values:
3130 * @arg @ref LL_HRTIM_TIMER_A
3131 * @arg @ref LL_HRTIM_TIMER_B
3132 * @arg @ref LL_HRTIM_TIMER_C
3133 * @arg @ref LL_HRTIM_TIMER_D
3134 * @arg @ref LL_HRTIM_TIMER_E
3135 * @retval None
3136 */
LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3137 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3138 {
3139 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3140 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3141 REG_OFFSET_TAB_TIMER[iTimer]));
3142 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
3143 }
3144
3145 /**
3146 * @brief Disable the push-pull mode.
3147 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
3148 * @param HRTIMx High Resolution Timer instance
3149 * @param Timer This parameter can be one of the following values:
3150 * @arg @ref LL_HRTIM_TIMER_A
3151 * @arg @ref LL_HRTIM_TIMER_B
3152 * @arg @ref LL_HRTIM_TIMER_C
3153 * @arg @ref LL_HRTIM_TIMER_D
3154 * @arg @ref LL_HRTIM_TIMER_E
3155 * @retval None
3156 */
LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3157 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3158 {
3159 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3160 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3161 REG_OFFSET_TAB_TIMER[iTimer]));
3162 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
3163 }
3164
3165 /**
3166 * @brief Indicate whether the push-pull mode is enabled.
3167 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
3168 * @param HRTIMx High Resolution Timer instance
3169 * @param Timer This parameter can be one of the following values:
3170 * @arg @ref LL_HRTIM_TIMER_A
3171 * @arg @ref LL_HRTIM_TIMER_B
3172 * @arg @ref LL_HRTIM_TIMER_C
3173 * @arg @ref LL_HRTIM_TIMER_D
3174 * @arg @ref LL_HRTIM_TIMER_E
3175 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
3176 */
LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3177 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3178 {
3179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3180 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3181 REG_OFFSET_TAB_TIMER[iTimer]));
3182 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
3183 }
3184
3185 /**
3186 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
3187 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
3188 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
3189 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
3190 * @param HRTIMx High Resolution Timer instance
3191 * @param Timer This parameter can be one of the following values:
3192 * @arg @ref LL_HRTIM_TIMER_A
3193 * @arg @ref LL_HRTIM_TIMER_B
3194 * @arg @ref LL_HRTIM_TIMER_C
3195 * @arg @ref LL_HRTIM_TIMER_D
3196 * @arg @ref LL_HRTIM_TIMER_E
3197 * @param CompareUnit This parameter can be one of the following values:
3198 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3199 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3200 * @param Mode This parameter can be one of the following values:
3201 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3202 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3203 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3204 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3205 * @retval None
3206 */
LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit,uint32_t Mode)3207 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
3208 uint32_t Mode)
3209 {
3210 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3211 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3212 REG_OFFSET_TAB_TIMER[iTimer]));
3213 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3214 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
3215 }
3216
3217 /**
3218 * @brief Get the functioning mode of the compare unit.
3219 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
3220 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
3221 * @param HRTIMx High Resolution Timer instance
3222 * @param Timer This parameter can be one of the following values:
3223 * @arg @ref LL_HRTIM_TIMER_A
3224 * @arg @ref LL_HRTIM_TIMER_B
3225 * @arg @ref LL_HRTIM_TIMER_C
3226 * @arg @ref LL_HRTIM_TIMER_D
3227 * @arg @ref LL_HRTIM_TIMER_E
3228 * @param CompareUnit This parameter can be one of the following values:
3229 * @arg @ref LL_HRTIM_COMPAREUNIT_2
3230 * @arg @ref LL_HRTIM_COMPAREUNIT_4
3231 * @retval Mode Returned value can be one of the following values:
3232 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
3233 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
3234 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
3235 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
3236 */
LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareUnit)3237 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
3238 {
3239 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3240 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3241 REG_OFFSET_TAB_TIMER[iTimer]));
3242 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
3243 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
3244 }
3245
3246 /**
3247 * @brief Set the timer counter value.
3248 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
3249 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
3250 * @note This function can only be called when the timer is stopped.
3251 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
3252 * significant bits of the counter are not significant. They cannot be
3253 * written and return 0 when read.
3254 * @note The timer behavior is not guaranteed if the counter value is set above
3255 * the period.
3256 * @param HRTIMx High Resolution Timer instance
3257 * @param Timer This parameter can be one of the following values:
3258 * @arg @ref LL_HRTIM_TIMER_MASTER
3259 * @arg @ref LL_HRTIM_TIMER_A
3260 * @arg @ref LL_HRTIM_TIMER_B
3261 * @arg @ref LL_HRTIM_TIMER_C
3262 * @arg @ref LL_HRTIM_TIMER_D
3263 * @arg @ref LL_HRTIM_TIMER_E
3264 * @param Counter Value between 0 and 0xFFFF
3265 * @retval None
3266 */
LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Counter)3267 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
3268 {
3269 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3270 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3271 REG_OFFSET_TAB_TIMER[iTimer]));
3272 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
3273 }
3274
3275 /**
3276 * @brief Get actual timer counter value.
3277 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
3278 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
3279 * @param HRTIMx High Resolution Timer instance
3280 * @param Timer This parameter can be one of the following values:
3281 * @arg @ref LL_HRTIM_TIMER_MASTER
3282 * @arg @ref LL_HRTIM_TIMER_A
3283 * @arg @ref LL_HRTIM_TIMER_B
3284 * @arg @ref LL_HRTIM_TIMER_C
3285 * @arg @ref LL_HRTIM_TIMER_D
3286 * @arg @ref LL_HRTIM_TIMER_E
3287 * @retval Counter Value between 0 and 0xFFFF
3288 */
LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3289 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3290 {
3291 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3292 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
3293 REG_OFFSET_TAB_TIMER[iTimer]));
3294 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
3295 }
3296
3297 /**
3298 * @brief Set the timer period value.
3299 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
3300 * PERxR PERx LL_HRTIM_TIM_SetPeriod
3301 * @param HRTIMx High Resolution Timer instance
3302 * @param Timer This parameter can be one of the following values:
3303 * @arg @ref LL_HRTIM_TIMER_MASTER
3304 * @arg @ref LL_HRTIM_TIMER_A
3305 * @arg @ref LL_HRTIM_TIMER_B
3306 * @arg @ref LL_HRTIM_TIMER_C
3307 * @arg @ref LL_HRTIM_TIMER_D
3308 * @arg @ref LL_HRTIM_TIMER_E
3309 * @param Period Value between 0 and 0xFFFF
3310 * @retval None
3311 */
LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Period)3312 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
3313 {
3314 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3315 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3316 REG_OFFSET_TAB_TIMER[iTimer]));
3317 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
3318 }
3319
3320 /**
3321 * @brief Get actual timer period value.
3322 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
3323 * PERxR PERx LL_HRTIM_TIM_GetPeriod
3324 * @param HRTIMx High Resolution Timer instance
3325 * @param Timer This parameter can be one of the following values:
3326 * @arg @ref LL_HRTIM_TIMER_MASTER
3327 * @arg @ref LL_HRTIM_TIMER_A
3328 * @arg @ref LL_HRTIM_TIMER_B
3329 * @arg @ref LL_HRTIM_TIMER_C
3330 * @arg @ref LL_HRTIM_TIMER_D
3331 * @arg @ref LL_HRTIM_TIMER_E
3332 * @retval Period Value between 0 and 0xFFFF
3333 */
LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3334 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3335 {
3336 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3337 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
3338 REG_OFFSET_TAB_TIMER[iTimer]));
3339 return (READ_BIT(*pReg, HRTIM_MPER_MPER));
3340 }
3341
3342 /**
3343 * @brief Set the timer repetition period value.
3344 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
3345 * REPxR REPx LL_HRTIM_TIM_SetRepetition
3346 * @param HRTIMx High Resolution Timer instance
3347 * @param Timer This parameter can be one of the following values:
3348 * @arg @ref LL_HRTIM_TIMER_MASTER
3349 * @arg @ref LL_HRTIM_TIMER_A
3350 * @arg @ref LL_HRTIM_TIMER_B
3351 * @arg @ref LL_HRTIM_TIMER_C
3352 * @arg @ref LL_HRTIM_TIMER_D
3353 * @arg @ref LL_HRTIM_TIMER_E
3354 * @param Repetition Value between 0 and 0xFF
3355 * @retval None
3356 */
LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Repetition)3357 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
3358 {
3359 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3361 REG_OFFSET_TAB_TIMER[iTimer]));
3362 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
3363 }
3364
3365 /**
3366 * @brief Get actual timer repetition period value.
3367 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
3368 * REPxR REPx LL_HRTIM_TIM_GetRepetition
3369 * @param HRTIMx High Resolution Timer instance
3370 * @param Timer This parameter can be one of the following values:
3371 * @arg @ref LL_HRTIM_TIMER_MASTER
3372 * @arg @ref LL_HRTIM_TIMER_A
3373 * @arg @ref LL_HRTIM_TIMER_B
3374 * @arg @ref LL_HRTIM_TIMER_C
3375 * @arg @ref LL_HRTIM_TIMER_D
3376 * @arg @ref LL_HRTIM_TIMER_E
3377 * @retval Repetition Value between 0 and 0xFF
3378 */
LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3379 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3380 {
3381 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3382 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
3383 REG_OFFSET_TAB_TIMER[iTimer]));
3384 return (READ_BIT(*pReg, HRTIM_MREP_MREP));
3385 }
3386
3387 /**
3388 * @brief Set the compare value of the compare unit 1.
3389 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
3390 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
3391 * @param HRTIMx High Resolution Timer instance
3392 * @param Timer This parameter can be one of the following values:
3393 * @arg @ref LL_HRTIM_TIMER_MASTER
3394 * @arg @ref LL_HRTIM_TIMER_A
3395 * @arg @ref LL_HRTIM_TIMER_B
3396 * @arg @ref LL_HRTIM_TIMER_C
3397 * @arg @ref LL_HRTIM_TIMER_D
3398 * @arg @ref LL_HRTIM_TIMER_E
3399 * @param CompareValue Compare value must be above or equal to 3
3400 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3401 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3402 * @retval None
3403 */
LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3404 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3405 {
3406 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3407 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3408 REG_OFFSET_TAB_TIMER[iTimer]));
3409 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
3410 }
3411
3412 /**
3413 * @brief Get actual compare value of the compare unit 1.
3414 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
3415 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
3416 * @param HRTIMx High Resolution Timer instance
3417 * @param Timer This parameter can be one of the following values:
3418 * @arg @ref LL_HRTIM_TIMER_MASTER
3419 * @arg @ref LL_HRTIM_TIMER_A
3420 * @arg @ref LL_HRTIM_TIMER_B
3421 * @arg @ref LL_HRTIM_TIMER_C
3422 * @arg @ref LL_HRTIM_TIMER_D
3423 * @arg @ref LL_HRTIM_TIMER_E
3424 * @retval CompareValue Compare value must be above or equal to 3
3425 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3426 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3427 */
LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3428 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3429 {
3430 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3431 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
3432 REG_OFFSET_TAB_TIMER[iTimer]));
3433 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
3434 }
3435
3436 /**
3437 * @brief Set the compare value of the compare unit 2.
3438 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
3439 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
3440 * @param HRTIMx High Resolution Timer instance
3441 * @param Timer This parameter can be one of the following values:
3442 * @arg @ref LL_HRTIM_TIMER_MASTER
3443 * @arg @ref LL_HRTIM_TIMER_A
3444 * @arg @ref LL_HRTIM_TIMER_B
3445 * @arg @ref LL_HRTIM_TIMER_C
3446 * @arg @ref LL_HRTIM_TIMER_D
3447 * @arg @ref LL_HRTIM_TIMER_E
3448 * @param CompareValue Compare value must be above or equal to 3
3449 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3450 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3451 * @retval None
3452 */
LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3453 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3454 {
3455 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3456 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3457 REG_OFFSET_TAB_TIMER[iTimer]));
3458 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
3459 }
3460
3461 /**
3462 * @brief Get actual compare value of the compare unit 2.
3463 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
3464 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
3465 * @param HRTIMx High Resolution Timer instance
3466 * @param Timer This parameter can be one of the following values:
3467 * @arg @ref LL_HRTIM_TIMER_MASTER
3468 * @arg @ref LL_HRTIM_TIMER_A
3469 * @arg @ref LL_HRTIM_TIMER_B
3470 * @arg @ref LL_HRTIM_TIMER_C
3471 * @arg @ref LL_HRTIM_TIMER_D
3472 * @arg @ref LL_HRTIM_TIMER_E
3473 * @retval CompareValue Compare value must be above or equal to 3
3474 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3475 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3476 */
LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3477 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3478 {
3479 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3480 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
3481 REG_OFFSET_TAB_TIMER[iTimer]));
3482 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
3483 }
3484
3485 /**
3486 * @brief Set the compare value of the compare unit 3.
3487 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
3488 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
3489 * @param HRTIMx High Resolution Timer instance
3490 * @param Timer This parameter can be one of the following values:
3491 * @arg @ref LL_HRTIM_TIMER_MASTER
3492 * @arg @ref LL_HRTIM_TIMER_A
3493 * @arg @ref LL_HRTIM_TIMER_B
3494 * @arg @ref LL_HRTIM_TIMER_C
3495 * @arg @ref LL_HRTIM_TIMER_D
3496 * @arg @ref LL_HRTIM_TIMER_E
3497 * @param CompareValue Compare value must be above or equal to 3
3498 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3499 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3500 * @retval None
3501 */
LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3502 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3503 {
3504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3506 REG_OFFSET_TAB_TIMER[iTimer]));
3507 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
3508 }
3509
3510 /**
3511 * @brief Get actual compare value of the compare unit 3.
3512 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
3513 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
3514 * @param HRTIMx High Resolution Timer instance
3515 * @param Timer This parameter can be one of the following values:
3516 * @arg @ref LL_HRTIM_TIMER_MASTER
3517 * @arg @ref LL_HRTIM_TIMER_A
3518 * @arg @ref LL_HRTIM_TIMER_B
3519 * @arg @ref LL_HRTIM_TIMER_C
3520 * @arg @ref LL_HRTIM_TIMER_D
3521 * @arg @ref LL_HRTIM_TIMER_E
3522 * @retval CompareValue Compare value must be above or equal to 3
3523 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3524 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3525 */
LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3526 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3527 {
3528 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3529 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
3530 REG_OFFSET_TAB_TIMER[iTimer]));
3531 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
3532 }
3533
3534 /**
3535 * @brief Set the compare value of the compare unit 4.
3536 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
3537 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
3538 * @param HRTIMx High Resolution Timer instance
3539 * @param Timer This parameter can be one of the following values:
3540 * @arg @ref LL_HRTIM_TIMER_MASTER
3541 * @arg @ref LL_HRTIM_TIMER_A
3542 * @arg @ref LL_HRTIM_TIMER_B
3543 * @arg @ref LL_HRTIM_TIMER_C
3544 * @arg @ref LL_HRTIM_TIMER_D
3545 * @arg @ref LL_HRTIM_TIMER_E
3546 * @param CompareValue Compare value must be above or equal to 3
3547 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3548 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3549 * @retval None
3550 */
LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CompareValue)3551 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
3552 {
3553 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3554 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3555 REG_OFFSET_TAB_TIMER[iTimer]));
3556 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
3557 }
3558
3559 /**
3560 * @brief Get actual compare value of the compare unit 4.
3561 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
3562 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
3563 * @param HRTIMx High Resolution Timer instance
3564 * @param Timer This parameter can be one of the following values:
3565 * @arg @ref LL_HRTIM_TIMER_MASTER
3566 * @arg @ref LL_HRTIM_TIMER_A
3567 * @arg @ref LL_HRTIM_TIMER_B
3568 * @arg @ref LL_HRTIM_TIMER_C
3569 * @arg @ref LL_HRTIM_TIMER_D
3570 * @arg @ref LL_HRTIM_TIMER_E
3571 * @retval CompareValue Compare value must be above or equal to 3
3572 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
3573 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
3574 */
LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3575 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3576 {
3577 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
3578 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
3579 REG_OFFSET_TAB_TIMER[iTimer]));
3580 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
3581 }
3582
3583 /**
3584 * @brief Set the reset trigger of a timer counter.
3585 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
3586 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
3587 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
3588 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
3589 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
3590 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
3591 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
3592 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
3593 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
3594 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
3595 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
3596 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
3597 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
3598 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
3599 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
3600 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
3601 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
3602 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
3603 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
3604 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
3605 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
3606 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
3607 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
3608 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
3609 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
3610 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
3611 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
3612 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
3613 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
3614 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
3615 * @note The reset of the timer counter can be triggered by up to 30 events
3616 * that can be selected among the following sources:
3617 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
3618 * @arg The master timer: Reset and Compare 1..4 (5 events).
3619 * @arg The external events EXTEVNT1..10 (10 events).
3620 * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
3621 * @param HRTIMx High Resolution Timer instance
3622 * @param Timer This parameter can be one of the following values:
3623 * @arg @ref LL_HRTIM_TIMER_A
3624 * @arg @ref LL_HRTIM_TIMER_B
3625 * @arg @ref LL_HRTIM_TIMER_C
3626 * @arg @ref LL_HRTIM_TIMER_D
3627 * @arg @ref LL_HRTIM_TIMER_E
3628 * @param ResetTrig This parameter can be a combination of the following values:
3629 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3630 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3631 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3632 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3633 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3634 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3635 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3636 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3637 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3638 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3639 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3640 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3641 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3642 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3643 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3644 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3645 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3646 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3647 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3648 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3649 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3650 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3651 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3652 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3653 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3654 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3655 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3656 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3657 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3658 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3659 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3660 * @retval None
3661 */
LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t ResetTrig)3662 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
3663 {
3664 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3665 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3666 REG_OFFSET_TAB_TIMER[iTimer]));
3667 WRITE_REG(*pReg, ResetTrig);
3668 }
3669
3670 /**
3671 * @brief Get actual reset trigger of a timer counter.
3672 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
3673 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
3674 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
3675 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
3676 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
3677 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
3678 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
3679 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
3680 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
3681 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
3682 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
3683 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
3684 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
3685 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
3686 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
3687 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
3688 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
3689 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
3690 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
3691 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
3692 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
3693 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
3694 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
3695 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
3696 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
3697 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
3698 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
3699 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
3700 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
3701 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
3702 * @param HRTIMx High Resolution Timer instance
3703 * @param Timer This parameter can be one of the following values:
3704 * @arg @ref LL_HRTIM_TIMER_A
3705 * @arg @ref LL_HRTIM_TIMER_B
3706 * @arg @ref LL_HRTIM_TIMER_C
3707 * @arg @ref LL_HRTIM_TIMER_D
3708 * @arg @ref LL_HRTIM_TIMER_E
3709 * @retval ResetTrig Returned value can be one of the following values:
3710 * @arg @ref LL_HRTIM_RESETTRIG_NONE
3711 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
3712 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
3713 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
3714 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
3715 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
3716 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
3717 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
3718 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
3719 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
3720 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
3721 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
3722 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
3723 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
3724 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
3725 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
3726 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
3727 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
3728 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
3729 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
3730 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
3731 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
3732 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
3733 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
3734 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
3735 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
3736 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
3737 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
3738 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
3739 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
3740 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
3741 */
LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3742 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3743 {
3744 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3745 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
3746 REG_OFFSET_TAB_TIMER[iTimer]));
3747 return (READ_REG(*pReg));
3748 }
3749
3750 /**
3751 * @brief Get captured value for capture unit 1.
3752 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
3753 * @param HRTIMx High Resolution Timer instance
3754 * @param Timer This parameter can be one of the following values:
3755 * @arg @ref LL_HRTIM_TIMER_A
3756 * @arg @ref LL_HRTIM_TIMER_B
3757 * @arg @ref LL_HRTIM_TIMER_C
3758 * @arg @ref LL_HRTIM_TIMER_D
3759 * @arg @ref LL_HRTIM_TIMER_E
3760 * @retval Captured value
3761 */
LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3762 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3763 {
3764 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3765 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
3766 REG_OFFSET_TAB_TIMER[iTimer]));
3767 return (READ_REG(*pReg));
3768 }
3769
3770 /**
3771 * @brief Get captured value for capture unit 2.
3772 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
3773 * @param HRTIMx High Resolution Timer instance
3774 * @param Timer This parameter can be one of the following values:
3775 * @arg @ref LL_HRTIM_TIMER_A
3776 * @arg @ref LL_HRTIM_TIMER_B
3777 * @arg @ref LL_HRTIM_TIMER_C
3778 * @arg @ref LL_HRTIM_TIMER_D
3779 * @arg @ref LL_HRTIM_TIMER_E
3780 * @retval Captured value
3781 */
LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)3782 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3783 {
3784 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3785 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
3786 REG_OFFSET_TAB_TIMER[iTimer]));
3787 return (READ_REG(*pReg));
3788 }
3789
3790 /**
3791 * @brief Set the trigger of a capture unit for a given timer.
3792 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
3793 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
3794 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
3795 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
3796 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
3797 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
3798 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
3799 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
3800 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
3801 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
3802 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
3803 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
3804 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
3805 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
3806 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3807 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3808 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
3809 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
3810 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3811 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3812 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
3813 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
3814 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3815 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3816 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
3817 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
3818 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3819 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
3820 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
3821 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
3822 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
3823 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
3824 * @param HRTIMx High Resolution Timer instance
3825 * @param Timer This parameter can be one of the following values:
3826 * @arg @ref LL_HRTIM_TIMER_A
3827 * @arg @ref LL_HRTIM_TIMER_B
3828 * @arg @ref LL_HRTIM_TIMER_C
3829 * @arg @ref LL_HRTIM_TIMER_D
3830 * @arg @ref LL_HRTIM_TIMER_E
3831 * @param CaptureUnit This parameter can be one of the following values:
3832 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3833 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3834 * @param CaptureTrig This parameter can be a combination of the following values:
3835 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3836 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3837 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3838 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3839 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3840 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3841 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
3842 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
3843 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
3844 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
3845 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
3846 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
3847 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
3848 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
3849 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
3850 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
3851 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
3852 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
3853 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
3854 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
3855 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
3856 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
3857 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
3858 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
3859 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
3860 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
3861 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
3862 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
3863 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
3864 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
3865 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
3866 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
3867 * @retval None
3868 */
LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit,uint32_t CaptureTrig)3869 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
3870 uint32_t CaptureTrig)
3871 {
3872 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3873 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
3874 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
3875 WRITE_REG(*pReg, CaptureTrig);
3876 }
3877
3878 /**
3879 * @brief Get actual trigger of a capture unit for a given timer.
3880 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
3881 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
3882 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
3883 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
3884 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
3885 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
3886 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
3887 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
3888 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
3889 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
3890 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
3891 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
3892 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
3893 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
3894 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3895 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3896 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
3897 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
3898 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3899 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3900 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
3901 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
3902 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3903 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3904 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
3905 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
3906 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3907 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
3908 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
3909 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
3910 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
3911 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
3912 * @param HRTIMx High Resolution Timer instance
3913 * @param Timer This parameter can be one of the following values:
3914 * @arg @ref LL_HRTIM_TIMER_A
3915 * @arg @ref LL_HRTIM_TIMER_B
3916 * @arg @ref LL_HRTIM_TIMER_C
3917 * @arg @ref LL_HRTIM_TIMER_D
3918 * @arg @ref LL_HRTIM_TIMER_E
3919 * @param CaptureUnit This parameter can be one of the following values:
3920 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
3921 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
3922 * @retval CaptureTrig This parameter can be a combination of the following values:
3923 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
3924 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
3925 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
3926 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
3927 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
3928 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
3929 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
3930 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
3931 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
3932 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
3933 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
3934 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
3935 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
3936 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
3937 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
3938 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
3939 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
3940 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
3941 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
3942 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
3943 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
3944 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
3945 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
3946 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
3947 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
3948 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
3949 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
3950 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
3951 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
3952 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
3953 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
3954 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
3955 */
LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t CaptureUnit)3956 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
3957 {
3958 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3959 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
3960 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
3961 return (READ_REG(*pReg));
3962 }
3963
3964 /**
3965 * @brief Enable deadtime insertion for a given timer.
3966 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
3967 * @param HRTIMx High Resolution Timer instance
3968 * @param Timer This parameter can be one of the following values:
3969 * @arg @ref LL_HRTIM_TIMER_A
3970 * @arg @ref LL_HRTIM_TIMER_B
3971 * @arg @ref LL_HRTIM_TIMER_C
3972 * @arg @ref LL_HRTIM_TIMER_D
3973 * @arg @ref LL_HRTIM_TIMER_E
3974 * @retval None
3975 */
LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3976 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3977 {
3978 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3979 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
3980 REG_OFFSET_TAB_TIMER[iTimer]));
3981 SET_BIT(*pReg, HRTIM_OUTR_DTEN);
3982 }
3983
3984 /**
3985 * @brief Disable deadtime insertion for a given timer.
3986 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
3987 * @param HRTIMx High Resolution Timer instance
3988 * @param Timer This parameter can be one of the following values:
3989 * @arg @ref LL_HRTIM_TIMER_A
3990 * @arg @ref LL_HRTIM_TIMER_B
3991 * @arg @ref LL_HRTIM_TIMER_C
3992 * @arg @ref LL_HRTIM_TIMER_D
3993 * @arg @ref LL_HRTIM_TIMER_E
3994 * @retval None
3995 */
LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef * HRTIMx,uint32_t Timer)3996 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3997 {
3998 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
3999 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4000 REG_OFFSET_TAB_TIMER[iTimer]));
4001 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
4002 }
4003
4004 /**
4005 * @brief Indicate whether deadtime insertion is enabled for a given timer.
4006 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
4007 * @param HRTIMx High Resolution Timer instance
4008 * @param Timer This parameter can be one of the following values:
4009 * @arg @ref LL_HRTIM_TIMER_A
4010 * @arg @ref LL_HRTIM_TIMER_B
4011 * @arg @ref LL_HRTIM_TIMER_C
4012 * @arg @ref LL_HRTIM_TIMER_D
4013 * @arg @ref LL_HRTIM_TIMER_E
4014 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
4015 */
LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4016 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4017 {
4018 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4019 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4020 REG_OFFSET_TAB_TIMER[iTimer]));
4021
4022 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
4023 }
4024
4025 /**
4026 * @brief Set the delayed protection (DLYPRT) mode.
4027 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
4028 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
4029 * @note This function must be called prior enabling the delayed protection
4030 * @note Balanced Idle mode is only available in push-pull mode
4031 * @param HRTIMx High Resolution Timer instance
4032 * @param Timer This parameter can be one of the following values:
4033 * @arg @ref LL_HRTIM_TIMER_A
4034 * @arg @ref LL_HRTIM_TIMER_B
4035 * @arg @ref LL_HRTIM_TIMER_C
4036 * @arg @ref LL_HRTIM_TIMER_D
4037 * @arg @ref LL_HRTIM_TIMER_E
4038 * @param DLYPRTMode Delayed protection (DLYPRT) mode
4039 *
4040 * For timers A, B and C this parameter can be one of the following values:
4041 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4042 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4043 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4044 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4045 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4046 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4047 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4048 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4049 *
4050 * For timers D and E this parameter can be one of the following values:
4051 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4052 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4053 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4054 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4055 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4056 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4057 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4058 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4059 * @retval None
4060 */
LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DLYPRTMode)4061 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
4062 {
4063 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4064 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4065 REG_OFFSET_TAB_TIMER[iTimer]));
4066 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
4067 }
4068
4069 /**
4070 * @brief Get the delayed protection (DLYPRT) mode.
4071 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
4072 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
4073 * @param HRTIMx High Resolution Timer instance
4074 * @param Timer This parameter can be one of the following values:
4075 * @arg @ref LL_HRTIM_TIMER_A
4076 * @arg @ref LL_HRTIM_TIMER_B
4077 * @arg @ref LL_HRTIM_TIMER_C
4078 * @arg @ref LL_HRTIM_TIMER_D
4079 * @arg @ref LL_HRTIM_TIMER_E
4080 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
4081 *
4082 * For timers A, B and C this parameter can be one of the following values:
4083 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
4084 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
4085 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
4086 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
4087 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
4088 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
4089 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
4090 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
4091 *
4092 * For timers D and E this parameter can be one of the following values:
4093 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
4094 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
4095 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
4096 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
4097 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
4098 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
4099 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
4100 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
4101 */
LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4102 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4103 {
4104 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4105 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4106 REG_OFFSET_TAB_TIMER[iTimer]));
4107 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
4108 }
4109
4110 /**
4111 * @brief Enable delayed protection (DLYPRT) for a given timer.
4112 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
4113 * @note This function must not be called once the concerned timer is enabled
4114 * @param HRTIMx High Resolution Timer instance
4115 * @param Timer This parameter can be one of the following values:
4116 * @arg @ref LL_HRTIM_TIMER_A
4117 * @arg @ref LL_HRTIM_TIMER_B
4118 * @arg @ref LL_HRTIM_TIMER_C
4119 * @arg @ref LL_HRTIM_TIMER_D
4120 * @arg @ref LL_HRTIM_TIMER_E
4121 * @retval None
4122 */
LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4123 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4124 {
4125 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4126 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4127 REG_OFFSET_TAB_TIMER[iTimer]));
4128 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
4129 }
4130
4131 /**
4132 * @brief Disable delayed protection (DLYPRT) for a given timer.
4133 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
4134 * @note This function must not be called once the concerned timer is enabled
4135 * @param HRTIMx High Resolution Timer instance
4136 * @param Timer This parameter can be one of the following values:
4137 * @arg @ref LL_HRTIM_TIMER_A
4138 * @arg @ref LL_HRTIM_TIMER_B
4139 * @arg @ref LL_HRTIM_TIMER_C
4140 * @arg @ref LL_HRTIM_TIMER_D
4141 * @arg @ref LL_HRTIM_TIMER_E
4142 * @retval None
4143 */
LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4144 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4145 {
4146 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4147 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4148 REG_OFFSET_TAB_TIMER[iTimer]));
4149 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
4150 }
4151
4152 /**
4153 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
4154 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
4155 * @param HRTIMx High Resolution Timer instance
4156 * @param Timer This parameter can be one of the following values:
4157 * @arg @ref LL_HRTIM_TIMER_A
4158 * @arg @ref LL_HRTIM_TIMER_B
4159 * @arg @ref LL_HRTIM_TIMER_C
4160 * @arg @ref LL_HRTIM_TIMER_D
4161 * @arg @ref LL_HRTIM_TIMER_E
4162 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
4163 */
LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4164 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4165 {
4166 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4167 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
4168 REG_OFFSET_TAB_TIMER[iTimer]));
4169 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
4170 }
4171
4172 /**
4173 * @brief Enable the fault channel(s) for a given timer.
4174 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
4175 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
4176 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
4177 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
4178 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
4179 * @param HRTIMx High Resolution Timer instance
4180 * @param Timer This parameter can be one of the following values:
4181 * @arg @ref LL_HRTIM_TIMER_A
4182 * @arg @ref LL_HRTIM_TIMER_B
4183 * @arg @ref LL_HRTIM_TIMER_C
4184 * @arg @ref LL_HRTIM_TIMER_D
4185 * @arg @ref LL_HRTIM_TIMER_E
4186 * @param Faults This parameter can be a combination of the following values:
4187 * @arg @ref LL_HRTIM_FAULT_1
4188 * @arg @ref LL_HRTIM_FAULT_2
4189 * @arg @ref LL_HRTIM_FAULT_3
4190 * @arg @ref LL_HRTIM_FAULT_4
4191 * @arg @ref LL_HRTIM_FAULT_5
4192 * @retval None
4193 */
LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)4194 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4195 {
4196 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4197 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4198 REG_OFFSET_TAB_TIMER[iTimer]));
4199 SET_BIT(*pReg, Faults);
4200 }
4201
4202 /**
4203 * @brief Disable the fault channel(s) for a given timer.
4204 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
4205 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
4206 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
4207 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
4208 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
4209 * @param HRTIMx High Resolution Timer instance
4210 * @param Timer This parameter can be one of the following values:
4211 * @arg @ref LL_HRTIM_TIMER_A
4212 * @arg @ref LL_HRTIM_TIMER_B
4213 * @arg @ref LL_HRTIM_TIMER_C
4214 * @arg @ref LL_HRTIM_TIMER_D
4215 * @arg @ref LL_HRTIM_TIMER_E
4216 * @param Faults This parameter can be a combination of the following values:
4217 * @arg @ref LL_HRTIM_FAULT_1
4218 * @arg @ref LL_HRTIM_FAULT_2
4219 * @arg @ref LL_HRTIM_FAULT_3
4220 * @arg @ref LL_HRTIM_FAULT_4
4221 * @arg @ref LL_HRTIM_FAULT_5
4222 * @retval None
4223 */
LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Faults)4224 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
4225 {
4226 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4227 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4228 REG_OFFSET_TAB_TIMER[iTimer]));
4229 CLEAR_BIT(*pReg, Faults);
4230 }
4231
4232 /**
4233 * @brief Indicate whether the fault channel is enabled for a given timer.
4234 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
4235 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
4236 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
4237 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
4238 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
4239 * @param HRTIMx High Resolution Timer instance
4240 * @param Timer This parameter can be one of the following values:
4241 * @arg @ref LL_HRTIM_TIMER_A
4242 * @arg @ref LL_HRTIM_TIMER_B
4243 * @arg @ref LL_HRTIM_TIMER_C
4244 * @arg @ref LL_HRTIM_TIMER_D
4245 * @arg @ref LL_HRTIM_TIMER_E
4246 * @param Fault This parameter can be one of the following values:
4247 * @arg @ref LL_HRTIM_FAULT_1
4248 * @arg @ref LL_HRTIM_FAULT_2
4249 * @arg @ref LL_HRTIM_FAULT_3
4250 * @arg @ref LL_HRTIM_FAULT_4
4251 * @arg @ref LL_HRTIM_FAULT_5
4252 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
4253 */
LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Fault)4254 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
4255 {
4256 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4257 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4258 REG_OFFSET_TAB_TIMER[iTimer]));
4259
4260 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
4261 }
4262
4263 /**
4264 * @brief Lock the fault conditioning set-up for a given timer.
4265 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
4266 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
4267 * @param HRTIMx High Resolution Timer instance
4268 * @param Timer This parameter can be one of the following values:
4269 * @arg @ref LL_HRTIM_TIMER_A
4270 * @arg @ref LL_HRTIM_TIMER_B
4271 * @arg @ref LL_HRTIM_TIMER_C
4272 * @arg @ref LL_HRTIM_TIMER_D
4273 * @arg @ref LL_HRTIM_TIMER_E
4274 * @retval None
4275 */
LL_HRTIM_TIM_LockFault(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4276 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4277 {
4278 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4279 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
4280 REG_OFFSET_TAB_TIMER[iTimer]));
4281 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
4282 }
4283
4284 /**
4285 * @brief Define how the timer behaves during a burst mode operation.
4286 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
4287 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
4288 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
4289 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
4290 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
4291 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
4292 * @note This function must not be called when the burst mode is enabled
4293 * @param HRTIMx High Resolution Timer instance
4294 * @param Timer This parameter can be one of the following values:
4295 * @arg @ref LL_HRTIM_TIMER_MASTER
4296 * @arg @ref LL_HRTIM_TIMER_A
4297 * @arg @ref LL_HRTIM_TIMER_B
4298 * @arg @ref LL_HRTIM_TIMER_C
4299 * @arg @ref LL_HRTIM_TIMER_D
4300 * @arg @ref LL_HRTIM_TIMER_E
4301 * @param BurtsModeOption This parameter can be one of the following values:
4302 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4303 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4304 * @retval None
4305 */
LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t BurtsModeOption)4306 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
4307 {
4308 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
4309 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
4310 }
4311
4312 /**
4313 * @brief Retrieve how the timer behaves during a burst mode operation.
4314 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
4315 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
4316 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
4317 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
4318 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
4319 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
4320 * @param HRTIMx High Resolution Timer instance
4321 * @param Timer This parameter can be one of the following values:
4322 * @arg @ref LL_HRTIM_TIMER_MASTER
4323 * @arg @ref LL_HRTIM_TIMER_A
4324 * @arg @ref LL_HRTIM_TIMER_B
4325 * @arg @ref LL_HRTIM_TIMER_C
4326 * @arg @ref LL_HRTIM_TIMER_D
4327 * @arg @ref LL_HRTIM_TIMER_E
4328 * @retval BurtsMode This parameter can be one of the following values:
4329 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
4330 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
4331 */
LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4332 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4333 {
4334 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
4335 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
4336 }
4337
4338 /**
4339 * @brief Program which registers are to be written by Burst DMA transfers.
4340 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
4341 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
4342 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4343 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4344 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
4345 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
4346 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4347 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4348 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4349 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4350 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
4351 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
4352 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
4353 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
4354 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
4355 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
4356 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
4357 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
4358 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
4359 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
4360 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
4361 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
4362 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
4363 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
4364 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
4365 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
4366 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
4367 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
4368 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
4369 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
4370 * @param HRTIMx High Resolution Timer instance
4371 * @param Timer This parameter can be one of the following values:
4372 * @arg @ref LL_HRTIM_TIMER_MASTER
4373 * @arg @ref LL_HRTIM_TIMER_A
4374 * @arg @ref LL_HRTIM_TIMER_B
4375 * @arg @ref LL_HRTIM_TIMER_C
4376 * @arg @ref LL_HRTIM_TIMER_D
4377 * @arg @ref LL_HRTIM_TIMER_E
4378 * @param Registers Registers to be updated by the DMA request
4379 *
4380 * For Master timer this parameter can be can be a combination of the following values:
4381 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4382 * @arg @ref LL_HRTIM_BURSTDMA_MCR
4383 * @arg @ref LL_HRTIM_BURSTDMA_MICR
4384 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
4385 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
4386 * @arg @ref LL_HRTIM_BURSTDMA_MPER
4387 * @arg @ref LL_HRTIM_BURSTDMA_MREP
4388 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
4389 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
4390 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
4391 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
4392 *
4393 * For Timers A..E this parameter can be can be a combination of the following values:
4394 * @arg @ref LL_HRTIM_BURSTDMA_NONE
4395 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
4396 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
4397 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
4398 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
4399 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
4400 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
4401 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
4402 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
4403 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
4404 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
4405 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
4406 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
4407 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
4408 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
4409 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
4410 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
4411 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
4412 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
4413 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
4414 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
4415 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
4416 * @retval None
4417 */
LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Registers)4418 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
4419 {
4420
4421 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4422 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));
4423 WRITE_REG(*pReg, Registers);
4424 }
4425
4426 /**
4427 * @brief Indicate on which output the signal is currently applied.
4428 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
4429 * @note Only significant when the timer operates in push-pull mode.
4430 * @param HRTIMx High Resolution Timer instance
4431 * @param Timer This parameter can be one of the following values:
4432 * @arg @ref LL_HRTIM_TIMER_A
4433 * @arg @ref LL_HRTIM_TIMER_B
4434 * @arg @ref LL_HRTIM_TIMER_C
4435 * @arg @ref LL_HRTIM_TIMER_D
4436 * @arg @ref LL_HRTIM_TIMER_E
4437 * @retval CPPSTAT This parameter can be one of the following values:
4438 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
4439 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
4440 */
LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4441 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4442 {
4443 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4444 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4445 REG_OFFSET_TAB_TIMER[iTimer]));
4446 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
4447 }
4448
4449 /**
4450 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
4451 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
4452 * @param HRTIMx High Resolution Timer instance
4453 * @param Timer This parameter can be one of the following values:
4454 * @arg @ref LL_HRTIM_TIMER_A
4455 * @arg @ref LL_HRTIM_TIMER_B
4456 * @arg @ref LL_HRTIM_TIMER_C
4457 * @arg @ref LL_HRTIM_TIMER_D
4458 * @arg @ref LL_HRTIM_TIMER_E
4459 * @retval IPPSTAT This parameter can be one of the following values:
4460 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
4461 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
4462 */
LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4463 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4464 {
4465 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
4466 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
4467 REG_OFFSET_TAB_TIMER[iTimer]));
4468 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
4469 }
4470
4471 /**
4472 * @brief Set the event filter for a given timer.
4473 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
4474 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
4475 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
4476 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
4477 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
4478 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
4479 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
4480 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
4481 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
4482 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
4483 * @note This function must not be called when the timer counter is enabled.
4484 * @param HRTIMx High Resolution Timer instance
4485 * @param Timer This parameter can be one of the following values:
4486 * @arg @ref LL_HRTIM_TIMER_A
4487 * @arg @ref LL_HRTIM_TIMER_B
4488 * @arg @ref LL_HRTIM_TIMER_C
4489 * @arg @ref LL_HRTIM_TIMER_D
4490 * @arg @ref LL_HRTIM_TIMER_E
4491 * @param Event This parameter can be one of the following values:
4492 * @arg @ref LL_HRTIM_EVENT_1
4493 * @arg @ref LL_HRTIM_EVENT_2
4494 * @arg @ref LL_HRTIM_EVENT_3
4495 * @arg @ref LL_HRTIM_EVENT_4
4496 * @arg @ref LL_HRTIM_EVENT_5
4497 * @arg @ref LL_HRTIM_EVENT_6
4498 * @arg @ref LL_HRTIM_EVENT_7
4499 * @arg @ref LL_HRTIM_EVENT_8
4500 * @arg @ref LL_HRTIM_EVENT_9
4501 * @arg @ref LL_HRTIM_EVENT_10
4502 * @param Filter This parameter can be one of the following values:
4503 * @arg @ref LL_HRTIM_EEFLTR_NONE
4504 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4505 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4506 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4507 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4508 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4509 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4510 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4511 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4512 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4513 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4514 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4515 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4516 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4517 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4518 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4519
4520 * @retval None
4521 */
LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t Filter)4522 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
4523 {
4524 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4525 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4526 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4527 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4528 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
4529 }
4530
4531 /**
4532 * @brief Get actual event filter settings for a given timer.
4533 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
4534 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
4535 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
4536 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
4537 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
4538 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
4539 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
4540 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
4541 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
4542 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
4543 * @param HRTIMx High Resolution Timer instance
4544 * @param Timer This parameter can be one of the following values:
4545 * @arg @ref LL_HRTIM_TIMER_A
4546 * @arg @ref LL_HRTIM_TIMER_B
4547 * @arg @ref LL_HRTIM_TIMER_C
4548 * @arg @ref LL_HRTIM_TIMER_D
4549 * @arg @ref LL_HRTIM_TIMER_E
4550 * @param Event This parameter can be one of the following values:
4551 * @arg @ref LL_HRTIM_EVENT_1
4552 * @arg @ref LL_HRTIM_EVENT_2
4553 * @arg @ref LL_HRTIM_EVENT_3
4554 * @arg @ref LL_HRTIM_EVENT_4
4555 * @arg @ref LL_HRTIM_EVENT_5
4556 * @arg @ref LL_HRTIM_EVENT_6
4557 * @arg @ref LL_HRTIM_EVENT_7
4558 * @arg @ref LL_HRTIM_EVENT_8
4559 * @arg @ref LL_HRTIM_EVENT_9
4560 * @arg @ref LL_HRTIM_EVENT_10
4561 * @retval Filter This parameter can be one of the following values:
4562 * @arg @ref LL_HRTIM_EEFLTR_NONE
4563 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
4564 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
4565 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
4566 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
4567 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
4568 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
4569 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
4570 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
4571 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
4572 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
4573 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
4574 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
4575 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
4576 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
4577 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
4578 */
LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)4579 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4580 {
4581 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4582 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4583 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4584 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4585 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4586 }
4587
4588 /**
4589 * @brief Enable or disable event latch mechanism for a given timer.
4590 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4591 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4592 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4593 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4594 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4595 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4596 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4597 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4598 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
4599 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
4600 * @note This function must not be called when the timer counter is enabled.
4601 * @param HRTIMx High Resolution Timer instance
4602 * @param Timer This parameter can be one of the following values:
4603 * @arg @ref LL_HRTIM_TIMER_A
4604 * @arg @ref LL_HRTIM_TIMER_B
4605 * @arg @ref LL_HRTIM_TIMER_C
4606 * @arg @ref LL_HRTIM_TIMER_D
4607 * @arg @ref LL_HRTIM_TIMER_E
4608 * @param Event This parameter can be one of the following values:
4609 * @arg @ref LL_HRTIM_EVENT_1
4610 * @arg @ref LL_HRTIM_EVENT_2
4611 * @arg @ref LL_HRTIM_EVENT_3
4612 * @arg @ref LL_HRTIM_EVENT_4
4613 * @arg @ref LL_HRTIM_EVENT_5
4614 * @arg @ref LL_HRTIM_EVENT_6
4615 * @arg @ref LL_HRTIM_EVENT_7
4616 * @arg @ref LL_HRTIM_EVENT_8
4617 * @arg @ref LL_HRTIM_EVENT_9
4618 * @arg @ref LL_HRTIM_EVENT_10
4619 * @param LatchStatus This parameter can be one of the following values:
4620 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4621 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4622 * @retval None
4623 */
LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event,uint32_t LatchStatus)4624 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
4625 uint32_t LatchStatus)
4626 {
4627 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4628 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4629 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4630 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4631 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
4632 }
4633
4634 /**
4635 * @brief Get actual event latch status for a given timer.
4636 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4637 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4638 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4639 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4640 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4641 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4642 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4643 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4644 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
4645 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
4646 * @param HRTIMx High Resolution Timer instance
4647 * @param Timer This parameter can be one of the following values:
4648 * @arg @ref LL_HRTIM_TIMER_A
4649 * @arg @ref LL_HRTIM_TIMER_B
4650 * @arg @ref LL_HRTIM_TIMER_C
4651 * @arg @ref LL_HRTIM_TIMER_D
4652 * @arg @ref LL_HRTIM_TIMER_E
4653 * @param Event This parameter can be one of the following values:
4654 * @arg @ref LL_HRTIM_EVENT_1
4655 * @arg @ref LL_HRTIM_EVENT_2
4656 * @arg @ref LL_HRTIM_EVENT_3
4657 * @arg @ref LL_HRTIM_EVENT_4
4658 * @arg @ref LL_HRTIM_EVENT_5
4659 * @arg @ref LL_HRTIM_EVENT_6
4660 * @arg @ref LL_HRTIM_EVENT_7
4661 * @arg @ref LL_HRTIM_EVENT_8
4662 * @arg @ref LL_HRTIM_EVENT_9
4663 * @arg @ref LL_HRTIM_EVENT_10
4664 * @retval LatchStatus This parameter can be one of the following values:
4665 * @arg @ref LL_HRTIM_EELATCH_DISABLED
4666 * @arg @ref LL_HRTIM_EELATCH_ENABLED
4667 */
LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Event)4668 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
4669 {
4670 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
4671 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
4672 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
4673 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
4674 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
4675 }
4676
4677 /**
4678 * @}
4679 */
4680
4681 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
4682 * @{
4683 */
4684
4685 /**
4686 * @brief Configure the dead time insertion feature for a given timer.
4687 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
4688 * DTxR SDTF LL_HRTIM_DT_Config\n
4689 * DTxR SDRT LL_HRTIM_DT_Config
4690 * @param HRTIMx High Resolution Timer instance
4691 * @param Timer This parameter can be one of the following values:
4692 * @arg @ref LL_HRTIM_TIMER_A
4693 * @arg @ref LL_HRTIM_TIMER_B
4694 * @arg @ref LL_HRTIM_TIMER_C
4695 * @arg @ref LL_HRTIM_TIMER_D
4696 * @arg @ref LL_HRTIM_TIMER_E
4697 * @param Configuration This parameter must be a combination of all the following values:
4698 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
4699 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
4700 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
4701 * @retval None
4702 */
LL_HRTIM_DT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)4703 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
4704 {
4705 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4706 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4707 REG_OFFSET_TAB_TIMER[iTimer]));
4708 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
4709 }
4710
4711 /**
4712 * @brief Set the deadtime prescaler value.
4713 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
4714 * @param HRTIMx High Resolution Timer instance
4715 * @param Timer This parameter can be one of the following values:
4716 * @arg @ref LL_HRTIM_TIMER_A
4717 * @arg @ref LL_HRTIM_TIMER_B
4718 * @arg @ref LL_HRTIM_TIMER_C
4719 * @arg @ref LL_HRTIM_TIMER_D
4720 * @arg @ref LL_HRTIM_TIMER_E
4721 * @param Prescaler This parameter can be one of the following values:
4722 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4723 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4724 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4725 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4726 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4727 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4728 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4729 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4730 * @retval None
4731 */
LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)4732 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
4733 {
4734 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4735 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4736 REG_OFFSET_TAB_TIMER[iTimer]));
4737 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
4738 }
4739
4740 /**
4741 * @brief Get actual deadtime prescaler value.
4742 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
4743 * @param HRTIMx High Resolution Timer instance
4744 * @param Timer This parameter can be one of the following values:
4745 * @arg @ref LL_HRTIM_TIMER_A
4746 * @arg @ref LL_HRTIM_TIMER_B
4747 * @arg @ref LL_HRTIM_TIMER_C
4748 * @arg @ref LL_HRTIM_TIMER_D
4749 * @arg @ref LL_HRTIM_TIMER_E
4750 * @retval Prescaler This parameter can be one of the following values:
4751 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
4752 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
4753 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
4754 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
4755 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
4756 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
4757 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
4758 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
4759 */
LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4760 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4761 {
4762 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4763 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4764 REG_OFFSET_TAB_TIMER[iTimer]));
4765 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
4766 }
4767
4768 /**
4769 * @brief Set the deadtime rising value.
4770 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
4771 * @param HRTIMx High Resolution Timer instance
4772 * @param Timer This parameter can be one of the following values:
4773 * @arg @ref LL_HRTIM_TIMER_A
4774 * @arg @ref LL_HRTIM_TIMER_B
4775 * @arg @ref LL_HRTIM_TIMER_C
4776 * @arg @ref LL_HRTIM_TIMER_D
4777 * @arg @ref LL_HRTIM_TIMER_E
4778 * @param RisingValue Value between 0 and 0x1FF
4779 * @retval None
4780 */
LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingValue)4781 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
4782 {
4783 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4784 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4785 REG_OFFSET_TAB_TIMER[iTimer]));
4786 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
4787 }
4788
4789 /**
4790 * @brief Get actual deadtime rising value.
4791 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
4792 * @param HRTIMx High Resolution Timer instance
4793 * @param Timer This parameter can be one of the following values:
4794 * @arg @ref LL_HRTIM_TIMER_A
4795 * @arg @ref LL_HRTIM_TIMER_B
4796 * @arg @ref LL_HRTIM_TIMER_C
4797 * @arg @ref LL_HRTIM_TIMER_D
4798 * @arg @ref LL_HRTIM_TIMER_E
4799 * @retval RisingValue Value between 0 and 0x1FF
4800 */
LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4801 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4802 {
4803 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4804 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4805 REG_OFFSET_TAB_TIMER[iTimer]));
4806 return (READ_BIT(*pReg, HRTIM_DTR_DTR));
4807 }
4808
4809 /**
4810 * @brief Set the deadtime sign on rising edge.
4811 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
4812 * @param HRTIMx High Resolution Timer instance
4813 * @param Timer This parameter can be one of the following values:
4814 * @arg @ref LL_HRTIM_TIMER_A
4815 * @arg @ref LL_HRTIM_TIMER_B
4816 * @arg @ref LL_HRTIM_TIMER_C
4817 * @arg @ref LL_HRTIM_TIMER_D
4818 * @arg @ref LL_HRTIM_TIMER_E
4819 * @param RisingSign This parameter can be one of the following values:
4820 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4821 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4822 * @retval None
4823 */
LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t RisingSign)4824 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
4825 {
4826 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4827 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4828 REG_OFFSET_TAB_TIMER[iTimer]));
4829 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
4830 }
4831
4832 /**
4833 * @brief Get actual deadtime sign on rising edge.
4834 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
4835 * @param HRTIMx High Resolution Timer instance
4836 * @param Timer This parameter can be one of the following values:
4837 * @arg @ref LL_HRTIM_TIMER_A
4838 * @arg @ref LL_HRTIM_TIMER_B
4839 * @arg @ref LL_HRTIM_TIMER_C
4840 * @arg @ref LL_HRTIM_TIMER_D
4841 * @arg @ref LL_HRTIM_TIMER_E
4842 * @retval RisingSign This parameter can be one of the following values:
4843 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
4844 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
4845 */
LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4846 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4847 {
4848 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4849 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4850 REG_OFFSET_TAB_TIMER[iTimer]));
4851 return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
4852 }
4853
4854 /**
4855 * @brief Set the deadime falling value.
4856 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
4857 * @param HRTIMx High Resolution Timer instance
4858 * @param Timer This parameter can be one of the following values:
4859 * @arg @ref LL_HRTIM_TIMER_A
4860 * @arg @ref LL_HRTIM_TIMER_B
4861 * @arg @ref LL_HRTIM_TIMER_C
4862 * @arg @ref LL_HRTIM_TIMER_D
4863 * @arg @ref LL_HRTIM_TIMER_E
4864 * @param FallingValue Value between 0 and 0x1FF
4865 * @retval None
4866 */
LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingValue)4867 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
4868 {
4869 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4870 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4871 REG_OFFSET_TAB_TIMER[iTimer]));
4872 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
4873 }
4874
4875 /**
4876 * @brief Get actual deadtime falling value
4877 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
4878 * @param HRTIMx High Resolution Timer instance
4879 * @param Timer This parameter can be one of the following values:
4880 * @arg @ref LL_HRTIM_TIMER_A
4881 * @arg @ref LL_HRTIM_TIMER_B
4882 * @arg @ref LL_HRTIM_TIMER_C
4883 * @arg @ref LL_HRTIM_TIMER_D
4884 * @arg @ref LL_HRTIM_TIMER_E
4885 * @retval FallingValue Value between 0 and 0x1FF
4886 */
LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4887 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4888 {
4889 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4890 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4891 REG_OFFSET_TAB_TIMER[iTimer]));
4892 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
4893 }
4894
4895 /**
4896 * @brief Set the deadtime sign on falling edge.
4897 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
4898 * @param HRTIMx High Resolution Timer instance
4899 * @param Timer This parameter can be one of the following values:
4900 * @arg @ref LL_HRTIM_TIMER_A
4901 * @arg @ref LL_HRTIM_TIMER_B
4902 * @arg @ref LL_HRTIM_TIMER_C
4903 * @arg @ref LL_HRTIM_TIMER_D
4904 * @arg @ref LL_HRTIM_TIMER_E
4905 * @param FallingSign This parameter can be one of the following values:
4906 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
4907 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
4908 * @retval None
4909 */
LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t FallingSign)4910 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
4911 {
4912 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4913 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4914 REG_OFFSET_TAB_TIMER[iTimer]));
4915 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
4916 }
4917
4918 /**
4919 * @brief Get actual deadtime sign on falling edge.
4920 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
4921 * @param HRTIMx High Resolution Timer instance
4922 * @param Timer This parameter can be one of the following values:
4923 * @arg @ref LL_HRTIM_TIMER_A
4924 * @arg @ref LL_HRTIM_TIMER_B
4925 * @arg @ref LL_HRTIM_TIMER_C
4926 * @arg @ref LL_HRTIM_TIMER_D
4927 * @arg @ref LL_HRTIM_TIMER_E
4928 * @retval FallingSign This parameter can be one of the following values:
4929 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
4930 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
4931 */
LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4932 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4933 {
4934 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4935 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4936 REG_OFFSET_TAB_TIMER[iTimer]));
4937 return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
4938 }
4939
4940 /**
4941 * @brief Lock the deadtime value and sign on rising edge.
4942 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
4943 * @param HRTIMx High Resolution Timer instance
4944 * @param Timer This parameter can be one of the following values:
4945 * @arg @ref LL_HRTIM_TIMER_A
4946 * @arg @ref LL_HRTIM_TIMER_B
4947 * @arg @ref LL_HRTIM_TIMER_C
4948 * @arg @ref LL_HRTIM_TIMER_D
4949 * @arg @ref LL_HRTIM_TIMER_E
4950 * @retval None
4951 */
LL_HRTIM_DT_LockRising(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)4952 __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4953 {
4954 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4955 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4956 REG_OFFSET_TAB_TIMER[iTimer]));
4957 SET_BIT(*pReg, HRTIM_DTR_DTRLK);
4958 }
4959
4960 /**
4961 * @brief Lock the deadtime sign on rising edge.
4962 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
4963 * @param HRTIMx High Resolution Timer instance
4964 * @param Timer This parameter can be one of the following values:
4965 * @arg @ref LL_HRTIM_TIMER_A
4966 * @arg @ref LL_HRTIM_TIMER_B
4967 * @arg @ref LL_HRTIM_TIMER_C
4968 * @arg @ref LL_HRTIM_TIMER_D
4969 * @arg @ref LL_HRTIM_TIMER_E
4970 * @retval None
4971 */
LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4972 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4973 {
4974 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4975 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4976 REG_OFFSET_TAB_TIMER[iTimer]));
4977 SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
4978 }
4979
4980 /**
4981 * @brief Lock the deadtime value and sign on falling edge.
4982 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
4983 * @param HRTIMx High Resolution Timer instance
4984 * @param Timer This parameter can be one of the following values:
4985 * @arg @ref LL_HRTIM_TIMER_A
4986 * @arg @ref LL_HRTIM_TIMER_B
4987 * @arg @ref LL_HRTIM_TIMER_C
4988 * @arg @ref LL_HRTIM_TIMER_D
4989 * @arg @ref LL_HRTIM_TIMER_E
4990 * @retval None
4991 */
LL_HRTIM_DT_LockFalling(HRTIM_TypeDef * HRTIMx,uint32_t Timer)4992 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4993 {
4994 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
4995 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
4996 REG_OFFSET_TAB_TIMER[iTimer]));
4997 SET_BIT(*pReg, HRTIM_DTR_DTFLK);
4998 }
4999
5000 /**
5001 * @brief Lock the deadtime sign on falling edge.
5002 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
5003 * @param HRTIMx High Resolution Timer instance
5004 * @param Timer This parameter can be one of the following values:
5005 * @arg @ref LL_HRTIM_TIMER_A
5006 * @arg @ref LL_HRTIM_TIMER_B
5007 * @arg @ref LL_HRTIM_TIMER_C
5008 * @arg @ref LL_HRTIM_TIMER_D
5009 * @arg @ref LL_HRTIM_TIMER_E
5010 * @retval None
5011 */
LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef * HRTIMx,uint32_t Timer)5012 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5013 {
5014 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5015 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
5016 REG_OFFSET_TAB_TIMER[iTimer]));
5017 SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
5018 }
5019
5020 /**
5021 * @}
5022 */
5023
5024 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
5025 * @{
5026 */
5027
5028 /**
5029 * @brief Configure the chopper stage for a given timer.
5030 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
5031 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
5032 * CHPxR STRTPW LL_HRTIM_CHP_Config
5033 * @note This function must not be called if the chopper mode is already
5034 * enabled for one of the timer outputs.
5035 * @param HRTIMx High Resolution Timer instance
5036 * @param Timer This parameter can be one of the following values:
5037 * @arg @ref LL_HRTIM_TIMER_A
5038 * @arg @ref LL_HRTIM_TIMER_B
5039 * @arg @ref LL_HRTIM_TIMER_C
5040 * @arg @ref LL_HRTIM_TIMER_D
5041 * @arg @ref LL_HRTIM_TIMER_E
5042 * @param Configuration This parameter must be a combination of all the following values:
5043 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
5044 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
5045 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
5046 * @retval None
5047 */
LL_HRTIM_CHP_Config(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Configuration)5048 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
5049 {
5050 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5052 REG_OFFSET_TAB_TIMER[iTimer]));
5053 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
5054 }
5055
5056 /**
5057 * @brief Set prescaler determining the carrier frequency to be added on top
5058 * of the timer output signals when chopper mode is enabled.
5059 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
5060 * @note This function must not be called if the chopper mode is already
5061 * enabled for one of the timer outputs.
5062 * @param HRTIMx High Resolution Timer instance
5063 * @param Timer This parameter can be one of the following values:
5064 * @arg @ref LL_HRTIM_TIMER_A
5065 * @arg @ref LL_HRTIM_TIMER_B
5066 * @arg @ref LL_HRTIM_TIMER_C
5067 * @arg @ref LL_HRTIM_TIMER_D
5068 * @arg @ref LL_HRTIM_TIMER_E
5069 * @param Prescaler This parameter can be one of the following values:
5070 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5071 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5072 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5073 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5074 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5075 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5076 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5077 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5078 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5079 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5080 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5081 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5082 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5083 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5084 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5085 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5086 * @retval None
5087 */
LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t Prescaler)5088 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
5089 {
5090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5091 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5092 REG_OFFSET_TAB_TIMER[iTimer]));
5093 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
5094 }
5095
5096 /**
5097 * @brief Get actual chopper stage prescaler value.
5098 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
5099 * @param HRTIMx High Resolution Timer instance
5100 * @param Timer This parameter can be one of the following values:
5101 * @arg @ref LL_HRTIM_TIMER_A
5102 * @arg @ref LL_HRTIM_TIMER_B
5103 * @arg @ref LL_HRTIM_TIMER_C
5104 * @arg @ref LL_HRTIM_TIMER_D
5105 * @arg @ref LL_HRTIM_TIMER_E
5106 * @retval Prescaler This parameter can be one of the following values:
5107 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
5108 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
5109 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
5110 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
5111 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
5112 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
5113 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
5114 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
5115 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
5116 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
5117 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
5118 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
5119 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
5120 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
5121 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
5122 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
5123 */
LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5124 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5125 {
5126 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5127 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5128 REG_OFFSET_TAB_TIMER[iTimer]));
5129 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
5130 }
5131
5132 /**
5133 * @brief Set the chopper duty cycle.
5134 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
5135 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
5136 * @note This function must not be called if the chopper mode is already
5137 * enabled for one of the timer outputs.
5138 * @param HRTIMx High Resolution Timer instance
5139 * @param Timer This parameter can be one of the following values:
5140 * @arg @ref LL_HRTIM_TIMER_A
5141 * @arg @ref LL_HRTIM_TIMER_B
5142 * @arg @ref LL_HRTIM_TIMER_C
5143 * @arg @ref LL_HRTIM_TIMER_D
5144 * @arg @ref LL_HRTIM_TIMER_E
5145 * @param DutyCycle This parameter can be one of the following values:
5146 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5147 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5148 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5149 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5150 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5151 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5152 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5153 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5154 * @retval None
5155 */
LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t DutyCycle)5156 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
5157 {
5158 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5159 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5160 REG_OFFSET_TAB_TIMER[iTimer]));
5161 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
5162 }
5163
5164 /**
5165 * @brief Get actual chopper duty cycle.
5166 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
5167 * @param HRTIMx High Resolution Timer instance
5168 * @param Timer This parameter can be one of the following values:
5169 * @arg @ref LL_HRTIM_TIMER_A
5170 * @arg @ref LL_HRTIM_TIMER_B
5171 * @arg @ref LL_HRTIM_TIMER_C
5172 * @arg @ref LL_HRTIM_TIMER_D
5173 * @arg @ref LL_HRTIM_TIMER_E
5174 * @retval DutyCycle This parameter can be one of the following values:
5175 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
5176 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
5177 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
5178 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
5179 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
5180 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
5181 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
5182 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
5183 */
LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5184 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5185 {
5186 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5187 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5188 REG_OFFSET_TAB_TIMER[iTimer]));
5189 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
5190 }
5191
5192 /**
5193 * @brief Set the start pulse width.
5194 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
5195 * @note This function must not be called if the chopper mode is already
5196 * enabled for one of the timer outputs.
5197 * @param HRTIMx High Resolution Timer instance
5198 * @param Timer This parameter can be one of the following values:
5199 * @arg @ref LL_HRTIM_TIMER_A
5200 * @arg @ref LL_HRTIM_TIMER_B
5201 * @arg @ref LL_HRTIM_TIMER_C
5202 * @arg @ref LL_HRTIM_TIMER_D
5203 * @arg @ref LL_HRTIM_TIMER_E
5204 * @param PulseWidth This parameter can be one of the following values:
5205 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5206 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5207 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5208 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5209 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5210 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5211 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5212 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5213 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5214 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5215 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5216 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5217 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5218 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5219 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5220 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5221 * @retval None
5222 */
LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef * HRTIMx,uint32_t Timer,uint32_t PulseWidth)5223 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
5224 {
5225 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5226 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5227 REG_OFFSET_TAB_TIMER[iTimer]));
5228 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
5229 }
5230
5231 /**
5232 * @brief Get actual start pulse width.
5233 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
5234 * @param HRTIMx High Resolution Timer instance
5235 * @param Timer This parameter can be one of the following values:
5236 * @arg @ref LL_HRTIM_TIMER_A
5237 * @arg @ref LL_HRTIM_TIMER_B
5238 * @arg @ref LL_HRTIM_TIMER_C
5239 * @arg @ref LL_HRTIM_TIMER_D
5240 * @arg @ref LL_HRTIM_TIMER_E
5241 * @retval PulseWidth This parameter can be one of the following values:
5242 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
5243 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
5244 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
5245 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
5246 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
5247 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
5248 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
5249 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
5250 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
5251 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
5252 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
5253 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
5254 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
5255 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
5256 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
5257 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
5258 */
LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)5259 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5260 {
5261 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
5262 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
5263 REG_OFFSET_TAB_TIMER[iTimer]));
5264 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
5265 }
5266
5267 /**
5268 * @}
5269 */
5270
5271 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
5272 * @{
5273 */
5274
5275 /**
5276 * @brief Set the timer output set source.
5277 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5278 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5279 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5280 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5281 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5282 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5283 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5284 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5285 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5286 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5287 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5288 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5289 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5290 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5291 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5292 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5293 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5294 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5295 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5296 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5297 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5298 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5299 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5300 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5301 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5302 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5303 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5304 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5305 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5306 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5307 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5308 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
5309 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
5310 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
5311 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
5312 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5313 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5314 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5315 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5316 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
5317 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
5318 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
5319 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
5320 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
5321 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5322 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5323 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5324 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5325 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5326 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5327 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5328 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5329 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5330 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
5331 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
5332 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
5333 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
5334 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
5335 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
5336 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
5337 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
5338 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
5339 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
5340 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
5341 * @param HRTIMx High Resolution Timer instance
5342 * @param Output This parameter can be one of the following values:
5343 * @arg @ref LL_HRTIM_OUTPUT_TA1
5344 * @arg @ref LL_HRTIM_OUTPUT_TA2
5345 * @arg @ref LL_HRTIM_OUTPUT_TB1
5346 * @arg @ref LL_HRTIM_OUTPUT_TB2
5347 * @arg @ref LL_HRTIM_OUTPUT_TC1
5348 * @arg @ref LL_HRTIM_OUTPUT_TC2
5349 * @arg @ref LL_HRTIM_OUTPUT_TD1
5350 * @arg @ref LL_HRTIM_OUTPUT_TD2
5351 * @arg @ref LL_HRTIM_OUTPUT_TE1
5352 * @arg @ref LL_HRTIM_OUTPUT_TE2
5353 * @param SetSrc This parameter can be a combination of the following values:
5354 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5355 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5356 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5357 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5358 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5359 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5360 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5361 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5362 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5363 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5364 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5365 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5366 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5367 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5368 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5369 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5370 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5371 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5372 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5373 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5374 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5375 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5376 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5377 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5378 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5379 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5380 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5381 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5382 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5383 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5384 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5385 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5386 * @retval None
5387 */
LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t SetSrc)5388 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
5389 {
5390 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5391 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5392 REG_OFFSET_TAB_SETxR[iOutput]));
5393 WRITE_REG(*pReg, SetSrc);
5394 }
5395
5396 /**
5397 * @brief Get the timer output set source.
5398 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5399 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5400 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5401 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5402 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5403 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5404 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5405 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5406 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5407 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5408 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5409 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5410 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5411 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5412 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5413 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5414 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5415 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5416 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5417 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5418 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5419 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5420 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5421 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5422 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5423 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5424 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5425 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5426 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5427 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5428 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5429 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
5430 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
5431 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
5432 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
5433 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5434 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5435 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5436 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5437 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
5438 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
5439 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
5440 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
5441 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
5442 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5443 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5444 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5445 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5446 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5447 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5448 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5449 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5450 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5451 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
5452 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
5453 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
5454 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
5455 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
5456 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
5457 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
5458 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
5459 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
5460 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
5461 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
5462 * @param HRTIMx High Resolution Timer instance
5463 * @param Output This parameter can be one of the following values:
5464 * @arg @ref LL_HRTIM_OUTPUT_TA1
5465 * @arg @ref LL_HRTIM_OUTPUT_TA2
5466 * @arg @ref LL_HRTIM_OUTPUT_TB1
5467 * @arg @ref LL_HRTIM_OUTPUT_TB2
5468 * @arg @ref LL_HRTIM_OUTPUT_TC1
5469 * @arg @ref LL_HRTIM_OUTPUT_TC2
5470 * @arg @ref LL_HRTIM_OUTPUT_TD1
5471 * @arg @ref LL_HRTIM_OUTPUT_TD2
5472 * @arg @ref LL_HRTIM_OUTPUT_TE1
5473 * @arg @ref LL_HRTIM_OUTPUT_TE2
5474 * @retval SetSrc This parameter can be a combination of the following values:
5475 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5476 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5477 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5478 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5479 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5480 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5481 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5482 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5483 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5484 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5485 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5486 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5487 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5488 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5489 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5490 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5491 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5492 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5493 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5494 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5495 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5496 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5497 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5498 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5499 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5500 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5501 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5502 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5503 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5504 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5505 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5506 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5507 */
LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5508 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5509 {
5510 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5511 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
5512 REG_OFFSET_TAB_SETxR[iOutput]));
5513 return (uint32_t) READ_REG(*pReg);
5514 }
5515
5516 /**
5517 * @brief Set the timer output reset source.
5518 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5519 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5520 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5521 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5522 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5523 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5524 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5525 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5526 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5527 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5528 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5529 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5530 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5531 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5532 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5533 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5534 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5535 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5536 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5537 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5538 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5539 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5540 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5541 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5542 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5543 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5544 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5545 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5546 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5547 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5548 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5549 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
5550 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
5551 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
5552 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
5553 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5554 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5555 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5556 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5557 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
5558 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
5559 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
5560 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
5561 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
5562 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5563 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5564 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5565 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5566 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5567 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5568 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5569 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5570 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5571 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
5572 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
5573 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
5574 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
5575 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
5576 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
5577 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
5578 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
5579 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
5580 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
5581 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
5582 * @param HRTIMx High Resolution Timer instance
5583 * @param Output This parameter can be one of the following values:
5584 * @arg @ref LL_HRTIM_OUTPUT_TA1
5585 * @arg @ref LL_HRTIM_OUTPUT_TA2
5586 * @arg @ref LL_HRTIM_OUTPUT_TB1
5587 * @arg @ref LL_HRTIM_OUTPUT_TB2
5588 * @arg @ref LL_HRTIM_OUTPUT_TC1
5589 * @arg @ref LL_HRTIM_OUTPUT_TC2
5590 * @arg @ref LL_HRTIM_OUTPUT_TD1
5591 * @arg @ref LL_HRTIM_OUTPUT_TD2
5592 * @arg @ref LL_HRTIM_OUTPUT_TE1
5593 * @arg @ref LL_HRTIM_OUTPUT_TE2
5594 * @param ResetSrc This parameter can be a combination of the following values:
5595 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5596 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5597 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5598 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5599 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5600 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5601 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5602 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5603 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5604 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5605 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5606 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5607 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5608 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5609 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5610 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5611 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5612 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5613 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5614 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5615 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5616 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5617 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5618 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5619 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5620 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5621 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5622 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5623 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5624 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5625 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5626 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5627 * @retval None
5628 */
LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ResetSrc)5629 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
5630 {
5631 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5632 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5633 REG_OFFSET_TAB_SETxR[iOutput]));
5634 WRITE_REG(*pReg, ResetSrc);
5635 }
5636
5637 /**
5638 * @brief Get the timer output set source.
5639 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5640 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5641 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5642 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5643 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5644 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5645 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5646 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5647 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5648 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5649 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5650 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5651 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5652 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5653 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5654 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5655 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5656 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5657 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5658 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5659 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5660 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5661 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5662 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5663 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5664 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5665 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5666 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5667 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5668 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5669 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5670 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
5671 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
5672 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
5673 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
5674 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5675 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5676 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5677 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5678 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
5679 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
5680 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
5681 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
5682 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
5683 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5684 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5685 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5686 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5687 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5688 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5689 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5690 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5691 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5692 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
5693 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
5694 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
5695 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
5696 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
5697 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
5698 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
5699 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
5700 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
5701 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
5702 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
5703 * @param HRTIMx High Resolution Timer instance
5704 * @param Output This parameter can be one of the following values:
5705 * @arg @ref LL_HRTIM_OUTPUT_TA1
5706 * @arg @ref LL_HRTIM_OUTPUT_TA2
5707 * @arg @ref LL_HRTIM_OUTPUT_TB1
5708 * @arg @ref LL_HRTIM_OUTPUT_TB2
5709 * @arg @ref LL_HRTIM_OUTPUT_TC1
5710 * @arg @ref LL_HRTIM_OUTPUT_TC2
5711 * @arg @ref LL_HRTIM_OUTPUT_TD1
5712 * @arg @ref LL_HRTIM_OUTPUT_TD2
5713 * @arg @ref LL_HRTIM_OUTPUT_TE1
5714 * @arg @ref LL_HRTIM_OUTPUT_TE2
5715 * @retval ResetSrc This parameter can be a combination of the following values:
5716 * @arg @ref LL_HRTIM_CROSSBAR_NONE
5717 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
5718 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
5719 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
5720 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
5721 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
5722 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
5723 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
5724 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
5725 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
5726 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
5727 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
5728 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
5729 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
5730 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
5731 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
5732 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
5733 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
5734 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
5735 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
5736 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
5737 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
5738 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
5739 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
5740 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
5741 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
5742 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
5743 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
5744 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
5745 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
5746 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
5747 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
5748 */
LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5749 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5750 {
5751 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5752 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
5753 REG_OFFSET_TAB_SETxR[iOutput]));
5754 return (uint32_t) READ_REG(*pReg);
5755 }
5756
5757 /**
5758 * @brief Configure a timer output.
5759 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
5760 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
5761 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
5762 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
5763 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
5764 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
5765 * OUTxR POL2 LL_HRTIM_OUT_Config\n
5766 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
5767 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
5768 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
5769 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
5770 * OUTxR DIDL2 LL_HRTIM_OUT_Config
5771 * @param HRTIMx High Resolution Timer instance
5772 * @param Output This parameter can be one of the following values:
5773 * @arg @ref LL_HRTIM_OUTPUT_TA1
5774 * @arg @ref LL_HRTIM_OUTPUT_TA2
5775 * @arg @ref LL_HRTIM_OUTPUT_TB1
5776 * @arg @ref LL_HRTIM_OUTPUT_TB2
5777 * @arg @ref LL_HRTIM_OUTPUT_TC1
5778 * @arg @ref LL_HRTIM_OUTPUT_TC2
5779 * @arg @ref LL_HRTIM_OUTPUT_TD1
5780 * @arg @ref LL_HRTIM_OUTPUT_TD2
5781 * @arg @ref LL_HRTIM_OUTPUT_TE1
5782 * @arg @ref LL_HRTIM_OUTPUT_TE2
5783 * @param Configuration This parameter must be a combination of all the following values:
5784 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5785 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5786 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5787 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
5788 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
5789 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
5790 * @retval None
5791 */
LL_HRTIM_OUT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Configuration)5792 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
5793 {
5794 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5795 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5796 REG_OFFSET_TAB_OUTxR[iOutput]));
5797 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
5798 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
5799 }
5800
5801 /**
5802 * @brief Set the polarity of a timer output.
5803 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
5804 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
5805 * @param HRTIMx High Resolution Timer instance
5806 * @param Output This parameter can be one of the following values:
5807 * @arg @ref LL_HRTIM_OUTPUT_TA1
5808 * @arg @ref LL_HRTIM_OUTPUT_TA2
5809 * @arg @ref LL_HRTIM_OUTPUT_TB1
5810 * @arg @ref LL_HRTIM_OUTPUT_TB2
5811 * @arg @ref LL_HRTIM_OUTPUT_TC1
5812 * @arg @ref LL_HRTIM_OUTPUT_TC2
5813 * @arg @ref LL_HRTIM_OUTPUT_TD1
5814 * @arg @ref LL_HRTIM_OUTPUT_TD2
5815 * @arg @ref LL_HRTIM_OUTPUT_TE1
5816 * @arg @ref LL_HRTIM_OUTPUT_TE2
5817 * @param Polarity This parameter can be one of the following values:
5818 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5819 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5820 * @retval None
5821 */
LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t Polarity)5822 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
5823 {
5824 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5825 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5826 REG_OFFSET_TAB_OUTxR[iOutput]));
5827 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
5828 }
5829
5830 /**
5831 * @brief Get actual polarity of the timer output.
5832 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
5833 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
5834 * @param HRTIMx High Resolution Timer instance
5835 * @param Output This parameter can be one of the following values:
5836 * @arg @ref LL_HRTIM_OUTPUT_TA1
5837 * @arg @ref LL_HRTIM_OUTPUT_TA2
5838 * @arg @ref LL_HRTIM_OUTPUT_TB1
5839 * @arg @ref LL_HRTIM_OUTPUT_TB2
5840 * @arg @ref LL_HRTIM_OUTPUT_TC1
5841 * @arg @ref LL_HRTIM_OUTPUT_TC2
5842 * @arg @ref LL_HRTIM_OUTPUT_TD1
5843 * @arg @ref LL_HRTIM_OUTPUT_TD2
5844 * @arg @ref LL_HRTIM_OUTPUT_TE1
5845 * @arg @ref LL_HRTIM_OUTPUT_TE2
5846 * @retval Polarity This parameter can be one of the following values:
5847 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
5848 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
5849 */
LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5850 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5851 {
5852 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5853 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5854 REG_OFFSET_TAB_OUTxR[iOutput]));
5855 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5856 }
5857
5858 /**
5859 * @brief Set the output IDLE mode.
5860 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
5861 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
5862 * @note This function must not be called when the burst mode is active
5863 * @param HRTIMx High Resolution Timer instance
5864 * @param Output This parameter can be one of the following values:
5865 * @arg @ref LL_HRTIM_OUTPUT_TA1
5866 * @arg @ref LL_HRTIM_OUTPUT_TA2
5867 * @arg @ref LL_HRTIM_OUTPUT_TB1
5868 * @arg @ref LL_HRTIM_OUTPUT_TB2
5869 * @arg @ref LL_HRTIM_OUTPUT_TC1
5870 * @arg @ref LL_HRTIM_OUTPUT_TC2
5871 * @arg @ref LL_HRTIM_OUTPUT_TD1
5872 * @arg @ref LL_HRTIM_OUTPUT_TD2
5873 * @arg @ref LL_HRTIM_OUTPUT_TE1
5874 * @arg @ref LL_HRTIM_OUTPUT_TE2
5875 * @param IdleMode This parameter can be one of the following values:
5876 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5877 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5878 * @retval None
5879 */
LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleMode)5880 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
5881 {
5882 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5883 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5884 REG_OFFSET_TAB_OUTxR[iOutput]));
5885 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
5886 }
5887
5888 /**
5889 * @brief Get actual output IDLE mode.
5890 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
5891 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
5892 * @param HRTIMx High Resolution Timer instance
5893 * @param Output This parameter can be one of the following values:
5894 * @arg @ref LL_HRTIM_OUTPUT_TA1
5895 * @arg @ref LL_HRTIM_OUTPUT_TA2
5896 * @arg @ref LL_HRTIM_OUTPUT_TB1
5897 * @arg @ref LL_HRTIM_OUTPUT_TB2
5898 * @arg @ref LL_HRTIM_OUTPUT_TC1
5899 * @arg @ref LL_HRTIM_OUTPUT_TC2
5900 * @arg @ref LL_HRTIM_OUTPUT_TD1
5901 * @arg @ref LL_HRTIM_OUTPUT_TD2
5902 * @arg @ref LL_HRTIM_OUTPUT_TE1
5903 * @arg @ref LL_HRTIM_OUTPUT_TE2
5904 * @retval IdleMode This parameter can be one of the following values:
5905 * @arg @ref LL_HRTIM_OUT_NO_IDLE
5906 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
5907 */
LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5908 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5909 {
5910 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5911 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5912 REG_OFFSET_TAB_OUTxR[iOutput]));
5913 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5914 }
5915
5916 /**
5917 * @brief Set the output IDLE level.
5918 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
5919 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
5920 * @note This function must be called prior enabling the timer.
5921 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
5922 * @param HRTIMx High Resolution Timer instance
5923 * @param Output This parameter can be one of the following values:
5924 * @arg @ref LL_HRTIM_OUTPUT_TA1
5925 * @arg @ref LL_HRTIM_OUTPUT_TA2
5926 * @arg @ref LL_HRTIM_OUTPUT_TB1
5927 * @arg @ref LL_HRTIM_OUTPUT_TB2
5928 * @arg @ref LL_HRTIM_OUTPUT_TC1
5929 * @arg @ref LL_HRTIM_OUTPUT_TC2
5930 * @arg @ref LL_HRTIM_OUTPUT_TD1
5931 * @arg @ref LL_HRTIM_OUTPUT_TD2
5932 * @arg @ref LL_HRTIM_OUTPUT_TE1
5933 * @arg @ref LL_HRTIM_OUTPUT_TE2
5934 * @param IdleLevel This parameter can be one of the following values:
5935 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
5936 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5937 * @retval None
5938 */
LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t IdleLevel)5939 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
5940 {
5941 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5942 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5943 REG_OFFSET_TAB_OUTxR[iOutput]));
5944 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
5945 }
5946
5947 /**
5948 * @brief Get actual output IDLE level.
5949 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
5950 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
5951 * @param HRTIMx High Resolution Timer instance
5952 * @param Output This parameter can be one of the following values:
5953 * @arg @ref LL_HRTIM_OUTPUT_TA1
5954 * @arg @ref LL_HRTIM_OUTPUT_TA2
5955 * @arg @ref LL_HRTIM_OUTPUT_TB1
5956 * @arg @ref LL_HRTIM_OUTPUT_TB2
5957 * @arg @ref LL_HRTIM_OUTPUT_TC1
5958 * @arg @ref LL_HRTIM_OUTPUT_TC2
5959 * @arg @ref LL_HRTIM_OUTPUT_TD1
5960 * @arg @ref LL_HRTIM_OUTPUT_TD2
5961 * @arg @ref LL_HRTIM_OUTPUT_TE1
5962 * @arg @ref LL_HRTIM_OUTPUT_TE2
5963 * @retval IdleLevel This parameter can be one of the following values:
5964 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
5965 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
5966 */
LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)5967 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
5968 {
5969 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
5970 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5971 REG_OFFSET_TAB_OUTxR[iOutput]));
5972 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
5973 }
5974
5975 /**
5976 * @brief Set the output FAULT state.
5977 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
5978 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
5979 * @note This function must not called when the timer is enabled and a fault
5980 * channel is enabled at timer level.
5981 * @param HRTIMx High Resolution Timer instance
5982 * @param Output This parameter can be one of the following values:
5983 * @arg @ref LL_HRTIM_OUTPUT_TA1
5984 * @arg @ref LL_HRTIM_OUTPUT_TA2
5985 * @arg @ref LL_HRTIM_OUTPUT_TB1
5986 * @arg @ref LL_HRTIM_OUTPUT_TB2
5987 * @arg @ref LL_HRTIM_OUTPUT_TC1
5988 * @arg @ref LL_HRTIM_OUTPUT_TC2
5989 * @arg @ref LL_HRTIM_OUTPUT_TD1
5990 * @arg @ref LL_HRTIM_OUTPUT_TD2
5991 * @arg @ref LL_HRTIM_OUTPUT_TE1
5992 * @arg @ref LL_HRTIM_OUTPUT_TE2
5993 * @param FaultState This parameter can be one of the following values:
5994 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
5995 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
5996 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
5997 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
5998 * @retval None
5999 */
LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t FaultState)6000 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
6001 {
6002 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6003 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6004 REG_OFFSET_TAB_OUTxR[iOutput]));
6005 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
6006 }
6007
6008 /**
6009 * @brief Get actual FAULT state.
6010 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
6011 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
6012 * @param HRTIMx High Resolution Timer instance
6013 * @param Output This parameter can be one of the following values:
6014 * @arg @ref LL_HRTIM_OUTPUT_TA1
6015 * @arg @ref LL_HRTIM_OUTPUT_TA2
6016 * @arg @ref LL_HRTIM_OUTPUT_TB1
6017 * @arg @ref LL_HRTIM_OUTPUT_TB2
6018 * @arg @ref LL_HRTIM_OUTPUT_TC1
6019 * @arg @ref LL_HRTIM_OUTPUT_TC2
6020 * @arg @ref LL_HRTIM_OUTPUT_TD1
6021 * @arg @ref LL_HRTIM_OUTPUT_TD2
6022 * @arg @ref LL_HRTIM_OUTPUT_TE1
6023 * @arg @ref LL_HRTIM_OUTPUT_TE2
6024 * @retval FaultState This parameter can be one of the following values:
6025 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
6026 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
6027 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
6028 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
6029 */
LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6030 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6031 {
6032 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6033 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6034 REG_OFFSET_TAB_OUTxR[iOutput]));
6035 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6036 }
6037
6038 /**
6039 * @brief Set the output chopper mode.
6040 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
6041 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
6042 * @note This function must not called when the timer is enabled.
6043 * @param HRTIMx High Resolution Timer instance
6044 * @param Output This parameter can be one of the following values:
6045 * @arg @ref LL_HRTIM_OUTPUT_TA1
6046 * @arg @ref LL_HRTIM_OUTPUT_TA2
6047 * @arg @ref LL_HRTIM_OUTPUT_TB1
6048 * @arg @ref LL_HRTIM_OUTPUT_TB2
6049 * @arg @ref LL_HRTIM_OUTPUT_TC1
6050 * @arg @ref LL_HRTIM_OUTPUT_TC2
6051 * @arg @ref LL_HRTIM_OUTPUT_TD1
6052 * @arg @ref LL_HRTIM_OUTPUT_TD2
6053 * @arg @ref LL_HRTIM_OUTPUT_TE1
6054 * @arg @ref LL_HRTIM_OUTPUT_TE2
6055 * @param ChopperMode This parameter can be one of the following values:
6056 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6057 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6058 * @retval None
6059 */
LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t ChopperMode)6060 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
6061 {
6062 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6063 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6064 REG_OFFSET_TAB_OUTxR[iOutput]));
6065 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6066 }
6067
6068 /**
6069 * @brief Get actual output chopper mode
6070 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
6071 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
6072 * @param HRTIMx High Resolution Timer instance
6073 * @param Output This parameter can be one of the following values:
6074 * @arg @ref LL_HRTIM_OUTPUT_TA1
6075 * @arg @ref LL_HRTIM_OUTPUT_TA2
6076 * @arg @ref LL_HRTIM_OUTPUT_TB1
6077 * @arg @ref LL_HRTIM_OUTPUT_TB2
6078 * @arg @ref LL_HRTIM_OUTPUT_TC1
6079 * @arg @ref LL_HRTIM_OUTPUT_TC2
6080 * @arg @ref LL_HRTIM_OUTPUT_TD1
6081 * @arg @ref LL_HRTIM_OUTPUT_TD2
6082 * @arg @ref LL_HRTIM_OUTPUT_TE1
6083 * @arg @ref LL_HRTIM_OUTPUT_TE2
6084 * @retval ChopperMode This parameter can be one of the following values:
6085 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
6086 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
6087 */
LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6088 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6089 {
6090 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6092 REG_OFFSET_TAB_OUTxR[iOutput]));
6093 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6094 }
6095
6096 /**
6097 * @brief Set the output burst mode entry mode.
6098 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
6099 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
6100 * @note This function must not called when the timer is enabled.
6101 * @param HRTIMx High Resolution Timer instance
6102 * @param Output This parameter can be one of the following values:
6103 * @arg @ref LL_HRTIM_OUTPUT_TA1
6104 * @arg @ref LL_HRTIM_OUTPUT_TA2
6105 * @arg @ref LL_HRTIM_OUTPUT_TB1
6106 * @arg @ref LL_HRTIM_OUTPUT_TB2
6107 * @arg @ref LL_HRTIM_OUTPUT_TC1
6108 * @arg @ref LL_HRTIM_OUTPUT_TC2
6109 * @arg @ref LL_HRTIM_OUTPUT_TD1
6110 * @arg @ref LL_HRTIM_OUTPUT_TD2
6111 * @arg @ref LL_HRTIM_OUTPUT_TE1
6112 * @arg @ref LL_HRTIM_OUTPUT_TE2
6113 * @param BMEntryMode This parameter can be one of the following values:
6114 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6115 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6116 * @retval None
6117 */
LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t BMEntryMode)6118 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
6119 {
6120 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6121 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6122 REG_OFFSET_TAB_OUTxR[iOutput]));
6123 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
6124 }
6125
6126 /**
6127 * @brief Get actual output burst mode entry mode.
6128 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
6129 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
6130 * @param HRTIMx High Resolution Timer instance
6131 * @param Output This parameter can be one of the following values:
6132 * @arg @ref LL_HRTIM_OUTPUT_TA1
6133 * @arg @ref LL_HRTIM_OUTPUT_TA2
6134 * @arg @ref LL_HRTIM_OUTPUT_TB1
6135 * @arg @ref LL_HRTIM_OUTPUT_TB2
6136 * @arg @ref LL_HRTIM_OUTPUT_TC1
6137 * @arg @ref LL_HRTIM_OUTPUT_TC2
6138 * @arg @ref LL_HRTIM_OUTPUT_TD1
6139 * @arg @ref LL_HRTIM_OUTPUT_TD2
6140 * @arg @ref LL_HRTIM_OUTPUT_TE1
6141 * @arg @ref LL_HRTIM_OUTPUT_TE2
6142 * @retval BMEntryMode This parameter can be one of the following values:
6143 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
6144 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
6145 */
LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6146 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6147 {
6148 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6149 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
6150 REG_OFFSET_TAB_OUTxR[iOutput]));
6151 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
6152 }
6153
6154 /**
6155 * @brief Get the level (active or inactive) of the designated output when the
6156 * delayed protection was triggered.
6157 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
6158 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
6159 * @param HRTIMx High Resolution Timer instance
6160 * @param Output This parameter can be one of the following values:
6161 * @arg @ref LL_HRTIM_OUTPUT_TA1
6162 * @arg @ref LL_HRTIM_OUTPUT_TA2
6163 * @arg @ref LL_HRTIM_OUTPUT_TB1
6164 * @arg @ref LL_HRTIM_OUTPUT_TB2
6165 * @arg @ref LL_HRTIM_OUTPUT_TC1
6166 * @arg @ref LL_HRTIM_OUTPUT_TC2
6167 * @arg @ref LL_HRTIM_OUTPUT_TD1
6168 * @arg @ref LL_HRTIM_OUTPUT_TD2
6169 * @arg @ref LL_HRTIM_OUTPUT_TE1
6170 * @arg @ref LL_HRTIM_OUTPUT_TE2
6171 * @retval OutputLevel This parameter can be one of the following values:
6172 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6173 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6174 */
LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6175 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6176 {
6177 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6178 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6179 REG_OFFSET_TAB_OUTxR[iOutput]));
6180 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6181 HRTIM_TIMISR_O1STAT_Pos);
6182 }
6183
6184 /**
6185 * @brief Force the timer output to its active or inactive level.
6186 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
6187 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
6188 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
6189 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
6190 * @param HRTIMx High Resolution Timer instance
6191 * @param Output This parameter can be one of the following values:
6192 * @arg @ref LL_HRTIM_OUTPUT_TA1
6193 * @arg @ref LL_HRTIM_OUTPUT_TA2
6194 * @arg @ref LL_HRTIM_OUTPUT_TB1
6195 * @arg @ref LL_HRTIM_OUTPUT_TB2
6196 * @arg @ref LL_HRTIM_OUTPUT_TC1
6197 * @arg @ref LL_HRTIM_OUTPUT_TC2
6198 * @arg @ref LL_HRTIM_OUTPUT_TD1
6199 * @arg @ref LL_HRTIM_OUTPUT_TD2
6200 * @arg @ref LL_HRTIM_OUTPUT_TE1
6201 * @arg @ref LL_HRTIM_OUTPUT_TE2
6202 * @param OutputLevel This parameter can be one of the following values:
6203 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6204 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6205 * @retval None
6206 */
LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef * HRTIMx,uint32_t Output,uint32_t OutputLevel)6207 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
6208 {
6209 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
6210 {
6211 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
6212 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
6213 };
6214
6215 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6216 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
6217 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
6218 SET_BIT(*pReg, HRTIM_SET1R_SST);
6219 }
6220
6221 /**
6222 * @brief Get actual output level, before the output stage (chopper, polarity).
6223 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
6224 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
6225 * @param HRTIMx High Resolution Timer instance
6226 * @param Output This parameter can be one of the following values:
6227 * @arg @ref LL_HRTIM_OUTPUT_TA1
6228 * @arg @ref LL_HRTIM_OUTPUT_TA2
6229 * @arg @ref LL_HRTIM_OUTPUT_TB1
6230 * @arg @ref LL_HRTIM_OUTPUT_TB2
6231 * @arg @ref LL_HRTIM_OUTPUT_TC1
6232 * @arg @ref LL_HRTIM_OUTPUT_TC2
6233 * @arg @ref LL_HRTIM_OUTPUT_TD1
6234 * @arg @ref LL_HRTIM_OUTPUT_TD2
6235 * @arg @ref LL_HRTIM_OUTPUT_TE1
6236 * @arg @ref LL_HRTIM_OUTPUT_TE2
6237 * @retval OutputLevel This parameter can be one of the following values:
6238 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
6239 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
6240 */
LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef * HRTIMx,uint32_t Output)6241 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
6242 {
6243 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
6244 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
6245 REG_OFFSET_TAB_OUTxR[iOutput]));
6246 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
6247 HRTIM_TIMISR_O1CPY_Pos);
6248 }
6249
6250 /**
6251 * @}
6252 */
6253
6254 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
6255 * @{
6256 */
6257
6258 /**
6259 * @brief Configure external event conditioning.
6260 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
6261 * EECR1 EE1POL LL_HRTIM_EE_Config\n
6262 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
6263 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
6264 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
6265 * EECR1 EE2POL LL_HRTIM_EE_Config\n
6266 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
6267 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
6268 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
6269 * EECR1 EE3POL LL_HRTIM_EE_Config\n
6270 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
6271 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
6272 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
6273 * EECR1 EE4POL LL_HRTIM_EE_Config\n
6274 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
6275 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
6276 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
6277 * EECR1 EE5POL LL_HRTIM_EE_Config\n
6278 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
6279 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
6280 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
6281 * EECR2 EE6POL LL_HRTIM_EE_Config\n
6282 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
6283 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
6284 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
6285 * EECR2 EE7POL LL_HRTIM_EE_Config\n
6286 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
6287 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
6288 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
6289 * EECR2 EE8POL LL_HRTIM_EE_Config\n
6290 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
6291 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
6292 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
6293 * EECR2 EE9POL LL_HRTIM_EE_Config\n
6294 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
6295 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
6296 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
6297 * EECR2 EE10POL LL_HRTIM_EE_Config\n
6298 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
6299 * EECR2 EE10FAST LL_HRTIM_EE_Config
6300 * @note This function must not be called when the timer counter is enabled.
6301 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
6302 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
6303 * @param HRTIMx High Resolution Timer instance
6304 * @param Event This parameter can be one of the following values:
6305 * @arg @ref LL_HRTIM_EVENT_1
6306 * @arg @ref LL_HRTIM_EVENT_2
6307 * @arg @ref LL_HRTIM_EVENT_3
6308 * @arg @ref LL_HRTIM_EVENT_4
6309 * @arg @ref LL_HRTIM_EVENT_5
6310 * @arg @ref LL_HRTIM_EVENT_6
6311 * @arg @ref LL_HRTIM_EVENT_7
6312 * @arg @ref LL_HRTIM_EVENT_8
6313 * @arg @ref LL_HRTIM_EVENT_9
6314 * @arg @ref LL_HRTIM_EVENT_10
6315 * @param Configuration This parameter must be a combination of all the following values:
6316 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
6317 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
6318 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6319 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
6320 * @retval None
6321 */
LL_HRTIM_EE_Config(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Configuration)6322 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
6323 {
6324 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6325 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6326 REG_OFFSET_TAB_EECR[iEvent]));
6327 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
6328 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
6329 }
6330
6331 /**
6332 * @brief Set the external event source.
6333 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
6334 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
6335 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
6336 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
6337 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
6338 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
6339 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
6340 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
6341 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
6342 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
6343 * @param HRTIMx High Resolution Timer instance
6344 * @param Event This parameter can be one of the following values:
6345 * @arg @ref LL_HRTIM_EVENT_1
6346 * @arg @ref LL_HRTIM_EVENT_2
6347 * @arg @ref LL_HRTIM_EVENT_3
6348 * @arg @ref LL_HRTIM_EVENT_4
6349 * @arg @ref LL_HRTIM_EVENT_5
6350 * @arg @ref LL_HRTIM_EVENT_6
6351 * @arg @ref LL_HRTIM_EVENT_7
6352 * @arg @ref LL_HRTIM_EVENT_8
6353 * @arg @ref LL_HRTIM_EVENT_9
6354 * @arg @ref LL_HRTIM_EVENT_10
6355 * @param Src This parameter can be one of the following values:
6356 * @arg External event source 1
6357 * @arg External event source 2
6358 * @arg External event source 3
6359 * @arg External event source 4
6360 * @retval None
6361 */
LL_HRTIM_EE_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Src)6362 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
6363 {
6364 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6365 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6366 REG_OFFSET_TAB_EECR[iEvent]));
6367 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
6368 }
6369
6370 /**
6371 * @brief Get actual external event source.
6372 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
6373 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
6374 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
6375 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
6376 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
6377 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
6378 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
6379 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
6380 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
6381 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
6382 * @param HRTIMx High Resolution Timer instance
6383 * @param Event This parameter can be one of the following values:
6384 * @arg @ref LL_HRTIM_EVENT_1
6385 * @arg @ref LL_HRTIM_EVENT_2
6386 * @arg @ref LL_HRTIM_EVENT_3
6387 * @arg @ref LL_HRTIM_EVENT_4
6388 * @arg @ref LL_HRTIM_EVENT_5
6389 * @arg @ref LL_HRTIM_EVENT_6
6390 * @arg @ref LL_HRTIM_EVENT_7
6391 * @arg @ref LL_HRTIM_EVENT_8
6392 * @arg @ref LL_HRTIM_EVENT_9
6393 * @arg @ref LL_HRTIM_EVENT_10
6394 * @retval EventSrc This parameter can be one of the following values:
6395 * @arg External event source 1
6396 * @arg External event source 2
6397 * @arg External event source 3
6398 * @arg External event source 4
6399 */
LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6400 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6401 {
6402 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6403 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6404 REG_OFFSET_TAB_EECR[iEvent]));
6405 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6406 }
6407
6408 /**
6409 * @brief Set the polarity of an external event.
6410 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
6411 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
6412 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
6413 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
6414 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
6415 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
6416 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
6417 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
6418 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
6419 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
6420 * @note This function must not be called when the timer counter is enabled.
6421 * @note Event polarity is only significant when event detection is level-sensitive.
6422 * @param HRTIMx High Resolution Timer instance
6423 * @param Event This parameter can be one of the following values:
6424 * @arg @ref LL_HRTIM_EVENT_1
6425 * @arg @ref LL_HRTIM_EVENT_2
6426 * @arg @ref LL_HRTIM_EVENT_3
6427 * @arg @ref LL_HRTIM_EVENT_4
6428 * @arg @ref LL_HRTIM_EVENT_5
6429 * @arg @ref LL_HRTIM_EVENT_6
6430 * @arg @ref LL_HRTIM_EVENT_7
6431 * @arg @ref LL_HRTIM_EVENT_8
6432 * @arg @ref LL_HRTIM_EVENT_9
6433 * @arg @ref LL_HRTIM_EVENT_10
6434 * @param Polarity This parameter can be one of the following values:
6435 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6436 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6437 * @retval None
6438 */
LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Polarity)6439 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
6440 {
6441 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6442 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6443 REG_OFFSET_TAB_EECR[iEvent]));
6444 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
6445 }
6446
6447 /**
6448 * @brief Get actual polarity setting of an external event.
6449 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
6450 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
6451 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
6452 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
6453 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
6454 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
6455 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
6456 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
6457 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
6458 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
6459 * @param HRTIMx High Resolution Timer instance
6460 * @param Event This parameter can be one of the following values:
6461 * @arg @ref LL_HRTIM_EVENT_1
6462 * @arg @ref LL_HRTIM_EVENT_2
6463 * @arg @ref LL_HRTIM_EVENT_3
6464 * @arg @ref LL_HRTIM_EVENT_4
6465 * @arg @ref LL_HRTIM_EVENT_5
6466 * @arg @ref LL_HRTIM_EVENT_6
6467 * @arg @ref LL_HRTIM_EVENT_7
6468 * @arg @ref LL_HRTIM_EVENT_8
6469 * @arg @ref LL_HRTIM_EVENT_9
6470 * @arg @ref LL_HRTIM_EVENT_10
6471 * @retval Polarity This parameter can be one of the following values:
6472 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
6473 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
6474 */
LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6475 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6476 {
6477 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6478 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6479 REG_OFFSET_TAB_EECR[iEvent]));
6480 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6481 }
6482
6483 /**
6484 * @brief Set the sensitivity of an external event.
6485 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
6486 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
6487 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
6488 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
6489 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
6490 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
6491 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
6492 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
6493 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
6494 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
6495 * @param HRTIMx High Resolution Timer instance
6496 * @param Event This parameter can be one of the following values:
6497 * @arg @ref LL_HRTIM_EVENT_1
6498 * @arg @ref LL_HRTIM_EVENT_2
6499 * @arg @ref LL_HRTIM_EVENT_3
6500 * @arg @ref LL_HRTIM_EVENT_4
6501 * @arg @ref LL_HRTIM_EVENT_5
6502 * @arg @ref LL_HRTIM_EVENT_6
6503 * @arg @ref LL_HRTIM_EVENT_7
6504 * @arg @ref LL_HRTIM_EVENT_8
6505 * @arg @ref LL_HRTIM_EVENT_9
6506 * @arg @ref LL_HRTIM_EVENT_10
6507 * @param Sensitivity This parameter can be one of the following values:
6508 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6509 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6510 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6511 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6512 * @retval None
6513 */
6514
LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Sensitivity)6515 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
6516 {
6517 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6518 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6519 REG_OFFSET_TAB_EECR[iEvent]));
6520 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
6521 }
6522
6523 /**
6524 * @brief Get actual sensitivity setting of an external event.
6525 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
6526 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
6527 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
6528 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
6529 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
6530 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
6531 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
6532 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
6533 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
6534 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
6535 * @param HRTIMx High Resolution Timer instance
6536 * @param Event This parameter can be one of the following values:
6537 * @arg @ref LL_HRTIM_EVENT_1
6538 * @arg @ref LL_HRTIM_EVENT_2
6539 * @arg @ref LL_HRTIM_EVENT_3
6540 * @arg @ref LL_HRTIM_EVENT_4
6541 * @arg @ref LL_HRTIM_EVENT_5
6542 * @arg @ref LL_HRTIM_EVENT_6
6543 * @arg @ref LL_HRTIM_EVENT_7
6544 * @arg @ref LL_HRTIM_EVENT_8
6545 * @arg @ref LL_HRTIM_EVENT_9
6546 * @arg @ref LL_HRTIM_EVENT_10
6547 * @retval Polarity This parameter can be one of the following values:
6548 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
6549 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
6550 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
6551 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
6552 */
LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6553 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6554 {
6555 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6556 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6557 REG_OFFSET_TAB_EECR[iEvent]));
6558 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6559 }
6560
6561 /**
6562 * @brief Set the fast mode of an external event.
6563 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
6564 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
6565 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
6566 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
6567 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
6568 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
6569 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
6570 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
6571 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
6572 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
6573 * @note This function must not be called when the timer counter is enabled.
6574 * @param HRTIMx High Resolution Timer instance
6575 * @param Event This parameter can be one of the following values:
6576 * @arg @ref LL_HRTIM_EVENT_1
6577 * @arg @ref LL_HRTIM_EVENT_2
6578 * @arg @ref LL_HRTIM_EVENT_3
6579 * @arg @ref LL_HRTIM_EVENT_4
6580 * @arg @ref LL_HRTIM_EVENT_5
6581 * @param FastMode This parameter can be one of the following values:
6582 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6583 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6584 * @retval None
6585 */
LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t FastMode)6586 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
6587 {
6588 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6589 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6590 REG_OFFSET_TAB_EECR[iEvent]));
6591 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
6592 }
6593
6594 /**
6595 * @brief Get actual fast mode setting of an external event.
6596 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
6597 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
6598 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
6599 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
6600 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
6601 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
6602 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
6603 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
6604 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
6605 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
6606 * @param HRTIMx High Resolution Timer instance
6607 * @param Event This parameter can be one of the following values:
6608 * @arg @ref LL_HRTIM_EVENT_1
6609 * @arg @ref LL_HRTIM_EVENT_2
6610 * @arg @ref LL_HRTIM_EVENT_3
6611 * @arg @ref LL_HRTIM_EVENT_4
6612 * @arg @ref LL_HRTIM_EVENT_5
6613 * @retval FastMode This parameter can be one of the following values:
6614 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
6615 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
6616 */
LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6617 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6618 {
6619 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6620 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
6621 REG_OFFSET_TAB_EECR[iEvent]));
6622 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6623 }
6624
6625 /**
6626 * @brief Set the digital noise filter of a external event.
6627 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
6628 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
6629 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
6630 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
6631 * EECR3 EE10F LL_HRTIM_EE_SetFilter
6632 * @param HRTIMx High Resolution Timer instance
6633 * @param Event This parameter can be one of the following values:
6634 * @arg @ref LL_HRTIM_EVENT_6
6635 * @arg @ref LL_HRTIM_EVENT_7
6636 * @arg @ref LL_HRTIM_EVENT_8
6637 * @arg @ref LL_HRTIM_EVENT_9
6638 * @arg @ref LL_HRTIM_EVENT_10
6639 * @param Filter This parameter can be one of the following values:
6640 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6641 * @arg @ref LL_HRTIM_EE_FILTER_1
6642 * @arg @ref LL_HRTIM_EE_FILTER_2
6643 * @arg @ref LL_HRTIM_EE_FILTER_3
6644 * @arg @ref LL_HRTIM_EE_FILTER_4
6645 * @arg @ref LL_HRTIM_EE_FILTER_5
6646 * @arg @ref LL_HRTIM_EE_FILTER_6
6647 * @arg @ref LL_HRTIM_EE_FILTER_7
6648 * @arg @ref LL_HRTIM_EE_FILTER_8
6649 * @arg @ref LL_HRTIM_EE_FILTER_9
6650 * @arg @ref LL_HRTIM_EE_FILTER_10
6651 * @arg @ref LL_HRTIM_EE_FILTER_11
6652 * @arg @ref LL_HRTIM_EE_FILTER_12
6653 * @arg @ref LL_HRTIM_EE_FILTER_13
6654 * @arg @ref LL_HRTIM_EE_FILTER_14
6655 * @arg @ref LL_HRTIM_EE_FILTER_15
6656 * @retval None
6657 */
LL_HRTIM_EE_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Event,uint32_t Filter)6658 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
6659 {
6660 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
6661 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
6662 (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6663 }
6664
6665 /**
6666 * @brief Get actual digital noise filter setting of a external event.
6667 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
6668 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
6669 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
6670 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
6671 * EECR3 EE10F LL_HRTIM_EE_GetFilter
6672 * @param HRTIMx High Resolution Timer instance
6673 * @param Event This parameter can be one of the following values:
6674 * @arg @ref LL_HRTIM_EVENT_6
6675 * @arg @ref LL_HRTIM_EVENT_7
6676 * @arg @ref LL_HRTIM_EVENT_8
6677 * @arg @ref LL_HRTIM_EVENT_9
6678 * @arg @ref LL_HRTIM_EVENT_10
6679 * @retval Filter This parameter can be one of the following values:
6680 * @arg @ref LL_HRTIM_EE_FILTER_NONE
6681 * @arg @ref LL_HRTIM_EE_FILTER_1
6682 * @arg @ref LL_HRTIM_EE_FILTER_2
6683 * @arg @ref LL_HRTIM_EE_FILTER_3
6684 * @arg @ref LL_HRTIM_EE_FILTER_4
6685 * @arg @ref LL_HRTIM_EE_FILTER_5
6686 * @arg @ref LL_HRTIM_EE_FILTER_6
6687 * @arg @ref LL_HRTIM_EE_FILTER_7
6688 * @arg @ref LL_HRTIM_EE_FILTER_8
6689 * @arg @ref LL_HRTIM_EE_FILTER_9
6690 * @arg @ref LL_HRTIM_EE_FILTER_10
6691 * @arg @ref LL_HRTIM_EE_FILTER_11
6692 * @arg @ref LL_HRTIM_EE_FILTER_12
6693 * @arg @ref LL_HRTIM_EE_FILTER_13
6694 * @arg @ref LL_HRTIM_EE_FILTER_14
6695 * @arg @ref LL_HRTIM_EE_FILTER_15
6696 */
LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Event)6697 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
6698 {
6699 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
6700 return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
6701 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
6702 }
6703
6704 /**
6705 * @brief Set the external event prescaler.
6706 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
6707 * @param HRTIMx High Resolution Timer instance
6708 * @param Prescaler This parameter can be one of the following values:
6709 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6710 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6711 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6712 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6713 * @retval None
6714 */
6715
LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)6716 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
6717 {
6718 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
6719 }
6720
6721 /**
6722 * @brief Get actual external event prescaler setting.
6723 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
6724 * @param HRTIMx High Resolution Timer instance
6725 * @retval Prescaler This parameter can be one of the following values:
6726 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
6727 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
6728 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
6729 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
6730 */
6731
LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef * HRTIMx)6732 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
6733 {
6734 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
6735 }
6736
6737 /**
6738 * @}
6739 */
6740
6741 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
6742 * @{
6743 */
6744 /**
6745 * @brief Configure fault signal conditioning Polarity and Source.
6746 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
6747 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
6748 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
6749 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
6750 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
6751 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
6752 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
6753 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
6754 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
6755 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
6756 * @note This function must not be called when the fault channel is enabled.
6757 * @param HRTIMx High Resolution Timer instance
6758 * @param Fault This parameter can be one of the following values:
6759 * @arg @ref LL_HRTIM_FAULT_1
6760 * @arg @ref LL_HRTIM_FAULT_2
6761 * @arg @ref LL_HRTIM_FAULT_3
6762 * @arg @ref LL_HRTIM_FAULT_4
6763 * @arg @ref LL_HRTIM_FAULT_5
6764 * @param Configuration This parameter must be a combination of all the following values:
6765 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL
6766 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
6767 * @retval None
6768 */
LL_HRTIM_FLT_Config(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Configuration)6769 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
6770 {
6771 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6773 REG_OFFSET_TAB_FLTINR[iFault]));
6774 MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
6775 (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
6776 }
6777
6778 /**
6779 * @brief Set the source of a fault signal.
6780 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
6781 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
6782 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
6783 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
6784 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
6785 * @note This function must not be called when the fault channel is enabled.
6786 * @param HRTIMx High Resolution Timer instance
6787 * @param Fault This parameter can be one of the following values:
6788 * @arg @ref LL_HRTIM_FAULT_1
6789 * @arg @ref LL_HRTIM_FAULT_2
6790 * @arg @ref LL_HRTIM_FAULT_3
6791 * @arg @ref LL_HRTIM_FAULT_4
6792 * @arg @ref LL_HRTIM_FAULT_5
6793 * @param Src This parameter can be one of the following values:
6794 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6795 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6796 * @retval None
6797 */
LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Src)6798 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
6799 {
6800 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6801 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6802 REG_OFFSET_TAB_FLTINR[iFault]));
6803 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
6804 }
6805
6806 /**
6807 * @brief Get actual source of a fault signal.
6808 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
6809 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
6810 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
6811 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
6812 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
6813 * @param HRTIMx High Resolution Timer instance
6814 * @param Fault This parameter can be one of the following values:
6815 * @arg @ref LL_HRTIM_FAULT_1
6816 * @arg @ref LL_HRTIM_FAULT_2
6817 * @arg @ref LL_HRTIM_FAULT_3
6818 * @arg @ref LL_HRTIM_FAULT_4
6819 * @arg @ref LL_HRTIM_FAULT_5
6820 * @retval Source This parameter can be one of the following values:
6821 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
6822 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
6823 */
LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)6824 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
6825 {
6826 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6827 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6828 REG_OFFSET_TAB_FLTINR[iFault]));
6829 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6830 }
6831
6832 /**
6833 * @brief Set the polarity of a fault signal.
6834 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
6835 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
6836 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
6837 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
6838 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
6839 * @note This function must not be called when the fault channel is enabled.
6840 * @param HRTIMx High Resolution Timer instance
6841 * @param Fault This parameter can be one of the following values:
6842 * @arg @ref LL_HRTIM_FAULT_1
6843 * @arg @ref LL_HRTIM_FAULT_2
6844 * @arg @ref LL_HRTIM_FAULT_3
6845 * @arg @ref LL_HRTIM_FAULT_4
6846 * @arg @ref LL_HRTIM_FAULT_5
6847 * @param Polarity This parameter can be one of the following values:
6848 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6849 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6850 * @retval None
6851 */
LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Polarity)6852 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
6853 {
6854 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6855 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6856 REG_OFFSET_TAB_FLTINR[iFault]));
6857 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
6858 }
6859
6860 /**
6861 * @brief Get actual polarity of a fault signal.
6862 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
6863 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
6864 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
6865 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
6866 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
6867 * @param HRTIMx High Resolution Timer instance
6868 * @param Fault This parameter can be one of the following values:
6869 * @arg @ref LL_HRTIM_FAULT_1
6870 * @arg @ref LL_HRTIM_FAULT_2
6871 * @arg @ref LL_HRTIM_FAULT_3
6872 * @arg @ref LL_HRTIM_FAULT_4
6873 * @arg @ref LL_HRTIM_FAULT_5
6874 * @retval Polarity This parameter can be one of the following values:
6875 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
6876 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
6877 */
LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)6878 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
6879 {
6880 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6881 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6882 REG_OFFSET_TAB_FLTINR[iFault]));
6883 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6884 }
6885
6886 /**
6887 * @brief Set the digital noise filter of a fault signal.
6888 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
6889 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
6890 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
6891 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
6892 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
6893 * @note This function must not be called when the fault channel is enabled.
6894 * @param HRTIMx High Resolution Timer instance
6895 * @param Fault This parameter can be one of the following values:
6896 * @arg @ref LL_HRTIM_FAULT_1
6897 * @arg @ref LL_HRTIM_FAULT_2
6898 * @arg @ref LL_HRTIM_FAULT_3
6899 * @arg @ref LL_HRTIM_FAULT_4
6900 * @arg @ref LL_HRTIM_FAULT_5
6901 * @param Filter This parameter can be one of the following values:
6902 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
6903 * @arg @ref LL_HRTIM_FLT_FILTER_1
6904 * @arg @ref LL_HRTIM_FLT_FILTER_2
6905 * @arg @ref LL_HRTIM_FLT_FILTER_3
6906 * @arg @ref LL_HRTIM_FLT_FILTER_4
6907 * @arg @ref LL_HRTIM_FLT_FILTER_5
6908 * @arg @ref LL_HRTIM_FLT_FILTER_6
6909 * @arg @ref LL_HRTIM_FLT_FILTER_7
6910 * @arg @ref LL_HRTIM_FLT_FILTER_8
6911 * @arg @ref LL_HRTIM_FLT_FILTER_9
6912 * @arg @ref LL_HRTIM_FLT_FILTER_10
6913 * @arg @ref LL_HRTIM_FLT_FILTER_11
6914 * @arg @ref LL_HRTIM_FLT_FILTER_12
6915 * @arg @ref LL_HRTIM_FLT_FILTER_13
6916 * @arg @ref LL_HRTIM_FLT_FILTER_14
6917 * @arg @ref LL_HRTIM_FLT_FILTER_15
6918 * @retval None
6919 */
LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef * HRTIMx,uint32_t Fault,uint32_t Filter)6920 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
6921 {
6922 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6923 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6924 REG_OFFSET_TAB_FLTINR[iFault]));
6925 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
6926 }
6927
6928 /**
6929 * @brief Get actual digital noise filter setting of a fault signal.
6930 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
6931 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
6932 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
6933 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
6934 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
6935 * @param HRTIMx High Resolution Timer instance
6936 * @param Fault This parameter can be one of the following values:
6937 * @arg @ref LL_HRTIM_FAULT_1
6938 * @arg @ref LL_HRTIM_FAULT_2
6939 * @arg @ref LL_HRTIM_FAULT_3
6940 * @arg @ref LL_HRTIM_FAULT_4
6941 * @arg @ref LL_HRTIM_FAULT_5
6942 * @retval Filter This parameter can be one of the following values:
6943 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
6944 * @arg @ref LL_HRTIM_FLT_FILTER_1
6945 * @arg @ref LL_HRTIM_FLT_FILTER_2
6946 * @arg @ref LL_HRTIM_FLT_FILTER_3
6947 * @arg @ref LL_HRTIM_FLT_FILTER_4
6948 * @arg @ref LL_HRTIM_FLT_FILTER_5
6949 * @arg @ref LL_HRTIM_FLT_FILTER_6
6950 * @arg @ref LL_HRTIM_FLT_FILTER_7
6951 * @arg @ref LL_HRTIM_FLT_FILTER_8
6952 * @arg @ref LL_HRTIM_FLT_FILTER_9
6953 * @arg @ref LL_HRTIM_FLT_FILTER_10
6954 * @arg @ref LL_HRTIM_FLT_FILTER_11
6955 * @arg @ref LL_HRTIM_FLT_FILTER_12
6956 * @arg @ref LL_HRTIM_FLT_FILTER_13
6957 * @arg @ref LL_HRTIM_FLT_FILTER_14
6958 * @arg @ref LL_HRTIM_FLT_FILTER_15
6959 */
LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)6960 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
6961 {
6962 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
6963 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
6964 REG_OFFSET_TAB_FLTINR[iFault]));
6965 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
6966
6967 }
6968
6969 /**
6970 * @brief Set the fault circuitry prescaler.
6971 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
6972 * @param HRTIMx High Resolution Timer instance
6973 * @param Prescaler This parameter can be one of the following values:
6974 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
6975 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
6976 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
6977 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
6978 * @retval None
6979 */
LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)6980 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
6981 {
6982 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
6983 }
6984
6985 /**
6986 * @brief Get actual fault circuitry prescaler setting.
6987 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
6988 * @param HRTIMx High Resolution Timer instance
6989 * @retval Prescaler This parameter can be one of the following values:
6990 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
6991 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
6992 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
6993 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
6994 */
LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef * HRTIMx)6995 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
6996 {
6997 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
6998 }
6999
7000 /**
7001 * @brief Lock the fault signal conditioning settings.
7002 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
7003 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
7004 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
7005 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
7006 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
7007 * @param HRTIMx High Resolution Timer instance
7008 * @param Fault This parameter can be one of the following values:
7009 * @arg @ref LL_HRTIM_FAULT_1
7010 * @arg @ref LL_HRTIM_FAULT_2
7011 * @arg @ref LL_HRTIM_FAULT_3
7012 * @arg @ref LL_HRTIM_FAULT_4
7013 * @arg @ref LL_HRTIM_FAULT_5
7014 * @retval None
7015 */
LL_HRTIM_FLT_Lock(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7016 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7017 {
7018 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7019 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7020 REG_OFFSET_TAB_FLTINR[iFault]));
7021 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
7022 }
7023
7024 /**
7025 * @brief Enable the fault circuitry for the designated fault input.
7026 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
7027 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
7028 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
7029 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
7030 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable
7031 * @param HRTIMx High Resolution Timer instance
7032 * @param Fault This parameter can be one of the following values:
7033 * @arg @ref LL_HRTIM_FAULT_1
7034 * @arg @ref LL_HRTIM_FAULT_2
7035 * @arg @ref LL_HRTIM_FAULT_3
7036 * @arg @ref LL_HRTIM_FAULT_4
7037 * @arg @ref LL_HRTIM_FAULT_5
7038 * @retval None
7039 */
LL_HRTIM_FLT_Enable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7040 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7041 {
7042 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7043 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7044 REG_OFFSET_TAB_FLTINR[iFault]));
7045 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
7046 }
7047
7048 /**
7049 * @brief Disable the fault circuitry for for the designated fault input.
7050 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
7051 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
7052 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
7053 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
7054 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable
7055 * @param HRTIMx High Resolution Timer instance
7056 * @param Fault This parameter can be one of the following values:
7057 * @arg @ref LL_HRTIM_FAULT_1
7058 * @arg @ref LL_HRTIM_FAULT_2
7059 * @arg @ref LL_HRTIM_FAULT_3
7060 * @arg @ref LL_HRTIM_FAULT_4
7061 * @arg @ref LL_HRTIM_FAULT_5
7062 * @retval None
7063 */
LL_HRTIM_FLT_Disable(HRTIM_TypeDef * HRTIMx,uint32_t Fault)7064 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7065 {
7066 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7067 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7068 REG_OFFSET_TAB_FLTINR[iFault]));
7069 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
7070 }
7071
7072 /**
7073 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
7074 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
7075 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
7076 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
7077 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
7078 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
7079 * @param HRTIMx High Resolution Timer instance
7080 * @param Fault This parameter can be one of the following values:
7081 * @arg @ref LL_HRTIM_FAULT_1
7082 * @arg @ref LL_HRTIM_FAULT_2
7083 * @arg @ref LL_HRTIM_FAULT_3
7084 * @arg @ref LL_HRTIM_FAULT_4
7085 * @arg @ref LL_HRTIM_FAULT_5
7086 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
7087 */
LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef * HRTIMx,uint32_t Fault)7088 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
7089 {
7090 uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
7091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
7092 REG_OFFSET_TAB_FLTINR[iFault]));
7093 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
7094 (HRTIM_IER_FLT1)) ? 1UL : 0UL);
7095 }
7096
7097 /**
7098 * @}
7099 */
7100
7101 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
7102 * @{
7103 */
7104
7105 /**
7106 * @brief Configure the burst mode controller.
7107 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
7108 * BMCR BMCLK LL_HRTIM_BM_Config\n
7109 * BMCR BMPRSC LL_HRTIM_BM_Config
7110 * @param HRTIMx High Resolution Timer instance
7111 * @param Configuration This parameter must be a combination of all the following values:
7112 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
7113 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7114 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
7115 * @retval None
7116 */
LL_HRTIM_BM_Config(HRTIM_TypeDef * HRTIMx,uint32_t Configuration)7117 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
7118 {
7119 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
7120 }
7121
7122 /**
7123 * @brief Set the burst mode controller operating mode.
7124 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
7125 * @param HRTIMx High Resolution Timer instance
7126 * @param Mode This parameter can be one of the following values:
7127 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7128 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7129 * @retval None
7130 */
LL_HRTIM_BM_SetMode(HRTIM_TypeDef * HRTIMx,uint32_t Mode)7131 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
7132 {
7133 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
7134 }
7135
7136 /**
7137 * @brief Get actual burst mode controller operating mode.
7138 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
7139 * @param HRTIMx High Resolution Timer instance
7140 * @retval Mode This parameter can be one of the following values:
7141 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
7142 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
7143 */
LL_HRTIM_BM_GetMode(const HRTIM_TypeDef * HRTIMx)7144 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
7145 {
7146 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
7147 }
7148
7149 /**
7150 * @brief Set the burst mode controller clock source.
7151 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
7152 * @param HRTIMx High Resolution Timer instance
7153 * @param ClockSrc This parameter can be one of the following values:
7154 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7155 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7156 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7157 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7158 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7159 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7160 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7161 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7162 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7163 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7164 * @retval None
7165 */
LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef * HRTIMx,uint32_t ClockSrc)7166 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
7167 {
7168 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
7169 }
7170
7171 /**
7172 * @brief Get actual burst mode controller clock source.
7173 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
7174 * @param HRTIMx High Resolution Timer instance
7175 * @retval ClockSrc This parameter can be one of the following values:
7176 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7177 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7178 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7179 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7180 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7181 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7182 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7183 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7184 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7185 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7186 * @retval ClockSrc This parameter can be one of the following values:
7187 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
7188 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
7189 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
7190 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
7191 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
7192 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
7193 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
7194 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
7195 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
7196 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
7197 */
LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef * HRTIMx)7198 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
7199 {
7200 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
7201 }
7202
7203 /**
7204 * @brief Set the burst mode controller prescaler.
7205 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
7206 * @param HRTIMx High Resolution Timer instance
7207 * @param Prescaler This parameter can be one of the following values:
7208 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7209 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7210 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7211 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7212 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7213 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7214 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7215 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7216 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7217 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7218 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7219 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7220 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7221 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7222 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7223 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7224 * @retval None
7225 */
LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef * HRTIMx,uint32_t Prescaler)7226 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
7227 {
7228 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
7229 }
7230
7231 /**
7232 * @brief Get actual burst mode controller prescaler setting.
7233 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
7234 * @param HRTIMx High Resolution Timer instance
7235 * @retval Prescaler This parameter can be one of the following values:
7236 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
7237 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
7238 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
7239 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
7240 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
7241 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
7242 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
7243 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
7244 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
7245 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
7246 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
7247 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
7248 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
7249 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
7250 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
7251 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
7252 */
LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef * HRTIMx)7253 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
7254 {
7255 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
7256 }
7257
7258 /**
7259 * @brief Enable burst mode compare and period registers preload.
7260 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
7261 * @param HRTIMx High Resolution Timer instance
7262 * @retval None
7263 */
LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef * HRTIMx)7264 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
7265 {
7266 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7267 }
7268
7269 /**
7270 * @brief Disable burst mode compare and period registers preload.
7271 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
7272 * @param HRTIMx High Resolution Timer instance
7273 * @retval None
7274 */
LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef * HRTIMx)7275 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
7276 {
7277 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7278 }
7279
7280 /**
7281 * @brief Indicate whether burst mode compare and period registers are preloaded.
7282 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
7283 * @param HRTIMx High Resolution Timer instance
7284 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
7285 */
LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef * HRTIMx)7286 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
7287 {
7288 uint32_t temp; /* MISRAC-2012 compliance */
7289 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
7290
7291 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
7292 }
7293
7294 /**
7295 * @brief Set the burst mode controller trigger
7296 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
7297 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
7298 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
7299 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
7300 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
7301 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
7302 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
7303 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
7304 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
7305 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
7306 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
7307 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
7308 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
7309 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
7310 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
7311 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
7312 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
7313 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
7314 * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
7315 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
7316 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
7317 * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
7318 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
7319 * BMTRGR TERST LL_HRTIM_BM_SetTrig\n
7320 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
7321 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
7322 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
7323 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
7324 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
7325 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
7326 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
7327 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
7328 * @param HRTIMx High Resolution Timer instance
7329 * @param Trig This parameter can be a combination of the following values:
7330 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7331 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7332 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7333 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7334 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7335 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7336 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7337 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7338 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7339 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7340 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7341 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7342 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7343 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7344 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7345 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7346 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7347 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7348 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7349 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7350 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7351 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7352 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7353 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7354 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7355 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7356 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7357 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7358 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7359 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7360 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7361 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7362 * @retval None
7363 */
LL_HRTIM_BM_SetTrig(HRTIM_TypeDef * HRTIMx,uint32_t Trig)7364 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
7365 {
7366 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
7367 }
7368
7369 /**
7370 * @brief Get actual burst mode controller trigger.
7371 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
7372 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
7373 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
7374 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
7375 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
7376 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
7377 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
7378 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
7379 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
7380 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
7381 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
7382 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
7383 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
7384 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
7385 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
7386 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
7387 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
7388 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
7389 * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
7390 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
7391 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
7392 * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
7393 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
7394 * BMTRGR TERST LL_HRTIM_BM_GetTrig\n
7395 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
7396 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
7397 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
7398 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
7399 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
7400 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
7401 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
7402 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
7403 * @param HRTIMx High Resolution Timer instance
7404 * @retval Trig This parameter can be a combination of the following values:
7405 * @arg @ref LL_HRTIM_BM_TRIG_NONE
7406 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
7407 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
7408 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
7409 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
7410 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
7411 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
7412 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
7413 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
7414 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
7415 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
7416 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
7417 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
7418 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
7419 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
7420 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
7421 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
7422 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
7423 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
7424 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
7425 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
7426 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
7427 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
7428 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
7429 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
7430 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
7431 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
7432 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
7433 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
7434 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
7435 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
7436 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
7437 */
LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef * HRTIMx)7438 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
7439 {
7440 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
7441 }
7442
7443 /**
7444 * @brief Set the burst mode controller compare value.
7445 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
7446 * @param HRTIMx High Resolution Timer instance
7447 * @param CompareValue Compare value must be above or equal to 3
7448 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7449 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7450 * @retval None
7451 */
LL_HRTIM_BM_SetCompare(HRTIM_TypeDef * HRTIMx,uint32_t CompareValue)7452 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
7453 {
7454 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
7455 }
7456
7457 /**
7458 * @brief Get actual burst mode controller compare value.
7459 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
7460 * @param HRTIMx High Resolution Timer instance
7461 * @retval CompareValue Compare value must be above or equal to 3
7462 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
7463 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7464 */
LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef * HRTIMx)7465 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
7466 {
7467 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
7468 }
7469
7470 /**
7471 * @brief Set the burst mode controller period.
7472 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
7473 * @param HRTIMx High Resolution Timer instance
7474 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
7475 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7476 * The maximum value is 0x0000 FFDF.
7477 * @retval None
7478 */
LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef * HRTIMx,uint32_t Period)7479 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
7480 {
7481 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
7482 }
7483
7484 /**
7485 * @brief Get actual burst mode controller period.
7486 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
7487 * @param HRTIMx High Resolution Timer instance
7488 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
7489 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
7490 * The maximum value is 0x0000 FFDF.
7491 */
LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef * HRTIMx)7492 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
7493 {
7494 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
7495 }
7496
7497 /**
7498 * @brief Enable the burst mode controller
7499 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
7500 * @param HRTIMx High Resolution Timer instance
7501 * @retval None
7502 */
LL_HRTIM_BM_Enable(HRTIM_TypeDef * HRTIMx)7503 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
7504 {
7505 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
7506 }
7507
7508 /**
7509 * @brief Disable the burst mode controller
7510 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
7511 * @param HRTIMx High Resolution Timer instance
7512 * @retval None
7513 */
LL_HRTIM_BM_Disable(HRTIM_TypeDef * HRTIMx)7514 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
7515 {
7516 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
7517 }
7518
7519 /**
7520 * @brief Indicate whether the burst mode controller is enabled.
7521 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
7522 * @param HRTIMx High Resolution Timer instance
7523 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
7524 */
LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef * HRTIMx)7525 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
7526 {
7527 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
7528 }
7529
7530 /**
7531 * @brief Trigger the burst operation (software trigger)
7532 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
7533 * @param HRTIMx High Resolution Timer instance
7534 * @retval None
7535 */
LL_HRTIM_BM_Start(HRTIM_TypeDef * HRTIMx)7536 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
7537 {
7538 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
7539 }
7540
7541 /**
7542 * @brief Stop the burst mode operation.
7543 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
7544 * @note Causes a burst mode early termination.
7545 * @param HRTIMx High Resolution Timer instance
7546 * @retval None
7547 */
LL_HRTIM_BM_Stop(HRTIM_TypeDef * HRTIMx)7548 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
7549 {
7550 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
7551 }
7552
7553 /**
7554 * @brief Get actual burst mode status
7555 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
7556 * @param HRTIMx High Resolution Timer instance
7557 * @retval Status This parameter can be one of the following values:
7558 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
7559 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
7560 */
LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef * HRTIMx)7561 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
7562 {
7563 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
7564 }
7565
7566 /**
7567 * @}
7568 */
7569
7570 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
7571 * @{
7572 */
7573
7574 /**
7575 * @brief Clear the Fault 1 interrupt flag.
7576 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
7577 * @param HRTIMx High Resolution Timer instance
7578 * @retval None
7579 */
LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef * HRTIMx)7580 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
7581 {
7582 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
7583 }
7584
7585 /**
7586 * @brief Indicate whether Fault 1 interrupt occurred.
7587 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
7588 * @param HRTIMx High Resolution Timer instance
7589 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
7590 */
LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef * HRTIMx)7591 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
7592 {
7593 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
7594 }
7595
7596 /**
7597 * @brief Clear the Fault 2 interrupt flag.
7598 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
7599 * @param HRTIMx High Resolution Timer instance
7600 * @retval None
7601 */
LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef * HRTIMx)7602 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
7603 {
7604 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
7605 }
7606
7607 /**
7608 * @brief Indicate whether Fault 2 interrupt occurred.
7609 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
7610 * @param HRTIMx High Resolution Timer instance
7611 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
7612 */
LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef * HRTIMx)7613 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
7614 {
7615 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
7616 }
7617
7618 /**
7619 * @brief Clear the Fault 3 interrupt flag.
7620 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
7621 * @param HRTIMx High Resolution Timer instance
7622 * @retval None
7623 */
LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef * HRTIMx)7624 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
7625 {
7626 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
7627 }
7628
7629 /**
7630 * @brief Indicate whether Fault 3 interrupt occurred.
7631 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
7632 * @param HRTIMx High Resolution Timer instance
7633 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
7634 */
LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef * HRTIMx)7635 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
7636 {
7637 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
7638 }
7639
7640 /**
7641 * @brief Clear the Fault 4 interrupt flag.
7642 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
7643 * @param HRTIMx High Resolution Timer instance
7644 * @retval None
7645 */
LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef * HRTIMx)7646 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
7647 {
7648 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
7649 }
7650
7651 /**
7652 * @brief Indicate whether Fault 4 interrupt occurred.
7653 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
7654 * @param HRTIMx High Resolution Timer instance
7655 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
7656 */
LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef * HRTIMx)7657 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
7658 {
7659 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
7660 }
7661
7662 /**
7663 * @brief Clear the Fault 5 interrupt flag.
7664 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
7665 * @param HRTIMx High Resolution Timer instance
7666 * @retval None
7667 */
LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef * HRTIMx)7668 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
7669 {
7670 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
7671 }
7672
7673 /**
7674 * @brief Indicate whether Fault 5 interrupt occurred.
7675 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
7676 * @param HRTIMx High Resolution Timer instance
7677 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
7678 */
LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef * HRTIMx)7679 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
7680 {
7681 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
7682 }
7683
7684 /**
7685 * @brief Clear the System Fault interrupt flag.
7686 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
7687 * @param HRTIMx High Resolution Timer instance
7688 * @retval None
7689 */
LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef * HRTIMx)7690 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
7691 {
7692 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
7693 }
7694
7695 /**
7696 * @brief Indicate whether System Fault interrupt occurred.
7697 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
7698 * @param HRTIMx High Resolution Timer instance
7699 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
7700 */
LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef * HRTIMx)7701 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
7702 {
7703 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
7704 }
7705
7706 /**
7707 * @brief Clear the Burst Mode period interrupt flag.
7708 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
7709 * @param HRTIMx High Resolution Timer instance
7710 * @retval None
7711 */
LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef * HRTIMx)7712 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
7713 {
7714 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
7715 }
7716
7717 /**
7718 * @brief Indicate whether Burst Mode period interrupt occurred.
7719 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
7720 * @param HRTIMx High Resolution Timer instance
7721 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
7722 */
LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef * HRTIMx)7723 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
7724 {
7725 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
7726 }
7727
7728 /**
7729 * @brief Clear the Synchronization Input interrupt flag.
7730 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
7731 * @param HRTIMx High Resolution Timer instance
7732 * @retval None
7733 */
LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef * HRTIMx)7734 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
7735 {
7736 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
7737 }
7738
7739 /**
7740 * @brief Indicate whether the Synchronization Input interrupt occurred.
7741 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
7742 * @param HRTIMx High Resolution Timer instance
7743 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
7744 */
LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef * HRTIMx)7745 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
7746 {
7747 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
7748 }
7749
7750 /**
7751 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
7752 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
7753 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
7754 * @param HRTIMx High Resolution Timer instance
7755 * @param Timer This parameter can be one of the following values:
7756 * @arg @ref LL_HRTIM_TIMER_MASTER
7757 * @arg @ref LL_HRTIM_TIMER_A
7758 * @arg @ref LL_HRTIM_TIMER_B
7759 * @arg @ref LL_HRTIM_TIMER_C
7760 * @arg @ref LL_HRTIM_TIMER_D
7761 * @arg @ref LL_HRTIM_TIMER_E
7762 * @retval None
7763 */
LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7764 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7765 {
7766 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7767 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7768 REG_OFFSET_TAB_TIMER[iTimer]));
7769 SET_BIT(*pReg, HRTIM_MICR_MUPD);
7770 }
7771
7772 /**
7773 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
7774 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
7775 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
7776 * @param HRTIMx High Resolution Timer instance
7777 * @param Timer This parameter can be one of the following values:
7778 * @arg @ref LL_HRTIM_TIMER_MASTER
7779 * @arg @ref LL_HRTIM_TIMER_A
7780 * @arg @ref LL_HRTIM_TIMER_B
7781 * @arg @ref LL_HRTIM_TIMER_C
7782 * @arg @ref LL_HRTIM_TIMER_D
7783 * @arg @ref LL_HRTIM_TIMER_E
7784 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7785 */
LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7786 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7787 {
7788 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7789 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7790 REG_OFFSET_TAB_TIMER[iTimer]));
7791
7792 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
7793 }
7794
7795 /**
7796 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
7797 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
7798 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
7799 * @param HRTIMx High Resolution Timer instance
7800 * @param Timer This parameter can be one of the following values:
7801 * @arg @ref LL_HRTIM_TIMER_MASTER
7802 * @arg @ref LL_HRTIM_TIMER_A
7803 * @arg @ref LL_HRTIM_TIMER_B
7804 * @arg @ref LL_HRTIM_TIMER_C
7805 * @arg @ref LL_HRTIM_TIMER_D
7806 * @arg @ref LL_HRTIM_TIMER_E
7807 * @retval None
7808 */
LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7809 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7810 {
7811 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7812 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7813 REG_OFFSET_TAB_TIMER[iTimer]));
7814 SET_BIT(*pReg, HRTIM_MICR_MREP);
7815
7816 }
7817
7818 /**
7819 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
7820 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
7821 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
7822 * @param HRTIMx High Resolution Timer instance
7823 * @param Timer This parameter can be one of the following values:
7824 * @arg @ref LL_HRTIM_TIMER_MASTER
7825 * @arg @ref LL_HRTIM_TIMER_A
7826 * @arg @ref LL_HRTIM_TIMER_B
7827 * @arg @ref LL_HRTIM_TIMER_C
7828 * @arg @ref LL_HRTIM_TIMER_D
7829 * @arg @ref LL_HRTIM_TIMER_E
7830 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7831 */
LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7832 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7833 {
7834 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7835 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7836 REG_OFFSET_TAB_TIMER[iTimer]));
7837
7838 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
7839 }
7840
7841 /**
7842 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
7843 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
7844 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
7845 * @param HRTIMx High Resolution Timer instance
7846 * @param Timer This parameter can be one of the following values:
7847 * @arg @ref LL_HRTIM_TIMER_MASTER
7848 * @arg @ref LL_HRTIM_TIMER_A
7849 * @arg @ref LL_HRTIM_TIMER_B
7850 * @arg @ref LL_HRTIM_TIMER_C
7851 * @arg @ref LL_HRTIM_TIMER_D
7852 * @arg @ref LL_HRTIM_TIMER_E
7853 * @retval None
7854 */
LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7855 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7856 {
7857 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7858 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7859 REG_OFFSET_TAB_TIMER[iTimer]));
7860 SET_BIT(*pReg, HRTIM_MICR_MCMP1);
7861 }
7862
7863 /**
7864 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
7865 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
7866 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
7867 * @param HRTIMx High Resolution Timer instance
7868 * @param Timer This parameter can be one of the following values:
7869 * @arg @ref LL_HRTIM_TIMER_MASTER
7870 * @arg @ref LL_HRTIM_TIMER_A
7871 * @arg @ref LL_HRTIM_TIMER_B
7872 * @arg @ref LL_HRTIM_TIMER_C
7873 * @arg @ref LL_HRTIM_TIMER_D
7874 * @arg @ref LL_HRTIM_TIMER_E
7875 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7876 */
LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7877 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7878 {
7879 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7880 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7881 REG_OFFSET_TAB_TIMER[iTimer]));
7882
7883 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
7884 }
7885
7886 /**
7887 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
7888 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
7889 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
7890 * @param HRTIMx High Resolution Timer instance
7891 * @param Timer This parameter can be one of the following values:
7892 * @arg @ref LL_HRTIM_TIMER_MASTER
7893 * @arg @ref LL_HRTIM_TIMER_A
7894 * @arg @ref LL_HRTIM_TIMER_B
7895 * @arg @ref LL_HRTIM_TIMER_C
7896 * @arg @ref LL_HRTIM_TIMER_D
7897 * @arg @ref LL_HRTIM_TIMER_E
7898 * @retval None
7899 */
LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7900 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7901 {
7902 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7903 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7904 REG_OFFSET_TAB_TIMER[iTimer]));
7905 SET_BIT(*pReg, HRTIM_MICR_MCMP2);
7906 }
7907
7908 /**
7909 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
7910 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
7911 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
7912 * @param HRTIMx High Resolution Timer instance
7913 * @param Timer This parameter can be one of the following values:
7914 * @arg @ref LL_HRTIM_TIMER_MASTER
7915 * @arg @ref LL_HRTIM_TIMER_A
7916 * @arg @ref LL_HRTIM_TIMER_B
7917 * @arg @ref LL_HRTIM_TIMER_C
7918 * @arg @ref LL_HRTIM_TIMER_D
7919 * @arg @ref LL_HRTIM_TIMER_E
7920 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7921 */
LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7922 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7923 {
7924 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7925 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7926 REG_OFFSET_TAB_TIMER[iTimer]));
7927
7928 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
7929 }
7930
7931 /**
7932 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
7933 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
7934 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
7935 * @param HRTIMx High Resolution Timer instance
7936 * @param Timer This parameter can be one of the following values:
7937 * @arg @ref LL_HRTIM_TIMER_MASTER
7938 * @arg @ref LL_HRTIM_TIMER_A
7939 * @arg @ref LL_HRTIM_TIMER_B
7940 * @arg @ref LL_HRTIM_TIMER_C
7941 * @arg @ref LL_HRTIM_TIMER_D
7942 * @arg @ref LL_HRTIM_TIMER_E
7943 * @retval None
7944 */
LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7945 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7946 {
7947 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7948 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7949 REG_OFFSET_TAB_TIMER[iTimer]));
7950 SET_BIT(*pReg, HRTIM_MICR_MCMP3);
7951 }
7952
7953 /**
7954 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
7955 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
7956 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
7957 * @param HRTIMx High Resolution Timer instance
7958 * @param Timer This parameter can be one of the following values:
7959 * @arg @ref LL_HRTIM_TIMER_MASTER
7960 * @arg @ref LL_HRTIM_TIMER_A
7961 * @arg @ref LL_HRTIM_TIMER_B
7962 * @arg @ref LL_HRTIM_TIMER_C
7963 * @arg @ref LL_HRTIM_TIMER_D
7964 * @arg @ref LL_HRTIM_TIMER_E
7965 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
7966 */
LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)7967 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7968 {
7969 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7970 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
7971 REG_OFFSET_TAB_TIMER[iTimer]));
7972
7973 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
7974 }
7975
7976 /**
7977 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
7978 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
7979 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
7980 * @param HRTIMx High Resolution Timer instance
7981 * @param Timer This parameter can be one of the following values:
7982 * @arg @ref LL_HRTIM_TIMER_MASTER
7983 * @arg @ref LL_HRTIM_TIMER_A
7984 * @arg @ref LL_HRTIM_TIMER_B
7985 * @arg @ref LL_HRTIM_TIMER_C
7986 * @arg @ref LL_HRTIM_TIMER_D
7987 * @arg @ref LL_HRTIM_TIMER_E
7988 * @retval None
7989 */
LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)7990 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
7991 {
7992 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
7993 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
7994 REG_OFFSET_TAB_TIMER[iTimer]));
7995 SET_BIT(*pReg, HRTIM_MICR_MCMP4);
7996 }
7997
7998 /**
7999 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
8000 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
8001 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
8002 * @param HRTIMx High Resolution Timer instance
8003 * @param Timer This parameter can be one of the following values:
8004 * @arg @ref LL_HRTIM_TIMER_MASTER
8005 * @arg @ref LL_HRTIM_TIMER_A
8006 * @arg @ref LL_HRTIM_TIMER_B
8007 * @arg @ref LL_HRTIM_TIMER_C
8008 * @arg @ref LL_HRTIM_TIMER_D
8009 * @arg @ref LL_HRTIM_TIMER_E
8010 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
8011 */
LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8012 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8013 {
8014 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8015 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8016 REG_OFFSET_TAB_TIMER[iTimer]));
8017
8018 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
8019 }
8020
8021 /**
8022 * @brief Clear the capture 1 interrupt flag for a given timer.
8023 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
8024 * @param HRTIMx High Resolution Timer instance
8025 * @param Timer This parameter can be one of the following values:
8026 * @arg @ref LL_HRTIM_TIMER_A
8027 * @arg @ref LL_HRTIM_TIMER_B
8028 * @arg @ref LL_HRTIM_TIMER_C
8029 * @arg @ref LL_HRTIM_TIMER_D
8030 * @arg @ref LL_HRTIM_TIMER_E
8031 * @retval None
8032 */
LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8033 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8034 {
8035 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8036 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8037 REG_OFFSET_TAB_TIMER[iTimer]));
8038 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
8039 }
8040
8041 /**
8042 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
8043 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
8044 * @param HRTIMx High Resolution Timer instance
8045 * @param Timer This parameter can be one of the following values:
8046 * @arg @ref LL_HRTIM_TIMER_A
8047 * @arg @ref LL_HRTIM_TIMER_B
8048 * @arg @ref LL_HRTIM_TIMER_C
8049 * @arg @ref LL_HRTIM_TIMER_D
8050 * @arg @ref LL_HRTIM_TIMER_E
8051 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
8052 */
LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8053 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8054 {
8055 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8056 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8057 REG_OFFSET_TAB_TIMER[iTimer]));
8058
8059 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
8060 }
8061
8062 /**
8063 * @brief Clear the capture 2 interrupt flag for a given timer.
8064 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
8065 * @param HRTIMx High Resolution Timer instance
8066 * @param Timer This parameter can be one of the following values:
8067 * @arg @ref LL_HRTIM_TIMER_A
8068 * @arg @ref LL_HRTIM_TIMER_B
8069 * @arg @ref LL_HRTIM_TIMER_C
8070 * @arg @ref LL_HRTIM_TIMER_D
8071 * @arg @ref LL_HRTIM_TIMER_E
8072 * @retval None
8073 */
LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8074 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8075 {
8076 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8077 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8078 REG_OFFSET_TAB_TIMER[iTimer]));
8079 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
8080 }
8081
8082 /**
8083 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
8084 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
8085 * @param HRTIMx High Resolution Timer instance
8086 * @param Timer This parameter can be one of the following values:
8087 * @arg @ref LL_HRTIM_TIMER_A
8088 * @arg @ref LL_HRTIM_TIMER_B
8089 * @arg @ref LL_HRTIM_TIMER_C
8090 * @arg @ref LL_HRTIM_TIMER_D
8091 * @arg @ref LL_HRTIM_TIMER_E
8092 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
8093 */
LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8094 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8095 {
8096 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8097 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8098 REG_OFFSET_TAB_TIMER[iTimer]));
8099
8100 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
8101 }
8102
8103 /**
8104 * @brief Clear the output 1 set interrupt flag for a given timer.
8105 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
8106 * @param HRTIMx High Resolution Timer instance
8107 * @param Timer This parameter can be one of the following values:
8108 * @arg @ref LL_HRTIM_TIMER_A
8109 * @arg @ref LL_HRTIM_TIMER_B
8110 * @arg @ref LL_HRTIM_TIMER_C
8111 * @arg @ref LL_HRTIM_TIMER_D
8112 * @arg @ref LL_HRTIM_TIMER_E
8113 * @retval None
8114 */
LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8115 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8116 {
8117 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8118 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8119 REG_OFFSET_TAB_TIMER[iTimer]));
8120 SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
8121 }
8122
8123 /**
8124 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
8125 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
8126 * @param HRTIMx High Resolution Timer instance
8127 * @param Timer This parameter can be one of the following values:
8128 * @arg @ref LL_HRTIM_TIMER_A
8129 * @arg @ref LL_HRTIM_TIMER_B
8130 * @arg @ref LL_HRTIM_TIMER_C
8131 * @arg @ref LL_HRTIM_TIMER_D
8132 * @arg @ref LL_HRTIM_TIMER_E
8133 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
8134 */
LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8135 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8136 {
8137 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8138 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8139 REG_OFFSET_TAB_TIMER[iTimer]));
8140
8141 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
8142 }
8143
8144 /**
8145 * @brief Clear the output 1 reset interrupt flag for a given timer.
8146 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
8147 * @param HRTIMx High Resolution Timer instance
8148 * @param Timer This parameter can be one of the following values:
8149 * @arg @ref LL_HRTIM_TIMER_A
8150 * @arg @ref LL_HRTIM_TIMER_B
8151 * @arg @ref LL_HRTIM_TIMER_C
8152 * @arg @ref LL_HRTIM_TIMER_D
8153 * @arg @ref LL_HRTIM_TIMER_E
8154 * @retval None
8155 */
LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8156 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8157 {
8158 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8159 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8160 REG_OFFSET_TAB_TIMER[iTimer]));
8161 SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
8162 }
8163
8164 /**
8165 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
8166 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
8167 * @param HRTIMx High Resolution Timer instance
8168 * @param Timer This parameter can be one of the following values:
8169 * @arg @ref LL_HRTIM_TIMER_A
8170 * @arg @ref LL_HRTIM_TIMER_B
8171 * @arg @ref LL_HRTIM_TIMER_C
8172 * @arg @ref LL_HRTIM_TIMER_D
8173 * @arg @ref LL_HRTIM_TIMER_E
8174 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
8175 */
LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8176 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8177 {
8178 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8179 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8180 REG_OFFSET_TAB_TIMER[iTimer]));
8181
8182 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
8183 }
8184
8185 /**
8186 * @brief Clear the output 2 set interrupt flag for a given timer.
8187 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
8188 * @param HRTIMx High Resolution Timer instance
8189 * @param Timer This parameter can be one of the following values:
8190 * @arg @ref LL_HRTIM_TIMER_A
8191 * @arg @ref LL_HRTIM_TIMER_B
8192 * @arg @ref LL_HRTIM_TIMER_C
8193 * @arg @ref LL_HRTIM_TIMER_D
8194 * @arg @ref LL_HRTIM_TIMER_E
8195 * @retval None
8196 */
LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8197 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8198 {
8199 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8200 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8201 REG_OFFSET_TAB_TIMER[iTimer]));
8202 SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
8203 }
8204
8205 /**
8206 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
8207 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
8208 * @param HRTIMx High Resolution Timer instance
8209 * @param Timer This parameter can be one of the following values:
8210 * @arg @ref LL_HRTIM_TIMER_A
8211 * @arg @ref LL_HRTIM_TIMER_B
8212 * @arg @ref LL_HRTIM_TIMER_C
8213 * @arg @ref LL_HRTIM_TIMER_D
8214 * @arg @ref LL_HRTIM_TIMER_E
8215 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
8216 */
LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8217 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8218 {
8219 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8220 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8221 REG_OFFSET_TAB_TIMER[iTimer]));
8222
8223 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
8224 }
8225
8226 /**
8227 * @brief Clear the output 2reset interrupt flag for a given timer.
8228 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
8229 * @param HRTIMx High Resolution Timer instance
8230 * @param Timer This parameter can be one of the following values:
8231 * @arg @ref LL_HRTIM_TIMER_A
8232 * @arg @ref LL_HRTIM_TIMER_B
8233 * @arg @ref LL_HRTIM_TIMER_C
8234 * @arg @ref LL_HRTIM_TIMER_D
8235 * @arg @ref LL_HRTIM_TIMER_E
8236 * @retval None
8237 */
LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8238 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8239 {
8240 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8241 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8242 REG_OFFSET_TAB_TIMER[iTimer]));
8243 SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
8244 }
8245
8246 /**
8247 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
8248 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
8249 * @param HRTIMx High Resolution Timer instance
8250 * @param Timer This parameter can be one of the following values:
8251 * @arg @ref LL_HRTIM_TIMER_A
8252 * @arg @ref LL_HRTIM_TIMER_B
8253 * @arg @ref LL_HRTIM_TIMER_C
8254 * @arg @ref LL_HRTIM_TIMER_D
8255 * @arg @ref LL_HRTIM_TIMER_E
8256 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
8257 */
LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8258 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8259 {
8260 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8261 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8262 REG_OFFSET_TAB_TIMER[iTimer]));
8263
8264 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
8265 }
8266
8267 /**
8268 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
8269 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
8270 * @param HRTIMx High Resolution Timer instance
8271 * @param Timer This parameter can be one of the following values:
8272 * @arg @ref LL_HRTIM_TIMER_A
8273 * @arg @ref LL_HRTIM_TIMER_B
8274 * @arg @ref LL_HRTIM_TIMER_C
8275 * @arg @ref LL_HRTIM_TIMER_D
8276 * @arg @ref LL_HRTIM_TIMER_E
8277 * @retval None
8278 */
LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8279 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8280 {
8281 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8283 REG_OFFSET_TAB_TIMER[iTimer]));
8284 SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
8285 }
8286
8287 /**
8288 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
8289 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
8290 * @param HRTIMx High Resolution Timer instance
8291 * @param Timer This parameter can be one of the following values:
8292 * @arg @ref LL_HRTIM_TIMER_A
8293 * @arg @ref LL_HRTIM_TIMER_B
8294 * @arg @ref LL_HRTIM_TIMER_C
8295 * @arg @ref LL_HRTIM_TIMER_D
8296 * @arg @ref LL_HRTIM_TIMER_E
8297 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
8298 */
LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8299 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8300 {
8301 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8302 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8303 REG_OFFSET_TAB_TIMER[iTimer]));
8304
8305 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
8306 }
8307
8308 /**
8309 * @brief Clear the delayed protection interrupt flag for a given timer.
8310 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
8311 * @param HRTIMx High Resolution Timer instance
8312 * @param Timer This parameter can be one of the following values:
8313 * @arg @ref LL_HRTIM_TIMER_A
8314 * @arg @ref LL_HRTIM_TIMER_B
8315 * @arg @ref LL_HRTIM_TIMER_C
8316 * @arg @ref LL_HRTIM_TIMER_D
8317 * @arg @ref LL_HRTIM_TIMER_E
8318 * @retval None
8319 */
LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8320 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8321 {
8322 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8323 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
8324 REG_OFFSET_TAB_TIMER[iTimer]));
8325 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
8326 }
8327
8328 /**
8329 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
8330 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
8331 * @param HRTIMx High Resolution Timer instance
8332 * @param Timer This parameter can be one of the following values:
8333 * @arg @ref LL_HRTIM_TIMER_A
8334 * @arg @ref LL_HRTIM_TIMER_B
8335 * @arg @ref LL_HRTIM_TIMER_C
8336 * @arg @ref LL_HRTIM_TIMER_D
8337 * @arg @ref LL_HRTIM_TIMER_E
8338 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
8339 */
LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8340 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8341 {
8342 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8343 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
8344 REG_OFFSET_TAB_TIMER[iTimer]));
8345
8346 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
8347 }
8348
8349 /**
8350 * @}
8351 */
8352
8353 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
8354 * @{
8355 */
8356
8357 /**
8358 * @brief Enable the fault 1 interrupt.
8359 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
8360 * @param HRTIMx High Resolution Timer instance
8361 * @retval None
8362 */
LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef * HRTIMx)8363 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
8364 {
8365 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
8366 }
8367
8368 /**
8369 * @brief Disable the fault 1 interrupt.
8370 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
8371 * @param HRTIMx High Resolution Timer instance
8372 * @retval None
8373 */
LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef * HRTIMx)8374 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
8375 {
8376 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
8377 }
8378
8379 /**
8380 * @brief Indicate whether the fault 1 interrupt is enabled.
8381 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
8382 * @param HRTIMx High Resolution Timer instance
8383 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
8384 */
LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef * HRTIMx)8385 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
8386 {
8387 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
8388 }
8389
8390 /**
8391 * @brief Enable the fault 2 interrupt.
8392 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
8393 * @param HRTIMx High Resolution Timer instance
8394 * @retval None
8395 */
LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef * HRTIMx)8396 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
8397 {
8398 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
8399 }
8400
8401 /**
8402 * @brief Disable the fault 2 interrupt.
8403 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
8404 * @param HRTIMx High Resolution Timer instance
8405 * @retval None
8406 */
LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef * HRTIMx)8407 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
8408 {
8409 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
8410 }
8411
8412 /**
8413 * @brief Indicate whether the fault 2 interrupt is enabled.
8414 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
8415 * @param HRTIMx High Resolution Timer instance
8416 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
8417 */
LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef * HRTIMx)8418 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
8419 {
8420 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
8421 }
8422
8423 /**
8424 * @brief Enable the fault 3 interrupt.
8425 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
8426 * @param HRTIMx High Resolution Timer instance
8427 * @retval None
8428 */
LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef * HRTIMx)8429 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
8430 {
8431 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
8432 }
8433
8434 /**
8435 * @brief Disable the fault 3 interrupt.
8436 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
8437 * @param HRTIMx High Resolution Timer instance
8438 * @retval None
8439 */
LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef * HRTIMx)8440 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
8441 {
8442 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
8443 }
8444
8445 /**
8446 * @brief Indicate whether the fault 3 interrupt is enabled.
8447 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
8448 * @param HRTIMx High Resolution Timer instance
8449 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
8450 */
LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef * HRTIMx)8451 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
8452 {
8453 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
8454 }
8455
8456 /**
8457 * @brief Enable the fault 4 interrupt.
8458 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
8459 * @param HRTIMx High Resolution Timer instance
8460 * @retval None
8461 */
LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef * HRTIMx)8462 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
8463 {
8464 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
8465 }
8466
8467 /**
8468 * @brief Disable the fault 4 interrupt.
8469 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
8470 * @param HRTIMx High Resolution Timer instance
8471 * @retval None
8472 */
LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef * HRTIMx)8473 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
8474 {
8475 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
8476 }
8477
8478 /**
8479 * @brief Indicate whether the fault 4 interrupt is enabled.
8480 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
8481 * @param HRTIMx High Resolution Timer instance
8482 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
8483 */
LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef * HRTIMx)8484 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
8485 {
8486 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
8487 }
8488
8489 /**
8490 * @brief Enable the fault 5 interrupt.
8491 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
8492 * @param HRTIMx High Resolution Timer instance
8493 * @retval None
8494 */
LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef * HRTIMx)8495 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
8496 {
8497 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
8498 }
8499
8500 /**
8501 * @brief Disable the fault 5 interrupt.
8502 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
8503 * @param HRTIMx High Resolution Timer instance
8504 * @retval None
8505 */
LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef * HRTIMx)8506 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
8507 {
8508 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
8509 }
8510
8511 /**
8512 * @brief Indicate whether the fault 5 interrupt is enabled.
8513 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
8514 * @param HRTIMx High Resolution Timer instance
8515 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
8516 */
LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef * HRTIMx)8517 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
8518 {
8519 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
8520 }
8521
8522 /**
8523 * @brief Enable the system fault interrupt.
8524 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
8525 * @param HRTIMx High Resolution Timer instance
8526 * @retval None
8527 */
LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)8528 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
8529 {
8530 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
8531 }
8532
8533 /**
8534 * @brief Disable the system fault interrupt.
8535 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
8536 * @param HRTIMx High Resolution Timer instance
8537 * @retval None
8538 */
LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef * HRTIMx)8539 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
8540 {
8541 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
8542 }
8543
8544 /**
8545 * @brief Indicate whether the system fault interrupt is enabled.
8546 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
8547 * @param HRTIMx High Resolution Timer instance
8548 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
8549 */
LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef * HRTIMx)8550 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
8551 {
8552 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
8553 }
8554
8555 /**
8556 * @brief Enable the burst mode period interrupt.
8557 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
8558 * @param HRTIMx High Resolution Timer instance
8559 * @retval None
8560 */
LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef * HRTIMx)8561 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
8562 {
8563 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
8564 }
8565
8566 /**
8567 * @brief Disable the burst mode period interrupt.
8568 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
8569 * @param HRTIMx High Resolution Timer instance
8570 * @retval None
8571 */
LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef * HRTIMx)8572 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
8573 {
8574 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
8575 }
8576
8577 /**
8578 * @brief Indicate whether the burst mode period interrupt is enabled.
8579 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
8580 * @param HRTIMx High Resolution Timer instance
8581 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
8582 */
LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef * HRTIMx)8583 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
8584 {
8585 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
8586 }
8587
8588 /**
8589 * @brief Enable the synchronization input interrupt.
8590 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
8591 * @param HRTIMx High Resolution Timer instance
8592 * @retval None
8593 */
LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef * HRTIMx)8594 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
8595 {
8596 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
8597 }
8598
8599 /**
8600 * @brief Disable the synchronization input interrupt.
8601 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
8602 * @param HRTIMx High Resolution Timer instance
8603 * @retval None
8604 */
LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef * HRTIMx)8605 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
8606 {
8607 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
8608 }
8609
8610 /**
8611 * @brief Indicate whether the synchronization input interrupt is enabled.
8612 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
8613 * @param HRTIMx High Resolution Timer instance
8614 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
8615 */
LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef * HRTIMx)8616 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
8617 {
8618 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
8619 }
8620
8621 /**
8622 * @brief Enable the update interrupt for a given timer.
8623 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
8624 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
8625 * @param HRTIMx High Resolution Timer instance
8626 * @param Timer This parameter can be one of the following values:
8627 * @arg @ref LL_HRTIM_TIMER_MASTER
8628 * @arg @ref LL_HRTIM_TIMER_A
8629 * @arg @ref LL_HRTIM_TIMER_B
8630 * @arg @ref LL_HRTIM_TIMER_C
8631 * @arg @ref LL_HRTIM_TIMER_D
8632 * @arg @ref LL_HRTIM_TIMER_E
8633 * @retval None
8634 */
LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8635 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8636 {
8637 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8638 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8639 REG_OFFSET_TAB_TIMER[iTimer]));
8640 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
8641 }
8642
8643 /**
8644 * @brief Disable the update interrupt for a given timer.
8645 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
8646 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
8647 * @param HRTIMx High Resolution Timer instance
8648 * @param Timer This parameter can be one of the following values:
8649 * @arg @ref LL_HRTIM_TIMER_MASTER
8650 * @arg @ref LL_HRTIM_TIMER_A
8651 * @arg @ref LL_HRTIM_TIMER_B
8652 * @arg @ref LL_HRTIM_TIMER_C
8653 * @arg @ref LL_HRTIM_TIMER_D
8654 * @arg @ref LL_HRTIM_TIMER_E
8655 * @retval None
8656 */
LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8657 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8658 {
8659 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8660 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8661 REG_OFFSET_TAB_TIMER[iTimer]));
8662 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
8663 }
8664
8665 /**
8666 * @brief Indicate whether the update interrupt is enabled for a given timer.
8667 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
8668 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
8669 * @param HRTIMx High Resolution Timer instance
8670 * @param Timer This parameter can be one of the following values:
8671 * @arg @ref LL_HRTIM_TIMER_MASTER
8672 * @arg @ref LL_HRTIM_TIMER_A
8673 * @arg @ref LL_HRTIM_TIMER_B
8674 * @arg @ref LL_HRTIM_TIMER_C
8675 * @arg @ref LL_HRTIM_TIMER_D
8676 * @arg @ref LL_HRTIM_TIMER_E
8677 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8678 */
LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8679 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8680 {
8681 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8682 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8683 REG_OFFSET_TAB_TIMER[iTimer]));
8684
8685 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
8686 }
8687
8688 /**
8689 * @brief Enable the repetition interrupt for a given timer.
8690 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
8691 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
8692 * @param HRTIMx High Resolution Timer instance
8693 * @param Timer This parameter can be one of the following values:
8694 * @arg @ref LL_HRTIM_TIMER_MASTER
8695 * @arg @ref LL_HRTIM_TIMER_A
8696 * @arg @ref LL_HRTIM_TIMER_B
8697 * @arg @ref LL_HRTIM_TIMER_C
8698 * @arg @ref LL_HRTIM_TIMER_D
8699 * @arg @ref LL_HRTIM_TIMER_E
8700 * @retval None
8701 */
LL_HRTIM_EnableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8702 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8703 {
8704 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8705 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8706 REG_OFFSET_TAB_TIMER[iTimer]));
8707 SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
8708 }
8709
8710 /**
8711 * @brief Disable the repetition interrupt for a given timer.
8712 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
8713 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
8714 * @param HRTIMx High Resolution Timer instance
8715 * @param Timer This parameter can be one of the following values:
8716 * @arg @ref LL_HRTIM_TIMER_MASTER
8717 * @arg @ref LL_HRTIM_TIMER_A
8718 * @arg @ref LL_HRTIM_TIMER_B
8719 * @arg @ref LL_HRTIM_TIMER_C
8720 * @arg @ref LL_HRTIM_TIMER_D
8721 * @arg @ref LL_HRTIM_TIMER_E
8722 * @retval None
8723 */
LL_HRTIM_DisableIT_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8724 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8725 {
8726 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8727 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8728 REG_OFFSET_TAB_TIMER[iTimer]));
8729 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
8730 }
8731
8732 /**
8733 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
8734 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
8735 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
8736 * @param HRTIMx High Resolution Timer instance
8737 * @param Timer This parameter can be one of the following values:
8738 * @arg @ref LL_HRTIM_TIMER_MASTER
8739 * @arg @ref LL_HRTIM_TIMER_A
8740 * @arg @ref LL_HRTIM_TIMER_B
8741 * @arg @ref LL_HRTIM_TIMER_C
8742 * @arg @ref LL_HRTIM_TIMER_D
8743 * @arg @ref LL_HRTIM_TIMER_E
8744 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8745 */
LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8746 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8747 {
8748 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8749 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8750 REG_OFFSET_TAB_TIMER[iTimer]));
8751
8752 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
8753 }
8754
8755 /**
8756 * @brief Enable the compare 1 interrupt for a given timer.
8757 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
8758 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
8759 * @param HRTIMx High Resolution Timer instance
8760 * @param Timer This parameter can be one of the following values:
8761 * @arg @ref LL_HRTIM_TIMER_MASTER
8762 * @arg @ref LL_HRTIM_TIMER_A
8763 * @arg @ref LL_HRTIM_TIMER_B
8764 * @arg @ref LL_HRTIM_TIMER_C
8765 * @arg @ref LL_HRTIM_TIMER_D
8766 * @arg @ref LL_HRTIM_TIMER_E
8767 * @retval None
8768 */
LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8769 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8770 {
8771 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8773 REG_OFFSET_TAB_TIMER[iTimer]));
8774 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
8775 }
8776
8777 /**
8778 * @brief Disable the compare 1 interrupt for a given timer.
8779 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
8780 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
8781 * @param HRTIMx High Resolution Timer instance
8782 * @param Timer This parameter can be one of the following values:
8783 * @arg @ref LL_HRTIM_TIMER_MASTER
8784 * @arg @ref LL_HRTIM_TIMER_A
8785 * @arg @ref LL_HRTIM_TIMER_B
8786 * @arg @ref LL_HRTIM_TIMER_C
8787 * @arg @ref LL_HRTIM_TIMER_D
8788 * @arg @ref LL_HRTIM_TIMER_E
8789 * @retval None
8790 */
LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8791 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8792 {
8793 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8794 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8795 REG_OFFSET_TAB_TIMER[iTimer]));
8796 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
8797 }
8798
8799 /**
8800 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
8801 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
8802 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
8803 * @param HRTIMx High Resolution Timer instance
8804 * @param Timer This parameter can be one of the following values:
8805 * @arg @ref LL_HRTIM_TIMER_MASTER
8806 * @arg @ref LL_HRTIM_TIMER_A
8807 * @arg @ref LL_HRTIM_TIMER_B
8808 * @arg @ref LL_HRTIM_TIMER_C
8809 * @arg @ref LL_HRTIM_TIMER_D
8810 * @arg @ref LL_HRTIM_TIMER_E
8811 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8812 */
LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8813 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8814 {
8815 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8816 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8817 REG_OFFSET_TAB_TIMER[iTimer]));
8818
8819 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
8820 }
8821
8822 /**
8823 * @brief Enable the compare 2 interrupt for a given timer.
8824 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
8825 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
8826 * @param HRTIMx High Resolution Timer instance
8827 * @param Timer This parameter can be one of the following values:
8828 * @arg @ref LL_HRTIM_TIMER_MASTER
8829 * @arg @ref LL_HRTIM_TIMER_A
8830 * @arg @ref LL_HRTIM_TIMER_B
8831 * @arg @ref LL_HRTIM_TIMER_C
8832 * @arg @ref LL_HRTIM_TIMER_D
8833 * @arg @ref LL_HRTIM_TIMER_E
8834 * @retval None
8835 */
LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8836 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8837 {
8838 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8839 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8840 REG_OFFSET_TAB_TIMER[iTimer]));
8841 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
8842 }
8843
8844 /**
8845 * @brief Disable the compare 2 interrupt for a given timer.
8846 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
8847 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
8848 * @param HRTIMx High Resolution Timer instance
8849 * @param Timer This parameter can be one of the following values:
8850 * @arg @ref LL_HRTIM_TIMER_MASTER
8851 * @arg @ref LL_HRTIM_TIMER_A
8852 * @arg @ref LL_HRTIM_TIMER_B
8853 * @arg @ref LL_HRTIM_TIMER_C
8854 * @arg @ref LL_HRTIM_TIMER_D
8855 * @arg @ref LL_HRTIM_TIMER_E
8856 * @retval None
8857 */
LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8858 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8859 {
8860 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8861 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8862 REG_OFFSET_TAB_TIMER[iTimer]));
8863 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
8864 }
8865
8866 /**
8867 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
8868 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
8869 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
8870 * @param HRTIMx High Resolution Timer instance
8871 * @param Timer This parameter can be one of the following values:
8872 * @arg @ref LL_HRTIM_TIMER_MASTER
8873 * @arg @ref LL_HRTIM_TIMER_A
8874 * @arg @ref LL_HRTIM_TIMER_B
8875 * @arg @ref LL_HRTIM_TIMER_C
8876 * @arg @ref LL_HRTIM_TIMER_D
8877 * @arg @ref LL_HRTIM_TIMER_E
8878 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8879 */
LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8880 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8881 {
8882 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8883 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8884 REG_OFFSET_TAB_TIMER[iTimer]));
8885
8886 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
8887 }
8888
8889 /**
8890 * @brief Enable the compare 3 interrupt for a given timer.
8891 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
8892 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
8893 * @param HRTIMx High Resolution Timer instance
8894 * @param Timer This parameter can be one of the following values:
8895 * @arg @ref LL_HRTIM_TIMER_MASTER
8896 * @arg @ref LL_HRTIM_TIMER_A
8897 * @arg @ref LL_HRTIM_TIMER_B
8898 * @arg @ref LL_HRTIM_TIMER_C
8899 * @arg @ref LL_HRTIM_TIMER_D
8900 * @arg @ref LL_HRTIM_TIMER_E
8901 * @retval None
8902 */
LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8903 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8904 {
8905 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8906 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8907 REG_OFFSET_TAB_TIMER[iTimer]));
8908 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
8909 }
8910
8911 /**
8912 * @brief Disable the compare 3 interrupt for a given timer.
8913 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
8914 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
8915 * @param HRTIMx High Resolution Timer instance
8916 * @param Timer This parameter can be one of the following values:
8917 * @arg @ref LL_HRTIM_TIMER_MASTER
8918 * @arg @ref LL_HRTIM_TIMER_A
8919 * @arg @ref LL_HRTIM_TIMER_B
8920 * @arg @ref LL_HRTIM_TIMER_C
8921 * @arg @ref LL_HRTIM_TIMER_D
8922 * @arg @ref LL_HRTIM_TIMER_E
8923 * @retval None
8924 */
LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8925 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8926 {
8927 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8929 REG_OFFSET_TAB_TIMER[iTimer]));
8930 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
8931 }
8932
8933 /**
8934 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
8935 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
8936 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
8937 * @param HRTIMx High Resolution Timer instance
8938 * @param Timer This parameter can be one of the following values:
8939 * @arg @ref LL_HRTIM_TIMER_MASTER
8940 * @arg @ref LL_HRTIM_TIMER_A
8941 * @arg @ref LL_HRTIM_TIMER_B
8942 * @arg @ref LL_HRTIM_TIMER_C
8943 * @arg @ref LL_HRTIM_TIMER_D
8944 * @arg @ref LL_HRTIM_TIMER_E
8945 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
8946 */
LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)8947 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8948 {
8949 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8950 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8951 REG_OFFSET_TAB_TIMER[iTimer]));
8952
8953 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
8954 }
8955
8956 /**
8957 * @brief Enable the compare 4 interrupt for a given timer.
8958 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
8959 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
8960 * @param HRTIMx High Resolution Timer instance
8961 * @param Timer This parameter can be one of the following values:
8962 * @arg @ref LL_HRTIM_TIMER_MASTER
8963 * @arg @ref LL_HRTIM_TIMER_A
8964 * @arg @ref LL_HRTIM_TIMER_B
8965 * @arg @ref LL_HRTIM_TIMER_C
8966 * @arg @ref LL_HRTIM_TIMER_D
8967 * @arg @ref LL_HRTIM_TIMER_E
8968 * @retval None
8969 */
LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8970 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8971 {
8972 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8973 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8974 REG_OFFSET_TAB_TIMER[iTimer]));
8975 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
8976 }
8977
8978 /**
8979 * @brief Disable the compare 4 interrupt for a given timer.
8980 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
8981 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
8982 * @param HRTIMx High Resolution Timer instance
8983 * @param Timer This parameter can be one of the following values:
8984 * @arg @ref LL_HRTIM_TIMER_MASTER
8985 * @arg @ref LL_HRTIM_TIMER_A
8986 * @arg @ref LL_HRTIM_TIMER_B
8987 * @arg @ref LL_HRTIM_TIMER_C
8988 * @arg @ref LL_HRTIM_TIMER_D
8989 * @arg @ref LL_HRTIM_TIMER_E
8990 * @retval None
8991 */
LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)8992 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
8993 {
8994 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
8995 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
8996 REG_OFFSET_TAB_TIMER[iTimer]));
8997 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
8998 }
8999
9000 /**
9001 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
9002 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
9003 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
9004 * @param HRTIMx High Resolution Timer instance
9005 * @param Timer This parameter can be one of the following values:
9006 * @arg @ref LL_HRTIM_TIMER_MASTER
9007 * @arg @ref LL_HRTIM_TIMER_A
9008 * @arg @ref LL_HRTIM_TIMER_B
9009 * @arg @ref LL_HRTIM_TIMER_C
9010 * @arg @ref LL_HRTIM_TIMER_D
9011 * @arg @ref LL_HRTIM_TIMER_E
9012 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9013 */
LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9014 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9015 {
9016 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9017 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9018 REG_OFFSET_TAB_TIMER[iTimer]));
9019
9020 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
9021 }
9022
9023 /**
9024 * @brief Enable the capture 1 interrupt for a given timer.
9025 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
9026 * @param HRTIMx High Resolution Timer instance
9027 * @param Timer This parameter can be one of the following values:
9028 * @arg @ref LL_HRTIM_TIMER_A
9029 * @arg @ref LL_HRTIM_TIMER_B
9030 * @arg @ref LL_HRTIM_TIMER_C
9031 * @arg @ref LL_HRTIM_TIMER_D
9032 * @arg @ref LL_HRTIM_TIMER_E
9033 * @retval None
9034 */
LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9035 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9036 {
9037 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9038 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9039 REG_OFFSET_TAB_TIMER[iTimer]));
9040 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
9041 }
9042
9043 /**
9044 * @brief Enable the capture 1 interrupt for a given timer.
9045 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
9046 * @param HRTIMx High Resolution Timer instance
9047 * @param Timer This parameter can be one of the following values:
9048 * @arg @ref LL_HRTIM_TIMER_A
9049 * @arg @ref LL_HRTIM_TIMER_B
9050 * @arg @ref LL_HRTIM_TIMER_C
9051 * @arg @ref LL_HRTIM_TIMER_D
9052 * @arg @ref LL_HRTIM_TIMER_E
9053 * @retval None
9054 */
LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9055 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9056 {
9057 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9058 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9059 REG_OFFSET_TAB_TIMER[iTimer]));
9060 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
9061 }
9062
9063 /**
9064 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
9065 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
9066 * @param HRTIMx High Resolution Timer instance
9067 * @param Timer This parameter can be one of the following values:
9068 * @arg @ref LL_HRTIM_TIMER_A
9069 * @arg @ref LL_HRTIM_TIMER_B
9070 * @arg @ref LL_HRTIM_TIMER_C
9071 * @arg @ref LL_HRTIM_TIMER_D
9072 * @arg @ref LL_HRTIM_TIMER_E
9073 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
9074 */
LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9075 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9076 {
9077 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9078 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9079 REG_OFFSET_TAB_TIMER[iTimer]));
9080
9081 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
9082 }
9083
9084 /**
9085 * @brief Enable the capture 2 interrupt for a given timer.
9086 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
9087 * @param HRTIMx High Resolution Timer instance
9088 * @param Timer This parameter can be one of the following values:
9089 * @arg @ref LL_HRTIM_TIMER_A
9090 * @arg @ref LL_HRTIM_TIMER_B
9091 * @arg @ref LL_HRTIM_TIMER_C
9092 * @arg @ref LL_HRTIM_TIMER_D
9093 * @arg @ref LL_HRTIM_TIMER_E
9094 * @retval None
9095 */
LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9096 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9097 {
9098 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9099 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9100 REG_OFFSET_TAB_TIMER[iTimer]));
9101 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
9102 }
9103
9104 /**
9105 * @brief Enable the capture 2 interrupt for a given timer.
9106 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
9107 * @param HRTIMx High Resolution Timer instance
9108 * @param Timer This parameter can be one of the following values:
9109 * @arg @ref LL_HRTIM_TIMER_A
9110 * @arg @ref LL_HRTIM_TIMER_B
9111 * @arg @ref LL_HRTIM_TIMER_C
9112 * @arg @ref LL_HRTIM_TIMER_D
9113 * @arg @ref LL_HRTIM_TIMER_E
9114 * @retval None
9115 */
LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9116 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9117 {
9118 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9119 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9120 REG_OFFSET_TAB_TIMER[iTimer]));
9121 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
9122 }
9123
9124 /**
9125 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
9126 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
9127 * @param HRTIMx High Resolution Timer instance
9128 * @param Timer This parameter can be one of the following values:
9129 * @arg @ref LL_HRTIM_TIMER_A
9130 * @arg @ref LL_HRTIM_TIMER_B
9131 * @arg @ref LL_HRTIM_TIMER_C
9132 * @arg @ref LL_HRTIM_TIMER_D
9133 * @arg @ref LL_HRTIM_TIMER_E
9134 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
9135 */
LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9136 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9137 {
9138 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9139 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9140 REG_OFFSET_TAB_TIMER[iTimer]));
9141
9142 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
9143 }
9144
9145 /**
9146 * @brief Enable the output 1 set interrupt for a given timer.
9147 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
9148 * @param HRTIMx High Resolution Timer instance
9149 * @param Timer This parameter can be one of the following values:
9150 * @arg @ref LL_HRTIM_TIMER_A
9151 * @arg @ref LL_HRTIM_TIMER_B
9152 * @arg @ref LL_HRTIM_TIMER_C
9153 * @arg @ref LL_HRTIM_TIMER_D
9154 * @arg @ref LL_HRTIM_TIMER_E
9155 * @retval None
9156 */
LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9157 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9158 {
9159 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9160 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9161 REG_OFFSET_TAB_TIMER[iTimer]));
9162 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
9163 }
9164
9165 /**
9166 * @brief Disable the output 1 set interrupt for a given timer.
9167 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
9168 * @param HRTIMx High Resolution Timer instance
9169 * @param Timer This parameter can be one of the following values:
9170 * @arg @ref LL_HRTIM_TIMER_A
9171 * @arg @ref LL_HRTIM_TIMER_B
9172 * @arg @ref LL_HRTIM_TIMER_C
9173 * @arg @ref LL_HRTIM_TIMER_D
9174 * @arg @ref LL_HRTIM_TIMER_E
9175 * @retval None
9176 */
LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9177 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9178 {
9179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9180 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9181 REG_OFFSET_TAB_TIMER[iTimer]));
9182 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
9183 }
9184
9185 /**
9186 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
9187 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
9188 * @param HRTIMx High Resolution Timer instance
9189 * @param Timer This parameter can be one of the following values:
9190 * @arg @ref LL_HRTIM_TIMER_A
9191 * @arg @ref LL_HRTIM_TIMER_B
9192 * @arg @ref LL_HRTIM_TIMER_C
9193 * @arg @ref LL_HRTIM_TIMER_D
9194 * @arg @ref LL_HRTIM_TIMER_E
9195 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9196 */
LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9197 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9198 {
9199 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9200 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9201 REG_OFFSET_TAB_TIMER[iTimer]));
9202
9203 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
9204 }
9205
9206 /**
9207 * @brief Enable the output 1 reset interrupt for a given timer.
9208 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
9209 * @param HRTIMx High Resolution Timer instance
9210 * @param Timer This parameter can be one of the following values:
9211 * @arg @ref LL_HRTIM_TIMER_A
9212 * @arg @ref LL_HRTIM_TIMER_B
9213 * @arg @ref LL_HRTIM_TIMER_C
9214 * @arg @ref LL_HRTIM_TIMER_D
9215 * @arg @ref LL_HRTIM_TIMER_E
9216 * @retval None
9217 */
LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9218 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9219 {
9220 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9221 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9222 REG_OFFSET_TAB_TIMER[iTimer]));
9223 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
9224 }
9225
9226 /**
9227 * @brief Disable the output 1 reset interrupt for a given timer.
9228 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
9229 * @param HRTIMx High Resolution Timer instance
9230 * @param Timer This parameter can be one of the following values:
9231 * @arg @ref LL_HRTIM_TIMER_A
9232 * @arg @ref LL_HRTIM_TIMER_B
9233 * @arg @ref LL_HRTIM_TIMER_C
9234 * @arg @ref LL_HRTIM_TIMER_D
9235 * @arg @ref LL_HRTIM_TIMER_E
9236 * @retval None
9237 */
LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9238 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9239 {
9240 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9241 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9242 REG_OFFSET_TAB_TIMER[iTimer]));
9243 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
9244 }
9245
9246 /**
9247 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
9248 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
9249 * @param HRTIMx High Resolution Timer instance
9250 * @param Timer This parameter can be one of the following values:
9251 * @arg @ref LL_HRTIM_TIMER_A
9252 * @arg @ref LL_HRTIM_TIMER_B
9253 * @arg @ref LL_HRTIM_TIMER_C
9254 * @arg @ref LL_HRTIM_TIMER_D
9255 * @arg @ref LL_HRTIM_TIMER_E
9256 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
9257 */
LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9258 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9259 {
9260 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9261 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9262 REG_OFFSET_TAB_TIMER[iTimer]));
9263
9264 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
9265 }
9266
9267 /**
9268 * @brief Enable the output 2 set interrupt for a given timer.
9269 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
9270 * @param HRTIMx High Resolution Timer instance
9271 * @param Timer This parameter can be one of the following values:
9272 * @arg @ref LL_HRTIM_TIMER_A
9273 * @arg @ref LL_HRTIM_TIMER_B
9274 * @arg @ref LL_HRTIM_TIMER_C
9275 * @arg @ref LL_HRTIM_TIMER_D
9276 * @arg @ref LL_HRTIM_TIMER_E
9277 * @retval None
9278 */
LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9279 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9280 {
9281 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9283 REG_OFFSET_TAB_TIMER[iTimer]));
9284 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
9285 }
9286
9287 /**
9288 * @brief Disable the output 2 set interrupt for a given timer.
9289 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
9290 * @param HRTIMx High Resolution Timer instance
9291 * @param Timer This parameter can be one of the following values:
9292 * @arg @ref LL_HRTIM_TIMER_A
9293 * @arg @ref LL_HRTIM_TIMER_B
9294 * @arg @ref LL_HRTIM_TIMER_C
9295 * @arg @ref LL_HRTIM_TIMER_D
9296 * @arg @ref LL_HRTIM_TIMER_E
9297 * @retval None
9298 */
LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9299 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9300 {
9301 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9302 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9303 REG_OFFSET_TAB_TIMER[iTimer]));
9304 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
9305 }
9306
9307 /**
9308 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
9309 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
9310 * @param HRTIMx High Resolution Timer instance
9311 * @param Timer This parameter can be one of the following values:
9312 * @arg @ref LL_HRTIM_TIMER_A
9313 * @arg @ref LL_HRTIM_TIMER_B
9314 * @arg @ref LL_HRTIM_TIMER_C
9315 * @arg @ref LL_HRTIM_TIMER_D
9316 * @arg @ref LL_HRTIM_TIMER_E
9317 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9318 */
LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9319 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9320 {
9321 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9322 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9323 REG_OFFSET_TAB_TIMER[iTimer]));
9324
9325 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
9326 }
9327
9328 /**
9329 * @brief Enable the output 2 reset interrupt for a given timer.
9330 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
9331 * @param HRTIMx High Resolution Timer instance
9332 * @param Timer This parameter can be one of the following values:
9333 * @arg @ref LL_HRTIM_TIMER_A
9334 * @arg @ref LL_HRTIM_TIMER_B
9335 * @arg @ref LL_HRTIM_TIMER_C
9336 * @arg @ref LL_HRTIM_TIMER_D
9337 * @arg @ref LL_HRTIM_TIMER_E
9338 * @retval None
9339 */
LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9340 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9341 {
9342 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9343 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9344 REG_OFFSET_TAB_TIMER[iTimer]));
9345 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
9346 }
9347
9348 /**
9349 * @brief Disable the output 2 reset interrupt for a given timer.
9350 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9351 * @param HRTIMx High Resolution Timer instance
9352 * @param Timer This parameter can be one of the following values:
9353 * @arg @ref LL_HRTIM_TIMER_A
9354 * @arg @ref LL_HRTIM_TIMER_B
9355 * @arg @ref LL_HRTIM_TIMER_C
9356 * @arg @ref LL_HRTIM_TIMER_D
9357 * @arg @ref LL_HRTIM_TIMER_E
9358 * @retval None
9359 */
LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9360 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9361 {
9362 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9363 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9364 REG_OFFSET_TAB_TIMER[iTimer]));
9365 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
9366 }
9367
9368 /**
9369 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
9370 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
9371 * @param HRTIMx High Resolution Timer instance
9372 * @param Timer This parameter can be one of the following values:
9373 * @arg @ref LL_HRTIM_TIMER_A
9374 * @arg @ref LL_HRTIM_TIMER_B
9375 * @arg @ref LL_HRTIM_TIMER_C
9376 * @arg @ref LL_HRTIM_TIMER_D
9377 * @arg @ref LL_HRTIM_TIMER_E
9378 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
9379 */
LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9380 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9381 {
9382 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9383 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9384 REG_OFFSET_TAB_TIMER[iTimer]));
9385
9386 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
9387 }
9388
9389 /**
9390 * @brief Enable the reset/roll-over interrupt for a given timer.
9391 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
9392 * @param HRTIMx High Resolution Timer instance
9393 * @param Timer This parameter can be one of the following values:
9394 * @arg @ref LL_HRTIM_TIMER_A
9395 * @arg @ref LL_HRTIM_TIMER_B
9396 * @arg @ref LL_HRTIM_TIMER_C
9397 * @arg @ref LL_HRTIM_TIMER_D
9398 * @arg @ref LL_HRTIM_TIMER_E
9399 * @retval None
9400 */
LL_HRTIM_EnableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9401 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9402 {
9403 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9404 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9405 REG_OFFSET_TAB_TIMER[iTimer]));
9406 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
9407 }
9408
9409 /**
9410 * @brief Disable the reset/roll-over interrupt for a given timer.
9411 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
9412 * @param HRTIMx High Resolution Timer instance
9413 * @param Timer This parameter can be one of the following values:
9414 * @arg @ref LL_HRTIM_TIMER_A
9415 * @arg @ref LL_HRTIM_TIMER_B
9416 * @arg @ref LL_HRTIM_TIMER_C
9417 * @arg @ref LL_HRTIM_TIMER_D
9418 * @arg @ref LL_HRTIM_TIMER_E
9419 * @retval None
9420 */
LL_HRTIM_DisableIT_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9421 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9422 {
9423 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9425 REG_OFFSET_TAB_TIMER[iTimer]));
9426 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
9427 }
9428
9429 /**
9430 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
9431 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
9432 * @param HRTIMx High Resolution Timer instance
9433 * @param Timer This parameter can be one of the following values:
9434 * @arg @ref LL_HRTIM_TIMER_A
9435 * @arg @ref LL_HRTIM_TIMER_B
9436 * @arg @ref LL_HRTIM_TIMER_C
9437 * @arg @ref LL_HRTIM_TIMER_D
9438 * @arg @ref LL_HRTIM_TIMER_E
9439 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
9440 */
LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9441 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9442 {
9443 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9444 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9445 REG_OFFSET_TAB_TIMER[iTimer]));
9446
9447 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
9448 }
9449
9450 /**
9451 * @brief Enable the delayed protection interrupt for a given timer.
9452 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
9453 * @param HRTIMx High Resolution Timer instance
9454 * @param Timer This parameter can be one of the following values:
9455 * @arg @ref LL_HRTIM_TIMER_A
9456 * @arg @ref LL_HRTIM_TIMER_B
9457 * @arg @ref LL_HRTIM_TIMER_C
9458 * @arg @ref LL_HRTIM_TIMER_D
9459 * @arg @ref LL_HRTIM_TIMER_E
9460 * @retval None
9461 */
LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9462 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9463 {
9464 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9465 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9466 REG_OFFSET_TAB_TIMER[iTimer]));
9467 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
9468 }
9469
9470 /**
9471 * @brief Disable the delayed protection interrupt for a given timer.
9472 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
9473 * @param HRTIMx High Resolution Timer instance
9474 * @param Timer This parameter can be one of the following values:
9475 * @arg @ref LL_HRTIM_TIMER_A
9476 * @arg @ref LL_HRTIM_TIMER_B
9477 * @arg @ref LL_HRTIM_TIMER_C
9478 * @arg @ref LL_HRTIM_TIMER_D
9479 * @arg @ref LL_HRTIM_TIMER_E
9480 * @retval None
9481 */
LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9482 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9483 {
9484 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9485 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9486 REG_OFFSET_TAB_TIMER[iTimer]));
9487 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
9488 }
9489
9490 /**
9491 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
9492 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
9493 * @param HRTIMx High Resolution Timer instance
9494 * @param Timer This parameter can be one of the following values:
9495 * @arg @ref LL_HRTIM_TIMER_A
9496 * @arg @ref LL_HRTIM_TIMER_B
9497 * @arg @ref LL_HRTIM_TIMER_C
9498 * @arg @ref LL_HRTIM_TIMER_D
9499 * @arg @ref LL_HRTIM_TIMER_E
9500 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
9501 */
LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9502 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9503 {
9504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9505 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9506 REG_OFFSET_TAB_TIMER[iTimer]));
9507
9508 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
9509 }
9510
9511 /**
9512 * @}
9513 */
9514
9515 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
9516 * @{
9517 */
9518
9519 /**
9520 * @brief Enable the synchronization input DMA request.
9521 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
9522 * @param HRTIMx High Resolution Timer instance
9523 * @retval None
9524 */
LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)9525 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
9526 {
9527 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
9528 }
9529
9530 /**
9531 * @brief Disable the synchronization input DMA request
9532 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
9533 * @param HRTIMx High Resolution Timer instance
9534 * @retval None
9535 */
LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef * HRTIMx)9536 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
9537 {
9538 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
9539 }
9540
9541 /**
9542 * @brief Indicate whether the synchronization input DMA request is enabled.
9543 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
9544 * @param HRTIMx High Resolution Timer instance
9545 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
9546 */
LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef * HRTIMx)9547 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
9548 {
9549 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
9550 }
9551
9552 /**
9553 * @brief Enable the update DMA request for a given timer.
9554 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
9555 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
9556 * @param HRTIMx High Resolution Timer instance
9557 * @param Timer This parameter can be one of the following values:
9558 * @arg @ref LL_HRTIM_TIMER_MASTER
9559 * @arg @ref LL_HRTIM_TIMER_A
9560 * @arg @ref LL_HRTIM_TIMER_B
9561 * @arg @ref LL_HRTIM_TIMER_C
9562 * @arg @ref LL_HRTIM_TIMER_D
9563 * @arg @ref LL_HRTIM_TIMER_E
9564 * @retval None
9565 */
LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9566 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9567 {
9568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9569 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9570 REG_OFFSET_TAB_TIMER[iTimer]));
9571 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
9572 }
9573
9574 /**
9575 * @brief Disable the update DMA request for a given timer.
9576 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
9577 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
9578 * @param HRTIMx High Resolution Timer instance
9579 * @param Timer This parameter can be one of the following values:
9580 * @arg @ref LL_HRTIM_TIMER_MASTER
9581 * @arg @ref LL_HRTIM_TIMER_A
9582 * @arg @ref LL_HRTIM_TIMER_B
9583 * @arg @ref LL_HRTIM_TIMER_C
9584 * @arg @ref LL_HRTIM_TIMER_D
9585 * @arg @ref LL_HRTIM_TIMER_E
9586 * @retval None
9587 */
LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9588 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9589 {
9590 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9591 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9592 REG_OFFSET_TAB_TIMER[iTimer]));
9593 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
9594 }
9595
9596 /**
9597 * @brief Indicate whether the update DMA request is enabled for a given timer.
9598 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
9599 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
9600 * @param HRTIMx High Resolution Timer instance
9601 * @param Timer This parameter can be one of the following values:
9602 * @arg @ref LL_HRTIM_TIMER_MASTER
9603 * @arg @ref LL_HRTIM_TIMER_A
9604 * @arg @ref LL_HRTIM_TIMER_B
9605 * @arg @ref LL_HRTIM_TIMER_C
9606 * @arg @ref LL_HRTIM_TIMER_D
9607 * @arg @ref LL_HRTIM_TIMER_E
9608 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9609 */
LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9610 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9611 {
9612 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9613 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9614 REG_OFFSET_TAB_TIMER[iTimer]));
9615
9616 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
9617 }
9618
9619 /**
9620 * @brief Enable the repetition DMA request for a given timer.
9621 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
9622 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
9623 * @param HRTIMx High Resolution Timer instance
9624 * @param Timer This parameter can be one of the following values:
9625 * @arg @ref LL_HRTIM_TIMER_MASTER
9626 * @arg @ref LL_HRTIM_TIMER_A
9627 * @arg @ref LL_HRTIM_TIMER_B
9628 * @arg @ref LL_HRTIM_TIMER_C
9629 * @arg @ref LL_HRTIM_TIMER_D
9630 * @arg @ref LL_HRTIM_TIMER_E
9631 * @retval None
9632 */
LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9633 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9634 {
9635 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9636 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9637 REG_OFFSET_TAB_TIMER[iTimer]));
9638 SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
9639 }
9640
9641 /**
9642 * @brief Disable the repetition DMA request for a given timer.
9643 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
9644 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
9645 * @param HRTIMx High Resolution Timer instance
9646 * @param Timer This parameter can be one of the following values:
9647 * @arg @ref LL_HRTIM_TIMER_MASTER
9648 * @arg @ref LL_HRTIM_TIMER_A
9649 * @arg @ref LL_HRTIM_TIMER_B
9650 * @arg @ref LL_HRTIM_TIMER_C
9651 * @arg @ref LL_HRTIM_TIMER_D
9652 * @arg @ref LL_HRTIM_TIMER_E
9653 * @retval None
9654 */
LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9655 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9656 {
9657 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9658 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9659 REG_OFFSET_TAB_TIMER[iTimer]));
9660 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
9661 }
9662
9663 /**
9664 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
9665 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
9666 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
9667 * @param HRTIMx High Resolution Timer instance
9668 * @param Timer This parameter can be one of the following values:
9669 * @arg @ref LL_HRTIM_TIMER_MASTER
9670 * @arg @ref LL_HRTIM_TIMER_A
9671 * @arg @ref LL_HRTIM_TIMER_B
9672 * @arg @ref LL_HRTIM_TIMER_C
9673 * @arg @ref LL_HRTIM_TIMER_D
9674 * @arg @ref LL_HRTIM_TIMER_E
9675 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9676 */
LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9677 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9678 {
9679 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9680 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9681 REG_OFFSET_TAB_TIMER[iTimer]));
9682
9683 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
9684 }
9685
9686 /**
9687 * @brief Enable the compare 1 DMA request for a given timer.
9688 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
9689 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
9690 * @param HRTIMx High Resolution Timer instance
9691 * @param Timer This parameter can be one of the following values:
9692 * @arg @ref LL_HRTIM_TIMER_MASTER
9693 * @arg @ref LL_HRTIM_TIMER_A
9694 * @arg @ref LL_HRTIM_TIMER_B
9695 * @arg @ref LL_HRTIM_TIMER_C
9696 * @arg @ref LL_HRTIM_TIMER_D
9697 * @arg @ref LL_HRTIM_TIMER_E
9698 * @retval None
9699 */
LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9700 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9701 {
9702 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9703 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9704 REG_OFFSET_TAB_TIMER[iTimer]));
9705 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
9706 }
9707
9708 /**
9709 * @brief Disable the compare 1 DMA request for a given timer.
9710 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
9711 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
9712 * @param HRTIMx High Resolution Timer instance
9713 * @param Timer This parameter can be one of the following values:
9714 * @arg @ref LL_HRTIM_TIMER_MASTER
9715 * @arg @ref LL_HRTIM_TIMER_A
9716 * @arg @ref LL_HRTIM_TIMER_B
9717 * @arg @ref LL_HRTIM_TIMER_C
9718 * @arg @ref LL_HRTIM_TIMER_D
9719 * @arg @ref LL_HRTIM_TIMER_E
9720 * @retval None
9721 */
LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9722 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9723 {
9724 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9725 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9726 REG_OFFSET_TAB_TIMER[iTimer]));
9727 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
9728 }
9729
9730 /**
9731 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
9732 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
9733 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
9734 * @param HRTIMx High Resolution Timer instance
9735 * @param Timer This parameter can be one of the following values:
9736 * @arg @ref LL_HRTIM_TIMER_MASTER
9737 * @arg @ref LL_HRTIM_TIMER_A
9738 * @arg @ref LL_HRTIM_TIMER_B
9739 * @arg @ref LL_HRTIM_TIMER_C
9740 * @arg @ref LL_HRTIM_TIMER_D
9741 * @arg @ref LL_HRTIM_TIMER_E
9742 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9743 */
LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9744 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9745 {
9746 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9747 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9748 REG_OFFSET_TAB_TIMER[iTimer]));
9749
9750 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
9751 }
9752
9753 /**
9754 * @brief Enable the compare 2 DMA request for a given timer.
9755 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
9756 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
9757 * @param HRTIMx High Resolution Timer instance
9758 * @param Timer This parameter can be one of the following values:
9759 * @arg @ref LL_HRTIM_TIMER_MASTER
9760 * @arg @ref LL_HRTIM_TIMER_A
9761 * @arg @ref LL_HRTIM_TIMER_B
9762 * @arg @ref LL_HRTIM_TIMER_C
9763 * @arg @ref LL_HRTIM_TIMER_D
9764 * @arg @ref LL_HRTIM_TIMER_E
9765 * @retval None
9766 */
LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9767 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9768 {
9769 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9770 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9771 REG_OFFSET_TAB_TIMER[iTimer]));
9772 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
9773 }
9774
9775 /**
9776 * @brief Disable the compare 2 DMA request for a given timer.
9777 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
9778 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
9779 * @param HRTIMx High Resolution Timer instance
9780 * @param Timer This parameter can be one of the following values:
9781 * @arg @ref LL_HRTIM_TIMER_MASTER
9782 * @arg @ref LL_HRTIM_TIMER_A
9783 * @arg @ref LL_HRTIM_TIMER_B
9784 * @arg @ref LL_HRTIM_TIMER_C
9785 * @arg @ref LL_HRTIM_TIMER_D
9786 * @arg @ref LL_HRTIM_TIMER_E
9787 * @retval None
9788 */
LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9789 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9790 {
9791 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9792 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9793 REG_OFFSET_TAB_TIMER[iTimer]));
9794 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
9795 }
9796
9797 /**
9798 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
9799 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
9800 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
9801 * @param HRTIMx High Resolution Timer instance
9802 * @param Timer This parameter can be one of the following values:
9803 * @arg @ref LL_HRTIM_TIMER_MASTER
9804 * @arg @ref LL_HRTIM_TIMER_A
9805 * @arg @ref LL_HRTIM_TIMER_B
9806 * @arg @ref LL_HRTIM_TIMER_C
9807 * @arg @ref LL_HRTIM_TIMER_D
9808 * @arg @ref LL_HRTIM_TIMER_E
9809 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9810 */
LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9811 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9812 {
9813 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9814 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9815 REG_OFFSET_TAB_TIMER[iTimer]));
9816
9817 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
9818 }
9819
9820 /**
9821 * @brief Enable the compare 3 DMA request for a given timer.
9822 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
9823 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
9824 * @param HRTIMx High Resolution Timer instance
9825 * @param Timer This parameter can be one of the following values:
9826 * @arg @ref LL_HRTIM_TIMER_MASTER
9827 * @arg @ref LL_HRTIM_TIMER_A
9828 * @arg @ref LL_HRTIM_TIMER_B
9829 * @arg @ref LL_HRTIM_TIMER_C
9830 * @arg @ref LL_HRTIM_TIMER_D
9831 * @arg @ref LL_HRTIM_TIMER_E
9832 * @retval None
9833 */
LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9834 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9835 {
9836 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9837 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9838 REG_OFFSET_TAB_TIMER[iTimer]));
9839 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
9840 }
9841
9842 /**
9843 * @brief Disable the compare 3 DMA request for a given timer.
9844 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
9845 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
9846 * @param HRTIMx High Resolution Timer instance
9847 * @param Timer This parameter can be one of the following values:
9848 * @arg @ref LL_HRTIM_TIMER_MASTER
9849 * @arg @ref LL_HRTIM_TIMER_A
9850 * @arg @ref LL_HRTIM_TIMER_B
9851 * @arg @ref LL_HRTIM_TIMER_C
9852 * @arg @ref LL_HRTIM_TIMER_D
9853 * @arg @ref LL_HRTIM_TIMER_E
9854 * @retval None
9855 */
LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9856 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9857 {
9858 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9859 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9860 REG_OFFSET_TAB_TIMER[iTimer]));
9861 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
9862 }
9863
9864 /**
9865 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
9866 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
9867 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
9868 * @param HRTIMx High Resolution Timer instance
9869 * @param Timer This parameter can be one of the following values:
9870 * @arg @ref LL_HRTIM_TIMER_MASTER
9871 * @arg @ref LL_HRTIM_TIMER_A
9872 * @arg @ref LL_HRTIM_TIMER_B
9873 * @arg @ref LL_HRTIM_TIMER_C
9874 * @arg @ref LL_HRTIM_TIMER_D
9875 * @arg @ref LL_HRTIM_TIMER_E
9876 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9877 */
LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9878 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9879 {
9880 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9881 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9882 REG_OFFSET_TAB_TIMER[iTimer]));
9883
9884 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
9885 }
9886
9887 /**
9888 * @brief Enable the compare 4 DMA request for a given timer.
9889 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
9890 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
9891 * @param HRTIMx High Resolution Timer instance
9892 * @param Timer This parameter can be one of the following values:
9893 * @arg @ref LL_HRTIM_TIMER_MASTER
9894 * @arg @ref LL_HRTIM_TIMER_A
9895 * @arg @ref LL_HRTIM_TIMER_B
9896 * @arg @ref LL_HRTIM_TIMER_C
9897 * @arg @ref LL_HRTIM_TIMER_D
9898 * @arg @ref LL_HRTIM_TIMER_E
9899 * @retval None
9900 */
LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9901 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9902 {
9903 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9904 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9905 REG_OFFSET_TAB_TIMER[iTimer]));
9906 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
9907 }
9908
9909 /**
9910 * @brief Disable the compare 4 DMA request for a given timer.
9911 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
9912 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
9913 * @param HRTIMx High Resolution Timer instance
9914 * @param Timer This parameter can be one of the following values:
9915 * @arg @ref LL_HRTIM_TIMER_MASTER
9916 * @arg @ref LL_HRTIM_TIMER_A
9917 * @arg @ref LL_HRTIM_TIMER_B
9918 * @arg @ref LL_HRTIM_TIMER_C
9919 * @arg @ref LL_HRTIM_TIMER_D
9920 * @arg @ref LL_HRTIM_TIMER_E
9921 * @retval None
9922 */
LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9923 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9924 {
9925 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9926 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9927 REG_OFFSET_TAB_TIMER[iTimer]));
9928 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
9929 }
9930
9931 /**
9932 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
9933 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
9934 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
9935 * @param HRTIMx High Resolution Timer instance
9936 * @param Timer This parameter can be one of the following values:
9937 * @arg @ref LL_HRTIM_TIMER_MASTER
9938 * @arg @ref LL_HRTIM_TIMER_A
9939 * @arg @ref LL_HRTIM_TIMER_B
9940 * @arg @ref LL_HRTIM_TIMER_C
9941 * @arg @ref LL_HRTIM_TIMER_D
9942 * @arg @ref LL_HRTIM_TIMER_E
9943 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
9944 */
LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)9945 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9946 {
9947 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9948 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9949 REG_OFFSET_TAB_TIMER[iTimer]));
9950
9951 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
9952 }
9953
9954 /**
9955 * @brief Enable the capture 1 DMA request for a given timer.
9956 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
9957 * @param HRTIMx High Resolution Timer instance
9958 * @param Timer This parameter can be one of the following values:
9959 * @arg @ref LL_HRTIM_TIMER_A
9960 * @arg @ref LL_HRTIM_TIMER_B
9961 * @arg @ref LL_HRTIM_TIMER_C
9962 * @arg @ref LL_HRTIM_TIMER_D
9963 * @arg @ref LL_HRTIM_TIMER_E
9964 * @retval None
9965 */
LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9966 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9967 {
9968 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9969 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9970 REG_OFFSET_TAB_TIMER[iTimer]));
9971 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
9972 }
9973
9974 /**
9975 * @brief Disable the capture 1 DMA request for a given timer.
9976 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
9977 * @param HRTIMx High Resolution Timer instance
9978 * @param Timer This parameter can be one of the following values:
9979 * @arg @ref LL_HRTIM_TIMER_A
9980 * @arg @ref LL_HRTIM_TIMER_B
9981 * @arg @ref LL_HRTIM_TIMER_C
9982 * @arg @ref LL_HRTIM_TIMER_D
9983 * @arg @ref LL_HRTIM_TIMER_E
9984 * @retval None
9985 */
LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)9986 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
9987 {
9988 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
9989 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
9990 REG_OFFSET_TAB_TIMER[iTimer]));
9991 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
9992 }
9993
9994 /**
9995 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
9996 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
9997 * @param HRTIMx High Resolution Timer instance
9998 * @param Timer This parameter can be one of the following values:
9999 * @arg @ref LL_HRTIM_TIMER_A
10000 * @arg @ref LL_HRTIM_TIMER_B
10001 * @arg @ref LL_HRTIM_TIMER_C
10002 * @arg @ref LL_HRTIM_TIMER_D
10003 * @arg @ref LL_HRTIM_TIMER_E
10004 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
10005 */
LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10006 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10007 {
10008 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10009 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10010 REG_OFFSET_TAB_TIMER[iTimer]));
10011
10012 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
10013 }
10014
10015 /**
10016 * @brief Enable the capture 2 DMA request for a given timer.
10017 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
10018 * @param HRTIMx High Resolution Timer instance
10019 * @param Timer This parameter can be one of the following values:
10020 * @arg @ref LL_HRTIM_TIMER_A
10021 * @arg @ref LL_HRTIM_TIMER_B
10022 * @arg @ref LL_HRTIM_TIMER_C
10023 * @arg @ref LL_HRTIM_TIMER_D
10024 * @arg @ref LL_HRTIM_TIMER_E
10025 * @retval None
10026 */
LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10027 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10028 {
10029 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10030 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10031 REG_OFFSET_TAB_TIMER[iTimer]));
10032 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10033 }
10034
10035 /**
10036 * @brief Disable the capture 2 DMA request for a given timer.
10037 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
10038 * @param HRTIMx High Resolution Timer instance
10039 * @param Timer This parameter can be one of the following values:
10040 * @arg @ref LL_HRTIM_TIMER_A
10041 * @arg @ref LL_HRTIM_TIMER_B
10042 * @arg @ref LL_HRTIM_TIMER_C
10043 * @arg @ref LL_HRTIM_TIMER_D
10044 * @arg @ref LL_HRTIM_TIMER_E
10045 * @retval None
10046 */
LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10047 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10048 {
10049 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10050 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10051 REG_OFFSET_TAB_TIMER[iTimer]));
10052 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
10053 }
10054
10055 /**
10056 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
10057 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
10058 * @param HRTIMx High Resolution Timer instance
10059 * @param Timer This parameter can be one of the following values:
10060 * @arg @ref LL_HRTIM_TIMER_A
10061 * @arg @ref LL_HRTIM_TIMER_B
10062 * @arg @ref LL_HRTIM_TIMER_C
10063 * @arg @ref LL_HRTIM_TIMER_D
10064 * @arg @ref LL_HRTIM_TIMER_E
10065 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
10066 */
LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10067 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10068 {
10069 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10070 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10071 REG_OFFSET_TAB_TIMER[iTimer]));
10072
10073 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
10074 }
10075
10076 /**
10077 * @brief Enable the output 1 set DMA request for a given timer.
10078 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
10079 * @param HRTIMx High Resolution Timer instance
10080 * @param Timer This parameter can be one of the following values:
10081 * @arg @ref LL_HRTIM_TIMER_A
10082 * @arg @ref LL_HRTIM_TIMER_B
10083 * @arg @ref LL_HRTIM_TIMER_C
10084 * @arg @ref LL_HRTIM_TIMER_D
10085 * @arg @ref LL_HRTIM_TIMER_E
10086 * @retval None
10087 */
LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10088 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10089 {
10090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10091 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10092 REG_OFFSET_TAB_TIMER[iTimer]));
10093 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10094 }
10095
10096 /**
10097 * @brief Disable the output 1 set DMA request for a given timer.
10098 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
10099 * @param HRTIMx High Resolution Timer instance
10100 * @param Timer This parameter can be one of the following values:
10101 * @arg @ref LL_HRTIM_TIMER_A
10102 * @arg @ref LL_HRTIM_TIMER_B
10103 * @arg @ref LL_HRTIM_TIMER_C
10104 * @arg @ref LL_HRTIM_TIMER_D
10105 * @arg @ref LL_HRTIM_TIMER_E
10106 * @retval None
10107 */
LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10108 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10109 {
10110 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10111 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10112 REG_OFFSET_TAB_TIMER[iTimer]));
10113 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
10114 }
10115
10116 /**
10117 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
10118 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
10119 * @param HRTIMx High Resolution Timer instance
10120 * @param Timer This parameter can be one of the following values:
10121 * @arg @ref LL_HRTIM_TIMER_A
10122 * @arg @ref LL_HRTIM_TIMER_B
10123 * @arg @ref LL_HRTIM_TIMER_C
10124 * @arg @ref LL_HRTIM_TIMER_D
10125 * @arg @ref LL_HRTIM_TIMER_E
10126 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10127 */
LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10128 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10129 {
10130 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10131 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10132 REG_OFFSET_TAB_TIMER[iTimer]));
10133
10134 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
10135 }
10136
10137 /**
10138 * @brief Enable the output 1 reset DMA request for a given timer.
10139 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
10140 * @param HRTIMx High Resolution Timer instance
10141 * @param Timer This parameter can be one of the following values:
10142 * @arg @ref LL_HRTIM_TIMER_A
10143 * @arg @ref LL_HRTIM_TIMER_B
10144 * @arg @ref LL_HRTIM_TIMER_C
10145 * @arg @ref LL_HRTIM_TIMER_D
10146 * @arg @ref LL_HRTIM_TIMER_E
10147 * @retval None
10148 */
LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10149 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10150 {
10151 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10152 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10153 REG_OFFSET_TAB_TIMER[iTimer]));
10154 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10155 }
10156
10157 /**
10158 * @brief Disable the output 1 reset DMA request for a given timer.
10159 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
10160 * @param HRTIMx High Resolution Timer instance
10161 * @param Timer This parameter can be one of the following values:
10162 * @arg @ref LL_HRTIM_TIMER_A
10163 * @arg @ref LL_HRTIM_TIMER_B
10164 * @arg @ref LL_HRTIM_TIMER_C
10165 * @arg @ref LL_HRTIM_TIMER_D
10166 * @arg @ref LL_HRTIM_TIMER_E
10167 * @retval None
10168 */
LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10169 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10170 {
10171 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10172 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10173 REG_OFFSET_TAB_TIMER[iTimer]));
10174 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
10175 }
10176
10177 /**
10178 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
10179 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
10180 * @param HRTIMx High Resolution Timer instance
10181 * @param Timer This parameter can be one of the following values:
10182 * @arg @ref LL_HRTIM_TIMER_A
10183 * @arg @ref LL_HRTIM_TIMER_B
10184 * @arg @ref LL_HRTIM_TIMER_C
10185 * @arg @ref LL_HRTIM_TIMER_D
10186 * @arg @ref LL_HRTIM_TIMER_E
10187 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
10188 */
LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10189 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10190 {
10191 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10192 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10193 REG_OFFSET_TAB_TIMER[iTimer]));
10194
10195 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
10196 }
10197
10198 /**
10199 * @brief Enable the output 2 set DMA request for a given timer.
10200 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
10201 * @param HRTIMx High Resolution Timer instance
10202 * @param Timer This parameter can be one of the following values:
10203 * @arg @ref LL_HRTIM_TIMER_A
10204 * @arg @ref LL_HRTIM_TIMER_B
10205 * @arg @ref LL_HRTIM_TIMER_C
10206 * @arg @ref LL_HRTIM_TIMER_D
10207 * @arg @ref LL_HRTIM_TIMER_E
10208 * @retval None
10209 */
LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10210 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10211 {
10212 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10213 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10214 REG_OFFSET_TAB_TIMER[iTimer]));
10215 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10216 }
10217
10218 /**
10219 * @brief Disable the output 2 set DMA request for a given timer.
10220 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
10221 * @param HRTIMx High Resolution Timer instance
10222 * @param Timer This parameter can be one of the following values:
10223 * @arg @ref LL_HRTIM_TIMER_A
10224 * @arg @ref LL_HRTIM_TIMER_B
10225 * @arg @ref LL_HRTIM_TIMER_C
10226 * @arg @ref LL_HRTIM_TIMER_D
10227 * @arg @ref LL_HRTIM_TIMER_E
10228 * @retval None
10229 */
LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10230 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10231 {
10232 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10233 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10234 REG_OFFSET_TAB_TIMER[iTimer]));
10235 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
10236 }
10237
10238 /**
10239 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
10240 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
10241 * @param HRTIMx High Resolution Timer instance
10242 * @param Timer This parameter can be one of the following values:
10243 * @arg @ref LL_HRTIM_TIMER_A
10244 * @arg @ref LL_HRTIM_TIMER_B
10245 * @arg @ref LL_HRTIM_TIMER_C
10246 * @arg @ref LL_HRTIM_TIMER_D
10247 * @arg @ref LL_HRTIM_TIMER_E
10248 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10249 */
LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10250 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10251 {
10252 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10253 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10254 REG_OFFSET_TAB_TIMER[iTimer]));
10255
10256 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
10257 }
10258
10259 /**
10260 * @brief Enable the output 2 reset DMA request for a given timer.
10261 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
10262 * @param HRTIMx High Resolution Timer instance
10263 * @param Timer This parameter can be one of the following values:
10264 * @arg @ref LL_HRTIM_TIMER_A
10265 * @arg @ref LL_HRTIM_TIMER_B
10266 * @arg @ref LL_HRTIM_TIMER_C
10267 * @arg @ref LL_HRTIM_TIMER_D
10268 * @arg @ref LL_HRTIM_TIMER_E
10269 * @retval None
10270 */
LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10271 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10272 {
10273 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10274 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10275 REG_OFFSET_TAB_TIMER[iTimer]));
10276 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10277 }
10278
10279 /**
10280 * @brief Disable the output 2 reset DMA request for a given timer.
10281 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
10282 * @param HRTIMx High Resolution Timer instance
10283 * @param Timer This parameter can be one of the following values:
10284 * @arg @ref LL_HRTIM_TIMER_A
10285 * @arg @ref LL_HRTIM_TIMER_B
10286 * @arg @ref LL_HRTIM_TIMER_C
10287 * @arg @ref LL_HRTIM_TIMER_D
10288 * @arg @ref LL_HRTIM_TIMER_E
10289 * @retval None
10290 */
LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10291 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10292 {
10293 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10294 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10295 REG_OFFSET_TAB_TIMER[iTimer]));
10296 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
10297 }
10298
10299 /**
10300 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
10301 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
10302 * @param HRTIMx High Resolution Timer instance
10303 * @param Timer This parameter can be one of the following values:
10304 * @arg @ref LL_HRTIM_TIMER_A
10305 * @arg @ref LL_HRTIM_TIMER_B
10306 * @arg @ref LL_HRTIM_TIMER_C
10307 * @arg @ref LL_HRTIM_TIMER_D
10308 * @arg @ref LL_HRTIM_TIMER_E
10309 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
10310 */
LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10311 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10312 {
10313 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10314 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10315 REG_OFFSET_TAB_TIMER[iTimer]));
10316
10317 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
10318 }
10319
10320 /**
10321 * @brief Enable the reset/roll-over DMA request for a given timer.
10322 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
10323 * @param HRTIMx High Resolution Timer instance
10324 * @param Timer This parameter can be one of the following values:
10325 * @arg @ref LL_HRTIM_TIMER_A
10326 * @arg @ref LL_HRTIM_TIMER_B
10327 * @arg @ref LL_HRTIM_TIMER_C
10328 * @arg @ref LL_HRTIM_TIMER_D
10329 * @arg @ref LL_HRTIM_TIMER_E
10330 * @retval None
10331 */
LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10332 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10333 {
10334 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10335 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10336 REG_OFFSET_TAB_TIMER[iTimer]));
10337 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10338 }
10339
10340 /**
10341 * @brief Disable the reset/roll-over DMA request for a given timer.
10342 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
10343 * @param HRTIMx High Resolution Timer instance
10344 * @param Timer This parameter can be one of the following values:
10345 * @arg @ref LL_HRTIM_TIMER_A
10346 * @arg @ref LL_HRTIM_TIMER_B
10347 * @arg @ref LL_HRTIM_TIMER_C
10348 * @arg @ref LL_HRTIM_TIMER_D
10349 * @arg @ref LL_HRTIM_TIMER_E
10350 * @retval None
10351 */
LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10352 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10353 {
10354 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10355 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10356 REG_OFFSET_TAB_TIMER[iTimer]));
10357 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
10358 }
10359
10360 /**
10361 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
10362 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
10363 * @param HRTIMx High Resolution Timer instance
10364 * @param Timer This parameter can be one of the following values:
10365 * @arg @ref LL_HRTIM_TIMER_A
10366 * @arg @ref LL_HRTIM_TIMER_B
10367 * @arg @ref LL_HRTIM_TIMER_C
10368 * @arg @ref LL_HRTIM_TIMER_D
10369 * @arg @ref LL_HRTIM_TIMER_E
10370 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
10371 */
LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10372 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10373 {
10374 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10375 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10376 REG_OFFSET_TAB_TIMER[iTimer]));
10377
10378 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
10379 }
10380
10381 /**
10382 * @brief Enable the delayed protection DMA request for a given timer.
10383 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
10384 * @param HRTIMx High Resolution Timer instance
10385 * @param Timer This parameter can be one of the following values:
10386 * @arg @ref LL_HRTIM_TIMER_A
10387 * @arg @ref LL_HRTIM_TIMER_B
10388 * @arg @ref LL_HRTIM_TIMER_C
10389 * @arg @ref LL_HRTIM_TIMER_D
10390 * @arg @ref LL_HRTIM_TIMER_E
10391 * @retval None
10392 */
LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10393 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10394 {
10395 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10396 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10397 REG_OFFSET_TAB_TIMER[iTimer]));
10398 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10399 }
10400
10401 /**
10402 * @brief Disable the delayed protection DMA request for a given timer.
10403 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
10404 * @param HRTIMx High Resolution Timer instance
10405 * @param Timer This parameter can be one of the following values:
10406 * @arg @ref LL_HRTIM_TIMER_A
10407 * @arg @ref LL_HRTIM_TIMER_B
10408 * @arg @ref LL_HRTIM_TIMER_C
10409 * @arg @ref LL_HRTIM_TIMER_D
10410 * @arg @ref LL_HRTIM_TIMER_E
10411 * @retval None
10412 */
LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef * HRTIMx,uint32_t Timer)10413 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10414 {
10415 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10416 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10417 REG_OFFSET_TAB_TIMER[iTimer]));
10418 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
10419 }
10420
10421 /**
10422 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
10423 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
10424 * @param HRTIMx High Resolution Timer instance
10425 * @param Timer This parameter can be one of the following values:
10426 * @arg @ref LL_HRTIM_TIMER_A
10427 * @arg @ref LL_HRTIM_TIMER_B
10428 * @arg @ref LL_HRTIM_TIMER_C
10429 * @arg @ref LL_HRTIM_TIMER_D
10430 * @arg @ref LL_HRTIM_TIMER_E
10431 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
10432 */
LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef * HRTIMx,uint32_t Timer)10433 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
10434 {
10435 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
10436 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
10437 REG_OFFSET_TAB_TIMER[iTimer]));
10438
10439 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
10440 }
10441
10442 /**
10443 * @}
10444 */
10445
10446 #if defined(USE_FULL_LL_DRIVER)
10447 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
10448 * @{
10449 */
10450 ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx);
10451 /**
10452 * @}
10453 */
10454 #endif /* USE_FULL_LL_DRIVER */
10455
10456 /**
10457 * @}
10458 */
10459
10460 /**
10461 * @}
10462 */
10463
10464 #endif /* HRTIM1 */
10465
10466 /**
10467 * @}
10468 */
10469
10470 #ifdef __cplusplus
10471 }
10472 #endif
10473
10474 #endif /* STM32H7xx_LL_HRTIM_H */
10475
10476