1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_hrtim.h 4 * @author MCD Application Team 5 * @brief Header file of HRTIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_HRTIM_H 21 #define STM32H7xx_HAL_HRTIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 #if defined(HRTIM1) 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HRTIM HRTIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants 41 * @{ 42 */ 43 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer 44 * @{ 45 */ 46 #define MAX_HRTIM_TIMER 6U 47 /** 48 * @} 49 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types 55 * @{ 56 */ 57 58 /** 59 * @brief HRTIM Configuration Structure definition - Time base related parameters 60 */ 61 typedef struct 62 { 63 uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. 64 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ 65 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. 66 The HRTIM instance can be configured to act as a slave (waiting for a trigger 67 to be synchronized) or a master (generating a synchronization signal) or both. 68 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ 69 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when 70 the HRTIM instance is configured as a slave). 71 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */ 72 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs 73 (significant only when the HRTIM instance is configured as a master). 74 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */ 75 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization 76 outputs (significant only when the HRTIM instance is configured as a master). 77 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */ 78 } HRTIM_InitTypeDef; 79 80 /** 81 * @brief HAL State structures definition 82 */ 83 typedef enum 84 { 85 HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 86 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 87 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 88 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ 89 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */ 90 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 91 HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */ 92 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 93 } HAL_HRTIM_StateTypeDef; 94 95 /** 96 * @brief HRTIM Timer Structure definition 97 */ 98 typedef struct 99 { 100 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1. 101 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 102 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 103 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2. 104 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 105 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 106 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */ 107 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */ 108 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */ 109 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */ 110 uint32_t DMASize; /*!< Size of the DMA transfer */ 111 } HRTIM_TimerParamTypeDef; 112 113 /** 114 * @brief HRTIM Handle Structure definition 115 */ 116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 117 typedef struct __HRTIM_HandleTypeDef 118 #else 119 typedef struct 120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 121 { 122 HRTIM_TypeDef *Instance; /*!< Register base address */ 123 124 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ 125 126 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */ 127 128 HAL_LockTypeDef Lock; /*!< Locking object */ 129 130 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ 131 132 DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ 133 DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ 134 DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ 135 DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ 136 DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ 137 DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ 138 139 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 140 void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ 141 void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */ 142 void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */ 143 void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */ 144 void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */ 145 void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */ 146 void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */ 147 void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */ 148 void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */ 149 150 void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */ 151 void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */ 152 void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */ 153 void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */ 154 void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */ 155 void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */ 156 void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */ 157 void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */ 158 void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */ 159 void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */ 160 void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */ 161 void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */ 162 void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */ 163 void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */ 164 void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */ 165 166 void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 167 void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 168 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 169 } HRTIM_HandleTypeDef; 170 171 /** 172 * @brief Simple output compare mode configuration definition 173 */ 174 typedef struct 175 { 176 uint32_t Period; /*!< Specifies the timer period. 177 The period value must be above 3 periods of the fHRTIM clock. 178 Maximum value is = 0xFFDFU */ 179 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period. 180 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 181 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. 182 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */ 183 uint32_t Mode; /*!< Specifies the counter operating mode. 184 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */ 185 } HRTIM_TimeBaseCfgTypeDef; 186 187 /** 188 * @brief Simple output compare mode configuration definition 189 */ 190 typedef struct 191 { 192 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive). 193 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */ 194 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 195 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 196 uint32_t Polarity; /*!< Specifies the output polarity. 197 This parameter can be any value of @ref HRTIM_Output_Polarity */ 198 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 199 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 200 } HRTIM_SimpleOCChannelCfgTypeDef; 201 202 /** 203 * @brief Simple PWM output mode configuration definition 204 */ 205 typedef struct 206 { 207 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 208 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 209 uint32_t Polarity; /*!< Specifies the output polarity. 210 This parameter can be any value of @ref HRTIM_Output_Polarity */ 211 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 212 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 213 } HRTIM_SimplePWMChannelCfgTypeDef; 214 215 /** 216 * @brief Simple capture mode configuration definition 217 */ 218 typedef struct 219 { 220 uint32_t Event; /*!< Specifies the external event triggering the capture. 221 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 222 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 223 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 224 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 225 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 226 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 227 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 228 } HRTIM_SimpleCaptureChannelCfgTypeDef; 229 230 /** 231 * @brief Simple One Pulse mode configuration definition 232 */ 233 typedef struct 234 { 235 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 236 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 237 uint32_t OutputPolarity; /*!< Specifies the output polarity. 238 This parameter can be any value of @ref HRTIM_Output_Polarity */ 239 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 240 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 241 uint32_t Event; /*!< Specifies the external event triggering the pulse generation. 242 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 243 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 244 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 245 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 246 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */ 247 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 248 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 249 } HRTIM_SimpleOnePulseChannelCfgTypeDef; 250 251 /** 252 * @brief Timer configuration definition 253 */ 254 typedef struct 255 { 256 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master. 257 Specifies which interrupts requests must enabled for the timer. 258 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable 259 or @ref HRTIM_Timing_Unit_Interrupt_Enable */ 260 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master. 261 Specifies which DMA requests must be enabled for the timer. 262 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable 263 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */ 264 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master. 265 Specifies the address of the source address of the DMA transfer */ 266 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master. 267 Specifies the address of the destination address of the DMA transfer */ 268 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. 269 Specifies the size of the DMA transfer */ 270 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. 271 Specifies whether or not half mode is enabled 272 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ 273 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. 274 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 275 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */ 276 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master. 277 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 278 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */ 279 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master. 280 Indicates whether or not the a DAC synchronization event is generated. 281 This parameter can be any value of @ref HRTIM_DAC_Synchronization */ 282 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master. 283 Specifies whether or not register preload is enabled. 284 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */ 285 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master. 286 Specifies how the update occurs with respect to a burst DMA transaction or 287 update enable inputs (Slave timers only). 288 This parameter can be any value of @ref HRTIM_Update_Gating */ 289 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master. 290 Specifies how the timer behaves during a burst mode operation. 291 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */ 292 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master. 293 Specifies whether or not registers update is triggered by the repetition event. 294 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */ 295 uint32_t PushPull; /*!< Relevant for Timer A to Timer E. 296 Specifies whether or not the push-pull mode is enabled. 297 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */ 298 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E. 299 Specifies which fault channels are enabled for the timer. 300 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */ 301 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E. 302 Specifies whether or not fault enabling status is write protected. 303 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */ 304 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E. 305 Specifies whether or not dead-time insertion is enabled for the timer. 306 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */ 307 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E. 308 Specifies the delayed protection mode. 309 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */ 310 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E. 311 Specifies source(s) triggering the timer registers update. 312 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */ 313 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E. 314 Specifies source(s) triggering the timer counter reset. 315 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */ 316 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E. 317 Specifies whether or not registers update is triggered when the timer counter is reset. 318 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */ 319 } HRTIM_TimerCfgTypeDef; 320 321 /** 322 * @brief Compare unit configuration definition 323 */ 324 typedef struct 325 { 326 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit. 327 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. 328 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */ 329 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4. 330 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */ 331 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected. 332 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */ 333 } HRTIM_CompareCfgTypeDef; 334 335 /** 336 * @brief Capture unit configuration definition 337 */ 338 typedef struct 339 { 340 uint32_t Trigger; /*!< Specifies source(s) triggering the capture. 341 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ 342 } HRTIM_CaptureCfgTypeDef; 343 344 /** 345 * @brief Output configuration definition 346 */ 347 typedef struct 348 { 349 uint32_t Polarity; /*!< Specifies the output polarity. 350 This parameter can be any value of @ref HRTIM_Output_Polarity */ 351 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. 352 This parameter can be a combination of @ref HRTIM_Output_Set_Source */ 353 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. 354 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ 355 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. 356 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ 357 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 358 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 359 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. 360 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ 361 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled 362 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ 363 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. 364 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ 365 } HRTIM_OutputCfgTypeDef; 366 367 /** 368 * @brief External event filtering in timing units configuration definition 369 */ 370 typedef struct 371 { 372 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit. 373 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */ 374 uint32_t Latch; /*!< Specifies whether or not the signal is latched. 375 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */ 376 } HRTIM_TimerEventFilteringCfgTypeDef; 377 378 /** 379 * @brief Dead time feature configuration definition 380 */ 381 typedef struct 382 { 383 uint32_t Prescaler; /*!< Specifies the dead-time prescaler. 384 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */ 385 uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge. 386 This parameter can be a number between 0x0 and 0x1FFU */ 387 uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. 388 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */ 389 uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected. 390 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */ 391 uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected. 392 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */ 393 uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge. 394 This parameter can be a number between 0x0 and 0x1FFU */ 395 uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. 396 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */ 397 uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected. 398 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */ 399 uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected. 400 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */ 401 } HRTIM_DeadTimeCfgTypeDef; 402 403 /** 404 * @brief Chopper mode configuration definition 405 */ 406 typedef struct 407 { 408 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. 409 This parameter can be a value of @ref HRTIM_Chopper_Frequency */ 410 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. 411 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */ 412 uint32_t StartPulse; /*!< Specifies the Timer pulse width value. 413 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */ 414 } HRTIM_ChopperModeCfgTypeDef; 415 416 /** 417 * @brief External event channel configuration definition 418 */ 419 typedef struct 420 { 421 uint32_t Source; /*!< Identifies the source of the external event. 422 This parameter can be a value of @ref HRTIM_External_Event_Sources */ 423 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 424 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 425 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event. 426 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 427 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 428 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 429 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. 430 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */ 431 } HRTIM_EventCfgTypeDef; 432 433 /** 434 * @brief Fault channel configuration definition 435 */ 436 typedef struct 437 { 438 uint32_t Source; /*!< Identifies the source of the fault. 439 This parameter can be a value of @ref HRTIM_Fault_Sources */ 440 uint32_t Polarity; /*!< Specifies the polarity of the fault event. 441 This parameter can be a value of @ref HRTIM_Fault_Polarity */ 442 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. 443 This parameter can be a value of @ref HRTIM_Fault_Filter */ 444 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. 445 This parameter can be a value of @ref HRTIM_Fault_Lock */ 446 } HRTIM_FaultCfgTypeDef; 447 448 /** 449 * @brief Burst mode configuration definition 450 */ 451 typedef struct 452 { 453 uint32_t Mode; /*!< Specifies the burst mode operating mode. 454 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */ 455 uint32_t ClockSource; /*!< Specifies the burst mode clock source. 456 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */ 457 uint32_t Prescaler; /*!< Specifies the burst mode prescaler. 458 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */ 459 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER). 460 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */ 461 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation. 462 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */ 463 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state. 464 This parameter can be a number between 0x0 and 0xFFFF */ 465 uint32_t Period; /*!< Specifies burst mode repetition period. 466 This parameter can be a number between 0x1 and 0xFFFF */ 467 } HRTIM_BurstModeCfgTypeDef; 468 469 /** 470 * @brief ADC trigger configuration definition 471 */ 472 typedef struct 473 { 474 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source. 475 This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */ 476 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion. 477 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */ 478 } HRTIM_ADCTriggerCfgTypeDef; 479 480 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 481 /** 482 * @brief HAL HRTIM Callback ID enumeration definition 483 */ 484 typedef enum 485 { 486 HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ 487 HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ 488 HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ 489 HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */ 490 HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */ 491 HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */ 492 HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */ 493 HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */ 494 HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */ 495 496 HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */ 497 HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */ 498 HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */ 499 HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */ 500 HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */ 501 HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */ 502 HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */ 503 HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */ 504 HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */ 505 HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */ 506 HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */ 507 HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */ 508 HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */ 509 HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */ 510 HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */ 511 512 HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ 513 HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ 514 } HAL_HRTIM_CallbackIDTypeDef; 515 516 /** 517 * @brief HAL HRTIM Callback function pointer definitions 518 */ 519 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */ 520 521 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */ 522 uint32_t TimerIdx); 523 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 524 525 /** 526 * @} 527 */ 528 529 /* Exported constants --------------------------------------------------------*/ 530 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants 531 * @{ 532 */ 533 534 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index 535 * @{ 536 * @brief Constants defining the timer indexes 537 */ 538 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */ 539 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */ 540 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */ 541 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */ 542 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */ 543 #define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */ 544 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier 550 * @{ 551 * @brief Constants defining timer identifiers 552 */ 553 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */ 554 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ 555 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ 556 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ 557 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ 558 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit 564 * @{ 565 * @brief Constants defining compare unit identifiers 566 */ 567 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */ 568 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ 569 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ 570 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ 571 /** 572 * @} 573 */ 574 575 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit 576 * @{ 577 * @brief Constants defining capture unit identifiers 578 */ 579 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */ 580 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output 586 * @{ 587 * @brief Constants defining timer output identifiers 588 */ 589 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */ 590 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */ 591 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */ 592 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */ 593 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */ 594 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */ 595 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */ 596 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */ 597 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */ 598 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger 604 * @{ 605 * @brief Constants defining ADC triggers identifiers 606 */ 607 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */ 608 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */ 609 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */ 610 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ 611 612 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ 613 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ 614 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ 615 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ 616 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) 617 /** 618 * @} 619 */ 620 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels 621 * @{ 622 * @brief Constants defining external event channel identifiers 623 */ 624 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ 625 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ 626 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ 627 #define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ 628 #define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ 629 #define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ 630 #define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ 631 #define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ 632 #define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ 633 #define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ 634 #define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel 640 * @{ 641 * @brief Constants defining fault channel identifiers 642 */ 643 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */ 644 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */ 645 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */ 646 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */ 647 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */ 648 /** 649 * @} 650 */ 651 652 653 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio 654 * @{ 655 * @brief Constants defining timer high-resolution clock prescaler ratio. 656 */ 657 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 658 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 659 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 660 /** 661 * @} 662 */ 663 664 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode 665 * @{ 666 * @brief Constants defining timer counter operating mode. 667 */ 668 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 669 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */ 670 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 671 /** 672 * @} 673 */ 674 675 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable 676 * @{ 677 * @brief Constants defining half mode enabling status. 678 */ 679 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */ 680 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */ 681 /** 682 * @} 683 */ 684 685 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event 686 * @{ 687 * @brief Constants defining the timer behavior following the synchronization event 688 */ 689 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 690 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ 691 /** 692 * @} 693 */ 694 695 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event 696 * @{ 697 * @brief Constants defining the timer behavior following the synchronization event 698 */ 699 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 700 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ 701 /** 702 * @} 703 */ 704 705 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization 706 * @{ 707 * @brief Constants defining on which output the DAC synchronization event is sent 708 */ 709 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */ 710 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 711 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 712 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable 718 * @{ 719 * @brief Constants defining whether a write access into a preloadable 720 * register is done into the active or the preload register. 721 */ 722 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */ 723 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ 724 /** 725 * @} 726 */ 727 728 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating 729 * @{ 730 * @brief Constants defining how the update occurs relatively to the burst DMA 731 * transaction and the external update request on update enable inputs 1 to 3. 732 */ 733 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 734 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 735 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 736 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */ 737 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */ 738 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */ 739 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */ 740 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */ 741 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */ 742 /** 743 * @} 744 */ 745 746 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode 747 * @{ 748 * @brief Constants defining how the timer behaves during a burst 749 mode operation. 750 */ 751 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */ 752 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 753 /** 754 * @} 755 */ 756 757 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update 758 * @{ 759 * @brief Constants defining whether registers are updated when the timer 760 * repetition period is completed (either due to roll-over or 761 * reset events) 762 */ 763 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */ 764 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ 765 /** 766 * @} 767 */ 768 769 770 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode 771 * @{ 772 * @brief Constants defining whether or not the push-pull mode is enabled for 773 * a timer. 774 */ 775 #define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */ 776 #define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling 782 * @{ 783 * @brief Constants defining whether a fault channel is enabled for a timer 784 */ 785 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ 786 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ 787 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ 788 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ 789 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ 790 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ 791 /** 792 * @} 793 */ 794 795 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock 796 * @{ 797 * @brief Constants defining whether or not fault enabling bits are write 798 * protected for a timer 799 */ 800 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */ 801 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */ 802 /** 803 * @} 804 */ 805 806 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion 807 * @{ 808 * @brief Constants defining whether or not fault the dead time insertion 809 * feature is enabled for a timer 810 */ 811 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */ 812 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */ 813 /** 814 * @} 815 */ 816 817 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode 818 * @{ 819 * @brief Constants defining all possible delayed protection modes 820 * for a timer. Also define the source and outputs on which the delayed 821 * protection schemes are applied 822 */ 823 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 824 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */ 825 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */ 826 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */ 827 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */ 828 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */ 829 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */ 830 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ 831 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ 832 833 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 834 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ 835 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ 836 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ 837 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ 838 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ 839 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ 840 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ 841 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ 842 /** 843 * @} 844 */ 845 846 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger 847 * @{ 848 * @brief Constants defining whether the registers update is done synchronously 849 * with any other timer or master update 850 */ 851 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */ 852 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ 853 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ 854 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ 855 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ 856 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ 857 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ 858 /** 859 * @} 860 */ 861 862 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger 863 * @{ 864 * @brief Constants defining the events that can be selected to trigger the reset 865 * of the timer counter 866 */ 867 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */ 868 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ 869 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ 870 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ 871 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ 872 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ 873 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ 874 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ 875 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ 876 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */ 877 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */ 878 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */ 879 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */ 880 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */ 881 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */ 882 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */ 883 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */ 884 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */ 885 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */ 886 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 887 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 888 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 889 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 890 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 891 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 892 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 893 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 894 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 895 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 896 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 897 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 898 /** 899 * @} 900 */ 901 902 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update 903 * @{ 904 * @brief Constants defining whether the register are updated upon Timerx 905 * counter reset or roll-over to 0 after reaching the period value 906 * in continuous mode 907 */ 908 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ 909 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ 910 /** 911 * @} 912 */ 913 914 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode 915 * @{ 916 * @brief Constants defining whether the compare register is behaving in 917 * regular mode (compare match issued as soon as counter equal compare), 918 * or in auto-delayed mode 919 */ 920 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */ 921 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 922 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 923 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 924 /** 925 * @} 926 */ 927 928 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode 929 * @{ 930 * @brief Constants defining the behavior of the output signal when the timer 931 operates in basic output compare mode 932 */ 933 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */ 934 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */ 935 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ 936 937 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ 938 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ 939 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ 940 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) 941 /** 942 * @} 943 */ 944 945 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity 946 * @{ 947 * @brief Constants defining the polarity of a timer output 948 */ 949 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ 950 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 951 /** 952 * @} 953 */ 954 955 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source 956 * @{ 957 * @brief Constants defining the events that can be selected to configure the 958 * set crossbar of a timer output 959 */ 960 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ 961 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ 962 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ 963 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ 964 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ 965 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ 966 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ 967 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ 968 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ 969 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ 970 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ 971 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ 972 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 973 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 974 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 975 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 976 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 977 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 978 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 979 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 980 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 981 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ 982 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ 983 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ 984 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ 985 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ 986 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ 987 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ 988 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ 989 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ 990 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ 991 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ 992 /** 993 * @} 994 */ 995 996 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source 997 * @{ 998 * @brief Constants defining the events that can be selected to configure the 999 * reset crossbar of a timer output 1000 */ 1001 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ 1002 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ 1003 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ 1004 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ 1005 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ 1006 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ 1007 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ 1008 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ 1009 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ 1010 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ 1011 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ 1012 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ 1013 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1014 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1015 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1016 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1017 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1018 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1019 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1020 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1021 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1022 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ 1023 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ 1024 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ 1025 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ 1026 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ 1027 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ 1028 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ 1029 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ 1030 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ 1031 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ 1032 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ 1033 /** 1034 * @} 1035 */ 1036 1037 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode 1038 * @{ 1039 * @brief Constants defining whether or not the timer output transition to its 1040 IDLE state when burst mode is entered 1041 */ 1042 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ 1043 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 1044 /** 1045 * @} 1046 */ 1047 1048 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level 1049 * @{ 1050 * @brief Constants defining the output level when output is in IDLE state 1051 */ 1052 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 1053 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 1054 /** 1055 * @} 1056 */ 1057 1058 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level 1059 * @{ 1060 * @brief Constants defining the output level when output is in FAULT state 1061 */ 1062 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ 1063 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 1064 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 1065 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable 1071 * @{ 1072 * @brief Constants defining whether or not chopper mode is enabled for a timer 1073 output 1074 */ 1075 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 1076 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 1077 /** 1078 * @} 1079 */ 1080 1081 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed 1082 * @{ 1083 * @brief Constants defining the idle mode entry is delayed by forcing a 1084 dead-time insertion before switching the outputs to their idle state 1085 */ 1086 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 1087 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */ 1088 /** 1089 * @} 1090 */ 1091 1092 1093 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger 1094 * @{ 1095 * @brief Constants defining the events that can be selected to trigger the 1096 * capture of the timing unit counter 1097 */ 1098 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ 1099 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ 1100 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ 1101 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ 1102 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ 1103 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ 1104 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ 1105 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ 1106 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ 1107 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ 1108 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ 1109 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ 1110 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ 1111 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ 1112 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */ 1113 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */ 1114 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ 1115 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ 1116 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */ 1117 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */ 1118 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ 1119 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ 1120 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */ 1121 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */ 1122 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ 1123 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ 1124 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */ 1125 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */ 1126 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ 1127 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ 1128 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */ 1129 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */ 1130 /** 1131 * @} 1132 */ 1133 1134 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter 1135 * @{ 1136 * @brief Constants defining the event filtering applied to external events 1137 * by a timer 1138 */ 1139 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) 1140 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ 1141 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ 1142 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ 1143 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ 1144 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1145 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1146 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1147 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1148 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1149 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1150 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1151 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1152 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ 1153 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ 1154 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 1155 /** 1156 * @} 1157 */ 1158 1159 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch 1160 * @{ 1161 * @brief Constants defining whether or not the external event is 1162 * memorized (latched) and generated as soon as the blanking period 1163 * is completed or the window ends 1164 */ 1165 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */ 1166 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 1167 /** 1168 * @} 1169 */ 1170 1171 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio 1172 * @{ 1173 * @brief Constants defining division ratio between the timer clock frequency 1174 * (fHRTIM) and the dead-time generator clock (fDTG) 1175 */ 1176 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 1177 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ 1178 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ 1179 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ 1180 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ 1181 /** 1182 * @} 1183 */ 1184 1185 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign 1186 * @{ 1187 * @brief Constants defining whether the dead-time is positive or negative 1188 * (overlapping signal) on rising edge 1189 */ 1190 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */ 1191 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */ 1192 /** 1193 * @} 1194 */ 1195 1196 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock 1197 * @{ 1198 * @brief Constants defining whether or not the dead-time (rising sign and 1199 * value) is write protected 1200 */ 1201 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */ 1202 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */ 1203 /** 1204 * @} 1205 */ 1206 1207 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock 1208 * @{ 1209 * @brief Constants defining whether or not the dead-time rising sign is write 1210 * protected 1211 */ 1212 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */ 1213 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */ 1214 /** 1215 * @} 1216 */ 1217 1218 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign 1219 * @{ 1220 * @brief Constants defining whether the dead-time is positive or negative 1221 * (overlapping signal) on falling edge 1222 */ 1223 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */ 1224 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */ 1225 /** 1226 * @} 1227 */ 1228 1229 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock 1230 * @{ 1231 * @brief Constants defining whether or not the dead-time (falling sign and 1232 * value) is write protected 1233 */ 1234 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */ 1235 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */ 1236 /** 1237 * @} 1238 */ 1239 1240 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock 1241 * @{ 1242 * @brief Constants defining whether or not the dead-time falling sign is write 1243 * protected 1244 */ 1245 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */ 1246 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */ 1247 /** 1248 * @} 1249 */ 1250 1251 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency 1252 * @{ 1253 * @brief Constants defining the frequency of the generated high frequency carrier 1254 */ 1255 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */ 1256 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 1257 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 1258 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 1259 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 1260 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 1261 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 1262 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 1263 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 1264 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 1265 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 1266 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 1267 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 1268 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 1269 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 1270 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 1271 /** 1272 * @} 1273 */ 1274 1275 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle 1276 * @{ 1277 * @brief Constants defining the duty cycle of the generated high frequency carrier 1278 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 1279 */ 1280 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ 1281 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ 1282 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ 1283 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ 1284 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */ 1285 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */ 1286 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */ 1287 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */ 1288 /** 1289 * @} 1290 */ 1291 1292 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width 1293 * @{ 1294 * @brief Constants defining the pulse width of the first pulse of the generated 1295 * high frequency carrier 1296 */ 1297 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ 1298 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 1299 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 1300 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 1301 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 1302 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 1303 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 1304 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 1305 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 1306 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 1307 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 1308 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 1309 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 1310 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 1311 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 1312 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 1313 /** 1314 * @} 1315 */ 1316 1317 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options 1318 * @{ 1319 * @brief Constants defining the options for synchronizing multiple HRTIM 1320 * instances, as a master unit (generating a synchronization signal) 1321 * or as a slave (waiting for a trigger to be synchronized) 1322 */ 1323 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */ 1324 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/ 1325 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */ 1326 /** 1327 * @} 1328 */ 1329 1330 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source 1331 * @{ 1332 * @brief Constants defining defining the synchronization input source 1333 */ 1334 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ 1335 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ 1336 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 1337 /** 1338 * @} 1339 */ 1340 1341 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source 1342 * @{ 1343 * @brief Constants defining the source and event to be sent on the 1344 * synchronization outputs 1345 */ 1346 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 1347 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 1348 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 1349 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 1350 /** 1351 * @} 1352 */ 1353 1354 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity 1355 * @{ 1356 * @brief Constants defining the routing and conditioning of the synchronization output event 1357 */ 1358 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ 1359 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 1360 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 1361 /** 1362 * @} 1363 */ 1364 1365 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources 1366 * @{ 1367 * @brief Constants defining available sources associated to external events 1368 */ 1369 #define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */ 1370 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */ 1371 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */ 1372 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */ 1373 /** 1374 * @} 1375 */ 1376 1377 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity 1378 * @{ 1379 * @brief Constants defining the polarity of an external event 1380 */ 1381 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */ 1382 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 1383 /** 1384 * @} 1385 */ 1386 1387 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity 1388 * @{ 1389 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) 1390 * of an external event 1391 */ 1392 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */ 1393 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 1394 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 1395 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 1396 /** 1397 * @} 1398 */ 1399 1400 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode 1401 * @{ 1402 * @brief Constants defining whether or not an external event is programmed in 1403 fast mode 1404 */ 1405 #define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 1406 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 1407 /** 1408 * @} 1409 */ 1410 1411 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter 1412 * @{ 1413 * @brief Constants defining the frequency used to sample an external event 6 1414 * input and the length (N) of the digital filter applied 1415 */ 1416 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1417 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1418 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1419 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1420 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */ 1421 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */ 1422 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */ 1423 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */ 1424 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */ 1425 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */ 1426 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */ 1427 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */ 1428 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */ 1429 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */ 1430 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */ 1431 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */ 1432 /** 1433 * @} 1434 */ 1435 1436 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler 1437 * @{ 1438 * @brief Constants defining division ratio between the timer clock frequency 1439 * fHRTIM) and the external event signal sampling clock (fEEVS) 1440 * used by the digital filters 1441 */ 1442 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */ 1443 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */ 1444 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */ 1445 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */ 1446 /** 1447 * @} 1448 */ 1449 1450 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources 1451 * @{ 1452 * @brief Constants defining whether a fault is triggered by any external 1453 * or internal fault source 1454 */ 1455 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ 1456 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 1457 /** 1458 * @} 1459 */ 1460 1461 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity 1462 * @{ 1463 * @brief Constants defining the polarity of a fault event 1464 */ 1465 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ 1466 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter 1472 * @{ 1473 * @ brief Constants defining the frequency used to sample the fault input and 1474 * the length (N) of the digital filter applied 1475 */ 1476 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1477 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1478 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1479 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1480 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */ 1481 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */ 1482 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */ 1483 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */ 1484 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */ 1485 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */ 1486 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */ 1487 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */ 1488 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */ 1489 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */ 1490 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */ 1491 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */ 1492 /** 1493 * @} 1494 */ 1495 1496 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock 1497 * @{ 1498 * @brief Constants defining whether or not the fault programming bits are 1499 write protected 1500 */ 1501 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ 1502 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ 1503 /** 1504 * @} 1505 */ 1506 1507 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler 1508 * @{ 1509 * @brief Constants defining the division ratio between the timer clock 1510 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used 1511 * by the digital filters. 1512 */ 1513 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */ 1514 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */ 1515 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */ 1516 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */ 1517 /** 1518 * @} 1519 */ 1520 1521 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode 1522 * @{ 1523 * @brief Constants defining if the burst mode is entered once or if it is 1524 * continuously operating 1525 */ 1526 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ 1527 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 1528 /** 1529 * @} 1530 */ 1531 1532 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source 1533 * @{ 1534 * @brief Constants defining the clock source for the burst mode counter 1535 */ 1536 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 1537 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 1538 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 1539 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 1540 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 1541 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 1542 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 1543 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 1544 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 1545 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 1546 /** 1547 * @} 1548 */ 1549 1550 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler 1551 * @{ 1552 * @brief Constants defining the prescaling ratio of the fHRTIM clock 1553 * for the burst mode controller 1554 */ 1555 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */ 1556 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */ 1557 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */ 1558 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */ 1559 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */ 1560 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */ 1561 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */ 1562 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */ 1563 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */ 1564 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */ 1565 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */ 1566 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/ 1567 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */ 1568 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */ 1569 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */ 1570 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */ 1571 /** 1572 * @} 1573 */ 1574 1575 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable 1576 * @{ 1577 * @brief Constants defining whether or not burst mode registers preload 1578 mechanism is enabled, i.e. a write access into a preloadable register 1579 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register 1580 */ 1581 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */ 1582 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ 1583 /** 1584 * @} 1585 */ 1586 1587 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger 1588 * @{ 1589 * @brief Constants defining the events that can be used to trig the burst 1590 * mode operation 1591 */ 1592 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ 1593 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ 1594 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ 1595 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ 1596 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */ 1597 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */ 1598 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */ 1599 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ 1600 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ 1601 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ 1602 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ 1603 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ 1604 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ 1605 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ 1606 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ 1607 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ 1608 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ 1609 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ 1610 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */ 1611 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ 1612 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ 1613 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */ 1614 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ 1615 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */ 1616 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ 1617 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ 1618 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ 1619 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ 1620 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ 1621 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */ 1622 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/ 1623 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ 1624 /** 1625 * @} 1626 */ 1627 1628 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source 1629 * @{ 1630 * @brief constants defining the source triggering the update of the 1631 HRTIM_ADCxR register (transfer from preload to active register). 1632 */ 1633 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ 1634 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ 1635 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ 1636 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ 1637 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ 1638 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ 1639 /** 1640 * @} 1641 */ 1642 1643 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event 1644 * @{ 1645 * @brief constants defining the events triggering ADC conversion. 1646 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 1647 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 1648 */ 1649 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ 1650 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ 1651 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ 1652 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ 1653 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */ 1654 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ 1655 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */ 1656 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */ 1657 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */ 1658 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */ 1659 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */ 1660 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */ 1661 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */ 1662 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */ 1663 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ 1664 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ 1665 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */ 1666 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */ 1667 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */ 1668 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ 1669 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ 1670 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */ 1671 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */ 1672 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */ 1673 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ 1674 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */ 1675 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */ 1676 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */ 1677 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ 1678 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */ 1679 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */ 1680 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */ 1681 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ 1682 1683 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */ 1684 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */ 1685 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */ 1686 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */ 1687 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */ 1688 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ 1689 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */ 1690 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */ 1691 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */ 1692 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */ 1693 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */ 1694 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */ 1695 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */ 1696 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */ 1697 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ 1698 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */ 1699 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */ 1700 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */ 1701 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ 1702 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */ 1703 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */ 1704 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */ 1705 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ 1706 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ 1707 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */ 1708 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */ 1709 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */ 1710 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ 1711 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ 1712 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */ 1713 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ 1714 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ 1715 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ 1716 1717 /** 1718 * @} 1719 */ 1720 1721 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update 1722 * @{ 1723 * @brief Constants defining the registers that can be written during a burst 1724 * DMA operation 1725 */ 1726 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 1727 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ 1728 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ 1729 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ 1730 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ 1731 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ 1732 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ 1733 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ 1734 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ 1735 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ 1736 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ 1737 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ 1738 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 1739 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 1740 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 1741 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 1742 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 1743 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 1744 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 1745 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 1746 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 1747 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 1748 /** 1749 * @} 1750 */ 1751 1752 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control 1753 * @{ 1754 * @brief Constants used to enable or disable the burst mode controller 1755 */ 1756 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ 1757 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ 1758 /** 1759 * @} 1760 */ 1761 1762 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control 1763 * @{ 1764 * @brief Constants used to enable or disable a fault channel 1765 */ 1766 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ 1767 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ 1768 /** 1769 * @} 1770 */ 1771 1772 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update 1773 * @{ 1774 * @brief Constants used to force timer registers update 1775 */ 1776 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */ 1777 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */ 1778 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */ 1779 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */ 1780 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */ 1781 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */ 1782 /** 1783 * @} 1784 */ 1785 1786 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset 1787 * @{ 1788 * @brief Constants used to force timer counter reset 1789 */ 1790 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */ 1791 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */ 1792 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */ 1793 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */ 1794 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */ 1795 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */ 1796 /** 1797 * @} 1798 */ 1799 1800 /** @defgroup HRTIM_Output_Level HRTIM Output Level 1801 * @{ 1802 * @brief Constants defining the level of a timer output 1803 */ 1804 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */ 1805 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ 1806 1807 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ 1808 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ 1809 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) 1810 /** 1811 * @} 1812 */ 1813 1814 /** @defgroup HRTIM_Output_State HRTIM Output State 1815 * @{ 1816 * @brief Constants defining the state of a timer output 1817 */ 1818 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or 1819 inactive level as programmed in the crossbar unit */ 1820 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the 1821 outputs are disabled by software or during a burst mode operation */ 1822 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on 1823 FAULTx inputs */ 1824 /** 1825 * @} 1826 */ 1827 1828 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status 1829 * @{ 1830 * @brief Constants defining the operating state of the burst mode controller 1831 */ 1832 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ 1833 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ 1834 /** 1835 * @} 1836 */ 1837 1838 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status 1839 * @{ 1840 * @brief Constants defining on which output the signal is currently applied 1841 * in push-pull mode 1842 */ 1843 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ 1844 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 1845 /** 1846 * @} 1847 */ 1848 1849 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status 1850 * @{ 1851 * @brief Constants defining on which output the signal was applied, in 1852 * push-pull mode balanced fault mode or delayed idle mode, when the 1853 * protection was triggered 1854 */ 1855 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 1856 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 1857 /** 1858 * @} 1859 */ 1860 1861 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable 1862 * @{ 1863 */ 1864 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1865 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ 1866 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ 1867 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ 1868 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */ 1869 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */ 1870 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */ 1871 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */ 1872 /** 1873 * @} 1874 */ 1875 1876 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable 1877 * @{ 1878 */ 1879 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1880 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ 1881 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ 1882 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ 1883 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */ 1884 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */ 1885 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */ 1886 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */ 1887 /** 1888 * @} 1889 */ 1890 1891 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable 1892 * @{ 1893 */ 1894 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1895 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ 1896 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ 1897 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ 1898 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */ 1899 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */ 1900 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */ 1901 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */ 1902 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */ 1903 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */ 1904 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */ 1905 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */ 1906 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */ 1907 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */ 1908 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */ 1909 /** 1910 * @} 1911 */ 1912 1913 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag 1914 * @{ 1915 */ 1916 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ 1917 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ 1918 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ 1919 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ 1920 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ 1921 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ 1922 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ 1923 /** 1924 * @} 1925 */ 1926 1927 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag 1928 * @{ 1929 */ 1930 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ 1931 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ 1932 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ 1933 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ 1934 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ 1935 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ 1936 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ 1937 /** 1938 * @} 1939 */ 1940 1941 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag 1942 * @{ 1943 */ 1944 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ 1945 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ 1946 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ 1947 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ 1948 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ 1949 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ 1950 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ 1951 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ 1952 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ 1953 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ 1954 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ 1955 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ 1956 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */ 1957 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ 1958 /** 1959 * @} 1960 */ 1961 1962 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable 1963 * @{ 1964 */ 1965 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ 1966 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ 1967 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ 1968 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ 1969 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */ 1970 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */ 1971 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */ 1972 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */ 1973 /** 1974 * @} 1975 */ 1976 1977 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable 1978 * @{ 1979 */ 1980 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ 1981 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ 1982 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ 1983 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ 1984 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */ 1985 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */ 1986 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */ 1987 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */ 1988 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */ 1989 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */ 1990 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */ 1991 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */ 1992 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */ 1993 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */ 1994 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */ 1995 /** 1996 * @} 1997 */ 1998 1999 /** 2000 * @} 2001 */ 2002 2003 /* Private macros --------------------------------------------------------*/ 2004 /** @addtogroup HRTIM_Private_Macros 2005 * @{ 2006 */ 2007 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ 2008 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ 2009 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2010 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2011 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2012 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2013 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 2014 2015 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ 2016 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2017 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2018 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2019 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2020 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 2021 2022 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) 2023 2024 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ 2025 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ 2026 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ 2027 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ 2028 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) 2029 2030 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ 2031 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ 2032 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) 2033 2034 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) 2035 2036 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ 2037 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2038 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ 2039 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ 2040 || \ 2041 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2042 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ 2043 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ 2044 || \ 2045 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2046 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ 2047 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ 2048 || \ 2049 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2050 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ 2051 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ 2052 || \ 2053 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2054 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ 2055 ((OUTPUT) == HRTIM_OUTPUT_TE2)))) 2056 2057 #define IS_HRTIM_EVENT(EVENT)\ 2058 (((EVENT) == HRTIM_EVENT_NONE)|| \ 2059 ((EVENT) == HRTIM_EVENT_1) || \ 2060 ((EVENT) == HRTIM_EVENT_2) || \ 2061 ((EVENT) == HRTIM_EVENT_3) || \ 2062 ((EVENT) == HRTIM_EVENT_4) || \ 2063 ((EVENT) == HRTIM_EVENT_5) || \ 2064 ((EVENT) == HRTIM_EVENT_6) || \ 2065 ((EVENT) == HRTIM_EVENT_7) || \ 2066 ((EVENT) == HRTIM_EVENT_8) || \ 2067 ((EVENT) == HRTIM_EVENT_9) || \ 2068 ((EVENT) == HRTIM_EVENT_10)) 2069 2070 #define IS_HRTIM_FAULT(FAULT)\ 2071 (((FAULT) == HRTIM_FAULT_1) || \ 2072 ((FAULT) == HRTIM_FAULT_2) || \ 2073 ((FAULT) == HRTIM_FAULT_3) || \ 2074 ((FAULT) == HRTIM_FAULT_4) || \ 2075 ((FAULT) == HRTIM_FAULT_5)) 2076 2077 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ 2078 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ 2079 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ 2080 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) 2081 2082 #define IS_HRTIM_MODE(MODE)\ 2083 (((MODE) == HRTIM_MODE_CONTINUOUS) || \ 2084 ((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2085 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2086 2087 #define IS_HRTIM_MODE_ONEPULSE(MODE)\ 2088 (((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2089 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2090 2091 2092 #define IS_HRTIM_HALFMODE(HALFMODE)\ 2093 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ 2094 ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) 2095 2096 #define IS_HRTIM_SYNCSTART(SYNCSTART)\ 2097 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ 2098 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) 2099 2100 #define IS_HRTIM_SYNCRESET(SYNCRESET)\ 2101 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ 2102 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) 2103 2104 #define IS_HRTIM_DACSYNC(DACSYNC)\ 2105 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ 2106 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ 2107 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ 2108 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) 2109 2110 #define IS_HRTIM_PRELOAD(PRELOAD)\ 2111 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ 2112 ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) 2113 2114 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ 2115 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2116 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2117 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) 2118 2119 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ 2120 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2121 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2122 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ 2123 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ 2124 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ 2125 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ 2126 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ 2127 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ 2128 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) 2129 2130 #define IS_HRTIM_TIMERBURSTMODE(MODE) \ 2131 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ 2132 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) 2133 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ 2134 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ 2135 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) 2136 2137 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ 2138 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ 2139 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) 2140 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) 2141 2142 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ 2143 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ 2144 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) 2145 2146 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ 2147 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ 2148 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ 2149 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ 2150 || \ 2151 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2152 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) 2153 2154 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ 2155 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ 2156 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ 2157 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ 2158 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ 2159 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ 2160 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ 2161 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ 2162 || \ 2163 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2164 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ 2165 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) 2166 2167 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) 2168 2169 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U) 2170 2171 2172 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ 2173 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ 2174 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) 2175 2176 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ 2177 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2178 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2179 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2180 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) 2181 2182 /* Auto delayed mode is only available for compare units 2 and 4U */ 2183 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ 2184 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ 2185 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2186 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2187 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2188 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ 2189 || \ 2190 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ 2191 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2192 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2193 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2194 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) 2195 2196 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ 2197 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ 2198 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) 2199 2200 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) 2201 2202 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ 2203 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ 2204 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ 2205 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ 2206 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ 2207 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ 2208 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ 2209 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ 2210 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ 2211 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ 2212 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ 2213 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ 2214 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ 2215 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ 2216 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ 2217 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ 2218 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ 2219 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ 2220 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ 2221 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ 2222 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ 2223 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ 2224 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ 2225 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ 2226 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ 2227 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ 2228 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ 2229 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ 2230 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ 2231 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ 2232 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ 2233 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ 2234 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) 2235 2236 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ 2237 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ 2238 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ 2239 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ 2240 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ 2241 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ 2242 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ 2243 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ 2244 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ 2245 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ 2246 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ 2247 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ 2248 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ 2249 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ 2250 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ 2251 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ 2252 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ 2253 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ 2254 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ 2255 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ 2256 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ 2257 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ 2258 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ 2259 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ 2260 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ 2261 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ 2262 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ 2263 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ 2264 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ 2265 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ 2266 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ 2267 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ 2268 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) 2269 2270 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ 2271 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ 2272 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) 2273 2274 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ 2275 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ 2276 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) 2277 2278 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ 2279 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ 2280 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ 2281 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ 2282 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) 2283 2284 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ 2285 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ 2286 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) 2287 2288 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ 2289 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ 2290 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) 2291 2292 2293 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ 2294 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ 2295 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ 2296 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ 2297 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ 2298 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ 2299 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ 2300 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ 2301 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ 2302 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ 2303 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ 2304 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ 2305 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ 2306 || \ 2307 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2308 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2309 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2310 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2311 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2312 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2313 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2314 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2315 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2316 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2317 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2318 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2319 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2320 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2321 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2322 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2323 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2324 || \ 2325 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2326 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2327 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2328 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2329 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2330 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2331 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2342 || \ 2343 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2344 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2347 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2348 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2349 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2350 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2351 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2352 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2353 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2354 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2355 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2356 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2357 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2358 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2359 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2360 || \ 2361 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2362 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2363 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2364 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2365 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2366 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2367 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2368 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2369 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2370 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2371 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2372 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2373 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2374 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2375 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2376 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2377 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2378 || \ 2379 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2380 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2381 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2382 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2383 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2384 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2385 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2386 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2387 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2388 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2389 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2390 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2391 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2392 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2393 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2394 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2395 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) 2396 2397 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ 2398 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ 2399 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ 2400 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ 2401 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ 2402 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ 2403 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ 2404 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ 2405 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ 2406 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ 2407 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ 2408 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ 2409 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ 2410 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ 2411 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ 2412 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ 2413 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) 2414 2415 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ 2416 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ 2417 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) 2418 2419 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ 2420 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ 2421 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ 2422 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ 2423 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ 2424 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) 2425 2426 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ 2427 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ 2428 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) 2429 2430 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ 2431 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ 2432 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) 2433 2434 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ 2435 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ 2436 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) 2437 2438 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ 2439 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ 2440 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) 2441 2442 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ 2443 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ 2444 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) 2445 2446 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ 2447 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ 2448 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) 2449 2450 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ 2451 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ 2452 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ 2453 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ 2454 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ 2455 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ 2456 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ 2457 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ 2458 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ 2459 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ 2460 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ 2461 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ 2462 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ 2463 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ 2464 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ 2465 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ 2466 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) 2467 2468 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ 2469 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ 2470 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ 2471 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ 2472 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ 2473 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ 2474 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ 2475 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ 2476 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) 2477 2478 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ 2479 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ 2480 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ 2481 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ 2482 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ 2483 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ 2484 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ 2485 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ 2486 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ 2487 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ 2488 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ 2489 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ 2490 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ 2491 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ 2492 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ 2493 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ 2494 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) 2495 2496 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ 2497 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ 2498 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ 2499 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) 2500 2501 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ 2502 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ 2503 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ 2504 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ 2505 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) 2506 2507 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ 2508 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ 2509 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ 2510 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) 2511 2512 #define IS_HRTIM_EVENTSRC(EVENTSRC)\ 2513 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ 2514 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ 2515 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ 2516 ((EVENTSRC) == HRTIM_EVENTSRC_4)) 2517 2518 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ 2519 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ 2520 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ 2521 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ 2522 || \ 2523 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 2524 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ 2525 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) 2526 2527 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ 2528 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ 2529 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 2530 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ 2531 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) 2532 2533 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ 2534 (((((EVENT) == HRTIM_EVENT_1) || \ 2535 ((EVENT) == HRTIM_EVENT_2) || \ 2536 ((EVENT) == HRTIM_EVENT_3) || \ 2537 ((EVENT) == HRTIM_EVENT_4) || \ 2538 ((EVENT) == HRTIM_EVENT_5)) && \ 2539 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ 2540 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ 2541 || \ 2542 (((EVENT) == HRTIM_EVENT_6) || \ 2543 ((EVENT) == HRTIM_EVENT_7) || \ 2544 ((EVENT) == HRTIM_EVENT_8) || \ 2545 ((EVENT) == HRTIM_EVENT_9) || \ 2546 ((EVENT) == HRTIM_EVENT_10))) 2547 2548 2549 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ 2550 ((((EVENT) == HRTIM_EVENT_1) || \ 2551 ((EVENT) == HRTIM_EVENT_2) || \ 2552 ((EVENT) == HRTIM_EVENT_3) || \ 2553 ((EVENT) == HRTIM_EVENT_4) || \ 2554 ((EVENT) == HRTIM_EVENT_5)) \ 2555 || \ 2556 ((((EVENT) == HRTIM_EVENT_6) || \ 2557 ((EVENT) == HRTIM_EVENT_7) || \ 2558 ((EVENT) == HRTIM_EVENT_8) || \ 2559 ((EVENT) == HRTIM_EVENT_9) || \ 2560 ((EVENT) == HRTIM_EVENT_10)) && \ 2561 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ 2562 ((FILTER) == HRTIM_EVENTFILTER_1) || \ 2563 ((FILTER) == HRTIM_EVENTFILTER_2) || \ 2564 ((FILTER) == HRTIM_EVENTFILTER_3) || \ 2565 ((FILTER) == HRTIM_EVENTFILTER_4) || \ 2566 ((FILTER) == HRTIM_EVENTFILTER_5) || \ 2567 ((FILTER) == HRTIM_EVENTFILTER_6) || \ 2568 ((FILTER) == HRTIM_EVENTFILTER_7) || \ 2569 ((FILTER) == HRTIM_EVENTFILTER_8) || \ 2570 ((FILTER) == HRTIM_EVENTFILTER_9) || \ 2571 ((FILTER) == HRTIM_EVENTFILTER_10) || \ 2572 ((FILTER) == HRTIM_EVENTFILTER_11) || \ 2573 ((FILTER) == HRTIM_EVENTFILTER_12) || \ 2574 ((FILTER) == HRTIM_EVENTFILTER_13) || \ 2575 ((FILTER) == HRTIM_EVENTFILTER_14) || \ 2576 ((FILTER) == HRTIM_EVENTFILTER_15)))) 2577 2578 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ 2579 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ 2580 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ 2581 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ 2582 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) 2583 2584 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ 2585 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ 2586 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) 2587 2588 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ 2589 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ 2590 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) 2591 2592 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ 2593 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ 2594 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) 2595 2596 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ 2597 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ 2598 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ 2599 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ 2600 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ 2601 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ 2602 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ 2603 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ 2604 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ 2605 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ 2606 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ 2607 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ 2608 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ 2609 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ 2610 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ 2611 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ 2612 ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) 2613 2614 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ 2615 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ 2616 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) 2617 2618 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ 2619 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ 2620 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ 2621 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ 2622 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) 2623 2624 #define IS_HRTIM_BURSTMODE(BURSTMODE)\ 2625 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ 2626 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) 2627 2628 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ 2629 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ 2630 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ 2631 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ 2632 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ 2633 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ 2634 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ 2635 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ 2636 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ 2637 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ 2638 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) 2639 2640 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ 2641 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ 2642 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ 2643 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ 2644 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ 2645 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ 2646 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ 2647 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ 2648 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ 2649 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ 2650 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ 2651 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ 2652 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ 2653 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ 2654 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ 2655 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ 2656 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) 2657 2658 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ 2659 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ 2660 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) 2661 2662 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ 2663 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ 2664 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ 2665 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ 2666 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ 2667 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ 2668 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ 2669 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ 2670 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ 2671 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ 2672 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ 2673 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ 2674 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ 2675 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ 2676 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ 2677 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ 2678 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ 2679 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ 2680 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ 2681 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ 2682 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ 2683 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ 2684 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ 2685 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ 2686 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ 2687 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ 2688 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ 2689 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ 2690 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ 2691 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ 2692 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ 2693 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ 2694 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) 2695 2696 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ 2697 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ 2698 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ 2699 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ 2700 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ 2701 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ 2702 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) 2703 2704 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ 2705 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ 2706 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ 2707 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ 2708 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ 2709 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) 2710 2711 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ 2712 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ 2713 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2714 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2715 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2716 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2717 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) 2718 2719 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ 2720 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ 2721 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) 2722 2723 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) 2724 2725 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U) 2726 2727 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U) 2728 2729 2730 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) 2731 2732 2733 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) 2734 2735 2736 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) 2737 2738 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U) 2739 /** 2740 * @} 2741 */ 2742 2743 /* Exported macros -----------------------------------------------------------*/ 2744 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros 2745 * @{ 2746 */ 2747 2748 /** @brief Reset HRTIM handle state 2749 * @param __HANDLE__ HRTIM handle. 2750 * @retval None 2751 */ 2752 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 2753 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ 2754 (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ 2755 (__HANDLE__)->MspInitCallback = NULL; \ 2756 (__HANDLE__)->MspDeInitCallback = NULL; \ 2757 } while(0) 2758 #else 2759 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) 2760 #endif 2761 2762 /** @brief Enables or disables the timer counter(s) 2763 * @param __HANDLE__ specifies the HRTIM Handle. 2764 * @param __TIMERS__ timers to enable/disable 2765 * This parameter can be any combinations of the following values: 2766 * @arg HRTIM_TIMERID_MASTER: Master timer identifier 2767 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier 2768 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier 2769 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier 2770 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier 2771 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier 2772 * @retval None 2773 */ 2774 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__)) 2775 2776 /* The counter of a timing unit is disabled only if all the timer outputs */ 2777 /* are disabled and no capture is configured */ 2778 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) 2779 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) 2780 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) 2781 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) 2782 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) 2783 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ 2784 do {\ 2785 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ 2786 {\ 2787 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ 2788 }\ 2789 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 2790 {\ 2791 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ 2792 {\ 2793 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ 2794 }\ 2795 }\ 2796 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 2797 {\ 2798 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ 2799 {\ 2800 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ 2801 }\ 2802 }\ 2803 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 2804 {\ 2805 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ 2806 {\ 2807 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ 2808 }\ 2809 }\ 2810 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 2811 {\ 2812 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ 2813 {\ 2814 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ 2815 }\ 2816 }\ 2817 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 2818 {\ 2819 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ 2820 {\ 2821 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ 2822 }\ 2823 }\ 2824 } while(0U) 2825 2826 2827 /** @brief Enables or disables the specified HRTIM common interrupts. 2828 * @param __HANDLE__ specifies the HRTIM Handle. 2829 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2830 * This parameter can be one of the following values: 2831 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 2832 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 2833 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable 2834 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable 2835 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable 2836 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 2837 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 2838 * @retval None 2839 */ 2840 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__)) 2841 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__)) 2842 2843 /** @brief Enables or disables the specified HRTIM Master timer interrupts. 2844 * @param __HANDLE__ specifies the HRTIM Handle. 2845 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2846 * This parameter can be one of the following values: 2847 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2848 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2849 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2850 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2851 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2852 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2853 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2854 * @retval None 2855 */ 2856 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ 2857 |= (__INTERRUPT__)) 2858 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ 2859 &= ~(__INTERRUPT__)) 2860 2861 /** @brief Enables or disables the specified HRTIM Timerx interrupts. 2862 * @param __HANDLE__ specifies the HRTIM Handle. 2863 * @param __TIMER__ specified the timing unit (Timer A to E) 2864 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2865 * This parameter can be one of the following values: 2866 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 2867 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 2868 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 2869 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 2870 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 2871 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 2872 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 2873 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 2874 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 2875 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 2876 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 2877 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 2878 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 2879 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 2880 * @retval None 2881 */ 2882 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__)) 2883 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__)) 2884 2885 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled. 2886 * @param __HANDLE__ specifies the HRTIM Handle. 2887 * @param __INTERRUPT__ specifies the interrupt source to check. 2888 * This parameter can be one of the following values: 2889 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 2890 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 2891 * @arg HRTIM_IT_FLT3: Fault 3 enable 2892 * @arg HRTIM_IT_FLT4: Fault 4 enable 2893 * @arg HRTIM_IT_FLT5: Fault 5 enable 2894 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 2895 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 2896 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2897 */ 2898 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ 2899 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2900 2901 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. 2902 * @param __HANDLE__ specifies the HRTIM Handle. 2903 * @param __INTERRUPT__ specifies the interrupt source to check. 2904 * This parameter can be one of the following values: 2905 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2906 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2907 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2908 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2909 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2910 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2911 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2912 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2913 */ 2914 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ 2915 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2916 2917 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. 2918 * @param __HANDLE__ specifies the HRTIM Handle. 2919 * @param __TIMER__ specified the timing unit (Timer A to E) 2920 * @param __INTERRUPT__ specifies the interrupt source to check. 2921 * This parameter can be one of the following values: 2922 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2923 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2924 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2925 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2926 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2927 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2928 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2929 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 2930 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 2931 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 2932 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 2933 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 2934 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 2935 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 2936 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 2937 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 2938 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 2939 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 2940 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 2941 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 2942 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 2943 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2944 */ 2945 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ 2946 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2947 2948 /** @brief Clears the specified HRTIM common pending flag. 2949 * @param __HANDLE__ specifies the HRTIM Handle. 2950 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2951 * This parameter can be one of the following values: 2952 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag 2953 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag 2954 * @arg HRTIM_IT_FLT3: Fault 3 clear flag 2955 * @arg HRTIM_IT_FLT4: Fault 4 clear flag 2956 * @arg HRTIM_IT_FLT5: Fault 5 clear flag 2957 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag 2958 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag 2959 * @retval None 2960 */ 2961 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 2962 2963 /** @brief Clears the specified HRTIM Master pending flag. 2964 * @param __HANDLE__ specifies the HRTIM Handle. 2965 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2966 * This parameter can be one of the following values: 2967 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag 2968 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag 2969 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag 2970 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag 2971 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag 2972 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag 2973 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag 2974 * @retval None 2975 */ 2976 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ 2977 = (__INTERRUPT__)) 2978 2979 /** @brief Clears the specified HRTIM Timerx pending flag. 2980 * @param __HANDLE__ specifies the HRTIM Handle. 2981 * @param __TIMER__ specified the timing unit (Timer A to E) 2982 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2983 * This parameter can be one of the following values: 2984 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag 2985 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag 2986 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag 2987 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag 2988 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag 2989 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag 2990 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag 2991 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag 2992 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag 2993 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag 2994 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag 2995 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag 2996 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag 2997 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag 2998 * @retval None 2999 */ 3000 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ 3001 = (__INTERRUPT__)) 3002 3003 /* DMA HANDLING */ 3004 /** @brief Enables or disables the specified HRTIM Master timer DMA requests. 3005 * @param __HANDLE__ specifies the HRTIM Handle. 3006 * @param __DMA__ specifies the DMA request to enable or disable. 3007 * This parameter can be one of the following values: 3008 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable 3009 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable 3010 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable 3011 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable 3012 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable 3013 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable 3014 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable 3015 * @retval None 3016 */ 3017 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__)) 3018 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__)) 3019 3020 /** @brief Enables or disables the specified HRTIM Timerx DMA requests. 3021 * @param __HANDLE__ specifies the HRTIM Handle. 3022 * @param __TIMER__ specified the timing unit (Timer A to E) 3023 * @param __DMA__ specifies the DMA request to enable or disable. 3024 * This parameter can be one of the following values: 3025 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable 3026 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable 3027 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable 3028 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable 3029 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable 3030 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable 3031 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable 3032 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable 3033 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable 3034 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable 3035 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable 3036 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable 3037 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable 3038 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable 3039 * @retval None 3040 */ 3041 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) 3042 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) 3043 3044 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ 3045 (__FLAG__)) == (__FLAG__)) 3046 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) 3047 3048 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ 3049 (__FLAG__)) == (__FLAG__)) 3050 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) 3051 3052 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ 3053 (__FLAG__)) == (__FLAG__)) 3054 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ 3055 = (__FLAG__)) 3056 3057 /** @brief Sets the HRTIM timer Counter Register value on runtime 3058 * @param __HANDLE__ HRTIM Handle. 3059 * @param __TIMER__ HRTIM timer 3060 * This parameter can be one of the following values: 3061 * @arg 0x5 for master timer 3062 * @arg 0x0 to 0x4 for timers A to E 3063 * @param __COUNTER__ specifies the Counter Register new value. 3064 * @retval None 3065 */ 3066 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \ 3067 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\ 3068 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__))) 3069 3070 /** @brief Gets the HRTIM timer Counter Register value on runtime 3071 * @param __HANDLE__ HRTIM Handle. 3072 * @param __TIMER__ HRTIM timer 3073 * This parameter can be one of the following values: 3074 * @arg 0x5 for master timer 3075 * @arg 0x0 to 0x4 for timers A to E 3076 * @retval HRTIM timer Counter Register value 3077 */ 3078 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \ 3079 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\ 3080 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR)) 3081 3082 /** @brief Sets the HRTIM timer Period value on runtime 3083 * @param __HANDLE__ HRTIM Handle. 3084 * @param __TIMER__ HRTIM timer 3085 * This parameter can be one of the following values: 3086 * @arg 0x5 for master timer 3087 * @arg 0x0 to 0x4 for timers A to E 3088 * @param __PERIOD__ specifies the Period Register new value. 3089 * @retval None 3090 */ 3091 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \ 3092 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\ 3093 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__))) 3094 3095 /** @brief Gets the HRTIM timer Period Register value on runtime 3096 * @param __HANDLE__ HRTIM Handle. 3097 * @param __TIMER__ HRTIM timer 3098 * This parameter can be one of the following values: 3099 * @arg 0x5 for master timer 3100 * @arg 0x0 to 0x4 for timers A to E 3101 * @retval timer Period Register 3102 */ 3103 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \ 3104 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\ 3105 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR)) 3106 3107 /** @brief Sets the HRTIM timer clock prescaler value on runtime 3108 * @param __HANDLE__ HRTIM Handle. 3109 * @param __TIMER__ HRTIM timer 3110 * This parameter can be one of the following values: 3111 * @arg 0x5 for master timer 3112 * @arg 0x0 to 0x4 for timers A to E 3113 * @param __PRESCALER__ specifies the clock prescaler new value. 3114 * This parameter can be one of the following values: 3115 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) 3116 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) 3117 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) 3118 * @retval None 3119 */ 3120 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \ 3121 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\ 3122 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__)))) 3123 3124 /** @brief Gets the HRTIM timer clock prescaler value on runtime 3125 * @param __HANDLE__ HRTIM Handle. 3126 * @param __TIMER__ HRTIM timer 3127 * This parameter can be one of the following values: 3128 * @arg 0x5 for master timer 3129 * @arg 0x0 to 0x4 for timers A to E 3130 * @retval timer clock prescaler value 3131 */ 3132 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \ 3133 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\ 3134 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC)) 3135 3136 /** @brief Sets the HRTIM timer Compare Register value on runtime 3137 * @param __HANDLE__ HRTIM Handle. 3138 * @param __TIMER__ HRTIM timer 3139 * This parameter can be one of the following values: 3140 * @arg 0x0 to 0x4 for timers A to E 3141 * @param __COMPAREUNIT__ timer compare unit 3142 * This parameter can be one of the following values: 3143 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 3144 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 3145 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 3146 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 3147 * @param __COMPARE__ specifies the Compare new value. 3148 * @retval None 3149 */ 3150 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ 3151 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 3152 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ 3153 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ 3154 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ 3155 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ 3156 : \ 3157 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ 3158 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ 3159 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ 3160 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) 3161 3162 /** @brief Gets the HRTIM timer Compare Register value on runtime 3163 * @param __HANDLE__ HRTIM Handle. 3164 * @param __TIMER__ HRTIM timer 3165 * This parameter can be one of the following values: 3166 * @arg 0x0 to 0x4 for timers A to E 3167 * @param __COMPAREUNIT__ timer compare unit 3168 * This parameter can be one of the following values: 3169 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 3170 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 3171 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 3172 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 3173 * @retval Compare value 3174 */ 3175 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ 3176 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 3177 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ 3178 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ 3179 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ 3180 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ 3181 : \ 3182 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ 3183 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ 3184 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ 3185 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) 3186 3187 /** 3188 * @} 3189 */ 3190 3191 /* Exported functions --------------------------------------------------------*/ 3192 /** @addtogroup HRTIM_Exported_Functions 3193 * @{ 3194 */ 3195 3196 /** @addtogroup HRTIM_Exported_Functions_Group1 3197 * @{ 3198 */ 3199 3200 /* Initialization and Configuration functions ********************************/ 3201 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); 3202 3203 HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); 3204 3205 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); 3206 3207 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); 3208 3209 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, 3210 uint32_t TimerIdx, 3211 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); 3212 /** 3213 * @} 3214 */ 3215 3216 /** @addtogroup HRTIM_Exported_Functions_Group2 3217 * @{ 3218 */ 3219 3220 /* Simple time base related functions *****************************************/ 3221 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, 3222 uint32_t TimerIdx); 3223 3224 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, 3225 uint32_t TimerIdx); 3226 3227 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, 3228 uint32_t TimerIdx); 3229 3230 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, 3231 uint32_t TimerIdx); 3232 3233 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3234 uint32_t TimerIdx, 3235 uint32_t SrcAddr, 3236 uint32_t DestAddr, 3237 uint32_t Length); 3238 3239 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3240 uint32_t TimerIdx); 3241 3242 /** 3243 * @} 3244 */ 3245 3246 /** @addtogroup HRTIM_Exported_Functions_Group3 3247 * @{ 3248 */ 3249 /* Simple output compare related functions ************************************/ 3250 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3251 uint32_t TimerIdx, 3252 uint32_t OCChannel, 3253 const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); 3254 3255 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, 3256 uint32_t TimerIdx, 3257 uint32_t OCChannel); 3258 3259 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, 3260 uint32_t TimerIdx, 3261 uint32_t OCChannel); 3262 3263 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, 3264 uint32_t TimerIdx, 3265 uint32_t OCChannel); 3266 3267 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, 3268 uint32_t TimerIdx, 3269 uint32_t OCChannel); 3270 3271 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3272 uint32_t TimerIdx, 3273 uint32_t OCChannel, 3274 uint32_t SrcAddr, 3275 uint32_t DestAddr, 3276 uint32_t Length); 3277 3278 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3279 uint32_t TimerIdx, 3280 uint32_t OCChannel); 3281 3282 /** 3283 * @} 3284 */ 3285 3286 /** @addtogroup HRTIM_Exported_Functions_Group4 3287 * @{ 3288 */ 3289 /* Simple PWM output related functions ****************************************/ 3290 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3291 uint32_t TimerIdx, 3292 uint32_t PWMChannel, 3293 const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); 3294 3295 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, 3296 uint32_t TimerIdx, 3297 uint32_t PWMChannel); 3298 3299 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, 3300 uint32_t TimerIdx, 3301 uint32_t PWMChannel); 3302 3303 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, 3304 uint32_t TimerIdx, 3305 uint32_t PWMChannel); 3306 3307 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, 3308 uint32_t TimerIdx, 3309 uint32_t PWMChannel); 3310 3311 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3312 uint32_t TimerIdx, 3313 uint32_t PWMChannel, 3314 uint32_t SrcAddr, 3315 uint32_t DestAddr, 3316 uint32_t Length); 3317 3318 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3319 uint32_t TimerIdx, 3320 uint32_t PWMChannel); 3321 3322 /** 3323 * @} 3324 */ 3325 3326 /** @addtogroup HRTIM_Exported_Functions_Group5 3327 * @{ 3328 */ 3329 /* Simple capture related functions *******************************************/ 3330 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3331 uint32_t TimerIdx, 3332 uint32_t CaptureChannel, 3333 const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); 3334 3335 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, 3336 uint32_t TimerIdx, 3337 uint32_t CaptureChannel); 3338 3339 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, 3340 uint32_t TimerIdx, 3341 uint32_t CaptureChannel); 3342 3343 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, 3344 uint32_t TimerIdx, 3345 uint32_t CaptureChannel); 3346 3347 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, 3348 uint32_t TimerIdx, 3349 uint32_t CaptureChannel); 3350 3351 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3352 uint32_t TimerIdx, 3353 uint32_t CaptureChannel, 3354 uint32_t SrcAddr, 3355 uint32_t DestAddr, 3356 uint32_t Length); 3357 3358 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3359 uint32_t TimerIdx, 3360 uint32_t CaptureChannel); 3361 3362 /** 3363 * @} 3364 */ 3365 3366 /** @addtogroup HRTIM_Exported_Functions_Group6 3367 * @{ 3368 */ 3369 /* Simple one pulse related functions *****************************************/ 3370 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3371 uint32_t TimerIdx, 3372 uint32_t OnePulseChannel, 3373 const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); 3374 3375 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, 3376 uint32_t TimerIdx, 3377 uint32_t OnePulseChannel); 3378 3379 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, 3380 uint32_t TimerIdx, 3381 uint32_t OnePulseChannel); 3382 3383 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, 3384 uint32_t TimerIdx, 3385 uint32_t OnePulseChannel); 3386 3387 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, 3388 uint32_t TimerIdx, 3389 uint32_t OnePulseChannel); 3390 3391 /** 3392 * @} 3393 */ 3394 3395 /** @addtogroup HRTIM_Exported_Functions_Group7 3396 * @{ 3397 */ 3398 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, 3399 const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); 3400 3401 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, 3402 uint32_t Event, 3403 const HRTIM_EventCfgTypeDef *pEventCfg); 3404 3405 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 3406 uint32_t Prescaler); 3407 3408 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, 3409 uint32_t Fault, 3410 const HRTIM_FaultCfgTypeDef *pFaultCfg); 3411 3412 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 3413 uint32_t Prescaler); 3414 3415 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, 3416 uint32_t Faults, 3417 uint32_t Enable); 3418 3419 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, 3420 uint32_t ADCTrigger, 3421 const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); 3422 3423 /** 3424 * @} 3425 */ 3426 3427 /** @addtogroup HRTIM_Exported_Functions_Group8 3428 * @{ 3429 */ 3430 /* Waveform related functions *************************************************/ 3431 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, 3432 uint32_t TimerIdx, 3433 const HRTIM_TimerCfgTypeDef *pTimerCfg); 3434 3435 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, 3436 uint32_t TimerIdx, 3437 uint32_t CompareUnit, 3438 const HRTIM_CompareCfgTypeDef *pCompareCfg); 3439 3440 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, 3441 uint32_t TimerIdx, 3442 uint32_t CaptureUnit, 3443 const HRTIM_CaptureCfgTypeDef *pCaptureCfg); 3444 3445 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, 3446 uint32_t TimerIdx, 3447 uint32_t Output, 3448 const HRTIM_OutputCfgTypeDef *pOutputCfg); 3449 3450 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 3451 uint32_t TimerIdx, 3452 uint32_t Output, 3453 uint32_t OutputLevel); 3454 3455 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, 3456 uint32_t TimerIdx, 3457 uint32_t Event, 3458 const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); 3459 3460 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, 3461 uint32_t TimerIdx, 3462 const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); 3463 3464 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, 3465 uint32_t TimerIdx, 3466 const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); 3467 3468 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, 3469 uint32_t TimerIdx, 3470 uint32_t RegistersToUpdate); 3471 3472 3473 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, 3474 uint32_t Timers); 3475 3476 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, 3477 uint32_t Timers); 3478 3479 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, 3480 uint32_t Timers); 3481 3482 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, 3483 uint32_t Timers); 3484 3485 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3486 uint32_t Timers); 3487 3488 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3489 uint32_t Timers); 3490 3491 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, 3492 uint32_t OutputsToStart); 3493 3494 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, 3495 uint32_t OutputsToStop); 3496 3497 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, 3498 uint32_t Enable); 3499 3500 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim); 3501 3502 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, 3503 uint32_t TimerIdx, 3504 uint32_t CaptureUnit); 3505 3506 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, 3507 uint32_t Timers); 3508 3509 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, 3510 uint32_t Timers); 3511 3512 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, 3513 uint32_t TimerIdx, 3514 uint32_t BurstBufferAddress, 3515 uint32_t BurstBufferLength); 3516 3517 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, 3518 uint32_t Timers); 3519 3520 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, 3521 uint32_t Timers); 3522 3523 /** 3524 * @} 3525 */ 3526 3527 /** @addtogroup HRTIM_Exported_Functions_Group9 3528 * @{ 3529 */ 3530 /* HRTIM peripheral state functions */ 3531 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); 3532 3533 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, 3534 uint32_t TimerIdx, 3535 uint32_t CaptureUnit); 3536 3537 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, 3538 uint32_t TimerIdx, 3539 uint32_t Output); 3540 3541 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, 3542 uint32_t TimerIdx, 3543 uint32_t Output); 3544 3545 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, 3546 uint32_t TimerIdx, 3547 uint32_t Output); 3548 3549 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim); 3550 3551 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 3552 uint32_t TimerIdx); 3553 3554 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 3555 uint32_t TimerIdx); 3556 3557 /** 3558 * @} 3559 */ 3560 3561 /** @addtogroup HRTIM_Exported_Functions_Group10 3562 * @{ 3563 */ 3564 /* IRQ handler */ 3565 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, 3566 uint32_t TimerIdx); 3567 3568 /* HRTIM events related callback functions */ 3569 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim); 3570 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim); 3571 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim); 3572 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim); 3573 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim); 3574 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim); 3575 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim); 3576 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); 3577 3578 /* Timer events related callback functions */ 3579 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, 3580 uint32_t TimerIdx); 3581 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, 3582 uint32_t TimerIdx); 3583 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, 3584 uint32_t TimerIdx); 3585 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, 3586 uint32_t TimerIdx); 3587 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, 3588 uint32_t TimerIdx); 3589 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, 3590 uint32_t TimerIdx); 3591 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, 3592 uint32_t TimerIdx); 3593 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, 3594 uint32_t TimerIdx); 3595 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, 3596 uint32_t TimerIdx); 3597 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, 3598 uint32_t TimerIdx); 3599 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, 3600 uint32_t TimerIdx); 3601 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, 3602 uint32_t TimerIdx); 3603 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, 3604 uint32_t TimerIdx); 3605 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, 3606 uint32_t TimerIdx); 3607 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, 3608 uint32_t TimerIdx); 3609 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); 3610 3611 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 3612 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, 3613 HAL_HRTIM_CallbackIDTypeDef CallbackID, 3614 pHRTIM_CallbackTypeDef pCallback); 3615 3616 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 3617 HAL_HRTIM_CallbackIDTypeDef CallbackID); 3618 3619 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 3620 HAL_HRTIM_CallbackIDTypeDef CallbackID, 3621 pHRTIM_TIMxCallbackTypeDef pCallback); 3622 3623 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 3624 HAL_HRTIM_CallbackIDTypeDef CallbackID); 3625 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 3626 3627 /** 3628 * @} 3629 */ 3630 3631 /** 3632 * @} 3633 */ 3634 3635 /** 3636 * @} 3637 */ 3638 3639 /** 3640 * @} 3641 */ 3642 3643 #endif /* HRTIM1 */ 3644 3645 #ifdef __cplusplus 3646 } 3647 #endif 3648 3649 #endif /* STM32H7xx_HAL_HRTIM_H */ 3650
