1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 *
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2019 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file
61 * in the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 *
64 ******************************************************************************
65 @verbatim
66 ==============================================================================
67 ##### Simple mode v.s. waveform mode #####
68 ==============================================================================
69 [..] The HRTIM HAL API is split into 2 categories:
70 (#)Simple functions: these functions allow for using a HRTIM timer as a
71 general purpose timer with high resolution capabilities.
72 HRTIM simple modes are managed through the set of functions named
73 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
74 to the one defined for the TIM peripheral. When a HRTIM timer operates in
75 simple mode, only a very limited set of HRTIM features are used.
76 Following simple modes are proposed:
77 (++)Output compare mode,
78 (++)PWM output mode,
79 (++)Input capture mode,
80 (++)One pulse mode.
81 (#)Waveform functions: These functions allow taking advantage of the HRTIM
82 flexibility to produce numerous types of control signal. When a HRTIM timer
83 operates in waveform mode, all the HRTIM features are accessible without
84 any restriction. HRTIM waveform modes are managed through the set of
85 functions named HAL_HRTIM_Waveform<Function>
86
87 ##### How to use this driver #####
88 ==============================================================================
89 [..]
90 (#)Initialize the HRTIM low level resources by implementing the
91 HAL_HRTIM_MspInit() function:
92 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
93 (##)Connect HRTIM pins to MCU I/Os
94 (+++) Enable the clock for the HRTIM GPIOs using the following
95 function: __HAL_RCC_GPIOx_CLK_ENABLE()
96 (+++) Configure these GPIO pins in Alternate Function mode using
97 HAL_GPIO_Init()
98 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
99 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
100 (+++)Initialize the DMA handle
101 (+++)Associate the initialized DMA handle to the appropriate DMA
102 handle of the HRTIM handle using __HAL_LINKDMA()
103 (+++)Initialize the DMA channel using HAL_DMA_Init()
104 (+++)Configure the priority and enable the NVIC for the transfer
105 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
106 and HAL_NVIC_EnableIRQ()
107 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
108 (+++)Configure the priority and enable the NVIC for the concerned
109 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
110
111 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
112 structure (field of the HRTIM handle) specifies which global interrupt of
113 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
114 It also contains the HRTIM external synchronization configuration. HRTIM
115 can act as a master (generating a synchronization signal) or as a slave
116 (waiting for a trigger to be synchronized).
117
118 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
119 calibration is executed periodically and compensate for potential voltage
120 and temperature drifts. DLL calibration period is specified by the
121 CalibrationRate argument.
122
123 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
124 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
125 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
126 is still going on when timeout given as argument expires. DLL calibration
127 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
128 In that case an interrupt is generated when the DLL calibration is completed.
129 Note that as DLL calibration is executed on a periodic basis an interrupt
130 will be generated at the end of every DLL calibration operation
131 (worst case: one interrupt every 14 micro seconds !).
132
133 (#) Configure HRTIM resources shared by all HRTIM timers
134 (##)Burst Mode Controller:
135 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
136 controller: operating mode (continuous or one-shot mode), clock
137 (source, prescaler) , trigger(s), period, idle duration.
138 (##)External Events Conditioning:
139 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
140 external event channel: source, polarity, edge-sensitivity.
141 External event can be used as triggers (timer reset, input
142 capture, burst mode, ADC triggers, delayed protection)
143 They can also be used to set or reset timer outputs. Up to
144 10 event channels are available.
145 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
146 event sampling clock (used for digital filtering).
147 (##)Fault Conditioning:
148 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
149 fault channel: source, polarity, edge-sensitivity. Fault
150 channels are used to disable the outputs in case of an
151 abnormal operation. Up to 6 fault channels are available.
152 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
153 sampling clock (used for digital filtering).
154 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
155 circuitry. By default all fault inputs are disabled.
156 (##)ADC trigger:
157 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
158 the update of the ADC trigger register and the ADC trigger.
159 4 independent triggers are available to start both the regular
160 and the injected sequencers of the 2 ADCs
161
162 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
163 function must be called whatever the HRTIM timer operating mode is
164 (simple v.s. waveform). It configures mainly:
165 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
166 (##)The HRTIM timer clock prescaler
167 (##)The HRTIM timer period
168 (##)The HRTIM timer repetition counter
169
170 *** If the HRTIM timer operates in simple mode ***
171 ===================================================
172 [..]
173 (#) Start or Stop simple timers
174 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
175 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
176 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
177 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
178 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
179 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
180 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
181 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
182 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
183 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
184 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
185 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
186 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
187 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
188 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
189 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
190 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
191 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
192
193 *** If the HRTIM timer operates in waveform mode ***
194 ====================================================
195 [..]
196 (#) Completes waveform timer configuration
197 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
198 operating in wave form mode mainly consists in:
199 (+++)Enabling the HRTIM timer interrupts and DMA requests.
200 (+++)Enabling the half mode for the HRTIM timer.
201 (+++)Defining how the HRTIM timer reacts to external synchronization input.
202 (+++)Enabling the push-pull mode for the HRTIM timer.
203 (+++)Enabling the fault channels for the HRTIM timer.
204 (+++)Enabling the dead-time insertion for the HRTIM timer.
205 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
206 on which the delayed protection are applied).
207 (+++)Specifying the HRTIM timer update and reset triggers.
208 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
209 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
210 event blanking and windowing circuitry of a HRTIM timer:
211 (+++)Blanking: to mask external events during a defined time period a defined time period
212 (+++)Windowing, to enable external events only during a defined time period
213 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
214 unit for a HRTIM timer. Allows to generate a couple of
215 complementary signals from a single reference waveform,
216 with programmable delays between active state.
217 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
218 the high-frequency carrier signal added on top of the timing
219 unit output. Chopper mode can be enabled or disabled for each
220 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
221 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
222 controller. Allows having multiple HRTIM registers updated
223 with a single DMA request. The burst DMA operation is started
224 by calling HAL_HRTIM_BurstDMATransfer().
225 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
226 of a HRTIM timer. This operation consists in setting the
227 compare value and possibly specifying the auto delayed mode
228 for compare units 2 and 4 (allows to have compare events
229 generated relatively to capture events). Note that when auto
230 delayed mode is needed, the capture unit associated to the
231 compare unit must be configured separately.
232 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
233 of a HRTIM timer. This operation consists in specifying the
234 source(s) triggering the capture (timer register update event,
235 external event, timer output set/reset event, other HRTIM
236 timer related events).
237 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
238 output mainly consists in:
239 (+++)Setting the output polarity (active high or active low),
240 (+++)Defining the set/reset crossbar for the output,
241 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
242
243 (#) Set waveform timer output(s) level
244 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
245 active or inactive level. For example, when deadtime insertion
246 is enabled it is necessary to force the output level by software
247 to have the outputs in a complementary state as soon as the RUN mode is entered.
248
249 (#) Enable or Disable waveform timer output(s)
250 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
251
252 (#) Start or Stop waveform HRTIM timer(s).
253 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
254 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
255 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
256 (#) Burst mode controller enabling:
257 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
258 burst mode controller.
259
260 (#) Some HRTIM operations can be triggered by software:
261 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
262 trigs the burst operation.
263 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
264 capture of the HRTIM timer counter.
265 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
266 update of the pre-loadable registers of the HRTIM timer
267 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
268 HRTIM timer counter.
269
270 (#) Some functions can be used any time to retrieve HRTIM timer related
271 information
272 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
273 capture register of the designated capture unit.
274 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
275 (ACTIVE/INACTIVE) of the designated timer output.
276 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
277 (IDLE/RUN/FAULT) of the designated timer output.
278 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
279 (ACTIVE/INACTIVE) of the designated output when the delayed
280 protection was triggered.
281 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
282 (ACTIVE/INACTIVE) of the burst mode controller.
283 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
284 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
285 the push-pull status indicates on which output the signal is currently
286 active (e.g signal applied on output 1 and output 2 forced
287 inactive or vice versa).
288 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
289 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
290 the idle push-pull status indicates during which period the
291 delayed protection request occurred (e.g. protection occurred
292 when the output 1 was active and output 2 forced inactive or
293 vice versa).
294
295 (#) Some functions can be used any time to retrieve actual HRTIM status
296 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
297
298 *** Callback registration ***
299 =============================
300 [..]
301 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
302 allows the user to configure dynamically the driver callbacks.
303 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
304 to register an interrupt callback.
305
306 [..]
307 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
308 (+) Fault1Callback : Fault 1 interrupt callback function
309 (+) Fault2Callback : Fault 2 interrupt callback function
310 (+) Fault3Callback : Fault 3 interrupt callback function
311 (+) Fault4Callback : Fault 4 interrupt callback function
312 (+) Fault5Callback : Fault 5 interrupt callback function
313 (+) Fault6Callback : Fault 6 interrupt callback function
314 (+) SystemFaultCallback : System fault interrupt callback function
315 (+) DLLCalibrationReadyCallback : DLL Ready interrupt callback function
316 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
317 (+) SynchronizationEventCallback : Sync Input interrupt callback function
318 (+) ErrorCallback : DMA error callback function
319 (+) MspInitCallback : HRTIM MspInit callback function
320 (+) MspDeInitCallback : HRTIM MspInit callback function
321
322 [..]
323 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
324 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
325 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
326 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
327 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
328 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
329 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
330 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
331 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
332 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
333 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
334 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
335 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
336 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
337 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
338 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
339
340 [..]
341 Both functions take as parameters the HAL peripheral handle, the Callback ID
342 and a pointer to the user callback function.
343
344 [..]
345 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
346 to reset a callback to the default weak function. Both functions take as parameters
347 the HAL peripheral handle and the Callback ID.
348
349 [..]
350 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
351 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
352 Exception done for MspInit and MspDeInit functions that are reset to the legacy
353 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
354 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
355 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
356 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
357
358 [..]
359 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
360 Exception done MspInit/MspDeInit functions that can be registered/unregistered
361 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
362 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
363 Then, the user first registers the MspInit/MspDeInit user callbacks
364 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
365 or HAL_HRTIM_Init() function.
366
367 [..]
368 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
369 not defined, the callback registration feature is not available and all
370 callbacks are set to the corresponding weak functions.
371
372 @endverbatim
373 ******************************************************************************
374 */
375
376 /* Includes ------------------------------------------------------------------*/
377 #include "stm32g4xx_hal.h"
378
379 /** @addtogroup STM32G4xx_HAL_Driver
380 * @{
381 */
382
383 #ifdef HAL_HRTIM_MODULE_ENABLED
384
385 #if defined(HRTIM1)
386
387 /** @defgroup HRTIM HRTIM
388 * @brief HRTIM HAL module driver
389 * @{
390 */
391
392 /* Private typedef -----------------------------------------------------------*/
393 /* Private define ------------------------------------------------------------*/
394 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
395 * @{
396 */
397 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
398 HRTIM_FLTR_FLT2EN |\
399 HRTIM_FLTR_FLT3EN |\
400 HRTIM_FLTR_FLT4EN | \
401 HRTIM_FLTR_FLT5EN | \
402 HRTIM_FLTR_FLT6EN)
403
404 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
405 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
406 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
407 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
408 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
409 HRTIM_TIMUPDATETRIGGER_TIMER_E |\
410 HRTIM_TIMUPDATETRIGGER_TIMER_F)
411
412 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
413 (HRTIM_FAULTLOCK_READONLY << 8U) | \
414 (HRTIM_FAULTLOCK_READONLY << 16U) | \
415 (HRTIM_FAULTLOCK_READONLY << 24U))
416
417 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
418 (HRTIM_FAULTLOCK_READONLY << 8U))
419 /**
420 * @}
421 */
422
423 /* Private macro -------------------------------------------------------------*/
424 /* Private variables ---------------------------------------------------------*/
425 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
426 * @{
427 */
428 static uint32_t TimerIdxToTimerId[] =
429 {
430 HRTIM_TIMERID_TIMER_A,
431 HRTIM_TIMERID_TIMER_B,
432 HRTIM_TIMERID_TIMER_C,
433 HRTIM_TIMERID_TIMER_D,
434 HRTIM_TIMERID_TIMER_E,
435 HRTIM_TIMERID_TIMER_F,
436 HRTIM_TIMERID_MASTER,
437 };
438 /**
439 * @}
440 */
441
442 /* Private function prototypes -----------------------------------------------*/
443 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
444 * @{
445 */
446 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
447 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
448
449 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
450 uint32_t TimerIdx,
451 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
452
453 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
454 const HRTIM_TimerCfgTypeDef *pTimerCfg);
455
456 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
457 uint32_t TimerIdx,
458 const HRTIM_TimerCfgTypeDef *pTimerCfg);
459
460 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim,
461 uint32_t TimerIdx,
462 const HRTIM_TimerCtlTypeDef *pTimerCtl);
463
464 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim,
465 uint32_t TimerIdx,
466 uint32_t pRollOverMode);
467
468
469 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
470 uint32_t TimerIdx,
471 uint32_t CaptureUnit,
472 uint32_t Event);
473
474 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
475 uint32_t TimerIdx,
476 uint32_t Output,
477 const HRTIM_OutputCfgTypeDef *pOutputCfg);
478
479 static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
480 uint32_t Event,
481 const HRTIM_EventCfgTypeDef *pEventCfg);
482
483 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
484 uint32_t TimerIdx,
485 uint32_t Event);
486
487 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
488 uint32_t TimerIdx,
489 uint32_t OCChannel);
490
491 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
492 uint32_t TimerIdx,
493 uint32_t OCChannel);
494
495 static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
496 uint32_t TimerIdx);
497
498 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
499 const DMA_HandleTypeDef *hdma);
500
501 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
502 uint32_t TimerIdx);
503
504 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim);
505
506 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim);
507
508 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
509 uint32_t TimerIdx);
510
511 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
512
513 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
514
515 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
516
517 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
518 /**
519 * @}
520 */
521
522 /* Exported functions ---------------------------------------------------------*/
523 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
524 * @{
525 */
526
527 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
528 * @brief Initialization and Configuration functions
529 @verbatim
530 ===============================================================================
531 ##### Initialization and Time Base Configuration functions #####
532 ===============================================================================
533 [..] This section provides functions allowing to:
534 (+) Initialize a HRTIM instance
535 (+) De-initialize a HRTIM instance
536 (+) Initialize the HRTIM MSP
537 (+) De-initialize the HRTIM MSP
538 (+) Start the high-resolution unit (start DLL calibration)
539 (+) Check that the high resolution unit is ready (DLL calibration done)
540 (+) Configure the time base unit of a HRTIM timer
541
542 @endverbatim
543 * @{
544 */
545
546 /**
547 * @brief Initialize a HRTIM instance
548 * @param hhrtim pointer to HAL HRTIM handle
549 * @retval HAL status
550 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)551 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim)
552 {
553 uint8_t timer_idx;
554 uint32_t hrtim_mcr;
555
556 /* Check the HRTIM handle allocation */
557 if (hhrtim == NULL)
558 {
559 return HAL_ERROR;
560 }
561
562 /* Check the parameters */
563 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
564 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests));
565
566 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
567 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
568 {
569 /* Initialize callback function pointers to their default values */
570 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
571 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
572 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
573 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
574 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
575 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
576 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
577 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
578 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
579 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
580 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
581 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
582 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
583 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
584 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
585 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
586 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
587 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
588 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
589 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
590 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
591 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
592 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
593 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
594 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
595 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
596
597 if (hhrtim->MspInitCallback == NULL)
598 {
599 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
600 }
601 }
602 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
603
604 /* Set the HRTIM state */
605 hhrtim->State = HAL_HRTIM_STATE_BUSY;
606
607 /* Initialize the DMA handles */
608 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
609 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
610 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
611 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
612 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
613 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
614 hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
615
616 /* HRTIM output synchronization configuration (if required) */
617 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
618 {
619 /* Check parameters */
620 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
621 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
622
623 /* The synchronization output initialization procedure must be done prior
624 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
625 */
626 if (hhrtim->Instance == HRTIM1)
627 {
628 /* Enable the HRTIM peripheral clock */
629 __HAL_RCC_HRTIM1_CLK_ENABLE();
630 }
631
632 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
633
634 /* Set the event to be sent on the synchronization output */
635 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
636 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
637
638 /* Set the polarity of the synchronization output */
639 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
640 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
641
642 /* Update the HRTIM registers */
643 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
644 }
645
646 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
647 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
648 hhrtim->MspInitCallback(hhrtim);
649 #else
650 HAL_HRTIM_MspInit(hhrtim);
651 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
652
653 /* HRTIM input synchronization configuration (if required) */
654 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
655 {
656 /* Check parameters */
657 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
658
659 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
660
661 /* Set the synchronization input source */
662 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
663 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
664
665 /* Update the HRTIM registers */
666 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
667 }
668
669 /* Initialize the HRTIM state*/
670 hhrtim->State = HAL_HRTIM_STATE_READY;
671
672 /* Initialize the lock status of the HRTIM HAL API */
673 __HAL_UNLOCK(hhrtim);
674
675 /* Initialize timer related parameters */
676 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
677 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
678 timer_idx++)
679 {
680 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
681 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
682 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
683 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
684 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
685 hhrtim->TimerParam[timer_idx].DMASize = 0U;
686 }
687
688 return HAL_OK;
689 }
690
691 /**
692 * @brief De-initialize a HRTIM instance
693 * @param hhrtim pointer to HAL HRTIM handle
694 * @retval HAL status
695 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)696 HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim)
697 {
698 /* Check the HRTIM handle allocation */
699 if (hhrtim == NULL)
700 {
701 return HAL_ERROR;
702 }
703
704 /* Check the parameters */
705 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
706
707 /* Set the HRTIM state */
708 hhrtim->State = HAL_HRTIM_STATE_BUSY;
709
710 /* DeInit the low level hardware */
711 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
712 if (hhrtim->MspDeInitCallback == NULL)
713 {
714 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
715 }
716
717 hhrtim->MspDeInitCallback(hhrtim);
718 #else
719 HAL_HRTIM_MspDeInit(hhrtim);
720 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
721
722 hhrtim->State = HAL_HRTIM_STATE_READY;
723
724 return HAL_OK;
725 }
726
727 /**
728 * @brief MSP initialization for a HRTIM instance
729 * @param hhrtim pointer to HAL HRTIM handle
730 * @retval None
731 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)732 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim)
733 {
734 /* Prevent unused argument(s) compilation warning */
735 UNUSED(hhrtim);
736
737 /* NOTE: This function should not be modified, when the callback is needed,
738 the HAL_HRTIM_MspInit could be implemented in the user file
739 */
740 }
741
742 /**
743 * @brief MSP de-initialization of a HRTIM instance
744 * @param hhrtim pointer to HAL HRTIM handle
745 * @retval None
746 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)747 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim)
748 {
749 /* Prevent unused argument(s) compilation warning */
750 UNUSED(hhrtim);
751
752 /* NOTE: This function should not be modified, when the callback is needed,
753 the HAL_HRTIM_MspDeInit could be implemented in the user file
754 */
755 }
756
757 /**
758 * @brief Start the DLL calibration
759 * @param hhrtim pointer to HAL HRTIM handle
760 * @param CalibrationRate DLL calibration period
761 * This parameter can be one of the following values:
762 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
763 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
764 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
765 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
766 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
767 * @retval HAL status
768 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
769 * within the HAL_HRTIM_PollForDLLCalibration function, just before
770 * exiting the function.
771 */
HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)772 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
773 uint32_t CalibrationRate)
774 {
775 /* Check the parameters */
776 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
777
778 /* Process Locked */
779 __HAL_LOCK(hhrtim);
780
781 hhrtim->State = HAL_HRTIM_STATE_BUSY;
782
783 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
784 {
785 /* One shot DLL calibration */
786 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
787 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
788 }
789 else
790 {
791 /* Periodic DLL calibration */
792 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
793 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
794 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
795 }
796
797 /* Set HRTIM state */
798 hhrtim->State = HAL_HRTIM_STATE_READY;
799
800 return HAL_OK;
801 }
802
803 /**
804 * @brief Start the DLL calibration.
805 * DLL ready interrupt is enabled
806 * @param hhrtim pointer to HAL HRTIM handle
807 * @param CalibrationRate DLL calibration period
808 * This parameter can be one of the following values:
809 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
810 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
811 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
812 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
813 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
814 * @retval HAL status
815 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
816 * within the IRQ processing function when processing the DLL ready
817 * interrupt.
818 * @note If this function is called for periodic calibration, the DLLRDY
819 * interrupt is generated every time the calibration completes which
820 * will significantly increases the overall interrupt rate.
821 */
HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)822 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
823 uint32_t CalibrationRate)
824 {
825 /* Check the parameters */
826 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
827
828 /* Process Locked */
829 __HAL_LOCK(hhrtim);
830
831 hhrtim->State = HAL_HRTIM_STATE_BUSY;
832
833 /* Enable DLL Ready interrupt flag */
834 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
835
836 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
837 {
838 /* One shot DLL calibration */
839 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
840 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
841 }
842 else
843 {
844 /* Periodic DLL calibration */
845 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
846 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
847 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
848 }
849
850 /* Set HRTIM state */
851 hhrtim->State = HAL_HRTIM_STATE_READY;
852
853 return HAL_OK;
854 }
855
856 /**
857 * @brief Poll the DLL calibration ready flag and returns when the flag is
858 * set (DLL calibration completed) or upon timeout expiration.
859 * @param hhrtim pointer to HAL HRTIM handle
860 * @param Timeout Timeout duration in millisecond
861 * @retval HAL status
862 */
HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,uint32_t Timeout)863 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
864 uint32_t Timeout)
865 {
866 uint32_t tickstart;
867
868 tickstart = HAL_GetTick();
869
870 /* Check End of conversion flag */
871 while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
872 {
873 if (Timeout != HAL_MAX_DELAY)
874 {
875 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
876 {
877 hhrtim->State = HAL_HRTIM_STATE_ERROR;
878 return HAL_TIMEOUT;
879 }
880 }
881 }
882
883 /* Set HRTIM State */
884 hhrtim->State = HAL_HRTIM_STATE_READY;
885
886 /* Process unlocked */
887 __HAL_UNLOCK(hhrtim);
888
889 return HAL_OK;
890 }
891
892 /**
893 * @brief Configure the time base unit of a timer
894 * @param hhrtim pointer to HAL HRTIM handle
895 * @param TimerIdx Timer index
896 * This parameter can be one of the following values:
897 * @arg HRTIM_TIMERINDEX_MASTER for master timer
898 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
899 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
900 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
901 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
902 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
903 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
904 * @param pTimeBaseCfg pointer to the time base configuration structure
905 * @note This function must be called prior starting the timer
906 * @note The time-base unit initialization parameters specify:
907 * The timer counter operating mode (continuous, one shot),
908 * The timer clock prescaler,
909 * The timer period,
910 * The timer repetition counter.
911 * @retval HAL status
912 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)913 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
914 uint32_t TimerIdx,
915 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
916 {
917 /* Check the parameters */
918 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
919 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
920 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
921
922 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
923 {
924 return HAL_BUSY;
925 }
926
927 /* Set the HRTIM state */
928 hhrtim->State = HAL_HRTIM_STATE_BUSY;
929
930 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
931 {
932 /* Configure master timer time base unit */
933 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
934 }
935 else
936 {
937 /* Configure timing unit time base unit */
938 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
939 }
940
941 /* Set HRTIM state */
942 hhrtim->State = HAL_HRTIM_STATE_READY;
943
944 return HAL_OK;
945 }
946
947 /**
948 * @}
949 */
950
951 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
952 * @brief Simple time base mode functions.
953 @verbatim
954 ===============================================================================
955 ##### Simple time base mode functions #####
956 ===============================================================================
957 [..] This section provides functions allowing to:
958 (+) Start simple time base
959 (+) Stop simple time base
960 (+) Start simple time base and enable interrupt
961 (+) Stop simple time base and disable interrupt
962 (+) Start simple time base and enable DMA transfer
963 (+) Stop simple time base and disable DMA transfer
964 -@- When a HRTIM timer operates in simple time base mode, the timer
965 counter counts from 0 to the period value.
966
967 @endverbatim
968 * @{
969 */
970
971 /**
972 * @brief Start the counter of a timer operating in simple time base mode.
973 * @param hhrtim pointer to HAL HRTIM handle
974 * @param TimerIdx Timer index.
975 * This parameter can be one of the following values:
976 * @arg HRTIM_TIMERINDEX_MASTER for master timer
977 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
978 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
979 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
980 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
981 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
982 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
983 * @retval HAL status
984 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)985 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
986 uint32_t TimerIdx)
987 {
988 /* Check the parameters */
989 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
990
991 /* Process Locked */
992 __HAL_LOCK(hhrtim);
993
994 hhrtim->State = HAL_HRTIM_STATE_BUSY;
995
996 /* Enable the timer counter */
997 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
998
999 hhrtim->State = HAL_HRTIM_STATE_READY;
1000
1001 /* Process Unlocked */
1002 __HAL_UNLOCK(hhrtim);
1003
1004 return HAL_OK;
1005 }
1006
1007 /**
1008 * @brief Stop the counter of a timer operating in simple time base mode.
1009 * @param hhrtim pointer to HAL HRTIM handle
1010 * @param TimerIdx Timer index.
1011 * This parameter can be one of the following values:
1012 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1013 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1014 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1015 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1016 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1017 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1018 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1019 * @retval HAL status
1020 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1021 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
1022 uint32_t TimerIdx)
1023 {
1024 /* Check the parameters */
1025 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1026
1027 /* Process Locked */
1028 __HAL_LOCK(hhrtim);
1029
1030 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1031
1032 /* Disable the timer counter */
1033 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1034
1035 hhrtim->State = HAL_HRTIM_STATE_READY;
1036
1037 /* Process Unlocked */
1038 __HAL_UNLOCK(hhrtim);
1039
1040 return HAL_OK;
1041 }
1042
1043 /**
1044 * @brief Start the counter of a timer operating in simple time base mode
1045 * (Timer repetition interrupt is enabled).
1046 * @param hhrtim pointer to HAL HRTIM handle
1047 * @param TimerIdx Timer index.
1048 * This parameter can be one of the following values:
1049 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1050 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1051 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1052 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1053 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1054 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1055 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1056 * @retval HAL status
1057 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1058 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
1059 uint32_t TimerIdx)
1060 {
1061 /* Check the parameters */
1062 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1063
1064 /* Process Locked */
1065 __HAL_LOCK(hhrtim);
1066
1067 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1068
1069 /* Enable the repetition interrupt */
1070 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1071 {
1072 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1073 }
1074 else
1075 {
1076 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1077 }
1078
1079 /* Enable the timer counter */
1080 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1081
1082 hhrtim->State = HAL_HRTIM_STATE_READY;
1083
1084 /* Process Unlocked */
1085 __HAL_UNLOCK(hhrtim);
1086
1087 return HAL_OK;
1088 }
1089
1090 /**
1091 * @brief Stop the counter of a timer operating in simple time base mode
1092 * (Timer repetition interrupt is disabled).
1093 * @param hhrtim pointer to HAL HRTIM handle
1094 * @param TimerIdx Timer index.
1095 * This parameter can be one of the following values:
1096 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1097 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1098 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1099 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1100 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1101 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1102 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1103 * @retval HAL status
1104 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1105 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
1106 uint32_t TimerIdx)
1107 {
1108 /* Check the parameters */
1109 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1110
1111 /* Process Locked */
1112 __HAL_LOCK(hhrtim);
1113
1114 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1115
1116 /* Disable the repetition interrupt */
1117 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1118 {
1119 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1120 }
1121 else
1122 {
1123 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1124 }
1125
1126 /* Disable the timer counter */
1127 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1128
1129 hhrtim->State = HAL_HRTIM_STATE_READY;
1130
1131 /* Process Unlocked */
1132 __HAL_UNLOCK(hhrtim);
1133
1134 return HAL_OK;
1135 }
1136
1137 /**
1138 * @brief Start the counter of a timer operating in simple time base mode
1139 * (Timer repetition DMA request is enabled).
1140 * @param hhrtim pointer to HAL HRTIM handle
1141 * @param TimerIdx Timer index.
1142 * This parameter can be one of the following values:
1143 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1144 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1145 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1146 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1147 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1148 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1149 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1150 * @param SrcAddr DMA transfer source address
1151 * @param DestAddr DMA transfer destination address
1152 * @param Length The length of data items (data size) to be transferred
1153 * from source to destination
1154 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1155 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
1156 uint32_t TimerIdx,
1157 uint32_t SrcAddr,
1158 uint32_t DestAddr,
1159 uint32_t Length)
1160 {
1161 DMA_HandleTypeDef *hdma;
1162
1163 /* Check the parameters */
1164 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1165
1166 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1167 {
1168 return HAL_BUSY;
1169 }
1170 if (hhrtim->State == HAL_HRTIM_STATE_READY)
1171 {
1172 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
1173 {
1174 return HAL_ERROR;
1175 }
1176 else
1177 {
1178 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1179 }
1180 }
1181
1182 /* Process Locked */
1183 __HAL_LOCK(hhrtim);
1184
1185 /* Get the timer DMA handler */
1186 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1187
1188 if (hdma == NULL)
1189 {
1190 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1191
1192 /* Process Unlocked */
1193 __HAL_UNLOCK(hhrtim);
1194
1195 return HAL_ERROR;
1196 }
1197
1198 /* Set the DMA transfer completed callback */
1199 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1200 {
1201 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1202 }
1203 else
1204 {
1205 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1206 }
1207
1208 /* Set the DMA error callback */
1209 hdma->XferErrorCallback = HRTIM_DMAError ;
1210
1211 /* Enable the DMA channel */
1212 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1213 {
1214 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1215
1216 /* Process Unlocked */
1217 __HAL_UNLOCK(hhrtim);
1218
1219 return HAL_ERROR;
1220 }
1221
1222 /* Enable the timer repetition DMA request */
1223 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1224 {
1225 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1226 }
1227 else
1228 {
1229 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1230 }
1231
1232 /* Enable the timer counter */
1233 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1234
1235 hhrtim->State = HAL_HRTIM_STATE_READY;
1236
1237 /* Process Unlocked */
1238 __HAL_UNLOCK(hhrtim);
1239
1240 return HAL_OK;
1241 }
1242
1243 /**
1244 * @brief Stop the counter of a timer operating in simple time base mode
1245 * (Timer repetition DMA request is disabled).
1246 * @param hhrtim pointer to HAL HRTIM handle
1247 * @param TimerIdx Timer index.
1248 * This parameter can be one of the following values:
1249 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1250 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1251 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1252 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1253 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1254 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1255 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1256 * @retval HAL status
1257 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1258 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
1259 uint32_t TimerIdx)
1260 {
1261 DMA_HandleTypeDef *hdma;
1262
1263 /* Check the parameters */
1264 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1265
1266 /* Process Locked */
1267 __HAL_LOCK(hhrtim);
1268
1269 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1270 {
1271 hhrtim->State = HAL_HRTIM_STATE_READY;
1272
1273 /* Disable the DMA */
1274 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1275 {
1276 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1277 }
1278 /* Disable the timer repetition DMA request */
1279 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1280 }
1281 else
1282 {
1283 /* Get the timer DMA handler */
1284 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1285
1286 if (hdma == NULL)
1287 {
1288 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1289 }
1290 else
1291 {
1292 hhrtim->State = HAL_HRTIM_STATE_READY;
1293
1294 /* Disable the DMA */
1295 if (HAL_DMA_Abort(hdma) != HAL_OK)
1296 {
1297 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1298 }
1299
1300 /* Disable the timer repetition DMA request */
1301 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1302 }
1303 }
1304
1305 /* Disable the timer counter */
1306 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1307
1308 /* Process Unlocked */
1309 __HAL_UNLOCK(hhrtim);
1310
1311 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1312 {
1313 return HAL_ERROR;
1314 }
1315 else
1316 {
1317 return HAL_OK;
1318 }
1319 }
1320
1321 /**
1322 * @}
1323 */
1324
1325 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1326 * @brief Simple output compare functions
1327 @verbatim
1328 ===============================================================================
1329 ##### Simple output compare functions #####
1330 ===============================================================================
1331 [..] This section provides functions allowing to:
1332 (+) Configure simple output channel
1333 (+) Start simple output compare
1334 (+) Stop simple output compare
1335 (+) Start simple output compare and enable interrupt
1336 (+) Stop simple output compare and disable interrupt
1337 (+) Start simple output compare and enable DMA transfer
1338 (+) Stop simple output compare and disable DMA transfer
1339 -@- When a HRTIM timer operates in simple output compare mode
1340 the output level is set to a programmable value when a match
1341 is found between the compare register and the counter.
1342 Compare unit 1 is automatically associated to output 1
1343 Compare unit 2 is automatically associated to output 2
1344 @endverbatim
1345 * @{
1346 */
1347
1348 /**
1349 * @brief Configure an output in simple output compare mode
1350 * @param hhrtim pointer to HAL HRTIM handle
1351 * @param TimerIdx Timer index
1352 * This parameter can be one of the following values:
1353 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1354 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1355 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1356 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1357 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1358 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1359 * @param OCChannel Timer output
1360 * This parameter can be one of the following values:
1361 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1362 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1363 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1364 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1365 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1366 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1367 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1368 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1369 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1370 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1371 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1372 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1373 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1374 * @note When the timer operates in simple output compare mode:
1375 * Output 1 is implicitly controlled by the compare unit 1
1376 * Output 2 is implicitly controlled by the compare unit 2
1377 * Output Set/Reset crossbar is set according to the selected output compare mode:
1378 * Toggle: SETxyR = RSTxyR = CMPy
1379 * Active: SETxyR = CMPy, RSTxyR = 0
1380 * Inactive: SETxy =0, RSTxy = CMPy
1381 * @retval HAL status
1382 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,const HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1383 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
1384 uint32_t TimerIdx,
1385 uint32_t OCChannel,
1386 const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
1387 {
1388 uint32_t CompareUnit = (uint32_t)RESET;
1389 HRTIM_OutputCfgTypeDef OutputCfg;
1390
1391 /* Check parameters */
1392 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1393 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1394 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1395 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1396 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1397
1398 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1399 {
1400 return HAL_BUSY;
1401 }
1402
1403 /* Process Locked */
1404 __HAL_LOCK(hhrtim);
1405
1406 /* Set HRTIM state */
1407 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1408
1409 /* Configure timer compare unit */
1410 switch (OCChannel)
1411 {
1412 case HRTIM_OUTPUT_TA1:
1413 case HRTIM_OUTPUT_TB1:
1414 case HRTIM_OUTPUT_TC1:
1415 case HRTIM_OUTPUT_TD1:
1416 case HRTIM_OUTPUT_TE1:
1417 case HRTIM_OUTPUT_TF1:
1418 {
1419 CompareUnit = HRTIM_COMPAREUNIT_1;
1420 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1421 break;
1422 }
1423 case HRTIM_OUTPUT_TA2:
1424 case HRTIM_OUTPUT_TB2:
1425 case HRTIM_OUTPUT_TC2:
1426 case HRTIM_OUTPUT_TD2:
1427 case HRTIM_OUTPUT_TE2:
1428 case HRTIM_OUTPUT_TF2:
1429 {
1430 CompareUnit = HRTIM_COMPAREUNIT_2;
1431 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1432 break;
1433 }
1434 default:
1435 {
1436 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1437
1438 /* Process Unlocked */
1439 __HAL_UNLOCK(hhrtim);
1440
1441 break;
1442 }
1443 }
1444
1445 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1446 {
1447 return HAL_ERROR;
1448 }
1449
1450 /* Configure timer output */
1451 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1452 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1453 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1454 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1455 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1456 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1457
1458 switch (pSimpleOCChannelCfg->Mode)
1459 {
1460 case HRTIM_BASICOCMODE_TOGGLE:
1461 {
1462 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1463 {
1464 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1465 }
1466 else
1467 {
1468 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1469 }
1470 OutputCfg.ResetSource = OutputCfg.SetSource;
1471 break;
1472 }
1473
1474 case HRTIM_BASICOCMODE_ACTIVE:
1475 {
1476 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1477 {
1478 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1479 }
1480 else
1481 {
1482 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1483 }
1484 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1485 break;
1486 }
1487
1488 case HRTIM_BASICOCMODE_INACTIVE:
1489 {
1490 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1491 {
1492 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1493 }
1494 else
1495 {
1496 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1497 }
1498 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1499 break;
1500 }
1501
1502 default:
1503 {
1504 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1505 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1506
1507 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1508
1509 /* Process Unlocked */
1510 __HAL_UNLOCK(hhrtim);
1511
1512 break;
1513 }
1514 }
1515
1516 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1517 {
1518 return HAL_ERROR;
1519 }
1520
1521 HRTIM_OutputConfig(hhrtim,
1522 TimerIdx,
1523 OCChannel,
1524 &OutputCfg);
1525
1526 /* Set HRTIM state */
1527 hhrtim->State = HAL_HRTIM_STATE_READY;
1528
1529 /* Process Unlocked */
1530 __HAL_UNLOCK(hhrtim);
1531
1532 return HAL_OK;
1533 }
1534
1535 /**
1536 * @brief Start the output compare signal generation on the designed timer output
1537 * @param hhrtim pointer to HAL HRTIM handle
1538 * @param TimerIdx Timer index
1539 * This parameter can be one of the following values:
1540 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1541 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1542 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1543 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1544 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1545 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1546 * @param OCChannel Timer output
1547 * This parameter can be one of the following values:
1548 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1549 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1550 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1551 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1552 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1553 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1554 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1555 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1556 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1557 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1558 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1559 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1560 * @retval HAL status
1561 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1562 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
1563 uint32_t TimerIdx,
1564 uint32_t OCChannel)
1565 {
1566 /* Check the parameters */
1567 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1568
1569 /* Process Locked */
1570 __HAL_LOCK(hhrtim);
1571
1572 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1573
1574 /* Enable the timer output */
1575 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1576
1577 /* Enable the timer counter */
1578 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1579
1580 hhrtim->State = HAL_HRTIM_STATE_READY;
1581
1582 /* Process Unlocked */
1583 __HAL_UNLOCK(hhrtim);
1584
1585 return HAL_OK;
1586 }
1587
1588 /**
1589 * @brief Stop the output compare signal generation on the designed timer output
1590 * @param hhrtim pointer to HAL HRTIM handle
1591 * @param TimerIdx Timer index
1592 * This parameter can be one of the following values:
1593 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1594 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1595 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1596 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1597 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1598 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1599 * @param OCChannel Timer output
1600 * This parameter can be one of the following values:
1601 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1602 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1603 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1604 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1605 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1606 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1607 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1608 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1609 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1610 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1611 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1612 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1613 * @retval HAL status
1614 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1615 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
1616 uint32_t TimerIdx,
1617 uint32_t OCChannel)
1618 {
1619 /* Check the parameters */
1620 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1621
1622 /* Process Locked */
1623 __HAL_LOCK(hhrtim);
1624
1625 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1626
1627 /* Disable the timer output */
1628 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1629
1630 /* Disable the timer counter */
1631 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1632
1633 hhrtim->State = HAL_HRTIM_STATE_READY;
1634
1635 /* Process Unlocked */
1636 __HAL_UNLOCK(hhrtim);
1637
1638 return HAL_OK;
1639 }
1640
1641 /**
1642 * @brief Start the output compare signal generation on the designed timer output
1643 * (Interrupt is enabled (see note note below)).
1644 * @param hhrtim pointer to HAL HRTIM handle
1645 * @param TimerIdx Timer index
1646 * This parameter can be one of the following values:
1647 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1648 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1649 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1650 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1651 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1652 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1653 * @param OCChannel Timer output
1654 * This parameter can be one of the following values:
1655 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1656 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1657 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1658 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1659 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1660 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1661 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1662 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1663 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1664 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1665 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1666 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1667 * @note Interrupt enabling depends on the chosen output compare mode
1668 * Output toggle: compare match interrupt is enabled
1669 * Output set active: output set interrupt is enabled
1670 * Output set inactive: output reset interrupt is enabled
1671 * @retval HAL status
1672 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1673 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
1674 uint32_t TimerIdx,
1675 uint32_t OCChannel)
1676 {
1677 uint32_t interrupt;
1678
1679 /* Check the parameters */
1680 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1681
1682 /* Process Locked */
1683 __HAL_LOCK(hhrtim);
1684
1685 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1686
1687 /* Get the interrupt to enable (depends on the output compare mode) */
1688 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1689
1690 /* Enable the timer output */
1691 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1692
1693 /* Enable the timer interrupt (depends on the output compare mode) */
1694 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1695
1696 /* Enable the timer counter */
1697 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1698
1699 hhrtim->State = HAL_HRTIM_STATE_READY;
1700
1701 /* Process Unlocked */
1702 __HAL_UNLOCK(hhrtim);
1703
1704 return HAL_OK;
1705 }
1706
1707 /**
1708 * @brief Stop the output compare signal generation on the designed timer output
1709 * (Interrupt is disabled).
1710 * @param hhrtim pointer to HAL HRTIM handle
1711 * @param TimerIdx Timer index
1712 * This parameter can be one of the following values:
1713 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1714 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1715 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1716 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1717 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1718 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1719 * @param OCChannel Timer output
1720 * This parameter can be one of the following values:
1721 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1722 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1723 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1724 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1725 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1726 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1727 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1728 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1729 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1730 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1731 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1732 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1733 * @retval HAL status
1734 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1735 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
1736 uint32_t TimerIdx,
1737 uint32_t OCChannel)
1738 {
1739 uint32_t interrupt;
1740
1741 /* Check the parameters */
1742 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1743
1744 /* Process Locked */
1745 __HAL_LOCK(hhrtim);
1746
1747 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1748
1749 /* Disable the timer output */
1750 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1751
1752 /* Get the interrupt to disable (depends on the output compare mode) */
1753 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1754
1755 /* Disable the timer interrupt */
1756 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1757
1758 /* Disable the timer counter */
1759 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1760
1761 hhrtim->State = HAL_HRTIM_STATE_READY;
1762
1763 /* Process Unlocked */
1764 __HAL_UNLOCK(hhrtim);
1765
1766 return HAL_OK;
1767 }
1768
1769 /**
1770 * @brief Start the output compare signal generation on the designed timer output
1771 * (DMA request is enabled (see note below)).
1772 * @param hhrtim pointer to HAL HRTIM handle
1773 * @param TimerIdx Timer index
1774 * This parameter can be one of the following values:
1775 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1776 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1777 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1778 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1779 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1780 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1781 * @param OCChannel Timer output
1782 * This parameter can be one of the following values:
1783 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1784 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1785 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1786 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1787 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1788 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1789 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1790 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1791 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1792 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1793 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1794 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1795 * @param SrcAddr DMA transfer source address
1796 * @param DestAddr DMA transfer destination address
1797 * @param Length The length of data items (data size) to be transferred
1798 * from source to destination
1799 * @note DMA request enabling depends on the chosen output compare mode
1800 * Output toggle: compare match DMA request is enabled
1801 * Output set active: output set DMA request is enabled
1802 * Output set inactive: output reset DMA request is enabled
1803 * @retval HAL status
1804 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1805 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
1806 uint32_t TimerIdx,
1807 uint32_t OCChannel,
1808 uint32_t SrcAddr,
1809 uint32_t DestAddr,
1810 uint32_t Length)
1811 {
1812 DMA_HandleTypeDef *hdma;
1813 uint32_t dma_request;
1814
1815 /* Check the parameters */
1816 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1817
1818 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
1819 {
1820 return HAL_BUSY;
1821 }
1822 if (hhrtim->State == HAL_HRTIM_STATE_READY)
1823 {
1824 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
1825 {
1826 return HAL_ERROR;
1827 }
1828 else
1829 {
1830 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1831 }
1832 }
1833
1834 /* Process Locked */
1835 __HAL_LOCK(hhrtim);
1836
1837 /* Enable the timer output */
1838 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1839
1840 /* Get the DMA request to enable */
1841 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1842
1843 /* Get the timer DMA handler */
1844 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1845
1846 if (hdma == NULL)
1847 {
1848 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1849
1850 /* Process Unlocked */
1851 __HAL_UNLOCK(hhrtim);
1852
1853 return HAL_ERROR;
1854 }
1855
1856 /* Set the DMA error callback */
1857 hdma->XferErrorCallback = HRTIM_DMAError ;
1858
1859 /* Set the DMA transfer completed callback */
1860 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1861
1862 /* Enable the DMA channel */
1863 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1864 {
1865 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1866
1867 /* Process Unlocked */
1868 __HAL_UNLOCK(hhrtim);
1869
1870 return HAL_ERROR;
1871 }
1872
1873 /* Enable the timer DMA request */
1874 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1875
1876 /* Enable the timer counter */
1877 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1878
1879 hhrtim->State = HAL_HRTIM_STATE_READY;
1880
1881 /* Process Unlocked */
1882 __HAL_UNLOCK(hhrtim);
1883
1884 return HAL_OK;
1885 }
1886
1887 /**
1888 * @brief Stop the output compare signal generation on the designed timer output
1889 * (DMA request is disabled).
1890 * @param hhrtim pointer to HAL HRTIM handle
1891 * @param TimerIdx Timer index
1892 * This parameter can be one of the following values:
1893 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1894 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1895 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1896 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1897 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1898 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1899 * @param OCChannel Timer output
1900 * This parameter can be one of the following values:
1901 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1902 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1903 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1904 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1905 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1906 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1907 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1908 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1909 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1910 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1911 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1912 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1913 * @retval HAL status
1914 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1915 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
1916 uint32_t TimerIdx,
1917 uint32_t OCChannel)
1918 {
1919 uint32_t dma_request;
1920
1921 /* Check the parameters */
1922 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1923
1924 /* Process Locked */
1925 __HAL_LOCK(hhrtim);
1926
1927 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1928
1929 /* Disable the timer output */
1930 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1931
1932 /* Get the timer DMA handler */
1933 /* Disable the DMA */
1934 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1935 {
1936 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1937
1938 /* Process Unlocked */
1939 __HAL_UNLOCK(hhrtim);
1940
1941 return HAL_ERROR;
1942 }
1943
1944 /* Get the DMA request to disable */
1945 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1946
1947 /* Disable the timer DMA request */
1948 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1949
1950 /* Disable the timer counter */
1951 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1952
1953 hhrtim->State = HAL_HRTIM_STATE_READY;
1954
1955 /* Process Unlocked */
1956 __HAL_UNLOCK(hhrtim);
1957
1958 return HAL_OK;
1959 }
1960
1961 /**
1962 * @}
1963 */
1964
1965 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1966 * @brief Simple PWM output functions
1967 @verbatim
1968 ===============================================================================
1969 ##### Simple PWM output functions #####
1970 ===============================================================================
1971 [..] This section provides functions allowing to:
1972 (+) Configure simple PWM output channel
1973 (+) Start simple PWM output
1974 (+) Stop simple PWM output
1975 (+) Start simple PWM output and enable interrupt
1976 (+) Stop simple PWM output and disable interrupt
1977 (+) Start simple PWM output and enable DMA transfer
1978 (+) Stop simple PWM output and disable DMA transfer
1979 -@- When a HRTIM timer operates in simple PWM output mode
1980 the output level is set to a programmable value when a match is
1981 found between the compare register and the counter and reset when
1982 the timer period is reached. Duty cycle is determined by the
1983 comparison value.
1984 Compare unit 1 is automatically associated to output 1
1985 Compare unit 2 is automatically associated to output 2
1986 @endverbatim
1987 * @{
1988 */
1989
1990 /**
1991 * @brief Configure an output in simple PWM mode
1992 * @param hhrtim pointer to HAL HRTIM handle
1993 * @param TimerIdx Timer index
1994 * This parameter can be one of the following values:
1995 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1996 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1997 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1998 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1999 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2000 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2001 * @param PWMChannel Timer output
2002 * This parameter can be one of the following values:
2003 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2004 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2005 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2006 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2007 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2008 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2009 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2010 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2011 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2012 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2013 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2014 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2015 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
2016 * @note When the timer operates in simple PWM output mode:
2017 * Output 1 is implicitly controlled by the compare unit 1
2018 * Output 2 is implicitly controlled by the compare unit 2
2019 * Output Set/Reset crossbar is set as follows:
2020 * Output 1: SETx1R = CMP1, RSTx1R = PER
2021 * Output 2: SETx2R = CMP2, RST2R = PER
2022 * @note When Simple PWM mode is used the registers preload mechanism is
2023 * enabled (otherwise the behavior is not guaranteed).
2024 * @retval HAL status
2025 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,const HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)2026 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
2027 uint32_t TimerIdx,
2028 uint32_t PWMChannel,
2029 const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
2030 {
2031 HRTIM_OutputCfgTypeDef OutputCfg;
2032 uint32_t hrtim_timcr;
2033
2034 /* Check parameters */
2035 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2036 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
2037 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
2038 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
2039
2040 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
2041 {
2042 return HAL_BUSY;
2043 }
2044
2045 /* Process Locked */
2046 __HAL_LOCK(hhrtim);
2047
2048 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2049
2050 /* Configure timer compare unit */
2051 switch (PWMChannel)
2052 {
2053 case HRTIM_OUTPUT_TA1:
2054 case HRTIM_OUTPUT_TB1:
2055 case HRTIM_OUTPUT_TC1:
2056 case HRTIM_OUTPUT_TD1:
2057 case HRTIM_OUTPUT_TE1:
2058 case HRTIM_OUTPUT_TF1:
2059 {
2060 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
2061 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2062 break;
2063 }
2064
2065 case HRTIM_OUTPUT_TA2:
2066 case HRTIM_OUTPUT_TB2:
2067 case HRTIM_OUTPUT_TC2:
2068 case HRTIM_OUTPUT_TD2:
2069 case HRTIM_OUTPUT_TE2:
2070 case HRTIM_OUTPUT_TF2:
2071 {
2072 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
2073 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2074 break;
2075 }
2076 default:
2077 {
2078 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
2079 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
2080
2081 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2082
2083 /* Process Unlocked */
2084 __HAL_UNLOCK(hhrtim);
2085
2086 break;
2087 }
2088 }
2089
2090 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2091 {
2092 return HAL_ERROR;
2093 }
2094
2095 /* Configure timer output */
2096 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
2097 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
2098 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2099 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2100 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2101 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2102 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
2103
2104 HRTIM_OutputConfig(hhrtim,
2105 TimerIdx,
2106 PWMChannel,
2107 &OutputCfg);
2108
2109 /* Enable the registers preload mechanism */
2110 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
2111 hrtim_timcr |= HRTIM_TIMCR_PREEN;
2112 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
2113
2114 hhrtim->State = HAL_HRTIM_STATE_READY;
2115
2116 /* Process Unlocked */
2117 __HAL_UNLOCK(hhrtim);
2118
2119 return HAL_OK;
2120 }
2121
2122 /**
2123 * @brief Start the PWM output signal generation on the designed timer output
2124 * @param hhrtim pointer to HAL HRTIM handle
2125 * @param TimerIdx Timer index
2126 * This parameter can be one of the following values:
2127 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2128 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2129 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2130 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2131 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2132 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2133 * @param PWMChannel Timer output
2134 * This parameter can be one of the following values:
2135 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2136 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2137 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2138 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2139 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2140 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2141 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2142 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2143 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2144 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2145 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2146 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2147 * @retval HAL status
2148 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2149 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
2150 uint32_t TimerIdx,
2151 uint32_t PWMChannel)
2152 {
2153 /* Check the parameters */
2154 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2155
2156 /* Process Locked */
2157 __HAL_LOCK(hhrtim);
2158
2159 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2160
2161 /* Enable the timer output */
2162 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2163
2164 /* Enable the timer counter */
2165 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2166
2167 hhrtim->State = HAL_HRTIM_STATE_READY;
2168
2169 /* Process Unlocked */
2170 __HAL_UNLOCK(hhrtim);
2171
2172 return HAL_OK;
2173 }
2174
2175 /**
2176 * @brief Stop the PWM output signal generation on the designed timer output
2177 * @param hhrtim pointer to HAL HRTIM handle
2178 * @param TimerIdx Timer index
2179 * This parameter can be one of the following values:
2180 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2181 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2182 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2183 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2184 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2185 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2186 * @param PWMChannel Timer output
2187 * This parameter can be one of the following values:
2188 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2189 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2190 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2191 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2192 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2193 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2194 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2195 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2196 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2197 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2198 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2199 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2200 * @retval HAL status
2201 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2202 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
2203 uint32_t TimerIdx,
2204 uint32_t PWMChannel)
2205 {
2206 /* Check the parameters */
2207 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2208
2209 /* Process Locked */
2210 __HAL_LOCK(hhrtim);
2211
2212 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2213
2214 /* Disable the timer output */
2215 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2216
2217 /* Disable the timer counter */
2218 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2219
2220 hhrtim->State = HAL_HRTIM_STATE_READY;
2221
2222 /* Process Unlocked */
2223 __HAL_UNLOCK(hhrtim);
2224
2225 return HAL_OK;
2226 }
2227
2228 /**
2229 * @brief Start the PWM output signal generation on the designed timer output
2230 * (The compare interrupt is enabled).
2231 * @param hhrtim pointer to HAL HRTIM handle
2232 * @param TimerIdx Timer index
2233 * This parameter can be one of the following values:
2234 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2235 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2236 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2237 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2238 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2239 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2240 * @param PWMChannel Timer output
2241 * This parameter can be one of the following values:
2242 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2243 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2244 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2245 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2246 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2247 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2248 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2249 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2250 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2251 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2252 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2253 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2254 * @retval HAL status
2255 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2256 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
2257 uint32_t TimerIdx,
2258 uint32_t PWMChannel)
2259 {
2260 /* Check the parameters */
2261 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2262
2263 /* Process Locked */
2264 __HAL_LOCK(hhrtim);
2265
2266 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2267
2268 /* Enable the timer output */
2269 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2270
2271 /* Enable the timer interrupt (depends on the PWM output) */
2272 switch (PWMChannel)
2273 {
2274 case HRTIM_OUTPUT_TA1:
2275 case HRTIM_OUTPUT_TB1:
2276 case HRTIM_OUTPUT_TC1:
2277 case HRTIM_OUTPUT_TD1:
2278 case HRTIM_OUTPUT_TE1:
2279 case HRTIM_OUTPUT_TF1:
2280 {
2281 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2282 break;
2283 }
2284
2285 case HRTIM_OUTPUT_TA2:
2286 case HRTIM_OUTPUT_TB2:
2287 case HRTIM_OUTPUT_TC2:
2288 case HRTIM_OUTPUT_TD2:
2289 case HRTIM_OUTPUT_TE2:
2290 case HRTIM_OUTPUT_TF2:
2291 {
2292 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2293 break;
2294 }
2295
2296 default:
2297 {
2298 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2299
2300 /* Process Unlocked */
2301 __HAL_UNLOCK(hhrtim);
2302
2303 break;
2304 }
2305 }
2306
2307 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2308 {
2309 return HAL_ERROR;
2310 }
2311
2312 /* Enable the timer counter */
2313 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2314
2315 hhrtim->State = HAL_HRTIM_STATE_READY;
2316
2317 /* Process Unlocked */
2318 __HAL_UNLOCK(hhrtim);
2319
2320 return HAL_OK;
2321 }
2322
2323 /**
2324 * @brief Stop the PWM output signal generation on the designed timer output
2325 * (The compare interrupt is disabled).
2326 * @param hhrtim pointer to HAL HRTIM handle
2327 * @param TimerIdx Timer index
2328 * This parameter can be one of the following values:
2329 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2330 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2331 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2332 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2333 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2334 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2335 * @param PWMChannel Timer output
2336 * This parameter can be one of the following values:
2337 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2338 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2339 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2340 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2341 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2342 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2343 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2344 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2345 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2346 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2347 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2348 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2349 * @retval HAL status
2350 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2351 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
2352 uint32_t TimerIdx,
2353 uint32_t PWMChannel)
2354 {
2355 /* Check the parameters */
2356 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2357
2358 /* Process Locked */
2359 __HAL_LOCK(hhrtim);
2360
2361 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2362
2363 /* Disable the timer output */
2364 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2365
2366 /* Disable the timer interrupt (depends on the PWM output) */
2367 switch (PWMChannel)
2368 {
2369 case HRTIM_OUTPUT_TA1:
2370 case HRTIM_OUTPUT_TB1:
2371 case HRTIM_OUTPUT_TC1:
2372 case HRTIM_OUTPUT_TD1:
2373 case HRTIM_OUTPUT_TE1:
2374 case HRTIM_OUTPUT_TF1:
2375 {
2376 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2377 break;
2378 }
2379
2380 case HRTIM_OUTPUT_TA2:
2381 case HRTIM_OUTPUT_TB2:
2382 case HRTIM_OUTPUT_TC2:
2383 case HRTIM_OUTPUT_TD2:
2384 case HRTIM_OUTPUT_TE2:
2385 case HRTIM_OUTPUT_TF2:
2386 {
2387 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2388 break;
2389 }
2390
2391 default:
2392 {
2393 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2394
2395 /* Process Unlocked */
2396 __HAL_UNLOCK(hhrtim);
2397
2398 break;
2399 }
2400 }
2401
2402 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2403 {
2404 return HAL_ERROR;
2405 }
2406
2407 /* Disable the timer counter */
2408 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2409
2410 hhrtim->State = HAL_HRTIM_STATE_READY;
2411
2412 /* Process Unlocked */
2413 __HAL_UNLOCK(hhrtim);
2414
2415 return HAL_OK;
2416 }
2417
2418 /**
2419 * @brief Start the PWM output signal generation on the designed timer output
2420 * (The compare DMA request is enabled).
2421 * @param hhrtim pointer to HAL HRTIM handle
2422 * @param TimerIdx Timer index
2423 * This parameter can be one of the following values:
2424 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2425 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2426 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2427 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2428 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2429 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2430 * @param PWMChannel Timer output
2431 * This parameter can be one of the following values:
2432 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2433 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2434 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2435 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2436 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2437 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2438 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2439 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2440 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2441 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2442 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2443 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2444 * @param SrcAddr DMA transfer source address
2445 * @param DestAddr DMA transfer destination address
2446 * @param Length The length of data items (data size) to be transferred
2447 * from source to destination
2448 * @retval HAL status
2449 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2450 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
2451 uint32_t TimerIdx,
2452 uint32_t PWMChannel,
2453 uint32_t SrcAddr,
2454 uint32_t DestAddr,
2455 uint32_t Length)
2456 {
2457 DMA_HandleTypeDef *hdma;
2458
2459 /* Check the parameters */
2460 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2461
2462 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
2463 {
2464 return HAL_BUSY;
2465 }
2466 if (hhrtim->State == HAL_HRTIM_STATE_READY)
2467 {
2468 if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
2469 {
2470 return HAL_ERROR;
2471 }
2472 else
2473 {
2474 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2475 }
2476 }
2477
2478 /* Process Locked */
2479 __HAL_LOCK(hhrtim);
2480
2481 /* Enable the timer output */
2482 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2483
2484 /* Get the timer DMA handler */
2485 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2486
2487 if (hdma == NULL)
2488 {
2489 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2490
2491 /* Process Unlocked */
2492 __HAL_UNLOCK(hhrtim);
2493
2494 return HAL_ERROR;
2495 }
2496
2497 /* Set the DMA error callback */
2498 hdma->XferErrorCallback = HRTIM_DMAError ;
2499
2500 /* Set the DMA transfer completed callback */
2501 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2502
2503 /* Enable the DMA channel */
2504 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2505 {
2506 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2507
2508 /* Process Unlocked */
2509 __HAL_UNLOCK(hhrtim);
2510
2511 return HAL_ERROR;
2512 }
2513
2514 /* Enable the timer DMA request */
2515 switch (PWMChannel)
2516 {
2517 case HRTIM_OUTPUT_TA1:
2518 case HRTIM_OUTPUT_TB1:
2519 case HRTIM_OUTPUT_TC1:
2520 case HRTIM_OUTPUT_TD1:
2521 case HRTIM_OUTPUT_TE1:
2522 case HRTIM_OUTPUT_TF1:
2523 {
2524 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2525 break;
2526 }
2527
2528 case HRTIM_OUTPUT_TA2:
2529 case HRTIM_OUTPUT_TB2:
2530 case HRTIM_OUTPUT_TC2:
2531 case HRTIM_OUTPUT_TD2:
2532 case HRTIM_OUTPUT_TE2:
2533 case HRTIM_OUTPUT_TF2:
2534 {
2535 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2536 break;
2537 }
2538
2539 default:
2540 {
2541 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2542
2543 /* Process Unlocked */
2544 __HAL_UNLOCK(hhrtim);
2545
2546 break;
2547 }
2548 }
2549
2550 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2551 {
2552 return HAL_ERROR;
2553 }
2554
2555 /* Enable the timer counter */
2556 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2557
2558 hhrtim->State = HAL_HRTIM_STATE_READY;
2559
2560 /* Process Unlocked */
2561 __HAL_UNLOCK(hhrtim);
2562
2563 return HAL_OK;
2564 }
2565
2566 /**
2567 * @brief Stop the PWM output signal generation on the designed timer output
2568 * (The compare DMA request is disabled).
2569 * @param hhrtim pointer to HAL HRTIM handle
2570 * @param TimerIdx Timer index
2571 * This parameter can be one of the following values:
2572 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2573 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2574 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2575 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2576 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2577 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2578 * @param PWMChannel Timer output
2579 * This parameter can be one of the following values:
2580 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2581 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2582 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2583 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2584 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2585 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2586 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2587 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2588 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2589 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2590 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2591 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2592 * @retval HAL status
2593 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2594 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
2595 uint32_t TimerIdx,
2596 uint32_t PWMChannel)
2597 {
2598 /* Check the parameters */
2599 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2600
2601 /* Process Locked */
2602 __HAL_LOCK(hhrtim);
2603
2604 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2605
2606 /* Disable the timer output */
2607 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2608
2609 /* Get the timer DMA handler */
2610 /* Disable the DMA */
2611 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2612 {
2613 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2614
2615 /* Process Unlocked */
2616 __HAL_UNLOCK(hhrtim);
2617
2618 return HAL_ERROR;
2619 }
2620
2621 /* Disable the timer DMA request */
2622 switch (PWMChannel)
2623 {
2624 case HRTIM_OUTPUT_TA1:
2625 case HRTIM_OUTPUT_TB1:
2626 case HRTIM_OUTPUT_TC1:
2627 case HRTIM_OUTPUT_TD1:
2628 case HRTIM_OUTPUT_TE1:
2629 case HRTIM_OUTPUT_TF1:
2630 {
2631 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2632 break;
2633 }
2634
2635 case HRTIM_OUTPUT_TA2:
2636 case HRTIM_OUTPUT_TB2:
2637 case HRTIM_OUTPUT_TC2:
2638 case HRTIM_OUTPUT_TD2:
2639 case HRTIM_OUTPUT_TE2:
2640 case HRTIM_OUTPUT_TF2:
2641 {
2642 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2643 break;
2644 }
2645
2646 default:
2647 {
2648 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2649
2650 /* Process Unlocked */
2651 __HAL_UNLOCK(hhrtim);
2652
2653 break;
2654 }
2655 }
2656
2657 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2658 {
2659 return HAL_ERROR;
2660 }
2661
2662 /* Disable the timer counter */
2663 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2664
2665 hhrtim->State = HAL_HRTIM_STATE_READY;
2666
2667 /* Process Unlocked */
2668 __HAL_UNLOCK(hhrtim);
2669
2670 return HAL_OK;
2671 }
2672
2673 /**
2674 * @}
2675 */
2676
2677 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2678 * @brief Simple input capture functions
2679 @verbatim
2680 ===============================================================================
2681 ##### Simple input capture functions #####
2682 ===============================================================================
2683 [..] This section provides functions allowing to:
2684 (+) Configure simple input capture channel
2685 (+) Start simple input capture
2686 (+) Stop simple input capture
2687 (+) Start simple input capture and enable interrupt
2688 (+) Stop simple input capture and disable interrupt
2689 (+) Start simple input capture and enable DMA transfer
2690 (+) Stop simple input capture and disable DMA transfer
2691 -@- When a HRTIM timer operates in simple input capture mode
2692 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2693 value of the timer counter counter after a transition detected
2694 on a given external event input.
2695 @endverbatim
2696 * @{
2697 */
2698
2699 /**
2700 * @brief Configure a simple capture
2701 * @param hhrtim pointer to HAL HRTIM handle
2702 * @param TimerIdx Timer index
2703 * This parameter can be one of the following values:
2704 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2705 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2706 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2707 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2708 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2709 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2710 * @param CaptureChannel Capture unit
2711 * This parameter can be one of the following values:
2712 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2713 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2714 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2715 * @note When the timer operates in simple capture mode the capture is triggered
2716 * by the designated external event and GPIO input is implicitly used as event source.
2717 * The cature can be triggered by a rising edge, a falling edge or both
2718 * edges on event channel.
2719 * @retval HAL status
2720 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,const HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2721 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
2722 uint32_t TimerIdx,
2723 uint32_t CaptureChannel,
2724 const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
2725 {
2726 HRTIM_EventCfgTypeDef EventCfg;
2727
2728 /* Check parameters */
2729 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2730 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2731 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2732 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2733 pSimpleCaptureChannelCfg->EventPolarity));
2734 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2735 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2736 pSimpleCaptureChannelCfg->EventFilter));
2737
2738 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
2739 {
2740 return HAL_BUSY;
2741 }
2742
2743 /* Process Locked */
2744 __HAL_LOCK(hhrtim);
2745
2746 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2747
2748 /* Configure external event channel */
2749 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2750 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2751 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2752 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2753 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
2754
2755 HRTIM_EventConfig(hhrtim,
2756 pSimpleCaptureChannelCfg->Event,
2757 &EventCfg);
2758
2759 /* Memorize capture trigger (will be configured when the capture is started */
2760 HRTIM_CaptureUnitConfig(hhrtim,
2761 TimerIdx,
2762 CaptureChannel,
2763 pSimpleCaptureChannelCfg->Event);
2764
2765 hhrtim->State = HAL_HRTIM_STATE_READY;
2766
2767 /* Process Unlocked */
2768 __HAL_UNLOCK(hhrtim);
2769
2770 return HAL_OK;
2771 }
2772
2773 /**
2774 * @brief Enable a simple capture on the designed capture unit
2775 * @param hhrtim pointer to HAL HRTIM handle
2776 * @param TimerIdx Timer index
2777 * This parameter can be one of the following values:
2778 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2779 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2780 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2781 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2782 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2783 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2784 * @param CaptureChannel Timer output
2785 * This parameter can be one of the following values:
2786 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2787 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2788 * @retval HAL status
2789 * @note The external event triggering the capture is available for all timing
2790 * units. It can be used directly and is active as soon as the timing
2791 * unit counter is enabled.
2792 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2793 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
2794 uint32_t TimerIdx,
2795 uint32_t CaptureChannel)
2796 {
2797 /* Check the parameters */
2798 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2799 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2800
2801 /* Process Locked */
2802 __HAL_LOCK(hhrtim);
2803
2804 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2805
2806 /* Set the capture unit trigger */
2807 switch (CaptureChannel)
2808 {
2809 case HRTIM_CAPTUREUNIT_1:
2810 {
2811 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2812 break;
2813 }
2814
2815 case HRTIM_CAPTUREUNIT_2:
2816 {
2817 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2818 break;
2819 }
2820
2821 default:
2822 {
2823 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2824
2825 /* Process Unlocked */
2826 __HAL_UNLOCK(hhrtim);
2827
2828 break;
2829 }
2830 }
2831
2832 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2833 {
2834 return HAL_ERROR;
2835 }
2836
2837 /* Enable the timer counter */
2838 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2839
2840 hhrtim->State = HAL_HRTIM_STATE_READY;
2841
2842 /* Process Unlocked */
2843 __HAL_UNLOCK(hhrtim);
2844
2845 return HAL_OK;
2846 }
2847
2848 /**
2849 * @brief Disable a simple capture on the designed capture unit
2850 * @param hhrtim pointer to HAL HRTIM handle
2851 * @param TimerIdx Timer index
2852 * This parameter can be one of the following values:
2853 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2854 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2855 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2856 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2857 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2858 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2859 * @param CaptureChannel Timer output
2860 * This parameter can be one of the following values:
2861 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2862 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2863 * @retval HAL status
2864 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2865 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
2866 uint32_t TimerIdx,
2867 uint32_t CaptureChannel)
2868 {
2869 uint32_t hrtim_cpt1cr;
2870 uint32_t hrtim_cpt2cr;
2871
2872 /* Check the parameters */
2873 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2874 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2875
2876 /* Process Locked */
2877 __HAL_LOCK(hhrtim);
2878
2879 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2880
2881 /* Set the capture unit trigger */
2882 switch (CaptureChannel)
2883 {
2884 case HRTIM_CAPTUREUNIT_1:
2885 {
2886 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2887 break;
2888 }
2889
2890 case HRTIM_CAPTUREUNIT_2:
2891 {
2892 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2893 break;
2894 }
2895
2896 default:
2897 {
2898 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2899
2900 /* Process Unlocked */
2901 __HAL_UNLOCK(hhrtim);
2902
2903 break;
2904 }
2905 }
2906
2907 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2908 {
2909 return HAL_ERROR;
2910 }
2911
2912 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2913 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2914
2915 /* Disable the timer counter */
2916 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2917 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2918 {
2919 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2920 }
2921
2922 hhrtim->State = HAL_HRTIM_STATE_READY;
2923
2924 /* Process Unlocked */
2925 __HAL_UNLOCK(hhrtim);
2926
2927 return HAL_OK;
2928 }
2929
2930 /**
2931 * @brief Enable a simple capture on the designed capture unit
2932 * (Capture interrupt is enabled).
2933 * @param hhrtim pointer to HAL HRTIM handle
2934 * @param TimerIdx Timer index
2935 * This parameter can be one of the following values:
2936 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2937 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2938 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2939 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2940 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2941 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2942 * @param CaptureChannel Timer output
2943 * This parameter can be one of the following values:
2944 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2945 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2946 * @retval HAL status
2947 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2948 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
2949 uint32_t TimerIdx,
2950 uint32_t CaptureChannel)
2951 {
2952 /* Check the parameters */
2953 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2954 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2955
2956 /* Process Locked */
2957 __HAL_LOCK(hhrtim);
2958
2959 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2960
2961 /* Set the capture unit trigger */
2962 switch (CaptureChannel)
2963 {
2964 case HRTIM_CAPTUREUNIT_1:
2965 {
2966 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2967
2968 /* Enable the capture unit 1 interrupt */
2969 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2970 break;
2971 }
2972
2973 case HRTIM_CAPTUREUNIT_2:
2974 {
2975 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2976
2977 /* Enable the capture unit 2 interrupt */
2978 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2979 break;
2980 }
2981
2982 default:
2983 {
2984 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2985
2986 /* Process Unlocked */
2987 __HAL_UNLOCK(hhrtim);
2988
2989 break;
2990 }
2991 }
2992
2993 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
2994 {
2995 return HAL_ERROR;
2996 }
2997
2998 /* Enable the timer counter */
2999 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3000
3001 hhrtim->State = HAL_HRTIM_STATE_READY;
3002
3003 /* Process Unlocked */
3004 __HAL_UNLOCK(hhrtim);
3005
3006 return HAL_OK;
3007 }
3008
3009 /**
3010 * @brief Disable a simple capture on the designed capture unit
3011 * (Capture interrupt is disabled).
3012 * @param hhrtim pointer to HAL HRTIM handle
3013 * @param TimerIdx Timer index
3014 * This parameter can be one of the following values:
3015 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3016 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3017 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3018 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3019 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3020 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3021 * @param CaptureChannel Timer output
3022 * This parameter can be one of the following values:
3023 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3024 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3025 * @retval HAL status
3026 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3027 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
3028 uint32_t TimerIdx,
3029 uint32_t CaptureChannel)
3030 {
3031
3032 uint32_t hrtim_cpt1cr;
3033 uint32_t hrtim_cpt2cr;
3034
3035 /* Check the parameters */
3036 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3037 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3038
3039 /* Process Locked */
3040 __HAL_LOCK(hhrtim);
3041
3042 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3043
3044 /* Set the capture unit trigger */
3045 switch (CaptureChannel)
3046 {
3047 case HRTIM_CAPTUREUNIT_1:
3048 {
3049 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3050
3051 /* Disable the capture unit 1 interrupt */
3052 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
3053 break;
3054 }
3055
3056 case HRTIM_CAPTUREUNIT_2:
3057 {
3058 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3059
3060 /* Disable the capture unit 2 interrupt */
3061 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
3062 break;
3063 }
3064
3065 default:
3066 {
3067 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3068
3069 /* Process Unlocked */
3070 __HAL_UNLOCK(hhrtim);
3071
3072 break;
3073 }
3074 }
3075
3076 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3077 {
3078 return HAL_ERROR;
3079 }
3080
3081 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3082 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3083
3084 /* Disable the timer counter */
3085 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3086 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3087 {
3088 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3089 }
3090
3091 hhrtim->State = HAL_HRTIM_STATE_READY;
3092
3093 /* Process Unlocked */
3094 __HAL_UNLOCK(hhrtim);
3095
3096 return HAL_OK;
3097 }
3098
3099 /**
3100 * @brief Enable a simple capture on the designed capture unit
3101 * (Capture DMA request is enabled).
3102 * @param hhrtim pointer to HAL HRTIM handle
3103 * @param TimerIdx Timer index
3104 * This parameter can be one of the following values:
3105 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3106 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3107 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3108 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3109 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3110 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3111 * @param CaptureChannel Timer output
3112 * This parameter can be one of the following values:
3113 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3114 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3115 * @param SrcAddr DMA transfer source address
3116 * @param DestAddr DMA transfer destination address
3117 * @param Length The length of data items (data size) to be transferred
3118 * from source to destination
3119 * @retval HAL status
3120 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)3121 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3122 uint32_t TimerIdx,
3123 uint32_t CaptureChannel,
3124 uint32_t SrcAddr,
3125 uint32_t DestAddr,
3126 uint32_t Length)
3127 {
3128 DMA_HandleTypeDef *hdma;
3129
3130 /* Check the parameters */
3131 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3132 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3133
3134 /* Process Locked */
3135 __HAL_LOCK(hhrtim);
3136
3137 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3138
3139 /* Get the timer DMA handler */
3140 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
3141
3142 if (hdma == NULL)
3143 {
3144 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3145
3146 /* Process Unlocked */
3147 __HAL_UNLOCK(hhrtim);
3148
3149 return HAL_ERROR;
3150 }
3151
3152 /* Set the DMA error callback */
3153 hdma->XferErrorCallback = HRTIM_DMAError ;
3154
3155 /* Set the DMA transfer completed callback */
3156 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
3157
3158 /* Enable the DMA channel */
3159 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
3160 {
3161 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3162
3163 /* Process Unlocked */
3164 __HAL_UNLOCK(hhrtim);
3165
3166 return HAL_ERROR;
3167 }
3168
3169 switch (CaptureChannel)
3170 {
3171 case HRTIM_CAPTUREUNIT_1:
3172 {
3173 /* Set the capture unit trigger */
3174 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
3175
3176 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3177 break;
3178 }
3179
3180 case HRTIM_CAPTUREUNIT_2:
3181 {
3182 /* Set the capture unit trigger */
3183 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
3184
3185 /* Enable the timer DMA request */
3186 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3187 break;
3188 }
3189
3190 default:
3191 {
3192 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3193
3194 /* Process Unlocked */
3195 __HAL_UNLOCK(hhrtim);
3196
3197 break;
3198 }
3199 }
3200
3201 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3202 {
3203 return HAL_ERROR;
3204 }
3205
3206 /* Enable the timer counter */
3207 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3208
3209 hhrtim->State = HAL_HRTIM_STATE_READY;
3210
3211 /* Process Unlocked */
3212 __HAL_UNLOCK(hhrtim);
3213
3214 return HAL_OK;
3215 }
3216
3217 /**
3218 * @brief Disable a simple capture on the designed capture unit
3219 * (Capture DMA request is disabled).
3220 * @param hhrtim pointer to HAL HRTIM handle
3221 * @param TimerIdx Timer index
3222 * This parameter can be one of the following values:
3223 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3224 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3225 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3226 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3227 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3228 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3229 * @param CaptureChannel Timer output
3230 * This parameter can be one of the following values:
3231 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3232 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3233 * @retval HAL status
3234 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3235 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3236 uint32_t TimerIdx,
3237 uint32_t CaptureChannel)
3238 {
3239
3240 uint32_t hrtim_cpt1cr;
3241 uint32_t hrtim_cpt2cr;
3242
3243 /* Check the parameters */
3244 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3245 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3246
3247 /* Process Locked */
3248 __HAL_LOCK(hhrtim);
3249
3250 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3251
3252 /* Get the timer DMA handler */
3253 /* Disable the DMA */
3254 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3255 {
3256 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3257
3258 /* Process Unlocked */
3259 __HAL_UNLOCK(hhrtim);
3260
3261 return HAL_ERROR;
3262 }
3263
3264 switch (CaptureChannel)
3265 {
3266 case HRTIM_CAPTUREUNIT_1:
3267 {
3268 /* Reset the capture unit trigger */
3269 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3270
3271 /* Disable the capture unit 1 DMA request */
3272 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3273 break;
3274 }
3275
3276 case HRTIM_CAPTUREUNIT_2:
3277 {
3278 /* Reset the capture unit trigger */
3279 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3280
3281 /* Disable the capture unit 2 DMA request */
3282 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3283 break;
3284 }
3285
3286 default:
3287 {
3288 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3289
3290 /* Process Unlocked */
3291 __HAL_UNLOCK(hhrtim);
3292
3293 break;
3294 }
3295 }
3296
3297 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3298 {
3299 return HAL_ERROR;
3300 }
3301
3302 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3303 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3304
3305 /* Disable the timer counter */
3306 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3307 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3308 {
3309 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3310 }
3311
3312 hhrtim->State = HAL_HRTIM_STATE_READY;
3313
3314 /* Process Unlocked */
3315 __HAL_UNLOCK(hhrtim);
3316
3317 return HAL_OK;
3318 }
3319
3320 /**
3321 * @}
3322 */
3323
3324 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3325 * @brief Simple one pulse functions
3326 @verbatim
3327 ===============================================================================
3328 ##### Simple one pulse functions #####
3329 ===============================================================================
3330 [..] This section provides functions allowing to:
3331 (+) Configure one pulse channel
3332 (+) Start one pulse generation
3333 (+) Stop one pulse generation
3334 (+) Start one pulse generation and enable interrupt
3335 (+) Stop one pulse generation and disable interrupt
3336 -@- When a HRTIM timer operates in simple one pulse mode
3337 the timer counter is started in response to transition detected
3338 on a given external event input to generate a pulse with a
3339 programmable length after a programmable delay.
3340 @endverbatim
3341 * @{
3342 */
3343
3344 /**
3345 * @brief Configure an output simple one pulse mode
3346 * @param hhrtim pointer to HAL HRTIM handle
3347 * @param TimerIdx Timer index
3348 * This parameter can be one of the following values:
3349 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3350 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3351 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3352 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3353 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3354 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3355 * @param OnePulseChannel Timer output
3356 * This parameter can be one of the following values:
3357 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3358 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3359 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3360 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3361 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3362 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3363 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3364 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3365 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3366 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3367 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3368 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3369 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3370 * @note When the timer operates in simple one pulse mode:
3371 * the timer counter is implicitly started by the reset event,
3372 * the reset of the timer counter is triggered by the designated external event
3373 * GPIO input is implicitly used as event source,
3374 * Output 1 is implicitly controlled by the compare unit 1,
3375 * Output 2 is implicitly controlled by the compare unit 2.
3376 * Output Set/Reset crossbar is set as follows:
3377 * Output 1: SETx1R = CMP1, RSTx1R = PER
3378 * Output 2: SETx2R = CMP2, RST2R = PER
3379 * @retval HAL status
3380 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3381 * outputs, the reset event related configuration data provided in the
3382 * second call will override the reset event related configuration data
3383 * provided in the first call.
3384 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,const HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3385 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3386 uint32_t TimerIdx,
3387 uint32_t OnePulseChannel,
3388 const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
3389 {
3390 HRTIM_OutputCfgTypeDef OutputCfg;
3391 HRTIM_EventCfgTypeDef EventCfg;
3392
3393 /* Check parameters */
3394 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3395 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3396 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3397 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3398 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3399 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3400 pSimpleOnePulseChannelCfg->EventPolarity));
3401 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3402 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3403 pSimpleOnePulseChannelCfg->EventFilter));
3404
3405 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3406 {
3407 return HAL_BUSY;
3408 }
3409
3410 /* Process Locked */
3411 __HAL_LOCK(hhrtim);
3412
3413 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3414
3415 /* Configure timer compare unit */
3416 switch (OnePulseChannel)
3417 {
3418 case HRTIM_OUTPUT_TA1:
3419 case HRTIM_OUTPUT_TB1:
3420 case HRTIM_OUTPUT_TC1:
3421 case HRTIM_OUTPUT_TD1:
3422 case HRTIM_OUTPUT_TE1:
3423 case HRTIM_OUTPUT_TF1:
3424 {
3425 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3426 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3427 break;
3428 }
3429
3430 case HRTIM_OUTPUT_TA2:
3431 case HRTIM_OUTPUT_TB2:
3432 case HRTIM_OUTPUT_TC2:
3433 case HRTIM_OUTPUT_TD2:
3434 case HRTIM_OUTPUT_TE2:
3435 case HRTIM_OUTPUT_TF2:
3436 {
3437 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3438 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3439 break;
3440 }
3441
3442 default:
3443 {
3444 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3445 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3446
3447 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3448
3449 /* Process Unlocked */
3450 __HAL_UNLOCK(hhrtim);
3451
3452 break;
3453 }
3454 }
3455
3456 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3457 {
3458 return HAL_ERROR;
3459 }
3460
3461 /* Configure timer output */
3462 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3463 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3464 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3465 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3466 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3467 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3468 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3469
3470 HRTIM_OutputConfig(hhrtim,
3471 TimerIdx,
3472 OnePulseChannel,
3473 &OutputCfg);
3474
3475 /* Configure external event channel */
3476 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3477 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3478 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3479 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
3480 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
3481
3482 HRTIM_EventConfig(hhrtim,
3483 pSimpleOnePulseChannelCfg->Event,
3484 &EventCfg);
3485
3486 /* Configure the timer reset register */
3487 HRTIM_TIM_ResetConfig(hhrtim,
3488 TimerIdx,
3489 pSimpleOnePulseChannelCfg->Event);
3490
3491 hhrtim->State = HAL_HRTIM_STATE_READY;
3492
3493 /* Process Unlocked */
3494 __HAL_UNLOCK(hhrtim);
3495
3496 return HAL_OK;
3497 }
3498
3499 /**
3500 * @brief Enable the simple one pulse signal generation on the designed output
3501 * @param hhrtim pointer to HAL HRTIM handle
3502 * @param TimerIdx Timer index
3503 * This parameter can be one of the following values:
3504 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3505 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3506 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3507 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3508 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3509 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3510 * @param OnePulseChannel Timer output
3511 * This parameter can be one of the following values:
3512 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3513 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3514 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3515 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3516 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3517 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3518 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3519 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3520 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3521 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3522 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3523 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3524 * @retval HAL status
3525 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3526 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
3527 uint32_t TimerIdx,
3528 uint32_t OnePulseChannel)
3529 {
3530 /* Check the parameters */
3531 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3532
3533 /* Process Locked */
3534 __HAL_LOCK(hhrtim);
3535
3536 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3537
3538 /* Enable the timer output */
3539 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3540
3541 /* Enable the timer counter */
3542 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3543
3544 hhrtim->State = HAL_HRTIM_STATE_READY;
3545
3546 /* Process Unlocked */
3547 __HAL_UNLOCK(hhrtim);
3548
3549 return HAL_OK;
3550 }
3551
3552 /**
3553 * @brief Disable the simple one pulse signal generation on the designed output
3554 * @param hhrtim pointer to HAL HRTIM handle
3555 * @param TimerIdx Timer index
3556 * This parameter can be one of the following values:
3557 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3558 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3559 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3560 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3561 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3562 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3563 * @param OnePulseChannel Timer output
3564 * This parameter can be one of the following values:
3565 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3566 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3567 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3568 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3569 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3570 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3571 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3572 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3573 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3574 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3575 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3576 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3577 * @retval HAL status
3578 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3579 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
3580 uint32_t TimerIdx,
3581 uint32_t OnePulseChannel)
3582 {
3583 /* Check the parameters */
3584 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3585
3586 /* Process Locked */
3587 __HAL_LOCK(hhrtim);
3588
3589 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3590
3591 /* Disable the timer output */
3592 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3593
3594 /* Disable the timer counter */
3595 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3596
3597 hhrtim->State = HAL_HRTIM_STATE_READY;
3598
3599 /* Process Unlocked */
3600 __HAL_UNLOCK(hhrtim);
3601
3602 return HAL_OK;
3603 }
3604
3605 /**
3606 * @brief Enable the simple one pulse signal generation on the designed output
3607 * (The compare interrupt is enabled (pulse start)).
3608 * @param hhrtim pointer to HAL HRTIM handle
3609 * @param TimerIdx Timer index
3610 * This parameter can be one of the following values:
3611 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3612 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3613 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3614 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3615 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3616 * @arg HRTIM_TIMERINDEX_TIMER_F for timer E
3617 * @param OnePulseChannel Timer output
3618 * This parameter can be one of the following values:
3619 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3620 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3621 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3622 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3623 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3624 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3625 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3626 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3627 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3628 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3629 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3630 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3631 * @retval HAL status
3632 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3633 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3634 uint32_t TimerIdx,
3635 uint32_t OnePulseChannel)
3636 {
3637 /* Check the parameters */
3638 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3639
3640 /* Process Locked */
3641 __HAL_LOCK(hhrtim);
3642
3643 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3644
3645 /* Enable the timer output */
3646 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3647
3648 /* Enable the timer interrupt (depends on the OnePulse output) */
3649 switch (OnePulseChannel)
3650 {
3651 case HRTIM_OUTPUT_TA1:
3652 case HRTIM_OUTPUT_TB1:
3653 case HRTIM_OUTPUT_TC1:
3654 case HRTIM_OUTPUT_TD1:
3655 case HRTIM_OUTPUT_TE1:
3656 case HRTIM_OUTPUT_TF1:
3657 {
3658 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3659 break;
3660 }
3661
3662 case HRTIM_OUTPUT_TA2:
3663 case HRTIM_OUTPUT_TB2:
3664 case HRTIM_OUTPUT_TC2:
3665 case HRTIM_OUTPUT_TD2:
3666 case HRTIM_OUTPUT_TE2:
3667 case HRTIM_OUTPUT_TF2:
3668 {
3669 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3670 break;
3671 }
3672
3673 default:
3674 {
3675 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3676
3677 /* Process Unlocked */
3678 __HAL_UNLOCK(hhrtim);
3679
3680 break;
3681 }
3682 }
3683
3684 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3685 {
3686 return HAL_ERROR;
3687 }
3688
3689 /* Enable the timer counter */
3690 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3691
3692 hhrtim->State = HAL_HRTIM_STATE_READY;
3693
3694 /* Process Unlocked */
3695 __HAL_UNLOCK(hhrtim);
3696
3697 return HAL_OK;
3698 }
3699
3700 /**
3701 * @brief Disable the simple one pulse signal generation on the designed output
3702 * (The compare interrupt is disabled).
3703 * @param hhrtim pointer to HAL HRTIM handle
3704 * @param TimerIdx Timer index
3705 * This parameter can be one of the following values:
3706 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3707 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3708 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3709 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3710 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3711 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3712 * @param OnePulseChannel Timer output
3713 * This parameter can be one of the following values:
3714 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3715 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3716 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3717 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3718 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3719 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3720 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3721 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3722 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3723 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3724 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3725 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3726 * @retval HAL status
3727 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3728 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3729 uint32_t TimerIdx,
3730 uint32_t OnePulseChannel)
3731 {
3732 /* Check the parameters */
3733 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3734
3735 /* Process Locked */
3736 __HAL_LOCK(hhrtim);
3737
3738 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3739
3740 /* Disable the timer output */
3741 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3742
3743 /* Disable the timer interrupt (depends on the OnePulse output) */
3744 switch (OnePulseChannel)
3745 {
3746 case HRTIM_OUTPUT_TA1:
3747 case HRTIM_OUTPUT_TB1:
3748 case HRTIM_OUTPUT_TC1:
3749 case HRTIM_OUTPUT_TD1:
3750 case HRTIM_OUTPUT_TE1:
3751 case HRTIM_OUTPUT_TF1:
3752 {
3753 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3754 break;
3755 }
3756
3757 case HRTIM_OUTPUT_TA2:
3758 case HRTIM_OUTPUT_TB2:
3759 case HRTIM_OUTPUT_TC2:
3760 case HRTIM_OUTPUT_TD2:
3761 case HRTIM_OUTPUT_TE2:
3762 case HRTIM_OUTPUT_TF2:
3763 {
3764 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3765 break;
3766 }
3767
3768 default:
3769 {
3770 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3771
3772 /* Process Unlocked */
3773 __HAL_UNLOCK(hhrtim);
3774
3775 break;
3776 }
3777 }
3778
3779 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
3780 {
3781 return HAL_ERROR;
3782 }
3783
3784 /* Disable the timer counter */
3785 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3786
3787 hhrtim->State = HAL_HRTIM_STATE_READY;
3788
3789 /* Process Unlocked */
3790 __HAL_UNLOCK(hhrtim);
3791
3792 return HAL_OK;
3793 }
3794
3795 /**
3796 * @}
3797 */
3798
3799 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3800 * @brief HRTIM configuration functions
3801 @verbatim
3802 ===============================================================================
3803 ##### HRTIM configuration functions #####
3804 ===============================================================================
3805 [..] This section provides functions allowing to configure the HRTIM
3806 resources shared by all the HRTIM timers operating in waveform mode:
3807 (+) Configure the burst mode controller
3808 (+) Configure an external event conditioning
3809 (+) Configure the external events sampling clock
3810 (+) Configure a fault conditioning
3811 (+) Enable or disable fault inputs
3812 (+) Configure the faults sampling clock
3813 (+) Configure an ADC trigger
3814
3815 @endverbatim
3816 * @{
3817 */
3818
3819 /**
3820 * @brief Configure the burst mode feature of the HRTIM
3821 * @param hhrtim pointer to HAL HRTIM handle
3822 * @param pBurstModeCfg pointer to the burst mode configuration structure
3823 * @retval HAL status
3824 * @note This function must be called before starting the burst mode
3825 * controller
3826 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,const HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3827 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
3828 const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
3829 {
3830 uint32_t hrtim_bmcr;
3831
3832 /* Check parameters */
3833 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3834 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3835 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3836 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3837 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3838
3839 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3840 {
3841 return HAL_BUSY;
3842 }
3843
3844 /* Process Locked */
3845 __HAL_LOCK(hhrtim);
3846
3847 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3848
3849 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3850
3851 /* Set the burst mode operating mode */
3852 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3853 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3854
3855 /* Set the burst mode clock source */
3856 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3857 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3858
3859 /* Set the burst mode prescaler */
3860 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3861 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3862
3863 /* Enable/disable burst mode registers preload */
3864 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3865 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3866
3867 /* Set the burst mode trigger */
3868 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3869
3870 /* Set the burst mode compare value */
3871 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3872
3873 /* Set the burst mode period */
3874 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3875
3876 /* Update the HRTIM registers */
3877 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3878
3879 hhrtim->State = HAL_HRTIM_STATE_READY;
3880
3881 /* Process Unlocked */
3882 __HAL_UNLOCK(hhrtim);
3883
3884 return HAL_OK;
3885 }
3886
3887 /**
3888 * @brief Configure the conditioning of an external event
3889 * @param hhrtim pointer to HAL HRTIM handle
3890 * @param Event external event to configure
3891 * This parameter can be one of the following values:
3892 * @arg HRTIM_EVENT_NONE: no external Event
3893 * @arg HRTIM_EVENT_1: External event 1
3894 * @arg HRTIM_EVENT_2: External event 2
3895 * @arg HRTIM_EVENT_3: External event 3
3896 * @arg HRTIM_EVENT_4: External event 4
3897 * @arg HRTIM_EVENT_5: External event 5
3898 * @arg HRTIM_EVENT_6: External event 6
3899 * @arg HRTIM_EVENT_7: External event 7
3900 * @arg HRTIM_EVENT_8: External event 8
3901 * @arg HRTIM_EVENT_9: External event 9
3902 * @arg HRTIM_EVENT_10: External event 10
3903 * @param pEventCfg pointer to the event conditioning configuration structure
3904 * @note This function must be called before starting the timer
3905 * @retval HAL status
3906 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)3907 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
3908 uint32_t Event,
3909 const HRTIM_EventCfgTypeDef *pEventCfg)
3910 {
3911 /* Check parameters */
3912 assert_param(IS_HRTIM_EVENT(Event));
3913 assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source));
3914 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3915 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3916 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3917 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3918
3919 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3920 {
3921 return HAL_BUSY;
3922 }
3923
3924 /* Process Locked */
3925 __HAL_LOCK(hhrtim);
3926
3927 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3928
3929 /* Configure the event channel */
3930 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3931
3932 hhrtim->State = HAL_HRTIM_STATE_READY;
3933
3934 /* Process Unlocked */
3935 __HAL_UNLOCK(hhrtim);
3936
3937 return HAL_OK;
3938 }
3939
3940 /**
3941 * @brief Configure the external event conditioning block prescaler
3942 * @param hhrtim pointer to HAL HRTIM handle
3943 * @param Prescaler Prescaler value
3944 * This parameter can be one of the following values:
3945 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3946 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3947 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3948 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3949 * @note This function must be called before starting the timer
3950 * @retval HAL status
3951 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3952 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3953 uint32_t Prescaler)
3954 {
3955 /* Check parameters */
3956 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3957
3958 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
3959 {
3960 return HAL_BUSY;
3961 }
3962
3963 /* Process Locked */
3964 __HAL_LOCK(hhrtim);
3965
3966 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3967
3968 /* Set the external event prescaler */
3969 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3970
3971 hhrtim->State = HAL_HRTIM_STATE_READY;
3972
3973 /* Process Unlocked */
3974 __HAL_UNLOCK(hhrtim);
3975
3976 return HAL_OK;
3977 }
3978
3979 /**
3980 * @brief Configure the conditioning of fault input
3981 * @param hhrtim pointer to HAL HRTIM handle
3982 * @param Fault fault input to configure
3983 * This parameter can be one of the following values:
3984 * @arg HRTIM_FAULT_1: Fault input 1
3985 * @arg HRTIM_FAULT_2: Fault input 2
3986 * @arg HRTIM_FAULT_3: Fault input 3
3987 * @arg HRTIM_FAULT_4: Fault input 4
3988 * @arg HRTIM_FAULT_5: Fault input 5
3989 * @arg HRTIM_FAULT_6: Fault input 6
3990 * @param pFaultCfg pointer to the fault conditioning configuration structure
3991 * @note This function must be called before starting the timer and before
3992 * enabling faults inputs
3993 * @retval HAL status
3994 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultCfgTypeDef * pFaultCfg)3995 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
3996 uint32_t Fault,
3997 const HRTIM_FaultCfgTypeDef *pFaultCfg)
3998 {
3999 uint32_t hrtim_fltinr1;
4000 uint32_t hrtim_fltinr2;
4001 uint32_t source0, source1;
4002
4003 /* Check parameters */
4004 assert_param(IS_HRTIM_FAULT(Fault));
4005 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
4006 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
4007 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
4008 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
4009
4010 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4011 {
4012 return HAL_BUSY;
4013 }
4014
4015 /* Process Locked */
4016 __HAL_LOCK(hhrtim);
4017
4018 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4019
4020 /* Configure fault channel */
4021 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
4022 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
4023
4024 source0 = (pFaultCfg->Source & 1U);
4025 source1 = ((pFaultCfg->Source & 2U) >> 1);
4026
4027 switch (Fault)
4028 {
4029 case HRTIM_FAULT_1:
4030 {
4031 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
4032 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
4033 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos);
4034 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1);
4035 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT1SRC_1_Pos);
4036 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
4037 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
4038 break;
4039 }
4040
4041 case HRTIM_FAULT_2:
4042 {
4043 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
4044 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
4045 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos);
4046 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1);
4047 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT2SRC_1_Pos);
4048 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
4049 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
4050 break;
4051 }
4052
4053 case HRTIM_FAULT_3:
4054 {
4055 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
4056 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
4057 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos);
4058 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1);
4059 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT3SRC_1_Pos);
4060 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
4061 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
4062 break;
4063 }
4064
4065 case HRTIM_FAULT_4:
4066 {
4067 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
4068 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
4069 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos);
4070 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1);
4071 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT4SRC_1_Pos);
4072 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
4073 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
4074 break;
4075 }
4076
4077 case HRTIM_FAULT_5:
4078 {
4079 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
4080 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
4081 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos);
4082 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1);
4083 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT5SRC_1_Pos);
4084 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
4085 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
4086 break;
4087 }
4088
4089 case HRTIM_FAULT_6:
4090 {
4091 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK);
4092 hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P);
4093 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos);
4094 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1);
4095 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT6SRC_1_Pos);
4096 hrtim_fltinr2 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR2_FLT6F);
4097 hrtim_fltinr2 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR2_FLT6LCK);
4098 break;
4099 }
4100
4101 default:
4102 {
4103 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4104
4105 /* Process Unlocked */
4106 __HAL_UNLOCK(hhrtim);
4107
4108 break;
4109 }
4110 }
4111
4112 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4113 {
4114 return HAL_ERROR;
4115 }
4116
4117 /* Update the HRTIM registers except LOCK bit */
4118 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
4119 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
4120
4121 /* Update the HRTIM registers LOCK bit */
4122 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
4123 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
4124
4125 hhrtim->State = HAL_HRTIM_STATE_READY;
4126
4127 /* Process Unlocked */
4128 __HAL_UNLOCK(hhrtim);
4129
4130 return HAL_OK;
4131 }
4132
4133 /**
4134 * @brief Configure the fault conditioning block prescaler
4135 * @param hhrtim pointer to HAL HRTIM handle
4136 * @param Prescaler Prescaler value
4137 * This parameter can be one of the following values:
4138 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
4139 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
4140 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
4141 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
4142 * @retval HAL status
4143 * @note This function must be called before starting the timer and before
4144 * enabling faults inputs
4145 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)4146 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
4147 uint32_t Prescaler)
4148 {
4149 /* Check parameters */
4150 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
4151
4152 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4153 {
4154 return HAL_BUSY;
4155 }
4156
4157 /* Process Locked */
4158 __HAL_LOCK(hhrtim);
4159
4160 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4161
4162 /* Set the external event prescaler */
4163 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
4164
4165 hhrtim->State = HAL_HRTIM_STATE_READY;
4166
4167 /* Process Unlocked */
4168 __HAL_UNLOCK(hhrtim);
4169
4170 return HAL_OK;
4171 }
4172
4173 /**
4174 * @brief Configure and Enable the blanking source of a Fault input
4175 * @param hhrtim pointer to HAL HRTIM handle
4176 * @param Fault fault input to configure
4177 * This parameter can be one of the following values:
4178 * @arg HRTIM_FAULT_1: Fault input 1
4179 * @arg HRTIM_FAULT_2: Fault input 2
4180 * @arg HRTIM_FAULT_3: Fault input 3
4181 * @arg HRTIM_FAULT_4: Fault input 4
4182 * @arg HRTIM_FAULT_5: Fault input 5
4183 * @arg HRTIM_FAULT_6: Fault input 6
4184 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4185 * @note This function automatically enables the Blanking on Fault
4186 * @note This function must be called when fault is not enabled
4187 * @retval HAL status
4188 */
HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultBlankingCfgTypeDef * pFaultBlkCfg)4189 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim,
4190 uint32_t Fault,
4191 const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
4192 {
4193 /* Check parameters */
4194 assert_param(IS_HRTIM_FAULT(Fault));
4195 assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource));
4196
4197 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4198 {
4199 return HAL_BUSY;
4200 }
4201
4202 /* Process Locked */
4203 __HAL_LOCK(hhrtim);
4204
4205 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4206
4207 switch (Fault)
4208 {
4209 case HRTIM_FAULT_1:
4210 {
4211 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4212 (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE),
4213 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) |
4214 HRTIM_FLTINR3_FLT1BLKE));
4215 break;
4216 }
4217 case HRTIM_FAULT_2:
4218 {
4219 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4220 (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE),
4221 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) |
4222 HRTIM_FLTINR3_FLT2BLKE));
4223 break;
4224 }
4225 case HRTIM_FAULT_3:
4226 {
4227 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4228 (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE),
4229 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) |
4230 HRTIM_FLTINR3_FLT3BLKE));
4231 break;
4232 }
4233 case HRTIM_FAULT_4:
4234 {
4235 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4236 (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE),
4237 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) |
4238 HRTIM_FLTINR3_FLT4BLKE));
4239 break;
4240 }
4241 case HRTIM_FAULT_5:
4242 {
4243 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4244 (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE),
4245 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) |
4246 HRTIM_FLTINR4_FLT5BLKE));
4247 break;
4248 }
4249 case HRTIM_FAULT_6:
4250 {
4251 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4252 (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE),
4253 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) |
4254 HRTIM_FLTINR4_FLT6BLKE));
4255 break;
4256 }
4257
4258 default:
4259 {
4260 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4261
4262 /* Process Unlocked */
4263 __HAL_UNLOCK(hhrtim);
4264
4265 break;
4266 }
4267 }
4268
4269 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4270 {
4271 return HAL_ERROR;
4272 }
4273
4274 hhrtim->State = HAL_HRTIM_STATE_READY;
4275
4276 /* Process Unlocked */
4277 __HAL_UNLOCK(hhrtim);
4278
4279 return HAL_OK;
4280 }
4281
4282 /**
4283 * @brief Configure the Fault Counter (Threshold and Reset Mode)
4284 * @param hhrtim pointer to HAL HRTIM handle
4285 * @param Fault fault input to configure
4286 * This parameter can be one of the following values:
4287 * @arg HRTIM_FAULT_1: Fault input 1
4288 * @arg HRTIM_FAULT_2: Fault input 2
4289 * @arg HRTIM_FAULT_3: Fault input 3
4290 * @arg HRTIM_FAULT_4: Fault input 4
4291 * @arg HRTIM_FAULT_5: Fault input 5
4292 * @arg HRTIM_FAULT_6: Fault input 6
4293 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4294 * @retval HAL status
4295 * @note A fault is considered valid when the number of
4296 * events is equal to the (FLTxCNT[3:0]+1) value
4297 *
4298 * @retval HAL status
4299 */
HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,const HRTIM_FaultBlankingCfgTypeDef * pFaultBlkCfg)4300 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim,
4301 uint32_t Fault,
4302 const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
4303 {
4304 /* Check parameters */
4305 assert_param(IS_HRTIM_FAULT(Fault));
4306 assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold));
4307 assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode));
4308
4309 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4310 {
4311 return HAL_BUSY;
4312 }
4313
4314 /* Process Locked */
4315 __HAL_LOCK(hhrtim);
4316
4317 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4318
4319 switch (Fault)
4320 {
4321 case HRTIM_FAULT_1:
4322 {
4323 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4324 (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT),
4325 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) |
4326 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos));
4327 break;
4328 }
4329 case HRTIM_FAULT_2:
4330 {
4331 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4332 (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT),
4333 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) |
4334 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos));
4335 break;
4336 }
4337 case HRTIM_FAULT_3:
4338 {
4339 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4340 (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT),
4341 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) |
4342 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos));
4343 break;
4344 }
4345 case HRTIM_FAULT_4:
4346 {
4347 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4348 (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT),
4349 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) |
4350 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos));
4351 break;
4352 }
4353 case HRTIM_FAULT_5:
4354 {
4355 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4356 (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT),
4357 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) |
4358 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos));
4359 break;
4360 }
4361 case HRTIM_FAULT_6:
4362 {
4363 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4364 (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT),
4365 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) |
4366 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos));
4367 break;
4368 }
4369
4370 default:
4371 {
4372 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4373
4374 /* Process Unlocked */
4375 __HAL_UNLOCK(hhrtim);
4376
4377 break;
4378 }
4379 }
4380
4381 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4382 {
4383 return HAL_ERROR;
4384 }
4385
4386 hhrtim->State = HAL_HRTIM_STATE_READY;
4387
4388 /* Process Unlocked */
4389 __HAL_UNLOCK(hhrtim);
4390
4391 return HAL_OK;
4392 }
4393
4394 /**
4395 * @brief Reset the fault Counter Reset
4396 * @param hhrtim pointer to HAL HRTIM handle
4397 * @param Fault fault input to reset
4398 * This parameter can be one of the following values:
4399 * @arg HRTIM_FAULT_1: Fault input 1
4400 * @arg HRTIM_FAULT_2: Fault input 2
4401 * @arg HRTIM_FAULT_3: Fault input 3
4402 * @arg HRTIM_FAULT_4: Fault input 4
4403 * @arg HRTIM_FAULT_5: Fault input 5
4404 * @arg HRTIM_FAULT_6: Fault input 6
4405 * @retval HAL status
4406 */
HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault)4407 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim,
4408 uint32_t Fault)
4409 {
4410 /* Check parameters */
4411 assert_param(IS_HRTIM_FAULT(Fault));
4412
4413 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4414 {
4415 return HAL_BUSY;
4416 }
4417
4418 /* Process Locked */
4419 __HAL_LOCK(hhrtim);
4420
4421 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4422
4423 switch (Fault)
4424 {
4425 case HRTIM_FAULT_1:
4426 {
4427 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ;
4428 break;
4429 }
4430 case HRTIM_FAULT_2:
4431 {
4432 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ;
4433 break;
4434 }
4435 case HRTIM_FAULT_3:
4436 {
4437 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ;
4438 break;
4439 }
4440 case HRTIM_FAULT_4:
4441 {
4442 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ;
4443 break;
4444 }
4445 case HRTIM_FAULT_5:
4446 {
4447 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ;
4448 break;
4449 }
4450 case HRTIM_FAULT_6:
4451 {
4452 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ;
4453 break;
4454 }
4455
4456 default:
4457 {
4458 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4459
4460 /* Process Unlocked */
4461 __HAL_UNLOCK(hhrtim);
4462
4463 break;
4464 }
4465 }
4466
4467 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4468 {
4469 return HAL_ERROR;
4470 }
4471
4472 hhrtim->State = HAL_HRTIM_STATE_READY;
4473
4474 /* Process Unlocked */
4475 __HAL_UNLOCK(hhrtim);
4476
4477 return HAL_OK;
4478 }
4479
4480 /**
4481 * @brief Enable or disables the HRTIMx Fault mode.
4482 * @param hhrtim pointer to HAL HRTIM handle
4483 * @param Faults fault input(s) to enable or disable
4484 * This parameter can be any combination of the following values:
4485 * @arg HRTIM_FAULT_1: Fault input 1
4486 * @arg HRTIM_FAULT_2: Fault input 2
4487 * @arg HRTIM_FAULT_3: Fault input 3
4488 * @arg HRTIM_FAULT_4: Fault input 4
4489 * @arg HRTIM_FAULT_5: Fault input 5
4490 * @arg HRTIM_FAULT_6: Fault input 6
4491 * @param Enable Fault(s) enabling
4492 * This parameter can be one of the following values:
4493 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
4494 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
4495 * @retval None
4496 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)4497 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim,
4498 uint32_t Faults,
4499 uint32_t Enable)
4500 {
4501 /* Check parameters */
4502 assert_param(IS_HRTIM_FAULT(Faults));
4503 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
4504
4505 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
4506 {
4507 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
4508 }
4509 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
4510 {
4511 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
4512 }
4513 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
4514 {
4515 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
4516 }
4517 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
4518 {
4519 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
4520 }
4521 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
4522 {
4523 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
4524 }
4525 if ((Faults & HRTIM_FAULT_6) != (uint32_t)RESET)
4526 {
4527 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT6E, ((Enable << 8U) & HRTIM_FLTINR2_FLT6E));
4528 }
4529 }
4530
4531 /**
4532 * @brief Configure both the ADC trigger register update source and the ADC
4533 * trigger source.
4534 * @param hhrtim pointer to HAL HRTIM handle
4535 * @param ADCTrigger ADC trigger to configure
4536 * This parameter can be one of the following values:
4537 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4538 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4539 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4540 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4541 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4542 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4543 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4544 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4545 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4546 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4547 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
4548 * for Trigger nb (1..4): pADCTriggerCfg->Trigger parameter
4549 * can be a combination of the following values
4550 * @arg HRTIM_ADCTRIGGEREVENT13_...
4551 * @arg HRTIM_ADCTRIGGEREVENT24_...
4552 * for Trigger nb (5..10): pADCTriggerCfg->Trigger parameter
4553 * can be one of the following values
4554 * @arg HRTIM_ADCTRIGGEREVENT579_...
4555 * @arg HRTIM_ADCTRIGGEREVENT6810_...
4556 * @retval HAL status
4557 * @note This function must be called before starting the timer
4558 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,const HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)4559 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
4560 uint32_t ADCTrigger,
4561 const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
4562 {
4563 uint32_t hrtim_cr1;
4564 uint32_t hrtim_adcur;
4565
4566 /* Check parameters */
4567 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4568 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
4569
4570 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4571 {
4572 return HAL_BUSY;
4573 }
4574
4575 /* Process Locked */
4576 __HAL_LOCK(hhrtim);
4577
4578 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4579
4580 /* Set the ADC trigger update source */
4581 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
4582 hrtim_adcur = hhrtim->Instance->sCommonRegs.ADCUR;
4583
4584 switch (ADCTrigger)
4585 {
4586 case HRTIM_ADCTRIGGER_1:
4587 {
4588 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
4589 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
4590
4591 /* Set the ADC trigger 1 source */
4592 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
4593 break;
4594 }
4595
4596 case HRTIM_ADCTRIGGER_2:
4597 {
4598 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
4599 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4600
4601 /* Set the ADC trigger 2 source */
4602 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4603 break;
4604 }
4605
4606 case HRTIM_ADCTRIGGER_3:
4607 {
4608 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4609 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4610
4611 /* Set the ADC trigger 3 source */
4612 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4613 break;
4614 }
4615
4616 case HRTIM_ADCTRIGGER_4:
4617 {
4618 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4619 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4620
4621 /* Set the ADC trigger 4 source */
4622 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4623 break;
4624 }
4625
4626 case HRTIM_ADCTRIGGER_5:
4627 {
4628 hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC);
4629 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC);
4630
4631 /* Set the ADC trigger 5 source */
4632 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD5TRG);
4633 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD5TRG_Pos) & HRTIM_ADCER_AD5TRG);
4634 break;
4635 }
4636
4637 case HRTIM_ADCTRIGGER_6:
4638 {
4639 hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC);
4640 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC);
4641
4642 /* Set the ADC trigger 6 source */
4643 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD6TRG);
4644 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD6TRG_Pos) & HRTIM_ADCER_AD6TRG);
4645 break;
4646 }
4647
4648 case HRTIM_ADCTRIGGER_7:
4649 {
4650 hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC);
4651 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC);
4652
4653 /* Set the ADC trigger 7 source */
4654 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD7TRG);
4655 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD7TRG_Pos) & HRTIM_ADCER_AD7TRG);
4656 break;
4657 }
4658
4659 case HRTIM_ADCTRIGGER_8:
4660 {
4661 hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC);
4662 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC);
4663
4664 /* Set the ADC trigger 8 source */
4665 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD8TRG);
4666 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD8TRG_Pos) & HRTIM_ADCER_AD8TRG);
4667 break;
4668 }
4669
4670 case HRTIM_ADCTRIGGER_9:
4671 {
4672 hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC);
4673 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC);
4674
4675 /* Set the ADC trigger 9 source */
4676 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD9TRG);
4677 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD9TRG_Pos) & HRTIM_ADCER_AD9TRG);
4678 break;
4679 }
4680
4681 case HRTIM_ADCTRIGGER_10:
4682 {
4683 hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC);
4684 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC);
4685
4686 /* Set the ADC trigger 10 source */
4687 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD10TRG);
4688 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD10TRG_Pos) & HRTIM_ADCER_AD10TRG);
4689 break;
4690 }
4691
4692 default:
4693 {
4694 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4695
4696 /* Process Unlocked */
4697 __HAL_UNLOCK(hhrtim);
4698
4699 break;
4700 }
4701 }
4702
4703 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4704 {
4705 return HAL_ERROR;
4706 }
4707
4708 /* Update the HRTIM registers */
4709 if (ADCTrigger < HRTIM_ADCTRIGGER_5)
4710 {
4711 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4712 }
4713 else
4714 {
4715 hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur;
4716 }
4717
4718 hhrtim->State = HAL_HRTIM_STATE_READY;
4719
4720 /* Process Unlocked */
4721 __HAL_UNLOCK(hhrtim);
4722
4723 return HAL_OK;
4724 }
4725
4726 /**
4727 * @brief Configure the ADC trigger postscaler register of the ADC
4728 * trigger source.
4729 * @param hhrtim pointer to HAL HRTIM handle
4730 * @param ADCTrigger ADC trigger to configure
4731 * This parameter can be one of the following values:
4732 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4733 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4734 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4735 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4736 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4737 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4738 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4739 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4740 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4741 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4742 * @param Postscaler value 0..1F
4743 * @retval HAL status
4744 * @note This function must be called before starting the timer
4745 */
HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,uint32_t Postscaler)4746 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim,
4747 uint32_t ADCTrigger,
4748 uint32_t Postscaler)
4749 {
4750 /* Check parameters */
4751 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4752
4753 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4754 {
4755 return HAL_BUSY;
4756 }
4757
4758 /* Process Locked */
4759 __HAL_LOCK(hhrtim);
4760
4761 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4762
4763 switch (ADCTrigger)
4764 {
4765 case HRTIM_ADCTRIGGER_1:
4766 {
4767 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC));
4768 break;
4769 }
4770
4771 case HRTIM_ADCTRIGGER_2:
4772 {
4773 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC));
4774 break;
4775 }
4776
4777 case HRTIM_ADCTRIGGER_3:
4778 {
4779 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC));
4780 break;
4781 }
4782
4783 case HRTIM_ADCTRIGGER_4:
4784 {
4785 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC));
4786 break;
4787 }
4788
4789 case HRTIM_ADCTRIGGER_5:
4790 {
4791 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC));
4792 break;
4793 }
4794
4795 case HRTIM_ADCTRIGGER_6:
4796 {
4797 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC));
4798 break;
4799 }
4800
4801 case HRTIM_ADCTRIGGER_7:
4802 {
4803 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC));
4804 break;
4805 }
4806
4807 case HRTIM_ADCTRIGGER_8:
4808 {
4809 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC));
4810 break;
4811 }
4812
4813 case HRTIM_ADCTRIGGER_9:
4814 {
4815 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC));
4816 break;
4817 }
4818
4819 case HRTIM_ADCTRIGGER_10:
4820 {
4821 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC));
4822 break;
4823 }
4824
4825 default:
4826 {
4827 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4828
4829 /* Process Unlocked */
4830 __HAL_UNLOCK(hhrtim);
4831
4832 break;
4833 }
4834 }
4835
4836 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
4837 {
4838 return HAL_ERROR;
4839 }
4840
4841 hhrtim->State = HAL_HRTIM_STATE_READY;
4842
4843 /* Process Unlocked */
4844 __HAL_UNLOCK(hhrtim);
4845
4846 return HAL_OK;
4847 }
4848
4849 /**
4850 * @brief Configure the ADC Roll-Over mode of the ADC
4851 * trigger source.
4852 * @param hhrtim pointer to HAL HRTIM handle
4853 * @param TimerIdx Timer index
4854 * This parameter can be one of the following values:
4855 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4856 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4857 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4858 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4859 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4860 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4861 * @param RollOverCfg This parameter can be a combination of all the following values:
4862 * @arg HRTIM_TIM_FEROM_BOTH or HRTIM_TIM_FEROM_CREST or HRTIM_TIM_FEROM_VALLEY
4863 * @arg HRTIM_TIM_BMROM_BOTH or HRTIM_TIM_BMROM_CREST or HRTIM_TIM_BMROM_VALLEY
4864 * @arg HRTIM_TIM_ADROM_BOTH or HRTIM_TIM_ADROM_CREST or HRTIM_TIM_ADROM_VALLEY
4865 * @arg HRTIM_TIM_OUTROM_BOTH or HRTIM_TIM_OUTROM_CREST or HRTIM_TIM_OUTROM_VALLEY
4866 * @arg HRTIM_TIM_ROM_BOTH or HRTIM_TIM_ROM_CREST or HRTIM_TIM_ROM_VALLEY
4867 * @note This function must be called before starting the timer
4868 */
HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RollOverCfg)4869 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim,
4870 uint32_t TimerIdx,
4871 uint32_t RollOverCfg)
4872 {
4873 /* Check parameters */
4874 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4875 assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg));
4876
4877 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4878 {
4879 return HAL_BUSY;
4880 }
4881
4882 /* Process Locked */
4883 __HAL_LOCK(hhrtim);
4884
4885 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4886
4887 HRTIM_TimingUnitRollOver_Config(hhrtim, TimerIdx, RollOverCfg);
4888
4889 hhrtim->State = HAL_HRTIM_STATE_READY;
4890
4891 /* Process Unlocked */
4892 __HAL_UNLOCK(hhrtim);
4893
4894 return HAL_OK;
4895 }
4896
4897
4898 /**
4899 * @}
4900 */
4901
4902 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4903 * @brief HRTIM timer configuration and control functions
4904 @verbatim
4905 ===============================================================================
4906 ##### HRTIM timer configuration and control functions #####
4907 ===============================================================================
4908 [..] This section provides functions used to configure and control a
4909 HRTIM timer operating in waveform mode:
4910 (+) Configure HRTIM timer general behavior
4911 (+) Configure HRTIM timer event filtering
4912 (+) Configure HRTIM timer deadtime insertion
4913 (+) Configure HRTIM timer chopper mode
4914 (+) Configure HRTIM timer burst DMA
4915 (+) Configure HRTIM timer compare unit
4916 (+) Configure HRTIM timer capture unit
4917 (+) Configure HRTIM timer output
4918 (+) Set HRTIM timer output level
4919 (+) Enable HRTIM timer output
4920 (+) Disable HRTIM timer output
4921 (+) Start HRTIM timer
4922 (+) Stop HRTIM timer
4923 (+) Start HRTIM timer and enable interrupt
4924 (+) Stop HRTIM timer and disable interrupt
4925 (+) Start HRTIM timer and enable DMA transfer
4926 (+) Stop HRTIM timer and disable DMA transfer
4927 (+) Enable or disable the burst mode controller
4928 (+) Start the burst mode controller (by software)
4929 (+) Trigger a Capture (by software)
4930 (+) Update the HRTIM timer preloadable registers (by software)
4931 (+) Reset the HRTIM timer counter (by software)
4932 (+) Start a burst DMA transfer
4933 (+) Enable timer register update
4934 (+) Disable timer register update
4935
4936 @endverbatim
4937 * @{
4938 */
4939
4940 /**
4941 * @brief Configure the general behavior of a timer operating in waveform mode
4942 * @param hhrtim pointer to HAL HRTIM handle
4943 * @param TimerIdx Timer index
4944 * This parameter can be one of the following values:
4945 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4946 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4947 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4948 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4949 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4950 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4951 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4952 * @param pTimerCfg pointer to the timer configuration structure
4953 * @note When the timer operates in waveform mode, all the features supported by
4954 * the HRTIM are available without any limitation.
4955 * @retval HAL status
4956 * @note This function must be called before starting the timer
4957 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)4958 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
4959 uint32_t TimerIdx,
4960 const HRTIM_TimerCfgTypeDef *pTimerCfg)
4961 {
4962 /* Check parameters */
4963 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4964
4965 /* Relevant for all HRTIM timers, including the master */
4966 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4967 assert_param(IS_HRTIM_INTERLEAVEDMODE(pTimerCfg->InterleavedMode));
4968 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4969 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4970 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4971 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4972 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4973 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4974
4975 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
4976 {
4977 return HAL_BUSY;
4978 }
4979
4980 /* Process Locked */
4981 __HAL_LOCK(hhrtim);
4982
4983 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4984
4985 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4986 {
4987 /* Check parameters */
4988 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4989 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4990 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4991
4992 /* Configure master timer */
4993 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4994 }
4995 else
4996 {
4997 /* Check parameters */
4998 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4999 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
5000 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
5001 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
5002 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
5003 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
5004 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
5005 pTimerCfg->DeadTimeInsertion));
5006 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
5007 pTimerCfg->DelayedProtectionMode));
5008 assert_param(IS_HRTIM_OUTPUTBALANCEDIDLE(pTimerCfg->BalancedIdleAutomaticResume));
5009 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
5010 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
5011 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
5012 assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
5013
5014 /* Configure timing unit */
5015 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
5016 }
5017
5018 /* Update timer parameters */
5019 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
5020 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
5021 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
5022 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
5023 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
5024
5025 /* Force a software update */
5026 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
5027
5028 /* Configure slave timer update re-synchronization */
5029 if ((TimerIdx != HRTIM_TIMERINDEX_MASTER)
5030 && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT))
5031 {
5032 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR,
5033 HRTIM_TIMCR_RSYNCU_Msk,
5034 pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos);
5035 }
5036
5037 hhrtim->State = HAL_HRTIM_STATE_READY;
5038
5039 /* Process Unlocked */
5040 __HAL_UNLOCK(hhrtim);
5041
5042 return HAL_OK;
5043 }
5044
5045 /**
5046 * @brief Configure the general behavior of a timer operating in waveform mode
5047 * @param hhrtim pointer to HAL HRTIM handle
5048 * @param TimerIdx Timer index
5049 * This parameter can be one of the following values:
5050 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5051 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5052 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5053 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5054 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5055 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5056 * @param pTimerCtl pointer to the timer configuration structure
5057 * @note When the timer operates in waveform mode, all the features supported by
5058 * the HRTIM are available without any limitation.
5059 * @retval HAL status
5060 * @note This function must be called before starting the timer
5061 */
HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCtlTypeDef * pTimerCtl)5062 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim,
5063 uint32_t TimerIdx,
5064 const HRTIM_TimerCtlTypeDef *pTimerCtl)
5065 {
5066 /* Check parameters */
5067 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5068 /* Relevant for all A..F HRTIM timers */
5069 assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode));
5070 assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf));
5071 assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3));
5072 assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
5073 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5074 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5075 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5076
5077 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5078 {
5079 return HAL_BUSY;
5080 }
5081
5082 /* Process Locked */
5083 __HAL_LOCK(hhrtim);
5084
5085 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5086
5087 /* Configure timing unit */
5088 HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
5089
5090 /* Force a software update */
5091 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
5092
5093 hhrtim->State = HAL_HRTIM_STATE_READY;
5094
5095 /* Process Unlocked */
5096 __HAL_UNLOCK(hhrtim);
5097
5098 return HAL_OK;
5099 }
5100
5101 /**
5102 * @brief Configure the Dual Channel Dac behavior of a timer operating in waveform mode
5103 * @param hhrtim: pointer to HAL HRTIM handle
5104 * @param TimerIdx Timer index
5105 * This parameter can be one of the following values:
5106 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5107 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5108 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5109 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5110 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5111 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5112 * @param pTimerCtl pointer to the timer DualChannel Dac configuration structure
5113 * @note When the timer operates in waveform mode, all the features supported by
5114 * the HRTIM are available without any limitation.
5115 * @retval HAL status
5116 * @note This function must be called before starting the timer
5117 */
HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCtlTypeDef * pTimerCtl)5118 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim,
5119 uint32_t TimerIdx,
5120 const HRTIM_TimerCtlTypeDef *pTimerCtl)
5121 {
5122 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5123 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5124 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5125
5126 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5127 {
5128 return HAL_BUSY;
5129 }
5130
5131 /* Process Locked */
5132 __HAL_LOCK(hhrtim);
5133
5134 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5135 /* clear DCDS,DCDR,DCDE bits */
5136 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
5137 (HRTIM_TIMER_DCDE_ENABLED |
5138 HRTIM_TIMER_DCDS_OUT1RST |
5139 HRTIM_TIMER_DCDR_OUT1SET));
5140
5141 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
5142 (HRTIM_TIMER_DCDE_ENABLED |
5143 HRTIM_TIMER_DCDS_OUT1RST |
5144 HRTIM_TIMER_DCDR_OUT1SET),
5145 (pTimerCtl->DualChannelDacReset |
5146 pTimerCtl->DualChannelDacStep |
5147 pTimerCtl->DualChannelDacEnable));
5148
5149 hhrtim->State = HAL_HRTIM_STATE_READY;
5150
5151 /* Process Unlocked */
5152 __HAL_UNLOCK(hhrtim);
5153
5154 return HAL_OK;
5155 }
5156
5157 /**
5158 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
5159 * @param hhrtim pointer to HAL HRTIM handle
5160 * @param TimerIdx Timer index
5161 * This parameter can be one of the following values:
5162 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5163 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5164 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5165 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5166 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5167 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5168 * @param Event external event for which timer event filtering must be configured
5169 * This parameter can be one of the following values:
5170 * @arg HRTIM_EVENT_1: External event 1
5171 * @arg HRTIM_EVENT_2: External event 2
5172 * @arg HRTIM_EVENT_3: External event 3
5173 * @arg HRTIM_EVENT_4: External event 4
5174 * @arg HRTIM_EVENT_5: External event 5
5175 * @arg HRTIM_EVENT_6: External event 6
5176 * @arg HRTIM_EVENT_7: External event 7
5177 * @arg HRTIM_EVENT_8: External event 8
5178 * @arg HRTIM_EVENT_9: External event 9
5179 * @arg HRTIM_EVENT_10: External event 10
5180 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
5181 * @note This function must be called before starting the timer
5182 * @retval HAL status
5183 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)5184 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
5185 uint32_t TimerIdx,
5186 uint32_t Event,
5187 const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
5188 {
5189 /* Check parameters */
5190 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5191 assert_param(IS_HRTIM_EVENT(Event));
5192 assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx, pTimerEventFilteringCfg->Filter));
5193
5194 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
5195
5196 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5197 {
5198 return HAL_BUSY;
5199 }
5200
5201 /* Process Locked */
5202 __HAL_LOCK(hhrtim);
5203
5204 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5205
5206 /* Configure timer event filtering capabilities */
5207 switch (Event)
5208 {
5209 case HRTIM_EVENT_NONE:
5210 {
5211 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
5212 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
5213 break;
5214 }
5215
5216 case HRTIM_EVENT_1:
5217 {
5218 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH),
5219 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
5220 break;
5221 }
5222
5223 case HRTIM_EVENT_2:
5224 {
5225 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH),
5226 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
5227 break;
5228 }
5229
5230 case HRTIM_EVENT_3:
5231 {
5232 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH),
5233 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
5234 break;
5235 }
5236
5237 case HRTIM_EVENT_4:
5238 {
5239 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH),
5240 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
5241 break;
5242 }
5243
5244 case HRTIM_EVENT_5:
5245 {
5246 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH),
5247 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
5248 break;
5249 }
5250
5251 case HRTIM_EVENT_6:
5252 {
5253 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH),
5254 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
5255 break;
5256 }
5257
5258 case HRTIM_EVENT_7:
5259 {
5260 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH),
5261 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
5262 break;
5263 }
5264
5265 case HRTIM_EVENT_8:
5266 {
5267 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH),
5268 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
5269 break;
5270 }
5271
5272 case HRTIM_EVENT_9:
5273 {
5274 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH),
5275 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
5276 break;
5277 }
5278
5279 case HRTIM_EVENT_10:
5280 {
5281 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH),
5282 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
5283 break;
5284 }
5285
5286 default:
5287 {
5288 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5289
5290 /* Process Unlocked */
5291 __HAL_UNLOCK(hhrtim);
5292
5293 break;
5294 }
5295 }
5296
5297 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5298 {
5299 return HAL_ERROR;
5300 }
5301
5302 hhrtim->State = HAL_HRTIM_STATE_READY;
5303
5304 /* Process Unlocked */
5305 __HAL_UNLOCK(hhrtim);
5306
5307 return HAL_OK;
5308 }
5309
5310 /**
5311 * @brief Configure the external Event Counter A or B of a timer (source, threshold, reset mode)
5312 * but does not enable : call HAL_HRTIM_ExternalEventCounterEnable afterwards
5313 * @param hhrtim pointer to HAL HRTIM handle
5314 * @param TimerIdx Timer index
5315 * This parameter can be one of the following values:
5316 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5317 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5318 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5319 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5320 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5321 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5322 * @param EventCounter external event Counter A or B for which timer event must be configured
5323 * This parameter can be one of the following values:
5324 * @arg HRTIM_EVENTCOUNTER_A
5325 * @arg HRTIM_EVENTCOUNTER_B
5326 * @param pTimerExternalEventCfg: pointer to the timer external event configuration structure
5327 * @note This function must be called before starting the timer
5328 * @retval HAL status
5329 */
HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter,const HRTIM_ExternalEventCfgTypeDef * pTimerExternalEventCfg)5330 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim,
5331 uint32_t TimerIdx,
5332 uint32_t EventCounter,
5333 const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg)
5334 {
5335 uint32_t hrtim_eefr3;
5336
5337 /* Check parameters */
5338 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5339 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5340 assert_param(IS_HRTIM_TIMEEVENT_RESETMODE(pTimerExternalEventCfg->ResetMode));
5341 assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter));
5342 assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source));
5343
5344 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5345 {
5346 return HAL_BUSY;
5347 }
5348
5349 /* Process Locked */
5350 __HAL_LOCK(hhrtim);
5351
5352 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5353
5354 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5355 {
5356 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5357 {
5358 /* reset External EventCounter A */
5359 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U);
5360 }
5361 else
5362 {
5363 /* Set timer External EventCounter A configuration */
5364 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos;
5365 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos;
5366 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos;
5367 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5368
5369 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,
5370 (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT), hrtim_eefr3);
5371 }
5372 }
5373
5374 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5375 {
5376 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5377 {
5378 /* reset External EventCounter B */
5379 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU);
5380 }
5381 else
5382 {
5383 /* Set timer External EventCounter B configuration */
5384 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos;
5385 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos;
5386 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos;
5387 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5388
5389 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,
5390 (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT), hrtim_eefr3);
5391 }
5392 }
5393 hhrtim->State = HAL_HRTIM_STATE_READY;
5394
5395 /* Process Unlocked */
5396 __HAL_UNLOCK(hhrtim);
5397
5398 return HAL_OK;
5399 }
5400
5401 /**
5402 * @brief Enable the external event Counter A or B of a timer
5403 * @param hhrtim: pointer to HAL HRTIM handle
5404 * @param TimerIdx: Timer index
5405 * This parameter can be one of the following values:
5406 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5407 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5408 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5409 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5410 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5411 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5412 * @param EventCounter external Event Counter A or B for which timer event must be configured
5413 * This parameter can be a one of the following values:
5414 * @arg HRTIM_EVENTCOUNTER_A
5415 * @arg HRTIM_EVENTCOUNTER_B
5416 * @note This function must be called before starting the timer
5417 * @retval HAL status
5418 */
HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5419 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim,
5420 uint32_t TimerIdx,
5421 uint32_t EventCounter)
5422 {
5423 /* Check parameters */
5424 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5425 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5426
5427 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5428 {
5429 return HAL_BUSY;
5430 }
5431
5432 /* Process Locked */
5433 __HAL_LOCK(hhrtim);
5434
5435 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5436
5437 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5438 {
5439 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5440 }
5441 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5442 {
5443 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5444 }
5445
5446 hhrtim->State = HAL_HRTIM_STATE_READY;
5447
5448 /* Process Unlocked */
5449 __HAL_UNLOCK(hhrtim);
5450
5451 return HAL_OK;
5452 }
5453
5454 /**
5455 * @brief Disable the external event Counter A or B of a timer
5456 * @param hhrtim: pointer to HAL HRTIM handle
5457 * @param TimerIdx: Timer index
5458 * This parameter can be one of the following values:
5459 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5460 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5461 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5462 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5463 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5464 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5465 * @param EventCounter external event Counter A or B for which timer event must be configured
5466 * This parameter can be a one of the following values:
5467 * @arg HRTIM_EVENTCOUNTER_A
5468 * @arg HRTIM_EVENTCOUNTER_B
5469 * @retval HAL status
5470 */
HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5471 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim,
5472 uint32_t TimerIdx,
5473 uint32_t EventCounter)
5474 {
5475 /* Check parameters */
5476 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5477 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5478
5479 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5480 {
5481 return HAL_BUSY;
5482 }
5483
5484 /* Process Locked */
5485 __HAL_LOCK(hhrtim);
5486
5487 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5488
5489 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5490 {
5491 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5492 }
5493
5494 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5495 {
5496 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5497 }
5498
5499 hhrtim->State = HAL_HRTIM_STATE_READY;
5500
5501 /* Process Unlocked */
5502 __HAL_UNLOCK(hhrtim);
5503
5504 return HAL_OK;
5505 }
5506
5507 /**
5508 * @brief Reset the external event Counter A or B of a timer
5509 * @param hhrtim pointer to HAL HRTIM handle
5510 * @param TimerIdx Timer index
5511 * This parameter can be one of the following values:
5512 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5513 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5514 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5515 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5516 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5517 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5518 * @param EventCounter external event Counter A or B for which timer event must be configured
5519 * This parameter can be one of the following values:
5520 * @arg HRTIM_EVENTCOUNTER_A
5521 * @arg HRTIM_EVENTCOUNTER_B
5522 * @note This function must be called before starting the timer
5523 * @retval HAL status
5524 */
HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5525 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim,
5526 uint32_t TimerIdx,
5527 uint32_t EventCounter)
5528 {
5529 /* Check parameters */
5530 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5531 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5532
5533 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5534 {
5535 return HAL_BUSY;
5536 }
5537
5538 /* Process Locked */
5539 __HAL_LOCK(hhrtim);
5540
5541 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5542
5543 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5544 {
5545 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES);
5546 }
5547 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5548 {
5549 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCRES);
5550 }
5551
5552 hhrtim->State = HAL_HRTIM_STATE_READY;
5553
5554 /* Process Unlocked */
5555 __HAL_UNLOCK(hhrtim);
5556
5557 return HAL_OK;
5558 }
5559
5560 /**
5561 * @brief Configure the dead-time insertion feature for a timer
5562 * @param hhrtim pointer to HAL HRTIM handle
5563 * @param TimerIdx Timer index
5564 * This parameter can be one of the following values:
5565 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5566 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5567 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5568 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5569 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5570 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5571 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
5572 * @retval HAL status
5573 * @note This function must be called before starting the timer
5574 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)5575 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
5576 uint32_t TimerIdx,
5577 const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
5578 {
5579 uint32_t hrtim_dtr;
5580
5581 /* Check parameters */
5582 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5583 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
5584 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
5585 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
5586 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
5587 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
5588 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
5589 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
5590
5591 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5592 {
5593 return HAL_BUSY;
5594 }
5595
5596 /* Process Locked */
5597 __HAL_LOCK(hhrtim);
5598
5599 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5600
5601 /* Set timer deadtime configuration */
5602 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
5603 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
5604 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
5605 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
5606 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
5607 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
5608 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
5609 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
5610 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
5611
5612 /* Update the HRTIM registers */
5613 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
5614 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
5615 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
5616 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
5617
5618 hhrtim->State = HAL_HRTIM_STATE_READY;
5619
5620 /* Process Unlocked */
5621 __HAL_UNLOCK(hhrtim);
5622
5623 return HAL_OK;
5624 }
5625
5626 /**
5627 * @brief Configure the chopper mode feature for a timer
5628 * @param hhrtim pointer to HAL HRTIM handle
5629 * @param TimerIdx Timer index
5630 * This parameter can be one of the following values:
5631 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5632 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5633 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5634 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5635 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5636 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5637 * @param pChopperModeCfg pointer to the chopper mode configuration structure
5638 * @retval HAL status
5639 * @note This function must be called before configuring the timer output(s)
5640 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)5641 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
5642 uint32_t TimerIdx,
5643 const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
5644 {
5645 uint32_t hrtim_chpr;
5646
5647 /* Check parameters */
5648 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5649 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
5650 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
5651 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
5652
5653 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5654 {
5655 return HAL_BUSY;
5656 }
5657
5658 /* Process Locked */
5659 __HAL_LOCK(hhrtim);
5660
5661 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5662
5663 /* Set timer choppe mode configuration */
5664 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
5665 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
5666 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
5667
5668 /* Update the HRTIM registers */
5669 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
5670 (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
5671 hrtim_chpr);
5672
5673 hhrtim->State = HAL_HRTIM_STATE_READY;
5674
5675 /* Process Unlocked */
5676 __HAL_UNLOCK(hhrtim);
5677
5678 return HAL_OK;
5679 }
5680
5681 /**
5682 * @brief Configure the burst DMA controller for a timer
5683 * @param hhrtim pointer to HAL HRTIM handle
5684 * @param TimerIdx Timer index
5685 * This parameter can be one of the following values:
5686 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5687 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5688 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5689 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5690 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5691 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5692 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5693 * @param RegistersToUpdate registers to be written by DMA
5694 * This parameter can be any combination of the following values:
5695 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
5696 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
5697 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
5698 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
5699 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
5700 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
5701 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
5702 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
5703 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
5704 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
5705 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
5706 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
5707 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
5708 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
5709 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
5710 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
5711 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
5712 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
5713 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
5714 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
5715 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
5716 * @retval HAL status
5717 * @note This function must be called before starting the timer
5718 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)5719 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
5720 uint32_t TimerIdx,
5721 uint32_t RegistersToUpdate)
5722 {
5723 /* Check parameters */
5724 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
5725
5726 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5727 {
5728 return HAL_BUSY;
5729 }
5730
5731 /* Process Locked */
5732 __HAL_LOCK(hhrtim);
5733
5734 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5735
5736 /* Set the burst DMA timer update register */
5737 switch (TimerIdx)
5738 {
5739 case HRTIM_TIMERINDEX_TIMER_A:
5740 {
5741 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
5742 break;
5743 }
5744
5745 case HRTIM_TIMERINDEX_TIMER_B:
5746 {
5747 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
5748 break;
5749 }
5750
5751 case HRTIM_TIMERINDEX_TIMER_C:
5752 {
5753 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
5754 break;
5755 }
5756
5757 case HRTIM_TIMERINDEX_TIMER_D:
5758 {
5759 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
5760 break;
5761 }
5762
5763 case HRTIM_TIMERINDEX_TIMER_E:
5764 {
5765 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
5766 break;
5767 }
5768
5769 case HRTIM_TIMERINDEX_TIMER_F:
5770 {
5771 hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate;
5772 break;
5773 }
5774
5775 case HRTIM_TIMERINDEX_MASTER:
5776 {
5777 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
5778 break;
5779 }
5780
5781 default:
5782 {
5783 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5784
5785 /* Process Unlocked */
5786 __HAL_UNLOCK(hhrtim);
5787
5788 break;
5789 }
5790 }
5791
5792 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5793 {
5794 return HAL_ERROR;
5795 }
5796
5797 hhrtim->State = HAL_HRTIM_STATE_READY;
5798
5799 /* Process Unlocked */
5800 __HAL_UNLOCK(hhrtim);
5801
5802 return HAL_OK;
5803 }
5804
5805 /**
5806 * @brief Configure the compare unit of a timer operating in waveform mode
5807 * @param hhrtim pointer to HAL HRTIM handle
5808 * @param TimerIdx Timer index
5809 * This parameter can be one of the following values:
5810 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5811 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5812 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5813 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5814 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5815 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5816 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5817 * @param CompareUnit Compare unit to configure
5818 * This parameter can be one of the following values:
5819 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
5820 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
5821 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
5822 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
5823 * @param pCompareCfg pointer to the compare unit configuration structure
5824 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
5825 * application has to configure separately the capture unit. Capture unit
5826 * to configure in that case depends on the compare unit auto delayed mode
5827 * is applied to (see below):
5828 * Auto delayed on output compare 2: capture unit 1 must be configured
5829 * Auto delayed on output compare 4: capture unit 2 must be configured
5830 * @retval HAL status
5831 * @note This function must be called before starting the timer
5832 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,const HRTIM_CompareCfgTypeDef * pCompareCfg)5833 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
5834 uint32_t TimerIdx,
5835 uint32_t CompareUnit,
5836 const HRTIM_CompareCfgTypeDef *pCompareCfg)
5837 {
5838 /* Check parameters */
5839 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5840
5841 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
5842 {
5843 return HAL_BUSY;
5844 }
5845
5846 /* Process Locked */
5847 __HAL_LOCK(hhrtim);
5848
5849 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5850
5851 /* Configure the compare unit */
5852 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
5853 {
5854 switch (CompareUnit)
5855 {
5856 case HRTIM_COMPAREUNIT_1:
5857 {
5858 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
5859 break;
5860 }
5861
5862 case HRTIM_COMPAREUNIT_2:
5863 {
5864 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
5865 break;
5866 }
5867
5868 case HRTIM_COMPAREUNIT_3:
5869 {
5870 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
5871 break;
5872 }
5873
5874 case HRTIM_COMPAREUNIT_4:
5875 {
5876 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
5877 break;
5878 }
5879
5880 default:
5881 {
5882 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5883
5884 /* Process Unlocked */
5885 __HAL_UNLOCK(hhrtim);
5886
5887 break;
5888 }
5889 }
5890
5891 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
5892 {
5893 return HAL_ERROR;
5894 }
5895
5896 }
5897 else
5898 {
5899 switch (CompareUnit)
5900 {
5901 case HRTIM_COMPAREUNIT_1:
5902 {
5903 /* Set the compare value */
5904 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
5905 break;
5906 }
5907
5908 case HRTIM_COMPAREUNIT_2:
5909 {
5910 /* Check parameters */
5911 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5912
5913 /* Set the compare value */
5914 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
5915
5916 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5917 {
5918 /* Configure auto-delayed mode */
5919 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
5920 /* to the other to reinitialize properly the auto-delayed mechanism */
5921 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
5922 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
5923
5924 /* Set the compare value for timeout compare unit (if any) */
5925 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5926 {
5927 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5928 }
5929 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5930 {
5931 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5932 }
5933 else
5934 {
5935 /* nothing to do */
5936 }
5937 }
5938 else
5939 {
5940 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
5941 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
5942 }
5943 break;
5944 }
5945
5946 case HRTIM_COMPAREUNIT_3:
5947 {
5948 /* Set the compare value */
5949 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
5950 break;
5951 }
5952
5953 case HRTIM_COMPAREUNIT_4:
5954 {
5955 /* Check parameters */
5956 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5957
5958 /* Set the compare value */
5959 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
5960
5961 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5962 {
5963 /* Configure auto-delayed mode */
5964 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
5965 /* to the other to reinitialize properly the auto-delayed mechanism */
5966 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
5967 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
5968
5969 /* Set the compare value for timeout compare unit (if any) */
5970 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5971 {
5972 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5973 }
5974 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5975 {
5976 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5977 }
5978 else
5979 {
5980 /* nothing to do */
5981 }
5982 }
5983 else
5984 {
5985 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
5986 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
5987 }
5988 break;
5989 }
5990
5991 default:
5992 {
5993 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5994
5995 /* Process Unlocked */
5996 __HAL_UNLOCK(hhrtim);
5997
5998 break;
5999 }
6000 }
6001
6002 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6003 {
6004 return HAL_ERROR;
6005 }
6006
6007 }
6008 hhrtim->State = HAL_HRTIM_STATE_READY;
6009
6010 /* Process Unlocked */
6011 __HAL_UNLOCK(hhrtim);
6012
6013 return HAL_OK;
6014 }
6015
6016 /**
6017 * @brief Configure the capture unit of a timer operating in waveform mode
6018 * @param hhrtim pointer to HAL HRTIM handle
6019 * @param TimerIdx Timer index
6020 * This parameter can be one of the following values:
6021 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6022 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6023 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6024 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6025 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6026 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6027 * @param CaptureUnit Capture unit to configure
6028 * This parameter can be one of the following values:
6029 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6030 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6031 * @param pCaptureCfg pointer to the compare unit configuration structure
6032 * @retval HAL status
6033 * @note This function must be called before starting the timer
6034 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,const HRTIM_CaptureCfgTypeDef * pCaptureCfg)6035 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
6036 uint32_t TimerIdx,
6037 uint32_t CaptureUnit,
6038 const HRTIM_CaptureCfgTypeDef *pCaptureCfg)
6039 {
6040 uint32_t Trigger;
6041 uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32);
6042
6043 /* Check parameters */
6044 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, (uint32_t)(pCaptureCfg->Trigger)));
6045 assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger));
6046 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6047
6048 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6049 {
6050 return HAL_BUSY;
6051 }
6052
6053 /* Process Locked */
6054 __HAL_LOCK(hhrtim);
6055
6056 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6057
6058 /* TimerF_Trigger is valid for setting other Timers than Timer F */
6059 if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A)
6060 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TA1SET_Pos); }
6061 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B)
6062 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TB1SET_Pos); }
6063 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C)
6064 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TC1SET_Pos); }
6065 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D)
6066 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TD1SET_Pos); }
6067 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E)
6068 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TE1SET_Pos); }
6069 else
6070 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); }
6071 /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */
6072
6073 /* Configure the capture unit */
6074
6075 switch (CaptureUnit)
6076 {
6077 case HRTIM_CAPTUREUNIT_1:
6078 {
6079 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger);
6080 break;
6081 }
6082
6083 case HRTIM_CAPTUREUNIT_2:
6084 {
6085 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger);
6086 break;
6087 }
6088
6089 default:
6090 {
6091 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6092
6093 /* Process Unlocked */
6094 __HAL_UNLOCK(hhrtim);
6095
6096 break;
6097 }
6098 }
6099
6100 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6101 {
6102 return HAL_ERROR;
6103 }
6104
6105
6106 hhrtim->State = HAL_HRTIM_STATE_READY;
6107
6108 /* Process Unlocked */
6109 __HAL_UNLOCK(hhrtim);
6110
6111 return HAL_OK;
6112 }
6113
6114 /**
6115 * @brief Configure the output of a timer operating in waveform mode
6116 * @param hhrtim pointer to HAL HRTIM handle
6117 * @param TimerIdx Timer index
6118 * This parameter can be one of the following values:
6119 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6120 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6121 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6122 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6123 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6124 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6125 * @param Output Timer output
6126 * This parameter can be one of the following values:
6127 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6128 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6129 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6130 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6131 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6132 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6133 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6134 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6135 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6136 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6137 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6138 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6139 * @param pOutputCfg pointer to the timer output configuration structure
6140 * @retval HAL status
6141 * @note This function must be called before configuring the timer and after
6142 * configuring the deadtime insertion feature (if required).
6143 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)6144 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
6145 uint32_t TimerIdx,
6146 uint32_t Output,
6147 const HRTIM_OutputCfgTypeDef *pOutputCfg)
6148 {
6149 /* Check parameters */
6150 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6151 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
6152 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
6153 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
6154 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
6155 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
6156 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
6157
6158 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6159 {
6160 return HAL_BUSY;
6161 }
6162
6163 /* Process Locked */
6164 __HAL_LOCK(hhrtim);
6165
6166 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6167
6168 /* Configure the timer output */
6169 HRTIM_OutputConfig(hhrtim,
6170 TimerIdx,
6171 Output,
6172 pOutputCfg);
6173
6174 hhrtim->State = HAL_HRTIM_STATE_READY;
6175
6176 /* Process Unlocked */
6177 __HAL_UNLOCK(hhrtim);
6178
6179 return HAL_OK;
6180 }
6181
6182 /**
6183 * @brief Force the timer output to its active or inactive state
6184 * @param hhrtim pointer to HAL HRTIM handle
6185 * @param TimerIdx Timer index
6186 * This parameter can be one of the following values:
6187 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6188 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6189 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6190 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6191 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6192 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6193 * @param Output Timer output
6194 * This parameter can be one of the following values:
6195 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6196 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6197 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6198 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6199 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6200 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6201 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6202 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6203 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6204 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6205 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6206 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6207 * @param OutputLevel indicates whether the output is forced to its active or inactive level
6208 * This parameter can be one of the following values:
6209 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
6210 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
6211 * @retval HAL status
6212 * @note The 'software set/reset trigger' bit in the output set/reset registers
6213 * is automatically reset by hardware
6214 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)6215 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
6216 uint32_t TimerIdx,
6217 uint32_t Output,
6218 uint32_t OutputLevel)
6219 {
6220 /* Check parameters */
6221 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6222 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
6223
6224 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6225 {
6226 return HAL_BUSY;
6227 }
6228
6229 /* Process Locked */
6230 __HAL_LOCK(hhrtim);
6231
6232 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6233
6234 /* Force timer output level */
6235 switch (Output)
6236 {
6237 case HRTIM_OUTPUT_TA1:
6238 case HRTIM_OUTPUT_TB1:
6239 case HRTIM_OUTPUT_TC1:
6240 case HRTIM_OUTPUT_TD1:
6241 case HRTIM_OUTPUT_TE1:
6242 case HRTIM_OUTPUT_TF1:
6243 {
6244 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6245 {
6246 /* Force output to its active state */
6247 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST);
6248 }
6249 else
6250 {
6251 /* Force output to its inactive state */
6252 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
6253 }
6254 break;
6255 }
6256
6257 case HRTIM_OUTPUT_TA2:
6258 case HRTIM_OUTPUT_TB2:
6259 case HRTIM_OUTPUT_TC2:
6260 case HRTIM_OUTPUT_TD2:
6261 case HRTIM_OUTPUT_TE2:
6262 case HRTIM_OUTPUT_TF2:
6263 {
6264 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6265 {
6266 /* Force output to its active state */
6267 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
6268 }
6269 else
6270 {
6271 /* Force output to its inactive state */
6272 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
6273 }
6274 break;
6275 }
6276
6277 default:
6278 {
6279 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6280
6281 /* Process Unlocked */
6282 __HAL_UNLOCK(hhrtim);
6283
6284 break;
6285 }
6286 }
6287
6288 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6289 {
6290 return HAL_ERROR;
6291 }
6292
6293 hhrtim->State = HAL_HRTIM_STATE_READY;
6294
6295 /* Process Unlocked */
6296 __HAL_UNLOCK(hhrtim);
6297
6298 return HAL_OK;
6299 }
6300
6301 /**
6302 * @brief Enable the generation of the waveform signal on the designated output(s)
6303 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
6304 * @param hhrtim pointer to HAL HRTIM handle
6305 * @param OutputsToStart Timer output(s) to enable
6306 * This parameter can be any combination of the following values:
6307 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6308 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6309 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6310 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6311 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6312 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6313 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6314 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6315 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6316 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6317 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6318 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6319 * @retval HAL status
6320 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)6321 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
6322 uint32_t OutputsToStart)
6323 {
6324 /* Check the parameters */
6325 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
6326
6327 /* Process Locked */
6328 __HAL_LOCK(hhrtim);
6329
6330 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6331
6332 /* Enable the HRTIM outputs */
6333 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
6334
6335 hhrtim->State = HAL_HRTIM_STATE_READY;
6336
6337 /* Process Unlocked */
6338 __HAL_UNLOCK(hhrtim);
6339
6340 return HAL_OK;
6341 }
6342
6343 /**
6344 * @brief Disable the generation of the waveform signal on the designated output(s)
6345 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
6346 * @param hhrtim pointer to HAL HRTIM handle
6347 * @param OutputsToStop Timer output(s) to disable
6348 * This parameter can be any combination of the following values:
6349 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6350 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6351 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6352 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6353 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6354 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6355 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6356 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6357 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6358 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6359 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6360 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6361 * @retval HAL status
6362 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)6363 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
6364 uint32_t OutputsToStop)
6365 {
6366 /* Check the parameters */
6367 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
6368
6369 /* Process Locked */
6370 __HAL_LOCK(hhrtim);
6371
6372 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6373
6374 /* Enable the HRTIM outputs */
6375 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
6376
6377 hhrtim->State = HAL_HRTIM_STATE_READY;
6378
6379 /* Process Unlocked */
6380 __HAL_UNLOCK(hhrtim);
6381
6382 return HAL_OK;
6383 }
6384
6385 /**
6386 * @brief Start the counter of the designated timer(s) operating in waveform mode
6387 * Timers can be combined (ORed) to allow for simultaneous counter start.
6388 * @param hhrtim pointer to HAL HRTIM handle
6389 * @param Timers Timer counter(s) to start
6390 * This parameter can be any combination of the following values:
6391 * @arg HRTIM_TIMERID_MASTER
6392 * @arg HRTIM_TIMERID_TIMER_A
6393 * @arg HRTIM_TIMERID_TIMER_B
6394 * @arg HRTIM_TIMERID_TIMER_C
6395 * @arg HRTIM_TIMERID_TIMER_D
6396 * @arg HRTIM_TIMERID_TIMER_E
6397 * @arg HRTIM_TIMERID_TIMER_F
6398 * @retval HAL status
6399 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6400 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
6401 uint32_t Timers)
6402 {
6403 /* Check the parameters */
6404 assert_param(IS_HRTIM_TIMERID(Timers));
6405
6406 /* Process Locked */
6407 __HAL_LOCK(hhrtim);
6408
6409 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6410
6411 /* Enable timer(s) counter */
6412 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6413
6414 hhrtim->State = HAL_HRTIM_STATE_READY;
6415
6416 /* Process Unlocked */
6417 __HAL_UNLOCK(hhrtim);
6418
6419 return HAL_OK;
6420 }
6421
6422 /**
6423 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6424 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6425 * @param hhrtim pointer to HAL HRTIM handle
6426 * @param Timers Timer counter(s) to stop
6427 * This parameter can be any combination of the following values:
6428 * @arg HRTIM_TIMERID_MASTER
6429 * @arg HRTIM_TIMERID_TIMER_A
6430 * @arg HRTIM_TIMERID_TIMER_B
6431 * @arg HRTIM_TIMERID_TIMER_C
6432 * @arg HRTIM_TIMERID_TIMER_D
6433 * @arg HRTIM_TIMERID_TIMER_E
6434 * @arg HRTIM_TIMERID_TIMER_F
6435 * @retval HAL status
6436 * @note The counter of a timer is stopped only if all timer outputs are disabled
6437 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6438 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
6439 uint32_t Timers)
6440 {
6441 /* Check the parameters */
6442 assert_param(IS_HRTIM_TIMERID(Timers));
6443
6444 /* Process Locked */
6445 __HAL_LOCK(hhrtim);
6446
6447 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6448
6449 /* Disable timer(s) counter */
6450 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6451
6452 hhrtim->State = HAL_HRTIM_STATE_READY;
6453
6454 /* Process Unlocked */
6455 __HAL_UNLOCK(hhrtim);
6456
6457 return HAL_OK;
6458 }
6459
6460 /**
6461 * @brief Start the counter of the designated timer(s) operating in waveform mode
6462 * Timers can be combined (ORed) to allow for simultaneous counter start.
6463 * @param hhrtim pointer to HAL HRTIM handle
6464 * @param Timers Timer counter(s) to start
6465 * This parameter can be any combination of the following values:
6466 * @arg HRTIM_TIMERID_MASTER
6467 * @arg HRTIM_TIMERID_TIMER_A
6468 * @arg HRTIM_TIMERID_TIMER_B
6469 * @arg HRTIM_TIMERID_TIMER_C
6470 * @arg HRTIM_TIMERID_TIMER_D
6471 * @arg HRTIM_TIMERID_TIMER_E
6472 * @arg HRTIM_TIMERID_TIMER_F
6473 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
6474 * to the timers to start are enabled within this function.
6475 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
6476 * function.
6477 * @retval HAL status
6478 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6479 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
6480 uint32_t Timers)
6481 {
6482 uint8_t timer_idx;
6483
6484 /* Check the parameters */
6485 assert_param(IS_HRTIM_TIMERID(Timers));
6486
6487 /* Process Locked */
6488 __HAL_LOCK(hhrtim);
6489
6490 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6491
6492 /* Enable HRTIM interrupts (if required) */
6493 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
6494
6495 /* Enable master timer related interrupts (if required) */
6496 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6497 {
6498 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
6499 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6500 }
6501
6502 /* Enable timing unit related interrupts (if required) */
6503 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6504 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6505 timer_idx++)
6506 {
6507 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6508 {
6509 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
6510 timer_idx,
6511 hhrtim->TimerParam[timer_idx].InterruptRequests);
6512 }
6513 }
6514
6515 /* Enable timer(s) counter */
6516 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6517
6518 hhrtim->State = HAL_HRTIM_STATE_READY;
6519
6520 /* Process Unlocked */
6521 __HAL_UNLOCK(hhrtim);
6522
6523 return HAL_OK;
6524 }
6525
6526 /**
6527 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6528 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6529 * @param hhrtim pointer to HAL HRTIM handle
6530 * @param Timers Timer counter(s) to stop
6531 * This parameter can be any combination of the following values:
6532 * @arg HRTIM_TIMERID_MASTER
6533 * @arg HRTIM_TIMERID_TIMER_A
6534 * @arg HRTIM_TIMERID_TIMER_B
6535 * @arg HRTIM_TIMERID_TIMER_C
6536 * @arg HRTIM_TIMERID_TIMER_D
6537 * @arg HRTIM_TIMERID_TIMER_E
6538 * @arg HRTIM_TIMERID_TIMER_F
6539 * @retval HAL status
6540 * @note The counter of a timer is stopped only if all timer outputs are disabled
6541 * @note All enabled timer related interrupts are disabled.
6542 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6543 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
6544 uint32_t Timers)
6545 {
6546 /* ++ WA */
6547 __IO uint32_t delai = (uint32_t)(0x17FU);
6548 /* -- WA */
6549
6550 uint8_t timer_idx;
6551
6552 /* Check the parameters */
6553 assert_param(IS_HRTIM_TIMERID(Timers));
6554
6555 /* Process Locked */
6556 __HAL_LOCK(hhrtim);
6557
6558 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6559
6560 /* Disable HRTIM interrupts (if required) */
6561 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
6562
6563 /* Disable master timer related interrupts (if required) */
6564 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6565 {
6566 /* Interrupts enable flag must be cleared one by one */
6567 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6568 }
6569
6570 /* Disable timing unit related interrupts (if required) */
6571 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6572 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6573 timer_idx++)
6574 {
6575 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6576 {
6577 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
6578 }
6579 }
6580
6581 /* ++ WA */
6582 do { delai--; } while (delai != 0U);
6583 /* -- WA */
6584
6585 /* Disable timer(s) counter */
6586 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6587
6588 hhrtim->State = HAL_HRTIM_STATE_READY;
6589
6590 /* Process Unlocked */
6591 __HAL_UNLOCK(hhrtim);
6592
6593 return HAL_OK;
6594 }
6595
6596 /**
6597 * @brief Start the counter of the designated timer(s) operating in waveform mode
6598 * Timers can be combined (ORed) to allow for simultaneous counter start.
6599 * @param hhrtim pointer to HAL HRTIM handle
6600 * @param Timers Timer counter(s) to start
6601 * This parameter can be any combination of the following values:
6602 * @arg HRTIM_TIMERID_MASTER
6603 * @arg HRTIM_TIMERID_TIMER_A
6604 * @arg HRTIM_TIMERID_TIMER_B
6605 * @arg HRTIM_TIMERID_TIMER_C
6606 * @arg HRTIM_TIMERID_TIMER_D
6607 * @arg HRTIM_TIMERID_TIMER_E
6608 * @arg HRTIM_TIMERID_TIMER_F
6609 * @retval HAL status
6610 * @note This function enables the dma request(s) mentioned in the timer
6611 * configuration data structure for every timers to start.
6612 * @note The source memory address, the destination memory address and the
6613 * size of each DMA transfer are specified at timer configuration time
6614 * (see HAL_HRTIM_WaveformTimerConfig)
6615 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6616 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
6617 uint32_t Timers)
6618 {
6619 uint8_t timer_idx;
6620 DMA_HandleTypeDef *hdma;
6621
6622 /* Check the parameters */
6623 assert_param(IS_HRTIM_TIMERID(Timers));
6624
6625 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6626 {
6627 return HAL_BUSY;
6628 }
6629
6630 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6631
6632 /* Process Locked */
6633 __HAL_LOCK(hhrtim);
6634
6635 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
6636 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6637 {
6638 /* Set the DMA error callback */
6639 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
6640
6641 /* Set the DMA transfer completed callback */
6642 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
6643
6644 /* Enable the DMA channel */
6645 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
6646 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
6647 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
6648 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
6649 {
6650 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6651
6652 /* Process Unlocked */
6653 __HAL_UNLOCK(hhrtim);
6654
6655 return HAL_ERROR;
6656 }
6657
6658 /* Enable the timer DMA request */
6659 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
6660 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6661 }
6662
6663 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6664 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6665 timer_idx++)
6666 {
6667 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
6668 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6669 {
6670 /* Get the timer DMA handler */
6671 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
6672
6673 if (hdma == NULL)
6674 {
6675 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6676
6677 /* Process Unlocked */
6678 __HAL_UNLOCK(hhrtim);
6679
6680 return HAL_ERROR;
6681 }
6682
6683 /* Set the DMA error callback */
6684 hdma->XferErrorCallback = HRTIM_DMAError ;
6685
6686 /* Set the DMA transfer completed callback */
6687 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
6688
6689 /* Enable the DMA channel */
6690 if (HAL_DMA_Start_IT(hdma,
6691 hhrtim->TimerParam[timer_idx].DMASrcAddress,
6692 hhrtim->TimerParam[timer_idx].DMADstAddress,
6693 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
6694 {
6695 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6696
6697 /* Process Unlocked */
6698 __HAL_UNLOCK(hhrtim);
6699
6700 return HAL_ERROR;
6701 }
6702
6703 /* Enable the timer DMA request */
6704 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
6705 timer_idx,
6706 hhrtim->TimerParam[timer_idx].DMARequests);
6707 }
6708 }
6709
6710 /* Enable the timer counter */
6711 __HAL_HRTIM_ENABLE(hhrtim, Timers);
6712
6713 hhrtim->State = HAL_HRTIM_STATE_READY;
6714
6715 /* Process Unlocked */
6716 __HAL_UNLOCK(hhrtim);
6717
6718 return HAL_OK;
6719 }
6720
6721 /**
6722 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6723 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6724 * @param hhrtim pointer to HAL HRTIM handle
6725 * @param Timers Timer counter(s) to stop
6726 * This parameter can be any combination of the following values:
6727 * @arg HRTIM_TIMERID_MASTER
6728 * @arg HRTIM_TIMERID_TIMER_A
6729 * @arg HRTIM_TIMERID_TIMER_B
6730 * @arg HRTIM_TIMERID_TIMER_C
6731 * @arg HRTIM_TIMERID_TIMER_D
6732 * @arg HRTIM_TIMERID_TIMER_E
6733 * @arg HRTIM_TIMERID_TIMER_F
6734 * @retval HAL status
6735 * @note The counter of a timer is stopped only if all timer outputs are disabled
6736 * @note All enabled timer related DMA requests are disabled.
6737 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6738 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
6739 uint32_t Timers)
6740 {
6741 uint8_t timer_idx;
6742
6743 /* Check the parameters */
6744 assert_param(IS_HRTIM_TIMERID(Timers));
6745
6746 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6747
6748 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
6749 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6750 {
6751 /* Disable the DMA */
6752 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
6753 {
6754 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6755 }
6756 else
6757 {
6758 hhrtim->State = HAL_HRTIM_STATE_READY;
6759 /* Disable the DMA request(s) */
6760 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
6761 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6762 }
6763 }
6764
6765 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6766 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6767 timer_idx++)
6768 {
6769 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
6770 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6771 {
6772 /* Get the timer DMA handler */
6773 /* Disable the DMA */
6774 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
6775 {
6776 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6777 }
6778 else
6779 {
6780 hhrtim->State = HAL_HRTIM_STATE_READY;
6781
6782 /* Disable the DMA request(s) */
6783 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
6784 timer_idx,
6785 hhrtim->TimerParam[timer_idx].DMARequests);
6786 }
6787 }
6788 }
6789
6790 /* Disable the timer counter */
6791 __HAL_HRTIM_DISABLE(hhrtim, Timers);
6792
6793 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6794 {
6795 return HAL_ERROR;
6796 }
6797 else
6798 {
6799 return HAL_OK;
6800 }
6801 }
6802
6803 /**
6804 * @brief Enable or disables the HRTIM burst mode controller.
6805 * @param hhrtim pointer to HAL HRTIM handle
6806 * @param Enable Burst mode controller enabling
6807 * This parameter can be one of the following values:
6808 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
6809 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
6810 * @retval HAL status
6811 * @note This function must be called after starting the timer(s)
6812 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)6813 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
6814 uint32_t Enable)
6815 {
6816 /* Check parameters */
6817 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
6818
6819 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6820 {
6821 return HAL_BUSY;
6822 }
6823
6824 /* Process Locked */
6825 __HAL_LOCK(hhrtim);
6826
6827 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6828
6829 /* Enable/Disable the burst mode controller */
6830 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
6831
6832 hhrtim->State = HAL_HRTIM_STATE_READY;
6833
6834 /* Process Unlocked */
6835 __HAL_UNLOCK(hhrtim);
6836
6837 return HAL_OK;
6838 }
6839
6840 /**
6841 * @brief Trig the burst mode operation.
6842 * @param hhrtim pointer to HAL HRTIM handle
6843 * @retval HAL status
6844 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)6845 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
6846 {
6847 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6848 {
6849 return HAL_BUSY;
6850 }
6851
6852 /* Process Locked */
6853 __HAL_LOCK(hhrtim);
6854
6855 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6856
6857 /* Software trigger of the burst mode controller */
6858 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
6859
6860 hhrtim->State = HAL_HRTIM_STATE_READY;
6861
6862 /* Process Unlocked */
6863 __HAL_UNLOCK(hhrtim);
6864
6865 return HAL_OK;
6866 }
6867
6868 /**
6869 * @brief Trig a software capture on the designed capture unit
6870 * @param hhrtim pointer to HAL HRTIM handle
6871 * @param TimerIdx Timer index
6872 * This parameter can be one of the following values:
6873 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6874 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6875 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6876 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6877 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6878 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6879 * @param CaptureUnit Capture unit to trig
6880 * This parameter can be one of the following values:
6881 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6882 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6883 * @retval HAL status
6884 * @note The 'software capture' bit in the capure configuration register is
6885 * automatically reset by hardware
6886 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)6887 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
6888 uint32_t TimerIdx,
6889 uint32_t CaptureUnit)
6890 {
6891 /* Check parameters */
6892 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6893 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
6894
6895 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6896 {
6897 return HAL_BUSY;
6898 }
6899
6900 /* Process Locked */
6901 __HAL_LOCK(hhrtim);
6902
6903 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6904
6905 /* Force a software capture on concerned capture unit */
6906 switch (CaptureUnit)
6907 {
6908 case HRTIM_CAPTUREUNIT_1:
6909 {
6910 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
6911 break;
6912 }
6913
6914 case HRTIM_CAPTUREUNIT_2:
6915 {
6916 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
6917 break;
6918 }
6919
6920 default:
6921 {
6922 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6923
6924 /* Process Unlocked */
6925 __HAL_UNLOCK(hhrtim);
6926
6927 break;
6928 }
6929 }
6930
6931 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6932 {
6933 return HAL_ERROR;
6934 }
6935
6936 hhrtim->State = HAL_HRTIM_STATE_READY;
6937
6938 /* Process Unlocked */
6939 __HAL_UNLOCK(hhrtim);
6940
6941 return HAL_OK;
6942 }
6943
6944 /**
6945 * @brief Trig the update of the registers of one or several timers
6946 * @param hhrtim pointer to HAL HRTIM handle
6947 * @param Timers timers concerned with the software register update
6948 * This parameter can be any combination of the following values:
6949 * @arg HRTIM_TIMERUPDATE_MASTER
6950 * @arg HRTIM_TIMERUPDATE_A
6951 * @arg HRTIM_TIMERUPDATE_B
6952 * @arg HRTIM_TIMERUPDATE_C
6953 * @arg HRTIM_TIMERUPDATE_D
6954 * @arg HRTIM_TIMERUPDATE_E
6955 * @arg HRTIM_TIMERUPDATE_F
6956 * @retval HAL status
6957 * @note The 'software update' bits in the HRTIM control register 2 register are
6958 * automatically reset by hardware
6959 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6960 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
6961 uint32_t Timers)
6962 {
6963 /* Check parameters */
6964 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6965
6966 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
6967 {
6968 return HAL_BUSY;
6969 }
6970
6971 /* Process Locked */
6972 __HAL_LOCK(hhrtim);
6973
6974 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6975
6976 /* Force timer(s) registers update */
6977 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
6978
6979 hhrtim->State = HAL_HRTIM_STATE_READY;
6980
6981 /* Process Unlocked */
6982 __HAL_UNLOCK(hhrtim);
6983
6984 return HAL_OK;
6985 }
6986
6987 /**
6988 * @brief Swap the Timer outputs
6989 * @param hhrtim pointer to HAL HRTIM handle
6990 * @param Timers timers concerned with the software register update
6991 * This parameter can be any combination of the following values:
6992 * @arg HRTIM_TIMERSWAP_A
6993 * @arg HRTIM_TIMERSWAP_B
6994 * @arg HRTIM_TIMERSWAP_C
6995 * @arg HRTIM_TIMERSWAP_D
6996 * @arg HRTIM_TIMERSWAP_E
6997 * @arg HRTIM_TIMERSWAP_F
6998 * @retval HAL status
6999 * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1)
7000 */
HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7001 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim,
7002 uint32_t Timers)
7003 {
7004 /* Check parameters */
7005 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7006
7007 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
7008 {
7009 return HAL_BUSY;
7010 }
7011
7012 /* Process Locked */
7013 __HAL_LOCK(hhrtim);
7014
7015 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7016
7017 /* Force timer(s) registers update */
7018 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
7019
7020 hhrtim->State = HAL_HRTIM_STATE_READY;
7021
7022 /* Process Unlocked */
7023 __HAL_UNLOCK(hhrtim);
7024
7025 return HAL_OK;
7026 }
7027
7028 /**
7029 * @brief Trig the reset of one or several timers
7030 * @param hhrtim pointer to HAL HRTIM handle
7031 * @param Timers timers concerned with the software counter reset
7032 * This parameter can be any combination of the following values:
7033 * @arg HRTIM_TIMERRESET_MASTER
7034 * @arg HRTIM_TIMERRESET_TIMER_A
7035 * @arg HRTIM_TIMERRESET_TIMER_B
7036 * @arg HRTIM_TIMERRESET_TIMER_C
7037 * @arg HRTIM_TIMERRESET_TIMER_D
7038 * @arg HRTIM_TIMERRESET_TIMER_E
7039 * @arg HRTIM_TIMERRESET_TIMER_F
7040 * @retval HAL status
7041 * @note The 'software reset' bits in the HRTIM control register 2 are
7042 * automatically reset by hardware
7043 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7044 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
7045 uint32_t Timers)
7046 {
7047 /* Check parameters */
7048 assert_param(IS_HRTIM_TIMERRESET(Timers));
7049
7050 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
7051 {
7052 return HAL_BUSY;
7053 }
7054
7055 /* Process Locked */
7056 __HAL_LOCK(hhrtim);
7057
7058 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7059
7060 /* Force timer(s) registers reset */
7061 hhrtim->Instance->sCommonRegs.CR2 = Timers;
7062
7063 hhrtim->State = HAL_HRTIM_STATE_READY;
7064
7065 /* Process Unlocked */
7066 __HAL_UNLOCK(hhrtim);
7067
7068 return HAL_OK;
7069 }
7070
7071 /**
7072 * @brief Swap the output of one or several timers
7073 * @param hhrtim: pointer to HAL HRTIM handle
7074 * @param Timers: timers concerned with the software register update
7075 * This parameter can be any combination of the following values:
7076 * @arg HRTIM_TIMERSWAP_A
7077 * @arg HRTIM_TIMERSWAP_B
7078 * @arg HRTIM_TIMERSWAP_C
7079 * @arg HRTIM_TIMERSWAP_D
7080 * @arg HRTIM_TIMERSWAP_E
7081 * @arg HRTIM_TIMERSWAP_F
7082 * @retval HAL status
7083 */
HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7084 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim,
7085 uint32_t Timers)
7086 {
7087 /* Check parameters */
7088 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7089
7090 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
7091 {
7092 return HAL_BUSY;
7093 }
7094
7095 /* Process Locked */
7096 __HAL_LOCK(hhrtim);
7097
7098 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7099
7100 /* Force timer(s) registers update */
7101 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
7102
7103 hhrtim->State = HAL_HRTIM_STATE_READY;
7104
7105 /* Process Unlocked */
7106 __HAL_UNLOCK(hhrtim);
7107
7108 return HAL_OK;
7109 }
7110
7111 /**
7112 * @brief Un-swap the output of one or several timers
7113 * @param hhrtim: pointer to HAL HRTIM handle
7114 * @param Timers: timers concerned with the software register update
7115 * This parameter can be any combination of the following values:
7116 * @arg HRTIM_TIMERSWAP_A
7117 * @arg HRTIM_TIMERSWAP_B
7118 * @arg HRTIM_TIMERSWAP_C
7119 * @arg HRTIM_TIMERSWAP_D
7120 * @arg HRTIM_TIMERSWAP_E
7121 * @arg HRTIM_TIMERSWAP_F
7122 * @retval HAL status
7123 */
HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7124 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim,
7125 uint32_t Timers)
7126 {
7127 /* Check parameters */
7128 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7129
7130 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
7131 {
7132 return HAL_BUSY;
7133 }
7134
7135 /* Process Locked */
7136 __HAL_LOCK(hhrtim);
7137
7138 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7139
7140 /* Force timer(s) registers update */
7141 hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers);
7142
7143 hhrtim->State = HAL_HRTIM_STATE_READY;
7144
7145 /* Process Unlocked */
7146 __HAL_UNLOCK(hhrtim);
7147
7148 return HAL_OK;
7149 }
7150
7151 /**
7152 * @brief Start a burst DMA operation to update HRTIM control registers content
7153 * @param hhrtim pointer to HAL HRTIM handle
7154 * @param TimerIdx Timer index
7155 * This parameter can be one of the following values:
7156 * @arg HRTIM_TIMERINDEX_MASTER for master timer
7157 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7158 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7159 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7160 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7161 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7162 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7163 * @param BurstBufferAddress address of the buffer the HRTIM control registers
7164 * content will be updated from.
7165 * @param BurstBufferLength size (in WORDS) of the burst buffer.
7166 * @retval HAL status
7167 * @note The TimerIdx parameter determines the dma channel to be used by the
7168 * DMA burst controller (see below)
7169 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
7170 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
7171 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
7172 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
7173 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
7174 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
7175 * HRTIM_TIMERINDEX_TIMER_F: DMA channel 8 is used by the DMA burst controller
7176 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)7177 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
7178 uint32_t TimerIdx,
7179 uint32_t BurstBufferAddress,
7180 uint32_t BurstBufferLength)
7181 {
7182 DMA_HandleTypeDef *hdma;
7183
7184 /* Check the parameters */
7185 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
7186
7187 if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
7188 {
7189 return HAL_BUSY;
7190 }
7191 if (hhrtim->State == HAL_HRTIM_STATE_READY)
7192 {
7193 if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U))
7194 {
7195 return HAL_ERROR;
7196 }
7197 else
7198 {
7199 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7200 }
7201 }
7202
7203 /* Process Locked */
7204 __HAL_LOCK(hhrtim);
7205
7206 /* Get the timer DMA handler */
7207 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
7208
7209 if (hdma == NULL)
7210 {
7211 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7212
7213 /* Process Unlocked */
7214 __HAL_UNLOCK(hhrtim);
7215
7216 return HAL_ERROR;
7217 }
7218
7219 /* Set the DMA transfer completed callback */
7220 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
7221
7222 /* Set the DMA error callback */
7223 hdma->XferErrorCallback = HRTIM_DMAError ;
7224
7225 /* Enable the DMA channel */
7226 if (HAL_DMA_Start_IT(hdma,
7227 BurstBufferAddress,
7228 (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR),
7229 BurstBufferLength) != HAL_OK)
7230 {
7231 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7232
7233 /* Process Unlocked */
7234 __HAL_UNLOCK(hhrtim);
7235
7236 return HAL_ERROR;
7237 }
7238
7239 hhrtim->State = HAL_HRTIM_STATE_READY;
7240
7241 /* Process Unlocked */
7242 __HAL_UNLOCK(hhrtim);
7243
7244 return HAL_OK;
7245 }
7246
7247 /**
7248 * @brief Enable the transfer from preload to active registers for one
7249 * or several timing units (including master timer).
7250 * @param hhrtim pointer to HAL HRTIM handle
7251 * @param Timers Timer(s) concerned by the register preload enabling command
7252 * This parameter can be any combination of the following values:
7253 * @arg HRTIM_TIMERUPDATE_MASTER
7254 * @arg HRTIM_TIMERUPDATE_A
7255 * @arg HRTIM_TIMERUPDATE_B
7256 * @arg HRTIM_TIMERUPDATE_C
7257 * @arg HRTIM_TIMERUPDATE_D
7258 * @arg HRTIM_TIMERUPDATE_E
7259 * @arg HRTIM_TIMERUPDATE_E
7260 * @retval HAL status
7261 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7262 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
7263 uint32_t Timers)
7264 {
7265 /* Check the parameters */
7266 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7267
7268 /* Process Locked */
7269 __HAL_LOCK(hhrtim);
7270
7271 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7272
7273 /* Enable timer(s) registers update */
7274 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
7275
7276 hhrtim->State = HAL_HRTIM_STATE_READY;
7277
7278 /* Process Unlocked */
7279 __HAL_UNLOCK(hhrtim);
7280
7281 return HAL_OK;
7282 }
7283
7284 /**
7285 * @brief Disable the transfer from preload to active registers for one
7286 * or several timing units (including master timer).
7287 * @param hhrtim pointer to HAL HRTIM handle
7288 * @param Timers Timer(s) concerned by the register preload disabling command
7289 * This parameter can be any combination of the following values:
7290 * @arg HRTIM_TIMERUPDATE_MASTER
7291 * @arg HRTIM_TIMERUPDATE_A
7292 * @arg HRTIM_TIMERUPDATE_B
7293 * @arg HRTIM_TIMERUPDATE_C
7294 * @arg HRTIM_TIMERUPDATE_D
7295 * @arg HRTIM_TIMERUPDATE_E
7296 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7297 * @retval HAL status
7298 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7299 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
7300 uint32_t Timers)
7301 {
7302 /* Check the parameters */
7303 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7304
7305 /* Process Locked */
7306 __HAL_LOCK(hhrtim);
7307
7308 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7309
7310 /* Enable timer(s) registers update */
7311 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
7312
7313 hhrtim->State = HAL_HRTIM_STATE_READY;
7314
7315 /* Process Unlocked */
7316 __HAL_UNLOCK(hhrtim);
7317
7318 return HAL_OK;
7319 }
7320
7321 /**
7322 * @}
7323 */
7324
7325 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
7326 * @brief Peripheral State functions
7327 @verbatim
7328 ===============================================================================
7329 ##### Peripheral State functions #####
7330 ===============================================================================
7331 [..] This section provides functions used to get HRTIM or HRTIM timer
7332 specific information:
7333 (+) Get HRTIM HAL state
7334 (+) Get captured value
7335 (+) Get HRTIM timer output level
7336 (+) Get HRTIM timer output state
7337 (+) Get delayed protection status
7338 (+) Get burst status
7339 (+) Get current push-pull status
7340 (+) Get idle push-pull status
7341
7342 @endverbatim
7343 * @{
7344 */
7345
7346 /**
7347 * @brief Return the HRTIM HAL state
7348 * @param hhrtim pointer to HAL HRTIM handle
7349 * @retval HAL state
7350 */
HAL_HRTIM_GetState(const HRTIM_HandleTypeDef * hhrtim)7351 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim)
7352 {
7353 /* Return HRTIM state */
7354 return hhrtim->State;
7355 }
7356
7357 /**
7358 * @brief Return actual value of the capture register of the designated capture unit
7359 * @param hhrtim pointer to HAL HRTIM handle
7360 * @param TimerIdx Timer index
7361 * This parameter can be one of the following values:
7362 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7363 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7364 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7365 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7366 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7367 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7368 * @param CaptureUnit Capture unit to trig
7369 * This parameter can be one of the following values:
7370 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7371 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7372 * @retval Captured value
7373 */
HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7374 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim,
7375 uint32_t TimerIdx,
7376 uint32_t CaptureUnit)
7377 {
7378 uint32_t captured_value;
7379
7380 /* Check parameters */
7381 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7382 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7383
7384 /* Read captured value */
7385 switch (CaptureUnit)
7386 {
7387 case HRTIM_CAPTUREUNIT_1:
7388 {
7389 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU;
7390 break;
7391 }
7392
7393 case HRTIM_CAPTUREUNIT_2:
7394 {
7395 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU;
7396 break;
7397 }
7398
7399 default:
7400 {
7401 captured_value = 0xFFFFFFFFUL;
7402 break;
7403 }
7404
7405 }
7406
7407 return captured_value;
7408 }
7409
7410 /**
7411 * @brief Return actual value and direction of the capture register of the designated capture unit
7412 * @param hhrtim pointer to HAL HRTIM handle
7413 * @param TimerIdx Timer index
7414 * This parameter can be one of the following values:
7415 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7416 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7417 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7418 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7419 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7420 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7421 * @param CaptureUnit Capture unit to trig
7422 * This parameter can be one of the following values:
7423 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7424 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7425 * @retval captured value and direction structure
7426 */
HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7427 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim,
7428 uint32_t TimerIdx,
7429 uint32_t CaptureUnit)
7430 {
7431 uint32_t tmp;
7432 HRTIM_CaptureValueTypeDef captured;
7433
7434 /* Check parameters */
7435 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7436 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7437
7438 /* Read captured value */
7439 switch (CaptureUnit)
7440 {
7441 case HRTIM_CAPTUREUNIT_1:
7442 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
7443 captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU;
7444 captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR) ? 1U : 0U);
7445 break;
7446 case HRTIM_CAPTUREUNIT_2:
7447 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
7448 captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU;
7449 captured.Dir = (((tmp & HRTIM_CPT2R_DIR) == HRTIM_CPT2R_DIR) ? 1U : 0U);
7450 break;
7451 default:
7452 captured.Value = 0xFFFFFFFFUL;
7453 captured.Dir = 0xFFFFFFFFUL;
7454 break;
7455 }
7456
7457 return captured;
7458 }
7459
7460 /**
7461 * @brief Return actual direction of the capture register of the designated capture unit
7462 * @param hhrtim pointer to HAL HRTIM handle
7463 * @param TimerIdx Timer index
7464 * This parameter can be one of the following values:
7465 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7466 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7467 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7468 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7469 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7470 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7471 * @param CaptureUnit Capture unit to trig
7472 * This parameter can be one of the following values:
7473 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7474 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7475 * @retval captured direction
7476 * @arg This parameter is one HRTIM_Timer_UpDown_Mode :
7477 * @arg HRTIM_TIMERUPDOWNMODE_UP
7478 * @arg HRTIM_TIMERUPDOWNMODE_UPDOWN
7479 */
HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7480 uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim,
7481 uint32_t TimerIdx,
7482 uint32_t CaptureUnit)
7483 {
7484 uint32_t tmp;
7485
7486 /* Check parameters */
7487 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7488 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7489
7490 /* Read captured value */
7491 switch (CaptureUnit)
7492 {
7493 case HRTIM_CAPTUREUNIT_1:
7494 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos);
7495 break;
7496 case HRTIM_CAPTUREUNIT_2:
7497 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos);
7498 break;
7499 default:
7500 tmp = 0xFFFFFFFFU;
7501 break;
7502 }
7503
7504 return tmp;
7505 }
7506
7507
7508 /**
7509 * @brief Return actual level (active or inactive) of the designated output
7510 * @param hhrtim pointer to HAL HRTIM handle
7511 * @param TimerIdx Timer index
7512 * This parameter can be one of the following values:
7513 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7514 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7515 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7516 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7517 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7518 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7519 * @param Output Timer output
7520 * This parameter can be one of the following values:
7521 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7522 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7523 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7524 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7525 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7526 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7527 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7528 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7529 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7530 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7531 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7532 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7533 * @retval Output level
7534 * @note Returned output level is taken before the output stage (chopper,
7535 * polarity).
7536 */
HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7537 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
7538 uint32_t TimerIdx,
7539 uint32_t Output)
7540 {
7541 uint32_t output_level;
7542
7543 /* Check parameters */
7544 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7545
7546 /* Read the output level */
7547 switch (Output)
7548 {
7549 case HRTIM_OUTPUT_TA1:
7550 case HRTIM_OUTPUT_TB1:
7551 case HRTIM_OUTPUT_TC1:
7552 case HRTIM_OUTPUT_TD1:
7553 case HRTIM_OUTPUT_TE1:
7554 case HRTIM_OUTPUT_TF1:
7555 {
7556 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
7557 {
7558 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7559 }
7560 else
7561 {
7562 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7563 }
7564 break;
7565 }
7566
7567 case HRTIM_OUTPUT_TA2:
7568 case HRTIM_OUTPUT_TB2:
7569 case HRTIM_OUTPUT_TC2:
7570 case HRTIM_OUTPUT_TD2:
7571 case HRTIM_OUTPUT_TE2:
7572 case HRTIM_OUTPUT_TF2:
7573 {
7574 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
7575 {
7576 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7577 }
7578 else
7579 {
7580 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7581 }
7582 break;
7583 }
7584
7585 default:
7586 {
7587 output_level = 0xFFFFFFFFUL;
7588 break;
7589 }
7590 }
7591
7592 return output_level;
7593 }
7594
7595 /**
7596 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
7597 * @param hhrtim pointer to HAL HRTIM handle
7598 * @param TimerIdx Timer index
7599 * This parameter can be one of the following values:
7600 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7601 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7602 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7603 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7604 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7605 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7606 * @param Output Timer output
7607 * This parameter can be one of the following values:
7608 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7609 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7610 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7611 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7612 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7613 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7614 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7615 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7616 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7617 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7618 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7619 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7620 * @retval Output state
7621 */
HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7622 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim,
7623 uint32_t TimerIdx,
7624 uint32_t Output)
7625 {
7626 uint32_t output_bit;
7627 uint32_t output_state;
7628
7629 /* Check parameters */
7630 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7631
7632 /* Prevent unused argument(s) compilation warning */
7633 UNUSED(TimerIdx);
7634
7635 /* Set output state according to output control status and output disable status */
7636 switch (Output)
7637 {
7638 case HRTIM_OUTPUT_TA1:
7639 {
7640 output_bit = HRTIM_OENR_TA1OEN;
7641 break;
7642 }
7643
7644 case HRTIM_OUTPUT_TA2:
7645 {
7646 output_bit = HRTIM_OENR_TA2OEN;
7647 break;
7648 }
7649
7650 case HRTIM_OUTPUT_TB1:
7651 {
7652 output_bit = HRTIM_OENR_TB1OEN;
7653 break;
7654 }
7655
7656 case HRTIM_OUTPUT_TB2:
7657 {
7658 output_bit = HRTIM_OENR_TB2OEN;
7659 break;
7660 }
7661
7662 case HRTIM_OUTPUT_TC1:
7663 {
7664 output_bit = HRTIM_OENR_TC1OEN;
7665 break;
7666 }
7667
7668 case HRTIM_OUTPUT_TC2:
7669 {
7670 output_bit = HRTIM_OENR_TC2OEN;
7671 break;
7672 }
7673
7674 case HRTIM_OUTPUT_TD1:
7675 {
7676 output_bit = HRTIM_OENR_TD1OEN;
7677 break;
7678 }
7679
7680 case HRTIM_OUTPUT_TD2:
7681 {
7682 output_bit = HRTIM_OENR_TD2OEN;
7683 break;
7684 }
7685
7686 case HRTIM_OUTPUT_TE1:
7687 {
7688 output_bit = HRTIM_OENR_TE1OEN;
7689 break;
7690 }
7691
7692 case HRTIM_OUTPUT_TE2:
7693 {
7694 output_bit = HRTIM_OENR_TE2OEN;
7695 break;
7696 }
7697
7698 case HRTIM_OUTPUT_TF1:
7699 {
7700 output_bit = HRTIM_OENR_TF1OEN;
7701 break;
7702 }
7703
7704 case HRTIM_OUTPUT_TF2:
7705 {
7706 output_bit = HRTIM_OENR_TF2OEN;
7707 break;
7708 }
7709
7710 default:
7711 {
7712 output_bit = 0UL;
7713 break;
7714 }
7715 }
7716
7717 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
7718 {
7719 /* Output is enabled: output in RUN state (whatever output disable status is)*/
7720 output_state = HRTIM_OUTPUTSTATE_RUN;
7721 }
7722 else
7723 {
7724 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
7725 {
7726 /* Output is disabled: output in FAULT state */
7727 output_state = HRTIM_OUTPUTSTATE_FAULT;
7728 }
7729 else
7730 {
7731 /* Output is disabled: output in IDLE state */
7732 output_state = HRTIM_OUTPUTSTATE_IDLE;
7733 }
7734 }
7735
7736 return (output_state);
7737 }
7738
7739 /**
7740 * @brief Return the level (active or inactive) of the designated output
7741 * when the delayed protection was triggered.
7742 * @param hhrtim pointer to HAL HRTIM handle
7743 * @param TimerIdx Timer index
7744 * This parameter can be one of the following values:
7745 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7746 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7747 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7748 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7749 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7750 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7751 * @param Output Timer output
7752 * This parameter can be one of the following values:
7753 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7754 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7755 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7756 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7757 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7758 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7759 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7760 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7761 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7762 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7763 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7764 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7765 * @retval Delayed protection status
7766 */
HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7767 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
7768 uint32_t TimerIdx,
7769 uint32_t Output)
7770 {
7771 uint32_t delayed_protection_status;
7772
7773 /* Check parameters */
7774 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7775
7776 /* Read the delayed protection status */
7777 switch (Output)
7778 {
7779 case HRTIM_OUTPUT_TA1:
7780 case HRTIM_OUTPUT_TB1:
7781 case HRTIM_OUTPUT_TC1:
7782 case HRTIM_OUTPUT_TD1:
7783 case HRTIM_OUTPUT_TE1:
7784 case HRTIM_OUTPUT_TF1:
7785 {
7786 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
7787 {
7788 /* Output 1 was active when the delayed idle protection was triggered */
7789 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7790 }
7791 else
7792 {
7793 /* Output 1 was inactive when the delayed idle protection was triggered */
7794 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7795 }
7796 break;
7797 }
7798
7799 case HRTIM_OUTPUT_TA2:
7800 case HRTIM_OUTPUT_TB2:
7801 case HRTIM_OUTPUT_TC2:
7802 case HRTIM_OUTPUT_TD2:
7803 case HRTIM_OUTPUT_TE2:
7804 case HRTIM_OUTPUT_TF2:
7805 {
7806 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
7807 {
7808 /* Output 2 was active when the delayed idle protection was triggered */
7809 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7810 }
7811 else
7812 {
7813 /* Output 2 was inactive when the delayed idle protection was triggered */
7814 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7815 }
7816 break;
7817 }
7818
7819 default:
7820 {
7821 delayed_protection_status = 0xFFFFFFFFUL;
7822 break;
7823 }
7824 }
7825
7826 return delayed_protection_status;
7827 }
7828
7829 /**
7830 * @brief Return the actual status (active or inactive) of the burst mode controller
7831 * @param hhrtim pointer to HAL HRTIM handle
7832 * @retval Burst mode controller status
7833 */
HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)7834 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim)
7835 {
7836 uint32_t burst_mode_status;
7837
7838 /* Read burst mode status */
7839 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
7840
7841 return burst_mode_status;
7842 }
7843
7844 /**
7845 * @brief Indicate on which output the signal is currently active (when the
7846 * push pull mode is enabled).
7847 * @param hhrtim pointer to HAL HRTIM handle
7848 * @param TimerIdx Timer index
7849 * This parameter can be one of the following values:
7850 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7851 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7852 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7853 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7854 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7855 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7856 * @retval Burst mode controller status
7857 */
HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7858 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
7859 uint32_t TimerIdx)
7860 {
7861 uint32_t current_pushpull_status;
7862
7863 /* Check the parameters */
7864 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7865
7866 /* Read current push pull status */
7867 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
7868
7869 return current_pushpull_status;
7870 }
7871
7872
7873 /**
7874 * @brief Indicate on which output the signal was applied, in push-pull mode,
7875 balanced fault mode or delayed idle mode, when the protection was triggered.
7876 * @param hhrtim pointer to HAL HRTIM handle
7877 * @param TimerIdx Timer index
7878 * This parameter can be one of the following values:
7879 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7880 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7881 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7882 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7883 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7884 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7885 * @retval Idle Push Pull Status
7886 */
HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7887 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
7888 uint32_t TimerIdx)
7889 {
7890 uint32_t idle_pushpull_status;
7891
7892 /* Check the parameters */
7893 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7894
7895 /* Read current push pull status */
7896 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
7897
7898 return idle_pushpull_status;
7899 }
7900
7901 /**
7902 * @}
7903 */
7904
7905 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
7906 * @brief Functions called when HRTIM generates an interrupt
7907 * 7 interrupts can be generated by the master timer:
7908 * - Master timer registers update
7909 * - Synchronization event received
7910 * - Master timer repetition event
7911 * - Master Compare 1 to 4 event
7912 * 14 interrupts can be generated by each timing unit:
7913 * - Delayed protection triggered
7914 * - Counter reset or roll-over event
7915 * - Output 1 and output 2 reset (transition active to inactive)
7916 * - Output 1 and output 2 set (transition inactive to active)
7917 * - Capture 1 and 2 events
7918 * - Timing unit registers update
7919 * - Repetition event
7920 * - Compare 1 to 4 event
7921 * 8 global interrupts are generated for the whole HRTIM:
7922 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
7923 * - DLL calibration done
7924 * - Burst mode period completed
7925 @verbatim
7926 ===============================================================================
7927 ##### HRTIM interrupts handling #####
7928 ===============================================================================
7929 [..]
7930 This subsection provides a set of functions allowing to manage the HRTIM
7931 interrupts:
7932 (+) HRTIM interrupt handler
7933 (+) Callback function called when Fault1 interrupt occurs
7934 (+) Callback function called when Fault2 interrupt occurs
7935 (+) Callback function called when Fault3 interrupt occurs
7936 (+) Callback function called when Fault4 interrupt occurs
7937 (+) Callback function called when Fault5 interrupt occurs
7938 (+) Callback function called when Fault6 interrupt occurs
7939 (+) Callback function called when system Fault interrupt occurs
7940 (+) Callback function called when DLL ready interrupt occurs
7941 (+) Callback function called when burst mode period interrupt occurs
7942 (+) Callback function called when synchronization input interrupt occurs
7943 (+) Callback function called when a timer register update interrupt occurs
7944 (+) Callback function called when a timer repetition interrupt occurs
7945 (+) Callback function called when a compare 1 match interrupt occurs
7946 (+) Callback function called when a compare 2 match interrupt occurs
7947 (+) Callback function called when a compare 3 match interrupt occurs
7948 (+) Callback function called when a compare 4 match interrupt occurs
7949 (+) Callback function called when a capture 1 interrupt occurs
7950 (+) Callback function called when a capture 2 interrupt occurs
7951 (+) Callback function called when a delayed protection interrupt occurs
7952 (+) Callback function called when a timer counter reset interrupt occurs
7953 (+) Callback function called when a timer output 1 set interrupt occurs
7954 (+) Callback function called when a timer output 1 reset interrupt occurs
7955 (+) Callback function called when a timer output 2 set interrupt occurs
7956 (+) Callback function called when a timer output 2 reset interrupt occurs
7957 (+) Callback function called when a timer output 2 reset interrupt occurs
7958 (+) Callback function called upon completion of a burst DMA transfer
7959 (+) HRTIM callback function registration
7960 (+) HRTIM callback function unregistration
7961 (+) HRTIM Timer x callback function registration
7962 (+) HRTIM Timer x callback function unregistration
7963
7964 @endverbatim
7965 * @{
7966 */
7967
7968 /**
7969 * @brief This function handles HRTIM interrupt request.
7970 * @param hhrtim pointer to HAL HRTIM handle
7971 * @param TimerIdx Timer index
7972 * This parameter can be any value of HRTIM_Timer_Index
7973 * @retval None
7974 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7975 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
7976 uint32_t TimerIdx)
7977 {
7978 /* HRTIM interrupts handling */
7979 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
7980 {
7981 HRTIM_HRTIM_ISR(hhrtim);
7982 }
7983 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
7984 {
7985 /* Master related interrupts handling */
7986 HRTIM_Master_ISR(hhrtim);
7987 }
7988 else
7989 {
7990 /* Timing unit related interrupts handling */
7991 HRTIM_Timer_ISR(hhrtim, TimerIdx);
7992 }
7993
7994 }
7995
7996 /**
7997 * @brief Callback function invoked when a fault 1 interrupt occurred
7998 * @param hhrtim pointer to HAL HRTIM handle * @retval None
7999 * @retval None
8000 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)8001 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim)
8002 {
8003 /* Prevent unused argument(s) compilation warning */
8004 UNUSED(hhrtim);
8005
8006 /* NOTE : This function should not be modified, when the callback is needed,
8007 the HAL_HRTIM_Fault1Callback could be implemented in the user file
8008 */
8009 }
8010
8011 /**
8012 * @brief Callback function invoked when a fault 2 interrupt occurred
8013 * @param hhrtim pointer to HAL HRTIM handle
8014 * @retval None
8015 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)8016 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim)
8017 {
8018 /* Prevent unused argument(s) compilation warning */
8019 UNUSED(hhrtim);
8020
8021 /* NOTE : This function should not be modified, when the callback is needed,
8022 the HAL_HRTIM_Fault2Callback could be implemented in the user file
8023 */
8024 }
8025
8026 /**
8027 * @brief Callback function invoked when a fault 3 interrupt occurred
8028 * @param hhrtim pointer to HAL HRTIM handle
8029 * @retval None
8030 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)8031 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim)
8032 {
8033 /* Prevent unused argument(s) compilation warning */
8034 UNUSED(hhrtim);
8035
8036 /* NOTE : This function should not be modified, when the callback is needed,
8037 the HAL_HRTIM_Fault3Callback could be implemented in the user file
8038 */
8039 }
8040
8041 /**
8042 * @brief Callback function invoked when a fault 4 interrupt occurred
8043 * @param hhrtim pointer to HAL HRTIM handle
8044 * @retval None
8045 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)8046 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim)
8047 {
8048 /* Prevent unused argument(s) compilation warning */
8049 UNUSED(hhrtim);
8050
8051 /* NOTE : This function should not be modified, when the callback is needed,
8052 the HAL_HRTIM_Fault4Callback could be implemented in the user file
8053 */
8054 }
8055
8056 /**
8057 * @brief Callback function invoked when a fault 5 interrupt occurred
8058 * @param hhrtim pointer to HAL HRTIM handle
8059 * @retval None
8060 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)8061 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim)
8062 {
8063 /* Prevent unused argument(s) compilation warning */
8064 UNUSED(hhrtim);
8065
8066 /* NOTE : This function should not be modified, when the callback is needed,
8067 the HAL_HRTIM_Fault5Callback could be implemented in the user file
8068 */
8069 }
8070
8071 /**
8072 * @brief Callback function invoked when a fault 6 interrupt occurred
8073 * @param hhrtim pointer to HAL HRTIM handle
8074 * @retval None
8075 */
HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim)8076 __weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim)
8077 {
8078 /* Prevent unused argument(s) compilation warning */
8079 UNUSED(hhrtim);
8080
8081 /* NOTE : This function should not be modified, when the callback is needed,
8082 the HAL_HRTIM_Fault6Callback could be implemented in the user file
8083 */
8084 }
8085
8086 /**
8087 * @brief Callback function invoked when a system fault interrupt occurred
8088 * @param hhrtim pointer to HAL HRTIM handle
8089 * @retval None
8090 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)8091 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim)
8092 {
8093 /* Prevent unused argument(s) compilation warning */
8094 UNUSED(hhrtim);
8095
8096 /* NOTE : This function should not be modified, when the callback is needed,
8097 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
8098 */
8099 }
8100
8101 /**
8102 * @brief Callback function invoked when the DLL calibration is completed
8103 * @param hhrtim pointer to HAL HRTIM handle
8104 * @retval None
8105 */
HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)8106 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim)
8107 {
8108 /* Prevent unused argument(s) compilation warning */
8109 UNUSED(hhrtim);
8110
8111 /* NOTE : This function should not be modified, when the callback is needed,
8112 the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
8113 */
8114 }
8115
8116 /**
8117 * @brief Callback function invoked when the end of the burst mode period is reached
8118 * @param hhrtim pointer to HAL HRTIM handle
8119 * @retval None
8120 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)8121 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim)
8122 {
8123 /* Prevent unused argument(s) compilation warning */
8124 UNUSED(hhrtim);
8125
8126 /* NOTE : This function should not be modified, when the callback is needed,
8127 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
8128 */
8129 }
8130
8131 /**
8132 * @brief Callback function invoked when a synchronization input event is received
8133 * @param hhrtim pointer to HAL HRTIM handle
8134 * @retval None
8135 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)8136 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim)
8137 {
8138 /* Prevent unused argument(s) compilation warning */
8139 UNUSED(hhrtim);
8140
8141 /* NOTE : This function should not be modified, when the callback is needed,
8142 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
8143 */
8144 }
8145
8146 /**
8147 * @brief Callback function invoked when timer registers are updated
8148 * @param hhrtim pointer to HAL HRTIM handle
8149 * @param TimerIdx Timer index
8150 * This parameter can be one of the following values:
8151 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8152 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8153 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8154 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8155 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8156 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8157 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8158 * @retval None
8159 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8160 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
8161 uint32_t TimerIdx)
8162 {
8163 /* Prevent unused argument(s) compilation warning */
8164 UNUSED(hhrtim);
8165 UNUSED(TimerIdx);
8166
8167 /* NOTE : This function should not be modified, when the callback is needed,
8168 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
8169 */
8170 }
8171
8172 /**
8173 * @brief Callback function invoked when timer repetition period has elapsed
8174 * @param hhrtim pointer to HAL HRTIM handle
8175 * @param TimerIdx Timer index
8176 * This parameter can be one of the following values:
8177 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8178 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8179 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8180 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8181 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8182 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8183 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8184 * @retval None
8185 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8186 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
8187 uint32_t TimerIdx)
8188 {
8189 /* Prevent unused argument(s) compilation warning */
8190 UNUSED(hhrtim);
8191 UNUSED(TimerIdx);
8192
8193 /* NOTE : This function should not be modified, when the callback is needed,
8194 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
8195 */
8196 }
8197
8198 /**
8199 * @brief Callback function invoked when the timer counter matches the value
8200 * programmed in the compare 1 register
8201 * @param hhrtim pointer to HAL HRTIM handle
8202 * @param TimerIdx Timer index
8203 * This parameter can be one of the following values:
8204 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8205 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8206 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8207 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8208 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8209 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8210 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8211 * @retval None
8212 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8213 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
8214 uint32_t TimerIdx)
8215 {
8216 /* Prevent unused argument(s) compilation warning */
8217 UNUSED(hhrtim);
8218 UNUSED(TimerIdx);
8219
8220 /* NOTE : This function should not be modified, when the callback is needed,
8221 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
8222 */
8223 }
8224
8225 /**
8226 * @brief Callback function invoked when the timer counter matches the value
8227 * programmed in the compare 2 register
8228 * @param hhrtim pointer to HAL HRTIM handle
8229 * @retval None
8230 * @param TimerIdx Timer index
8231 * This parameter can be one of the following values:
8232 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8233 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8234 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8235 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8236 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8237 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8238 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8239 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8240 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
8241 uint32_t TimerIdx)
8242 {
8243 /* Prevent unused argument(s) compilation warning */
8244 UNUSED(hhrtim);
8245 UNUSED(TimerIdx);
8246
8247 /* NOTE : This function should not be modified, when the callback is needed,
8248 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
8249 */
8250 }
8251
8252 /**
8253 * @brief Callback function invoked when the timer counter matches the value
8254 * programmed in the compare 3 register
8255 * @param hhrtim pointer to HAL HRTIM handle
8256 * @param TimerIdx Timer index
8257 * This parameter can be one of the following values:
8258 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8259 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8260 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8261 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8262 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8263 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8264 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8265 * @retval None
8266 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8267 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
8268 uint32_t TimerIdx)
8269 {
8270 /* Prevent unused argument(s) compilation warning */
8271 UNUSED(hhrtim);
8272 UNUSED(TimerIdx);
8273
8274 /* NOTE : This function should not be modified, when the callback is needed,
8275 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
8276 */
8277 }
8278
8279 /**
8280 * @brief Callback function invoked when the timer counter matches the value
8281 * programmed in the compare 4 register.
8282 * @param hhrtim pointer to HAL HRTIM handle
8283 * @param TimerIdx Timer index
8284 * This parameter can be one of the following values:
8285 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8286 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8287 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8288 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8289 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8290 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8291 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8292 * @retval None
8293 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8294 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
8295 uint32_t TimerIdx)
8296 {
8297 /* Prevent unused argument(s) compilation warning */
8298 UNUSED(hhrtim);
8299 UNUSED(TimerIdx);
8300
8301 /* NOTE : This function should not be modified, when the callback is needed,
8302 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
8303 */
8304 }
8305
8306 /**
8307 * @brief Callback function invoked when the timer x capture 1 event occurs
8308 * @param hhrtim pointer to HAL HRTIM handle
8309 * @param TimerIdx Timer index
8310 * This parameter can be one of the following values:
8311 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8312 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8313 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8314 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8315 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8316 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8317 * @retval None
8318 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8319 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
8320 uint32_t TimerIdx)
8321 {
8322 /* Prevent unused argument(s) compilation warning */
8323 UNUSED(hhrtim);
8324 UNUSED(TimerIdx);
8325
8326 /* NOTE : This function should not be modified, when the callback is needed,
8327 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
8328 */
8329 }
8330
8331 /**
8332 * @brief Callback function invoked when the timer x capture 2 event occurs
8333 * @param hhrtim pointer to HAL HRTIM handle
8334 * @param TimerIdx Timer index
8335 * This parameter can be one of the following values:
8336 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8337 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8338 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8339 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8340 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8341 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8342 * @retval None
8343 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8344 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
8345 uint32_t TimerIdx)
8346 {
8347 /* Prevent unused argument(s) compilation warning */
8348 UNUSED(hhrtim);
8349 UNUSED(TimerIdx);
8350
8351 /* NOTE : This function should not be modified, when the callback is needed,
8352 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
8353 */
8354 }
8355
8356 /**
8357 * @brief Callback function invoked when the delayed idle or balanced idle mode is
8358 * entered.
8359 * @param hhrtim pointer to HAL HRTIM handle
8360 * @param TimerIdx Timer index
8361 * This parameter can be one of the following values:
8362 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8363 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8364 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8365 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8366 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8367 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8368 * @retval None
8369 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8370 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
8371 uint32_t TimerIdx)
8372 {
8373 /* Prevent unused argument(s) compilation warning */
8374 UNUSED(hhrtim);
8375 UNUSED(TimerIdx);
8376
8377 /* NOTE : This function should not be modified, when the callback is needed,
8378 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
8379 */
8380 }
8381
8382 /**
8383 * @brief Callback function invoked when the timer x counter reset/roll-over
8384 * event occurs.
8385 * @param hhrtim pointer to HAL HRTIM handle
8386 * @param TimerIdx Timer index
8387 * This parameter can be one of the following values:
8388 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8389 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8390 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8391 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8392 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8393 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8394 * @retval None
8395 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8396 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
8397 uint32_t TimerIdx)
8398 {
8399 /* Prevent unused argument(s) compilation warning */
8400 UNUSED(hhrtim);
8401 UNUSED(TimerIdx);
8402
8403 /* NOTE : This function should not be modified, when the callback is needed,
8404 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
8405 */
8406 }
8407
8408 /**
8409 * @brief Callback function invoked when the timer x output 1 is set
8410 * @param hhrtim pointer to HAL HRTIM handle
8411 * @param TimerIdx Timer index
8412 * This parameter can be one of the following values:
8413 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8414 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8415 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8416 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8417 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8418 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8419 * @retval None
8420 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8421 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
8422 uint32_t TimerIdx)
8423 {
8424 /* Prevent unused argument(s) compilation warning */
8425 UNUSED(hhrtim);
8426 UNUSED(TimerIdx);
8427
8428 /* NOTE : This function should not be modified, when the callback is needed,
8429 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
8430 */
8431 }
8432
8433 /**
8434 * @brief Callback function invoked when the timer x output 1 is reset
8435 * @param hhrtim pointer to HAL HRTIM handle
8436 * @param TimerIdx Timer index
8437 * This parameter can be one of the following values:
8438 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8439 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8440 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8441 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8442 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8443 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8444 * @retval None
8445 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8446 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
8447 uint32_t TimerIdx)
8448 {
8449 /* Prevent unused argument(s) compilation warning */
8450 UNUSED(hhrtim);
8451 UNUSED(TimerIdx);
8452
8453 /* NOTE : This function should not be modified, when the callback is needed,
8454 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
8455 */
8456 }
8457
8458 /**
8459 * @brief Callback function invoked when the timer x output 2 is set
8460 * @param hhrtim pointer to HAL HRTIM handle
8461 * @param TimerIdx Timer index
8462 * This parameter can be one of the following values:
8463 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8464 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8465 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8466 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8467 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8468 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8469 * @retval None
8470 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8471 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
8472 uint32_t TimerIdx)
8473 {
8474 /* Prevent unused argument(s) compilation warning */
8475 UNUSED(hhrtim);
8476 UNUSED(TimerIdx);
8477
8478 /* NOTE : This function should not be modified, when the callback is needed,
8479 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
8480 */
8481 }
8482
8483 /**
8484 * @brief Callback function invoked when the timer x output 2 is reset
8485 * @param hhrtim pointer to HAL HRTIM handle
8486 * @param TimerIdx Timer index
8487 * This parameter can be one of the following values:
8488 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8489 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8490 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8491 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8492 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8493 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8494 * @retval None
8495 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8496 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
8497 uint32_t TimerIdx)
8498 {
8499 /* Prevent unused argument(s) compilation warning */
8500 UNUSED(hhrtim);
8501 UNUSED(TimerIdx);
8502
8503 /* NOTE : This function should not be modified, when the callback is needed,
8504 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
8505 */
8506 }
8507
8508 /**
8509 * @brief Callback function invoked when a DMA burst transfer is completed
8510 * @param hhrtim pointer to HAL HRTIM handle
8511 * @param TimerIdx Timer index
8512 * This parameter can be one of the following values:
8513 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8514 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8515 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8516 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8517 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8518 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8519 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8520 * @retval None
8521 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8522 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
8523 uint32_t TimerIdx)
8524 {
8525 /* Prevent unused argument(s) compilation warning */
8526 UNUSED(hhrtim);
8527 UNUSED(TimerIdx);
8528
8529 /* NOTE : This function should not be modified, when the callback is needed,
8530 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
8531 */
8532 }
8533
8534 /**
8535 * @brief Callback function invoked when a DMA error occurs
8536 * @param hhrtim pointer to HAL HRTIM handle
8537 * @retval None
8538 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)8539 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
8540 {
8541 /* Prevent unused argument(s) compilation warning */
8542 UNUSED(hhrtim);
8543
8544 /* NOTE : This function should not be modified, when the callback is needed,
8545 the HAL_HRTIM_ErrorCallback could be implemented in the user file
8546 */
8547 }
8548
8549 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8550 /**
8551 * @brief HRTIM callback function registration
8552 * @param hhrtim pointer to HAL HRTIM handle
8553 * @param CallbackID ID of the HRTIM callback function to register
8554 * This parameter can be one of the following values:
8555 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8556 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8557 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8558 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8559 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8560 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8561 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8562 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8563 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8564 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8565 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8566 * @arg HAL_HRTIM_MSPINIT_CB_ID
8567 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8568 * @param pCallback Callback function pointer
8569 * @retval HAL status
8570 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)8571 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim,
8572 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8573 pHRTIM_CallbackTypeDef pCallback)
8574 {
8575 HAL_StatusTypeDef status = HAL_OK;
8576
8577 if (pCallback == NULL)
8578 {
8579 /* Update the state */
8580 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8581
8582 return HAL_ERROR;
8583 }
8584
8585 /* Process locked */
8586 __HAL_LOCK(hhrtim);
8587
8588 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8589 {
8590 switch (CallbackID)
8591 {
8592 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8593 hhrtim->Fault1Callback = pCallback;
8594 break;
8595
8596 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8597 hhrtim->Fault2Callback = pCallback;
8598 break;
8599
8600 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8601 hhrtim->Fault3Callback = pCallback;
8602 break;
8603
8604 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8605 hhrtim->Fault4Callback = pCallback;
8606 break;
8607
8608 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8609 hhrtim->Fault5Callback = pCallback;
8610 break;
8611
8612 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8613 hhrtim->Fault6Callback = pCallback;
8614 break;
8615
8616 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8617 hhrtim->SystemFaultCallback = pCallback;
8618 break;
8619
8620 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8621 hhrtim->DLLCalibrationReadyCallback = pCallback;
8622 break;
8623
8624 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8625 hhrtim->BurstModePeriodCallback = pCallback;
8626 break;
8627
8628 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8629 hhrtim->SynchronizationEventCallback = pCallback;
8630 break;
8631
8632 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8633 hhrtim->ErrorCallback = pCallback;
8634 break;
8635
8636 case HAL_HRTIM_MSPINIT_CB_ID :
8637 hhrtim->MspInitCallback = pCallback;
8638 break;
8639
8640 case HAL_HRTIM_MSPDEINIT_CB_ID :
8641 hhrtim->MspDeInitCallback = pCallback;
8642 break;
8643
8644 default :
8645 /* Update the state */
8646 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8647
8648 /* Return error status */
8649 status = HAL_ERROR;
8650 break;
8651 }
8652 }
8653 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8654 {
8655 switch (CallbackID)
8656 {
8657 case HAL_HRTIM_MSPINIT_CB_ID :
8658 hhrtim->MspInitCallback = pCallback;
8659 break;
8660
8661 case HAL_HRTIM_MSPDEINIT_CB_ID :
8662 hhrtim->MspDeInitCallback = pCallback;
8663 break;
8664
8665 default :
8666 /* Update the state */
8667 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8668
8669 /* Return error status */
8670 status = HAL_ERROR;
8671 break;
8672 }
8673 }
8674 else
8675 {
8676 /* Update the state */
8677 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8678
8679 /* Return error status */
8680 status = HAL_ERROR;
8681 }
8682
8683 /* Release Lock */
8684 __HAL_UNLOCK(hhrtim);
8685
8686 return status;
8687 }
8688
8689 /**
8690 * @brief HRTIM callback function un-registration
8691 * @param hhrtim pointer to HAL HRTIM handle
8692 * @param CallbackID ID of the HRTIM callback function to unregister
8693 * This parameter can be one of the following values:
8694 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8695 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8696 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8697 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8698 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8699 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8700 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8701 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8702 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8703 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8704 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8705 * @arg HAL_HRTIM_MSPINIT_CB_ID
8706 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8707 * @retval HAL status
8708 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)8709 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
8710 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8711 {
8712 HAL_StatusTypeDef status = HAL_OK;
8713
8714 /* Process locked */
8715 __HAL_LOCK(hhrtim);
8716
8717 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8718 {
8719 switch (CallbackID)
8720 {
8721 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8722 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
8723 break;
8724
8725 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8726 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
8727 break;
8728
8729 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8730 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
8731 break;
8732
8733 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8734 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
8735 break;
8736
8737 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8738 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
8739 break;
8740
8741 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8742 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
8743 break;
8744
8745 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8746 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
8747 break;
8748
8749 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8750 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
8751 break;
8752
8753 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8754 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
8755 break;
8756
8757 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8758 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
8759 break;
8760
8761 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8762 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
8763 break;
8764
8765 case HAL_HRTIM_MSPINIT_CB_ID :
8766 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8767 break;
8768
8769 case HAL_HRTIM_MSPDEINIT_CB_ID :
8770 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8771 break;
8772
8773 default :
8774 /* Update the state */
8775 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8776
8777 /* Return error status */
8778 status = HAL_ERROR;
8779 break;
8780 }
8781 }
8782 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8783 {
8784 switch (CallbackID)
8785 {
8786 case HAL_HRTIM_MSPINIT_CB_ID :
8787 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8788 break;
8789
8790 case HAL_HRTIM_MSPDEINIT_CB_ID :
8791 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8792 break;
8793
8794 default :
8795 /* Update the state */
8796 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8797
8798 /* Return error status */
8799 status = HAL_ERROR;
8800 break;
8801 }
8802 }
8803 else
8804 {
8805 /* Update the state */
8806 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8807
8808 /* Return error status */
8809 status = HAL_ERROR;
8810 }
8811
8812 /* Release Lock */
8813 __HAL_UNLOCK(hhrtim);
8814
8815 return status;
8816 }
8817
8818 /**
8819 * @brief HRTIM Timer x callback function registration
8820 * @param hhrtim pointer to HAL HRTIM handle
8821 * @param CallbackID ID of the HRTIM Timer x callback function to register
8822 * This parameter can be one of the following values:
8823 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8824 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8825 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8826 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8827 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8828 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8829 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8830 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8831 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8832 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8833 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8834 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8835 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8836 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8837 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8838 * @param pCallback Callback function pointer
8839 * @retval HAL status
8840 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)8841 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
8842 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8843 pHRTIM_TIMxCallbackTypeDef pCallback)
8844 {
8845 HAL_StatusTypeDef status = HAL_OK;
8846
8847 if (pCallback == NULL)
8848 {
8849 /* Update the state */
8850 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8851
8852 return HAL_ERROR;
8853 }
8854
8855 /* Process locked */
8856 __HAL_LOCK(hhrtim);
8857
8858 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8859 {
8860 switch (CallbackID)
8861 {
8862 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
8863 hhrtim->RegistersUpdateCallback = pCallback;
8864 break;
8865
8866 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
8867 hhrtim->RepetitionEventCallback = pCallback;
8868 break;
8869
8870 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
8871 hhrtim->Compare1EventCallback = pCallback;
8872 break;
8873
8874 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
8875 hhrtim->Compare2EventCallback = pCallback;
8876 break;
8877
8878 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
8879 hhrtim->Compare3EventCallback = pCallback;
8880 break;
8881
8882 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
8883 hhrtim->Compare4EventCallback = pCallback;
8884 break;
8885
8886 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
8887 hhrtim->Capture1EventCallback = pCallback;
8888 break;
8889
8890 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
8891 hhrtim->Capture2EventCallback = pCallback;
8892 break;
8893
8894 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
8895 hhrtim->DelayedProtectionCallback = pCallback;
8896 break;
8897
8898 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
8899 hhrtim->CounterResetCallback = pCallback;
8900 break;
8901
8902 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
8903 hhrtim->Output1SetCallback = pCallback;
8904 break;
8905
8906 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
8907 hhrtim->Output1ResetCallback = pCallback;
8908 break;
8909
8910 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
8911 hhrtim->Output2SetCallback = pCallback;
8912 break;
8913
8914 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
8915 hhrtim->Output2ResetCallback = pCallback;
8916 break;
8917
8918 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
8919 hhrtim->BurstDMATransferCallback = pCallback;
8920 break;
8921
8922 default :
8923 /* Update the state */
8924 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8925
8926 /* Return error status */
8927 status = HAL_ERROR;
8928 break;
8929 }
8930 }
8931 else
8932 {
8933 /* Update the state */
8934 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8935
8936 /* Return error status */
8937 status = HAL_ERROR;
8938 }
8939
8940 /* Release Lock */
8941 __HAL_UNLOCK(hhrtim);
8942
8943 return status;
8944 }
8945
8946 /**
8947 * @brief HRTIM Timer x callback function un-registration
8948 * @param hhrtim pointer to HAL HRTIM handle
8949 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
8950 * This parameter can be one of the following values:
8951 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8952 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8953 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8954 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8955 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8956 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8957 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8958 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8959 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8960 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8961 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8962 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8963 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8964 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8965 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8966 * @retval HAL status
8967 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)8968 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
8969 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8970 {
8971 HAL_StatusTypeDef status = HAL_OK;
8972
8973 /* Process locked */
8974 __HAL_LOCK(hhrtim);
8975
8976 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8977 {
8978 switch (CallbackID)
8979 {
8980 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
8981 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
8982 break;
8983
8984 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
8985 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
8986 break;
8987
8988 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
8989 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
8990 break;
8991
8992 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
8993 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
8994 break;
8995
8996 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
8997 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
8998 break;
8999
9000 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
9001 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
9002 break;
9003
9004 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
9005 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
9006 break;
9007
9008 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
9009 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
9010 break;
9011
9012 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
9013 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
9014 break;
9015
9016 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
9017 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
9018 break;
9019
9020 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
9021 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
9022 break;
9023
9024 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
9025 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
9026 break;
9027
9028 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
9029 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
9030 break;
9031
9032 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
9033 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
9034 break;
9035
9036 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
9037 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
9038 break;
9039
9040 default :
9041 /* Update the state */
9042 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9043
9044 /* Return error status */
9045 status = HAL_ERROR;
9046 break;
9047 }
9048 }
9049 else
9050 {
9051 /* Update the state */
9052 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9053
9054 /* Return error status */
9055 status = HAL_ERROR;
9056 }
9057
9058 /* Release Lock */
9059 __HAL_UNLOCK(hhrtim);
9060
9061 return status;
9062 }
9063 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9064 /**
9065 * @}
9066 */
9067
9068 /**
9069 * @}
9070 */
9071
9072 /** @addtogroup HRTIM_Private_Functions
9073 * @{
9074 */
9075
9076 /**
9077 * @brief Configure the master timer time base
9078 * @param hhrtim pointer to HAL HRTIM handle
9079 * @param pTimeBaseCfg pointer to the time base configuration structure
9080 * @retval None
9081 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)9082 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
9083 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
9084 {
9085 uint32_t hrtim_mcr;
9086
9087 /* Configure master timer */
9088 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9089
9090 /* Set the prescaler ratio */
9091 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
9092 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9093
9094 /* Set the operating mode */
9095 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
9096 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
9097
9098 /* Update the HRTIM registers */
9099 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9100 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
9101 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
9102 }
9103
9104 /**
9105 * @brief Configure timing unit (Timer A to Timer F) time base
9106 * @param hhrtim pointer to HAL HRTIM handle
9107 * @param TimerIdx Timer index
9108 * @param pTimeBaseCfg pointer to the time base configuration structure
9109 * @retval None
9110 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)9111 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
9112 uint32_t TimerIdx,
9113 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
9114 {
9115 uint32_t hrtim_timcr;
9116
9117 /* Configure master timing unit */
9118 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9119
9120 /* Set the prescaler ratio */
9121 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
9122 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9123
9124 /* Set the operating mode */
9125 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
9126 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
9127
9128 /* Update the HRTIM registers */
9129 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9130 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
9131 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
9132 }
9133
9134 /**
9135 * @brief Configure the master timer in waveform mode
9136 * @param hhrtim pointer to HAL HRTIM handle
9137 * @param pTimerCfg pointer to the timer configuration data structure
9138 * @retval None
9139 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,const HRTIM_TimerCfgTypeDef * pTimerCfg)9140 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
9141 const HRTIM_TimerCfgTypeDef *pTimerCfg)
9142 {
9143 uint32_t hrtim_mcr;
9144 uint32_t hrtim_bmcr;
9145
9146 /* Configure master timer */
9147 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9148 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9149
9150 /* Enable/Disable the half mode */
9151 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9152 hrtim_mcr |= pTimerCfg->HalfModeEnable;
9153
9154 /* INTLVD bits are set to 00 */
9155 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9156 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
9157 || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9158 {
9159 /* INTLVD bits set to 00 */
9160 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9161 hrtim_mcr |= (HRTIM_MCR_HALF);
9162 }
9163 else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9164 {
9165 hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
9166 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
9167 }
9168 else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9169 {
9170 hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
9171 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
9172 }
9173 else
9174 {
9175 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9176 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9177 }
9178
9179 /* Enable/Disable the timer start upon synchronization event reception */
9180 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
9181 hrtim_mcr |= pTimerCfg->StartOnSync;
9182
9183 /* Enable/Disable the timer reset upon synchronization event reception */
9184 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
9185 hrtim_mcr |= pTimerCfg->ResetOnSync;
9186
9187 /* Enable/Disable the DAC synchronization event generation */
9188 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
9189 hrtim_mcr |= pTimerCfg->DACSynchro;
9190
9191 /* Enable/Disable preload mechanism for timer registers */
9192 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
9193 hrtim_mcr |= pTimerCfg->PreloadEnable;
9194
9195 /* Master timer registers update handling */
9196 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
9197 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
9198
9199 /* Enable/Disable registers update on repetition */
9200 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
9201 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
9202
9203 /* Set the timer burst mode */
9204 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
9205 hrtim_bmcr |= pTimerCfg->BurstMode;
9206
9207 /* Update the HRTIM registers */
9208 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9209 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9210 }
9211
9212 /**
9213 * @brief Configure timing unit (Timer A to Timer F) in waveform mode
9214 * @param hhrtim pointer to HAL HRTIM handle
9215 * @param TimerIdx Timer index
9216 * @param pTimerCfg pointer to the timer configuration data structure
9217 * @retval None
9218 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCfgTypeDef * pTimerCfg)9219 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
9220 uint32_t TimerIdx,
9221 const HRTIM_TimerCfgTypeDef *pTimerCfg)
9222 {
9223 uint32_t hrtim_timcr;
9224 uint32_t hrtim_timfltr;
9225 uint32_t hrtim_timoutr;
9226 uint32_t hrtim_timrstr;
9227 uint32_t hrtim_bmcr;
9228
9229 /* UPDGAT bitfield must be reset before programming a new value */
9230 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
9231
9232 /* Configure timing unit (Timer A to Timer F) */
9233 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9234 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
9235 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9236 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9237
9238 /* Enable/Disable the half mode */
9239 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9240 hrtim_timcr |= pTimerCfg->HalfModeEnable;
9241
9242 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
9243 || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9244 {
9245 /* INTLVD bits set to 00 */
9246 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9247 hrtim_timcr |= (HRTIM_TIMCR_HALF);
9248 }
9249 else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9250 {
9251 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
9252 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
9253 }
9254 else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9255 {
9256 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
9257 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
9258 }
9259 else
9260 {
9261 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9262 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9263 }
9264
9265 /* Enable/Disable the timer start upon synchronization event reception */
9266 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
9267 hrtim_timcr |= pTimerCfg->StartOnSync;
9268
9269 /* Enable/Disable the timer reset upon synchronization event reception */
9270 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
9271 hrtim_timcr |= pTimerCfg->ResetOnSync;
9272
9273 /* Enable/Disable the DAC synchronization event generation */
9274 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
9275 hrtim_timcr |= pTimerCfg->DACSynchro;
9276
9277 /* Enable/Disable preload mechanism for timer registers */
9278 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
9279 hrtim_timcr |= pTimerCfg->PreloadEnable;
9280
9281 /* Timing unit registers update handling */
9282 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
9283 hrtim_timcr |= pTimerCfg->UpdateGating;
9284
9285 /* Enable/Disable registers update on repetition */
9286 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
9287 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
9288 {
9289 hrtim_timcr |= HRTIM_TIMCR_TREPU;
9290 }
9291
9292 /* Set the push-pull mode */
9293 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
9294 hrtim_timcr |= pTimerCfg->PushPull;
9295
9296 /* Enable/Disable registers update on timer counter reset */
9297 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
9298 hrtim_timcr |= pTimerCfg->ResetUpdate;
9299
9300 /* Set the timer update trigger */
9301 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
9302 hrtim_timcr |= pTimerCfg->UpdateTrigger;
9303
9304 /* Enable/Disable the fault channel at timer level */
9305 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
9306 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
9307
9308 /* Lock/Unlock fault sources at timer level */
9309 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
9310 hrtim_timfltr |= pTimerCfg->FaultLock;
9311
9312 /* Enable/Disable dead time insertion at timer level */
9313 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
9314 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
9315
9316 /* Enable/Disable delayed protection at timer level
9317 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
9318 Balanced Idle is only available in push-pull mode
9319 */
9320 if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
9321 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
9322 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
9323 {
9324 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN);
9325 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
9326 }
9327
9328 /* Set the BIAR mode : one bit for both outputs */
9329 hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
9330 hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
9331
9332 /* Set the timer counter reset trigger */
9333 hrtim_timrstr = pTimerCfg->ResetTrigger;
9334
9335 /* Set the timer burst mode */
9336 switch (TimerIdx)
9337 {
9338 case HRTIM_TIMERINDEX_TIMER_A:
9339 {
9340 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
9341 hrtim_bmcr |= (pTimerCfg->BurstMode << 1U);
9342 break;
9343 }
9344
9345 case HRTIM_TIMERINDEX_TIMER_B:
9346 {
9347 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
9348 hrtim_bmcr |= (pTimerCfg->BurstMode << 2U);
9349 break;
9350 }
9351
9352 case HRTIM_TIMERINDEX_TIMER_C:
9353 {
9354 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
9355 hrtim_bmcr |= (pTimerCfg->BurstMode << 3U);
9356 break;
9357 }
9358
9359 case HRTIM_TIMERINDEX_TIMER_D:
9360 {
9361 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
9362 hrtim_bmcr |= (pTimerCfg->BurstMode << 4U);
9363 break;
9364 }
9365
9366 case HRTIM_TIMERINDEX_TIMER_E:
9367 {
9368 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
9369 hrtim_bmcr |= (pTimerCfg->BurstMode << 5U);
9370 break;
9371 }
9372
9373 case HRTIM_TIMERINDEX_TIMER_F:
9374 {
9375 hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
9376 hrtim_bmcr |= (pTimerCfg->BurstMode << 6U);
9377 break;
9378 }
9379
9380 default:
9381 break;
9382 }
9383
9384 /* Update the HRTIM registers */
9385 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9386 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
9387 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
9388 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
9389 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9390 }
9391
9392 /**
9393 * @brief Control timing unit (timer A to timer F) in waveform mode
9394 * @param hhrtim pointer to HAL HRTIM handle
9395 * @param TimerIdx Timer index
9396 * @param pTimerCtl pointer to the timer configuration data structure
9397 * @retval None
9398 */
HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,const HRTIM_TimerCtlTypeDef * pTimerCtl)9399 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim,
9400 uint32_t TimerIdx,
9401 const HRTIM_TimerCtlTypeDef *pTimerCtl)
9402 {
9403 uint32_t hrtim_timcr2;
9404
9405 /* Configure timing unit (Timer A to Timer F) */
9406 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9407
9408 /* Set the UpDown counting Mode */
9409 hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
9410 hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
9411
9412 /* Set the TrigHalf Mode : requires the counter to be disabled */
9413 hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
9414 hrtim_timcr2 |= pTimerCtl->TrigHalf;
9415
9416 /* define the compare event operating mode */
9417 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
9418 hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
9419
9420 /* define the compare event operating mode */
9421 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
9422 hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
9423
9424 if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
9425 {
9426 /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
9427 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
9428 hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
9429
9430 /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
9431 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
9432 hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
9433
9434 /* Enable the DualChannel DAC trigger */
9435 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
9436 hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
9437 }
9438 /* Update the HRTIM registers */
9439 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9440
9441 }
9442
9443 /**
9444 * @brief Configure timing RollOver Mode (Timer A to Timer F)
9445 * @param hhrtim pointer to HAL HRTIM handle
9446 * @param TimerIdx Timer index
9447 * @param pRollOverMode: a combination of the timer RollOver Mode configuration
9448 * @retval None
9449 */
HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t pRollOverMode)9450 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim,
9451 uint32_t TimerIdx,
9452 uint32_t pRollOverMode)
9453 {
9454 uint32_t hrtim_timcr2;
9455
9456 /* Configure timing unit (Timer A to Timer F) */
9457 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9458
9459 if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U)
9460 {
9461 /* xxROM bitfield must be reset before programming a new value */
9462 hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9463 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9464
9465 /* Update the HRTIM TIMxCR2 register */
9466 hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9467 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9468
9469 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9470 }
9471 }
9472
9473 /**
9474 * @brief Configure a capture unit
9475 * @param hhrtim pointer to HAL HRTIM handle
9476 * @param TimerIdx Timer index
9477 * @param CaptureUnit Capture unit identifier
9478 * @param Event Event reference
9479 * @retval None
9480 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)9481 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
9482 uint32_t TimerIdx,
9483 uint32_t CaptureUnit,
9484 uint32_t Event)
9485 {
9486 uint32_t CaptureTrigger = 0xFFFFFFFFU;
9487
9488 switch (Event)
9489 {
9490 case HRTIM_EVENT_1:
9491 {
9492 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
9493 break;
9494 }
9495
9496 case HRTIM_EVENT_2:
9497 {
9498 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
9499 break;
9500 }
9501
9502 case HRTIM_EVENT_3:
9503 {
9504 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
9505 break;
9506 }
9507
9508 case HRTIM_EVENT_4:
9509 {
9510 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
9511 break;
9512 }
9513
9514 case HRTIM_EVENT_5:
9515 {
9516 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
9517 break;
9518 }
9519
9520 case HRTIM_EVENT_6:
9521 {
9522 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
9523 break;
9524 }
9525
9526 case HRTIM_EVENT_7:
9527 {
9528 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
9529 break;
9530 }
9531
9532 case HRTIM_EVENT_8:
9533 {
9534 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
9535 break;
9536 }
9537
9538 case HRTIM_EVENT_9:
9539 {
9540 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
9541 break;
9542 }
9543
9544 case HRTIM_EVENT_10:
9545 {
9546 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
9547 break;
9548 }
9549
9550 default:
9551 break;
9552 }
9553
9554 switch (CaptureUnit)
9555 {
9556 case HRTIM_CAPTUREUNIT_1:
9557 {
9558 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
9559 break;
9560 }
9561
9562 case HRTIM_CAPTUREUNIT_2:
9563 {
9564 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
9565 break;
9566 }
9567
9568 default:
9569 break;
9570 }
9571 }
9572
9573 /**
9574 * @brief Configure the output of a timing unit
9575 * @param hhrtim pointer to HAL HRTIM handle
9576 * @param TimerIdx Timer index
9577 * @param Output timing unit output identifier
9578 * @param pOutputCfg pointer to the output configuration data structure
9579 * @retval None
9580 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,const HRTIM_OutputCfgTypeDef * pOutputCfg)9581 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
9582 uint32_t TimerIdx,
9583 uint32_t Output,
9584 const HRTIM_OutputCfgTypeDef *pOutputCfg)
9585 {
9586 uint32_t hrtim_outr;
9587 uint32_t hrtim_dtr;
9588
9589 uint32_t shift = 0U;
9590
9591 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9592 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
9593
9594 switch (Output)
9595 {
9596 case HRTIM_OUTPUT_TA1:
9597 case HRTIM_OUTPUT_TB1:
9598 case HRTIM_OUTPUT_TC1:
9599 case HRTIM_OUTPUT_TD1:
9600 case HRTIM_OUTPUT_TE1:
9601 case HRTIM_OUTPUT_TF1:
9602 {
9603 /* Set the output set/reset crossbar */
9604 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
9605 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
9606 break;
9607 }
9608
9609 case HRTIM_OUTPUT_TA2:
9610 case HRTIM_OUTPUT_TB2:
9611 case HRTIM_OUTPUT_TC2:
9612 case HRTIM_OUTPUT_TD2:
9613 case HRTIM_OUTPUT_TE2:
9614 case HRTIM_OUTPUT_TF2:
9615 {
9616 /* Set the output set/reset crossbar */
9617 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
9618 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
9619 shift = 16U;
9620 break;
9621 }
9622
9623 default:
9624 break;
9625 }
9626
9627 /* Clear output config */
9628 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
9629 HRTIM_OUTR_IDLM1 |
9630 HRTIM_OUTR_IDLES1 |
9631 HRTIM_OUTR_FAULT1 |
9632 HRTIM_OUTR_CHP1 |
9633 HRTIM_OUTR_DIDL1) << shift);
9634
9635 /* Set the polarity */
9636 hrtim_outr |= (pOutputCfg->Polarity << shift);
9637
9638 /* Set the IDLE mode */
9639 hrtim_outr |= (pOutputCfg->IdleMode << shift);
9640
9641 /* Set the IDLE state */
9642 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
9643
9644 /* Set the FAULT state */
9645 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
9646
9647 /* Set the chopper mode */
9648 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
9649
9650 /* Set the burst mode entry mode : deadtime insertion when entering the idle
9651 state during a burst mode operation is allowed only under the following
9652 conditions:
9653 - the outputs is active during the burst mode (IDLES=1U)
9654 - positive deadtimes (SDTR/SDTF set to 0U)
9655 */
9656 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
9657 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
9658 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
9659 {
9660 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
9661 }
9662
9663 /* Update HRTIM register */
9664 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
9665 }
9666
9667 /**
9668 * @brief Configure an external event channel
9669 * @param hhrtim pointer to HAL HRTIM handle
9670 * @param Event Event channel identifier
9671 * @param pEventCfg pointer to the event channel configuration data structure
9672 * @retval None
9673 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,const HRTIM_EventCfgTypeDef * pEventCfg)9674 static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
9675 uint32_t Event,
9676 const HRTIM_EventCfgTypeDef *pEventCfg)
9677 {
9678 uint32_t hrtim_eecr1;
9679 uint32_t hrtim_eecr2;
9680 uint32_t hrtim_eecr3;
9681
9682 /* Configure external event channel */
9683 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
9684 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
9685 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
9686
9687 switch (Event)
9688 {
9689 case HRTIM_EVENT_NONE:
9690 {
9691 /* Update the HRTIM registers */
9692 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
9693 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
9694 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
9695 break;
9696 }
9697
9698 case HRTIM_EVENT_1:
9699 {
9700 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
9701 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
9702 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
9703 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
9704 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
9705 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9706 /* Update the HRTIM registers (EE1FAST bit) */
9707 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
9708 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9709 break;
9710 }
9711
9712 case HRTIM_EVENT_2:
9713 {
9714 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
9715 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
9716 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
9717 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
9718 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
9719 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9720 /* Update the HRTIM registers (EE2FAST bit) */
9721 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
9722 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9723 break;
9724 }
9725
9726 case HRTIM_EVENT_3:
9727 {
9728 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
9729 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
9730 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
9731 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
9732 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
9733 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9734 /* Update the HRTIM registers (EE3FAST bit) */
9735 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
9736 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9737 break;
9738 }
9739
9740 case HRTIM_EVENT_4:
9741 {
9742 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
9743 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
9744 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
9745 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
9746 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
9747 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9748 /* Update the HRTIM registers (EE4FAST bit) */
9749 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
9750 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9751 break;
9752 }
9753
9754 case HRTIM_EVENT_5:
9755 {
9756 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
9757 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
9758 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
9759 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
9760 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
9761 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9762 /* Update the HRTIM registers (EE5FAST bit) */
9763 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
9764 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9765 break;
9766 }
9767
9768 case HRTIM_EVENT_6:
9769 {
9770 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
9771 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
9772 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
9773 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
9774 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
9775 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
9776 /* Update the HRTIM registers */
9777 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9778 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9779 break;
9780 }
9781
9782 case HRTIM_EVENT_7:
9783 {
9784 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
9785 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
9786 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
9787 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
9788 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
9789 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
9790 /* Update the HRTIM registers */
9791 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9792 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9793 break;
9794 }
9795
9796 case HRTIM_EVENT_8:
9797 {
9798 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
9799 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
9800 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
9801 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
9802 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
9803 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F);
9804 /* Update the HRTIM registers */
9805 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9806 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9807 break;
9808 }
9809
9810 case HRTIM_EVENT_9:
9811 {
9812 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
9813 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
9814 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
9815 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
9816 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
9817 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
9818 /* Update the HRTIM registers */
9819 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9820 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9821 break;
9822 }
9823
9824 case HRTIM_EVENT_10:
9825 {
9826 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
9827 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
9828 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
9829 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
9830 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
9831 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
9832 /* Update the HRTIM registers */
9833 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9834 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9835 break;
9836 }
9837
9838 default:
9839 break;
9840 }
9841 }
9842
9843 /**
9844 * @brief Configure the timer counter reset
9845 * @param hhrtim pointer to HAL HRTIM handle
9846 * @param TimerIdx Timer index
9847 * @param Event Event channel identifier
9848 * @retval None
9849 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)9850 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
9851 uint32_t TimerIdx,
9852 uint32_t Event)
9853 {
9854 switch (Event)
9855 {
9856 case HRTIM_EVENT_1:
9857 {
9858 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
9859 break;
9860 }
9861
9862 case HRTIM_EVENT_2:
9863 {
9864 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
9865 break;
9866 }
9867
9868 case HRTIM_EVENT_3:
9869 {
9870 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
9871 break;
9872 }
9873
9874 case HRTIM_EVENT_4:
9875 {
9876 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
9877 break;
9878 }
9879
9880 case HRTIM_EVENT_5:
9881 {
9882 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
9883 break;
9884 }
9885
9886 case HRTIM_EVENT_6:
9887 {
9888 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
9889 break;
9890 }
9891
9892 case HRTIM_EVENT_7:
9893 {
9894 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
9895 break;
9896 }
9897
9898 case HRTIM_EVENT_8:
9899 {
9900 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
9901 break;
9902 }
9903
9904 case HRTIM_EVENT_9:
9905 {
9906 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
9907 break;
9908 }
9909
9910 case HRTIM_EVENT_10:
9911 {
9912 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
9913 break;
9914 }
9915
9916 default:
9917 break;
9918 }
9919 }
9920
9921 /**
9922 * @brief Return the interrupt to enable or disable according to the
9923 * OC mode.
9924 * @param hhrtim pointer to HAL HRTIM handle
9925 * @param TimerIdx Timer index
9926 * @param OCChannel Timer output
9927 * This parameter can be one of the following values:
9928 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
9929 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
9930 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
9931 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
9932 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
9933 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
9934 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
9935 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
9936 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
9937 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
9938 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
9939 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
9940 * @retval Interrupt to enable or disable
9941 */
HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)9942 static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
9943 uint32_t TimerIdx,
9944 uint32_t OCChannel)
9945 {
9946 uint32_t hrtim_set;
9947 uint32_t hrtim_reset;
9948 uint32_t interrupt = 0U;
9949
9950 switch (OCChannel)
9951 {
9952 case HRTIM_OUTPUT_TA1:
9953 case HRTIM_OUTPUT_TB1:
9954 case HRTIM_OUTPUT_TC1:
9955 case HRTIM_OUTPUT_TD1:
9956 case HRTIM_OUTPUT_TE1:
9957 case HRTIM_OUTPUT_TF1:
9958 {
9959 /* Retrieves actual OC mode and set interrupt accordingly */
9960 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
9961 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
9962
9963 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9964 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
9965 {
9966 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
9967 interrupt = HRTIM_TIM_IT_CMP1;
9968 }
9969 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9970 (hrtim_reset == 0U))
9971 {
9972 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
9973 interrupt = HRTIM_TIM_IT_SET1;
9974 }
9975 else if ((hrtim_set == 0U) &&
9976 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
9977 {
9978 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
9979 interrupt = HRTIM_TIM_IT_RST1;
9980 }
9981 else
9982 {
9983 /* nothing to do */
9984 }
9985 break;
9986 }
9987
9988 case HRTIM_OUTPUT_TA2:
9989 case HRTIM_OUTPUT_TB2:
9990 case HRTIM_OUTPUT_TC2:
9991 case HRTIM_OUTPUT_TD2:
9992 case HRTIM_OUTPUT_TE2:
9993 case HRTIM_OUTPUT_TF2:
9994 {
9995 /* Retrieves actual OC mode and set interrupt accordingly */
9996 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
9997 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
9998
9999 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10000 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10001 {
10002 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10003 interrupt = HRTIM_TIM_IT_CMP2;
10004 }
10005 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10006 (hrtim_reset == 0U))
10007 {
10008 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10009 interrupt = HRTIM_TIM_IT_SET2;
10010 }
10011 else if ((hrtim_set == 0U) &&
10012 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10013 {
10014 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10015 interrupt = HRTIM_TIM_IT_RST2;
10016 }
10017 else
10018 {
10019 /* nothing to do */
10020 }
10021 break;
10022 }
10023
10024 default:
10025 break;
10026 }
10027
10028 return interrupt;
10029 }
10030
10031 /**
10032 * @brief Return the DMA request to enable or disable according to the
10033 * OC mode.
10034 * @param hhrtim pointer to HAL HRTIM handle
10035 * @param TimerIdx Timer index
10036 * @param OCChannel Timer output
10037 * This parameter can be one of the following values:
10038 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
10039 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
10040 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
10041 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
10042 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
10043 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
10044 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
10045 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
10046 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
10047 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
10048 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
10049 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
10050 * @retval DMA request to enable or disable
10051 */
HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)10052 static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
10053 uint32_t TimerIdx,
10054 uint32_t OCChannel)
10055 {
10056 uint32_t hrtim_set;
10057 uint32_t hrtim_reset;
10058 uint32_t dma_request = 0U;
10059
10060 switch (OCChannel)
10061 {
10062 case HRTIM_OUTPUT_TA1:
10063 case HRTIM_OUTPUT_TB1:
10064 case HRTIM_OUTPUT_TC1:
10065 case HRTIM_OUTPUT_TD1:
10066 case HRTIM_OUTPUT_TE1:
10067 case HRTIM_OUTPUT_TF1:
10068 {
10069 /* Retrieves actual OC mode and set dma_request accordingly */
10070 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
10071 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
10072
10073 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10074 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10075 {
10076 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10077 dma_request = HRTIM_TIM_DMA_CMP1;
10078 }
10079 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10080 (hrtim_reset == 0U))
10081 {
10082 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10083 dma_request = HRTIM_TIM_DMA_SET1;
10084 }
10085 else if ((hrtim_set == 0U) &&
10086 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10087 {
10088 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10089 dma_request = HRTIM_TIM_DMA_RST1;
10090 }
10091 else
10092 {
10093 /* nothing to do */
10094 }
10095 break;
10096 }
10097
10098 case HRTIM_OUTPUT_TA2:
10099 case HRTIM_OUTPUT_TB2:
10100 case HRTIM_OUTPUT_TC2:
10101 case HRTIM_OUTPUT_TD2:
10102 case HRTIM_OUTPUT_TE2:
10103 case HRTIM_OUTPUT_TF2:
10104 {
10105 /* Retrieves actual OC mode and set dma_request accordingly */
10106 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
10107 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
10108
10109 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10110 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10111 {
10112 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10113 dma_request = HRTIM_TIM_DMA_CMP2;
10114 }
10115 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10116 (hrtim_reset == 0U))
10117 {
10118 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10119 dma_request = HRTIM_TIM_DMA_SET2;
10120 }
10121 else if ((hrtim_set == 0U) &&
10122 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10123 {
10124 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10125 dma_request = HRTIM_TIM_DMA_RST2;
10126 }
10127 else
10128 {
10129 /* nothing to do */
10130 }
10131 break;
10132 }
10133
10134 default:
10135 break;
10136 }
10137
10138 return dma_request;
10139 }
10140
HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10141 static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
10142 uint32_t TimerIdx)
10143 {
10144 DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL;
10145
10146 switch (TimerIdx)
10147 {
10148 case HRTIM_TIMERINDEX_MASTER:
10149 {
10150 hdma = hhrtim->hdmaMaster;
10151 break;
10152 }
10153
10154 case HRTIM_TIMERINDEX_TIMER_A:
10155 {
10156 hdma = hhrtim->hdmaTimerA;
10157 break;
10158 }
10159
10160 case HRTIM_TIMERINDEX_TIMER_B:
10161 {
10162 hdma = hhrtim->hdmaTimerB;
10163 break;
10164 }
10165
10166 case HRTIM_TIMERINDEX_TIMER_C:
10167 {
10168 hdma = hhrtim->hdmaTimerC;
10169 break;
10170 }
10171
10172 case HRTIM_TIMERINDEX_TIMER_D:
10173 {
10174 hdma = hhrtim->hdmaTimerD;
10175 break;
10176 }
10177
10178 case HRTIM_TIMERINDEX_TIMER_E:
10179 {
10180 hdma = hhrtim->hdmaTimerE;
10181 break;
10182 }
10183
10184 case HRTIM_TIMERINDEX_TIMER_F:
10185 {
10186 hdma = hhrtim->hdmaTimerF;
10187 break;
10188 }
10189
10190 default:
10191 break;
10192 }
10193
10194 return hdma;
10195 }
10196
GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,const DMA_HandleTypeDef * hdma)10197 static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
10198 const DMA_HandleTypeDef *hdma)
10199 {
10200 uint32_t timed_idx = 0xFFFFFFFFU;
10201
10202 if (hdma == hhrtim->hdmaMaster)
10203 {
10204 timed_idx = HRTIM_TIMERINDEX_MASTER;
10205 }
10206 else if (hdma == hhrtim->hdmaTimerA)
10207 {
10208 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
10209 }
10210 else if (hdma == hhrtim->hdmaTimerB)
10211 {
10212 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
10213 }
10214 else if (hdma == hhrtim->hdmaTimerC)
10215 {
10216 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
10217 }
10218 else if (hdma == hhrtim->hdmaTimerD)
10219 {
10220 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
10221 }
10222 else if (hdma == hhrtim->hdmaTimerE)
10223 {
10224 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
10225 }
10226 else if (hdma == hhrtim->hdmaTimerF)
10227 {
10228 timed_idx = HRTIM_TIMERINDEX_TIMER_F;
10229 }
10230 else
10231 {
10232 /* nothing to do */
10233 }
10234 return timed_idx;
10235 }
10236
10237 /**
10238 * @brief Force an immediate transfer from the preload to the active
10239 * registers.
10240 * @param hhrtim pointer to HAL HRTIM handle
10241 * @param TimerIdx Timer index
10242 * @retval None
10243 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10244 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
10245 uint32_t TimerIdx)
10246 {
10247 switch (TimerIdx)
10248 {
10249 case HRTIM_TIMERINDEX_MASTER:
10250 {
10251 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
10252 break;
10253 }
10254
10255 case HRTIM_TIMERINDEX_TIMER_A:
10256 {
10257 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
10258 break;
10259 }
10260
10261 case HRTIM_TIMERINDEX_TIMER_B:
10262 {
10263 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
10264 break;
10265 }
10266
10267 case HRTIM_TIMERINDEX_TIMER_C:
10268 {
10269 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
10270 break;
10271 }
10272
10273 case HRTIM_TIMERINDEX_TIMER_D:
10274 {
10275 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
10276 break;
10277 }
10278
10279 case HRTIM_TIMERINDEX_TIMER_E:
10280 {
10281 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
10282 break;
10283 }
10284
10285 case HRTIM_TIMERINDEX_TIMER_F:
10286 {
10287 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
10288 break;
10289 }
10290
10291 default:
10292 break;
10293 }
10294 }
10295
10296
10297 /**
10298 * @brief HRTIM interrupts service routine
10299 * @param hhrtim pointer to HAL HRTIM handle
10300 * @retval None
10301 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)10302 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim)
10303 {
10304 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10305 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10306
10307 /* Fault 1 event */
10308 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
10309 {
10310 if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
10311 {
10312 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
10313
10314 /* Invoke Fault 1 event callback */
10315 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10316 hhrtim->Fault1Callback(hhrtim);
10317 #else
10318 HAL_HRTIM_Fault1Callback(hhrtim);
10319 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10320 }
10321 }
10322
10323 /* Fault 2 event */
10324 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
10325 {
10326 if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
10327 {
10328 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
10329
10330 /* Invoke Fault 2 event callback */
10331 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10332 hhrtim->Fault2Callback(hhrtim);
10333 #else
10334 HAL_HRTIM_Fault2Callback(hhrtim);
10335 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10336 }
10337 }
10338
10339 /* Fault 3 event */
10340 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
10341 {
10342 if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
10343 {
10344 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
10345
10346 /* Invoke Fault 3 event callback */
10347 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10348 hhrtim->Fault3Callback(hhrtim);
10349 #else
10350 HAL_HRTIM_Fault3Callback(hhrtim);
10351 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10352 }
10353 }
10354
10355 /* Fault 4 event */
10356 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
10357 {
10358 if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
10359 {
10360 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
10361
10362 /* Invoke Fault 4 event callback */
10363 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10364 hhrtim->Fault4Callback(hhrtim);
10365 #else
10366 HAL_HRTIM_Fault4Callback(hhrtim);
10367 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10368 }
10369 }
10370
10371 /* Fault 5 event */
10372 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
10373 {
10374 if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
10375 {
10376 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
10377
10378 /* Invoke Fault 5 event callback */
10379 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10380 hhrtim->Fault5Callback(hhrtim);
10381 #else
10382 HAL_HRTIM_Fault5Callback(hhrtim);
10383 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10384 }
10385 }
10386
10387 /* Fault 6 event */
10388 if ((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET)
10389 {
10390 if ((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET)
10391 {
10392 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
10393
10394 /* Invoke Fault 6 event callback */
10395 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10396 hhrtim->Fault6Callback(hhrtim);
10397 #else
10398 HAL_HRTIM_Fault6Callback(hhrtim);
10399 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10400 }
10401 }
10402
10403 /* System fault event */
10404 if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
10405 {
10406 if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
10407 {
10408 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
10409
10410 /* Invoke System fault event callback */
10411 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10412 hhrtim->SystemFaultCallback(hhrtim);
10413 #else
10414 HAL_HRTIM_SystemFaultCallback(hhrtim);
10415 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10416 }
10417 }
10418 }
10419
10420 /**
10421 * @brief Master timer interrupts service routine
10422 * @param hhrtim pointer to HAL HRTIM handle
10423 * @retval None
10424 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)10425 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim)
10426 {
10427 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10428 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10429 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
10430 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
10431
10432 /* DLL calibration ready event */
10433 if ((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
10434 {
10435 if ((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
10436 {
10437 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
10438
10439 /* Set HRTIM State */
10440 hhrtim->State = HAL_HRTIM_STATE_READY;
10441
10442 /* Process unlocked */
10443 __HAL_UNLOCK(hhrtim);
10444
10445 /* Invoke System fault event callback */
10446 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10447 hhrtim->DLLCalibrationReadyCallback(hhrtim);
10448 #else
10449 HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
10450 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10451 }
10452 }
10453
10454 /* Burst mode period event */
10455 if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
10456 {
10457 if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
10458 {
10459 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
10460
10461 /* Invoke Burst mode period event callback */
10462 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10463 hhrtim->BurstModePeriodCallback(hhrtim);
10464 #else
10465 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
10466 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10467 }
10468 }
10469
10470 /* Master timer compare 1 event */
10471 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
10472 {
10473 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
10474 {
10475 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
10476
10477 /* Invoke compare 1 event callback */
10478 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10479 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10480 #else
10481 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10482 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10483 }
10484 }
10485
10486 /* Master timer compare 2 event */
10487 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
10488 {
10489 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
10490 {
10491 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
10492
10493 /* Invoke compare 2 event callback */
10494 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10495 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10496 #else
10497 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10498 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10499 }
10500 }
10501
10502 /* Master timer compare 3 event */
10503 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
10504 {
10505 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
10506 {
10507 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
10508
10509 /* Invoke compare 3 event callback */
10510 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10511 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10512 #else
10513 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10514 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10515 }
10516 }
10517
10518 /* Master timer compare 4 event */
10519 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
10520 {
10521 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
10522 {
10523 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
10524
10525 /* Invoke compare 4 event callback */
10526 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10527 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10528 #else
10529 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10530 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10531 }
10532 }
10533
10534 /* Master timer repetition event */
10535 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
10536 {
10537 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
10538 {
10539 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
10540
10541 /* Invoke repetition event callback */
10542 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10543 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10544 #else
10545 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10546 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10547 }
10548 }
10549
10550 /* Synchronization input event */
10551 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
10552 {
10553 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
10554 {
10555 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
10556
10557 /* Invoke synchronization event callback */
10558 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10559 hhrtim->SynchronizationEventCallback(hhrtim);
10560 #else
10561 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
10562 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10563 }
10564 }
10565
10566 /* Master timer registers update event */
10567 if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
10568 {
10569 if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
10570 {
10571 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
10572
10573 /* Invoke registers update event callback */
10574 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10575 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10576 #else
10577 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10578 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10579 }
10580 }
10581 }
10582
10583 /**
10584 * @brief Timer interrupts service routine
10585 * @param hhrtim pointer to HAL HRTIM handle
10586 * @param TimerIdx Timer index
10587 * This parameter can be one of the following values:
10588 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
10589 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
10590 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
10591 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
10592 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
10593 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
10594 * @retval None
10595 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10596 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
10597 uint32_t TimerIdx)
10598 {
10599 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
10600 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
10601
10602 /* Timer compare 1 event */
10603 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
10604 {
10605 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
10606 {
10607 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
10608
10609 /* Invoke compare 1 event callback */
10610 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10611 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
10612 #else
10613 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
10614 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10615 }
10616 }
10617
10618 /* Timer compare 2 event */
10619 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
10620 {
10621 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
10622 {
10623 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
10624
10625 /* Invoke compare 2 event callback */
10626 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10627 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
10628 #else
10629 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
10630 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10631 }
10632 }
10633
10634 /* Timer compare 3 event */
10635 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
10636 {
10637 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
10638 {
10639 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
10640
10641 /* Invoke compare 3 event callback */
10642 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10643 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
10644 #else
10645 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
10646 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10647 }
10648 }
10649
10650 /* Timer compare 4 event */
10651 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
10652 {
10653 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
10654 {
10655 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
10656
10657 /* Invoke compare 4 event callback */
10658 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10659 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
10660 #else
10661 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
10662 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10663 }
10664 }
10665
10666 /* Timer repetition event */
10667 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
10668 {
10669 if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
10670 {
10671 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
10672
10673 /* Invoke repetition event callback */
10674 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10675 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
10676 #else
10677 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
10678 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10679 }
10680 }
10681
10682 /* Timer registers update event */
10683 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
10684 {
10685 if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
10686 {
10687 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
10688
10689 /* Invoke registers update event callback */
10690 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10691 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
10692 #else
10693 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
10694 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10695 }
10696 }
10697
10698 /* Timer capture 1 event */
10699 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
10700 {
10701 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
10702 {
10703 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
10704
10705 /* Invoke capture 1 event callback */
10706 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10707 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
10708 #else
10709 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
10710 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10711 }
10712 }
10713
10714 /* Timer capture 2 event */
10715 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
10716 {
10717 if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
10718 {
10719 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
10720
10721 /* Invoke capture 2 event callback */
10722 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10723 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
10724 #else
10725 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
10726 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10727 }
10728 }
10729
10730 /* Timer output 1 set event */
10731 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
10732 {
10733 if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
10734 {
10735 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
10736
10737 /* Invoke output 1 set event callback */
10738 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10739 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
10740 #else
10741 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
10742 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10743 }
10744 }
10745
10746 /* Timer output 1 reset event */
10747 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
10748 {
10749 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
10750 {
10751 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
10752
10753 /* Invoke output 1 reset event callback */
10754 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10755 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
10756 #else
10757 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
10758 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10759 }
10760 }
10761
10762 /* Timer output 2 set event */
10763 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
10764 {
10765 if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
10766 {
10767 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
10768
10769 /* Invoke output 2 set event callback */
10770 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10771 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
10772 #else
10773 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
10774 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10775 }
10776 }
10777
10778 /* Timer output 2 reset event */
10779 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
10780 {
10781 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
10782 {
10783 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
10784
10785 /* Invoke output 2 reset event callback */
10786 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10787 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
10788 #else
10789 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
10790 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10791 }
10792 }
10793
10794 /* Timer reset event */
10795 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
10796 {
10797 if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
10798 {
10799 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
10800
10801 /* Invoke timer reset callback */
10802 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10803 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
10804 #else
10805 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
10806 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10807 }
10808 }
10809
10810 /* Delayed protection event */
10811 if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
10812 {
10813 if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
10814 {
10815 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
10816
10817 /* Invoke delayed protection callback */
10818 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10819 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
10820 #else
10821 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
10822 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10823 }
10824 }
10825 }
10826
10827 /**
10828 * @brief DMA callback invoked upon master timer related DMA request completion
10829 * @param hdma pointer to DMA handle.
10830 * @retval None
10831 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)10832 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
10833 {
10834 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
10835
10836 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
10837 {
10838 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10839 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10840 #else
10841 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10842 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10843 }
10844 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
10845 {
10846 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10847 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10848 #else
10849 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10850 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10851 }
10852 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
10853 {
10854 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10855 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10856 #else
10857 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10858 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10859 }
10860 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
10861 {
10862 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10863 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10864 #else
10865 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10866 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10867 }
10868 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
10869 {
10870 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10871 hrtim->SynchronizationEventCallback(hrtim);
10872 #else
10873 HAL_HRTIM_SynchronizationEventCallback(hrtim);
10874 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10875 }
10876 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
10877 {
10878 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10879 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10880 #else
10881 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10882 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10883 }
10884 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
10885 {
10886 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10887 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10888 #else
10889 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10890 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10891 }
10892 else
10893 {
10894 /* nothing to do */
10895 }
10896 }
10897
10898 /**
10899 * @brief DMA callback invoked upon timer A..F related DMA request completion
10900 * @param hdma pointer to DMA handle.
10901 * @retval None
10902 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)10903 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
10904 {
10905 uint8_t timer_idx;
10906
10907 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
10908
10909 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
10910
10911 if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;}
10912
10913 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
10914 {
10915 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10916 hrtim->Compare1EventCallback(hrtim, timer_idx);
10917 #else
10918 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
10919 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10920 }
10921 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
10922 {
10923 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10924 hrtim->Compare2EventCallback(hrtim, timer_idx);
10925 #else
10926 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
10927 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10928 }
10929 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
10930 {
10931 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10932 hrtim->Compare3EventCallback(hrtim, timer_idx);
10933 #else
10934 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
10935 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10936 }
10937 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
10938 {
10939 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10940 hrtim->Compare4EventCallback(hrtim, timer_idx);
10941 #else
10942 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
10943 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10944 }
10945 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
10946 {
10947 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10948 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
10949 #else
10950 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
10951 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10952 }
10953 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
10954 {
10955 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10956 hrtim->Capture1EventCallback(hrtim, timer_idx);
10957 #else
10958 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
10959 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10960 }
10961 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
10962 {
10963 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10964 hrtim->Capture2EventCallback(hrtim, timer_idx);
10965 #else
10966 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
10967 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10968 }
10969 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
10970 {
10971 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10972 hrtim->Output1SetCallback(hrtim, timer_idx);
10973 #else
10974 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
10975 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10976 }
10977 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
10978 {
10979 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10980 hrtim->Output1ResetCallback(hrtim, timer_idx);
10981 #else
10982 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
10983 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10984 }
10985 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
10986 {
10987 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10988 hrtim->Output2SetCallback(hrtim, timer_idx);
10989 #else
10990 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
10991 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10992 }
10993 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
10994 {
10995 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10996 hrtim->Output2ResetCallback(hrtim, timer_idx);
10997 #else
10998 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
10999 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11000 }
11001 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
11002 {
11003 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11004 hrtim->CounterResetCallback(hrtim, timer_idx);
11005 #else
11006 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
11007 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11008 }
11009 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
11010 {
11011 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11012 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
11013 #else
11014 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
11015 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11016 }
11017 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
11018 {
11019 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11020 hrtim->RepetitionEventCallback(hrtim, timer_idx);
11021 #else
11022 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
11023 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11024 }
11025 else
11026 {
11027 /* nothing to do */
11028 }
11029 }
11030
11031 /**
11032 * @brief DMA error callback
11033 * @param hdma pointer to DMA handle.
11034 * @retval None
11035 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)11036 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
11037 {
11038 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
11039
11040 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11041 hrtim->ErrorCallback(hrtim);
11042 #else
11043 HAL_HRTIM_ErrorCallback(hrtim);
11044 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11045 }
11046
11047 /**
11048 * @brief DMA callback invoked upon burst DMA transfer completion
11049 * @param hdma pointer to DMA handle.
11050 * @retval None
11051 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)11052 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
11053 {
11054 HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
11055
11056 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11057 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11058 #else
11059 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11060 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11061 }
11062
11063 /**
11064 * @}
11065 */
11066
11067 /**
11068 * @}
11069 */
11070
11071 #endif /* HRTIM1 */
11072
11073 #endif /* HAL_HRTIM_MODULE_ENABLED */
11074
11075 /**
11076 * @}
11077 */
11078
