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Searched refs:SPI_CR1_SPE_Msk (Results 1 – 25 of 256) sorted by relevance

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/hal_stm32-3.5.0/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h4327 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4328 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f101xb.h4389 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4390 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f100xb.h4794 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4795 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f102x6.h5446 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
5447 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f100xe.h5308 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
5309 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f101xe.h5320 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
5321 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f101xg.h5394 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
5395 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
/hal_stm32-3.5.0/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h3772 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
3773 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f030x8.h3816 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
3817 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f070x6.h3852 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
3853 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f070xb.h4010 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4011 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f030xc.h4142 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4143 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f031x6.h3927 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
3928 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f038xx.h3899 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
3900 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32f058xx.h4399 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4400 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
/hal_stm32-3.5.0/stm32cube/stm32l0xx/soc/
Dstm32l031xx.h4554 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4555 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l051xx.h4663 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4664 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l010x4.h4322 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4323 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l010xb.h4414 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4415 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l010x6.h4374 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4375 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l041xx.h4691 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4692 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l010x8.h4366 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4367 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l011xx.h4431 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4432 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l021xx.h4568 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4569 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Dstm32l081xx.h4934 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ macro
4935 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */

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