1 /** 2 ****************************************************************************** 3 * @file stm32f030xc.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F0xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2016 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 /** @addtogroup CMSIS 27 * @{ 28 */ 29 30 /** @addtogroup stm32f030xc 31 * @{ 32 */ 33 34 #ifndef __STM32F030xC_H 35 #define __STM32F030xC_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** @addtogroup Configuration_section_for_CMSIS 42 * @{ 43 */ 44 /** 45 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals 46 */ 47 #define __CM0_REV 0 /*!< Core Revision r0p0 */ 48 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ 49 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ 50 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 51 52 /** 53 * @} 54 */ 55 56 /** @addtogroup Peripheral_interrupt_number_definition 57 * @{ 58 */ 59 60 /** 61 * @brief STM32F0xx Interrupt Number Definition, according to the selected device 62 * in @ref Library_configuration_section 63 */ 64 65 /*!< Interrupt Number Definition */ 66 typedef enum 67 { 68 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ 69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 70 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 71 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 72 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 73 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 74 75 /****** STM32F0 specific Interrupt Numbers ******************************************************************/ 76 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 77 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 78 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 79 RCC_IRQn = 4, /*!< RCC global Interrupt */ 80 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ 81 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ 82 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ 83 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 84 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ 85 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */ 86 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 87 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ 88 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 89 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 90 TIM6_IRQn = 17, /*!< TIM6 global Interrupt */ 91 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ 92 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 93 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 94 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 95 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 96 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 97 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ 98 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 99 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 100 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 101 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ 102 USART3_6_IRQn = 29, /*!< USART3 to USART6 global Interrupt */ 103 } IRQn_Type; 104 105 /** 106 * @} 107 */ 108 109 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ 110 #include "system_stm32f0xx.h" /* STM32F0xx System Header */ 111 #include <stdint.h> 112 113 /** @addtogroup Peripheral_registers_structures 114 * @{ 115 */ 116 117 /** 118 * @brief Analog to Digital Converter 119 */ 120 121 typedef struct 122 { 123 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 124 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 125 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 126 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ 127 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 128 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ 129 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 130 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 131 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 132 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 133 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ 134 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 135 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 136 } ADC_TypeDef; 137 138 typedef struct 139 { 140 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ 141 } ADC_Common_TypeDef; 142 143 /** 144 * @brief CRC calculation unit 145 */ 146 147 typedef struct 148 { 149 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 150 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 151 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 152 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 153 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 154 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 155 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 156 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */ 157 } CRC_TypeDef; 158 159 /** 160 * @brief Debug MCU 161 */ 162 163 typedef struct 164 { 165 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 166 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 167 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 168 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 169 }DBGMCU_TypeDef; 170 171 /** 172 * @brief DMA Controller 173 */ 174 175 typedef struct 176 { 177 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 178 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 179 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 180 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 181 } DMA_Channel_TypeDef; 182 183 typedef struct 184 { 185 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 186 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 187 uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */ 188 __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */ 189 } DMA_TypeDef; 190 191 /** 192 * @brief External Interrupt/Event Controller 193 */ 194 195 typedef struct 196 { 197 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 198 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 199 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 200 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 201 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 202 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 203 } EXTI_TypeDef; 204 205 /** 206 * @brief FLASH Registers 207 */ 208 typedef struct 209 { 210 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ 211 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ 212 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ 213 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ 214 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ 215 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ 216 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ 217 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ 218 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ 219 } FLASH_TypeDef; 220 221 /** 222 * @brief Option Bytes Registers 223 */ 224 typedef struct 225 { 226 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ 227 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ 228 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ 229 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ 230 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ 231 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ 232 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ 233 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ 234 } OB_TypeDef; 235 236 /** 237 * @brief General Purpose I/O 238 */ 239 240 typedef struct 241 { 242 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 243 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 244 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 245 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 246 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 247 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 248 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ 249 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 250 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 251 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 252 } GPIO_TypeDef; 253 254 /** 255 * @brief SysTem Configuration 256 */ 257 258 typedef struct 259 { 260 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 261 uint32_t RESERVED; /*!< Reserved, 0x04 */ 262 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 263 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 264 } SYSCFG_TypeDef; 265 266 /** 267 * @brief Inter-integrated Circuit Interface 268 */ 269 270 typedef struct 271 { 272 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 273 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 274 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 275 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 276 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 277 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 278 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 279 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 280 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 281 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 282 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 283 } I2C_TypeDef; 284 285 /** 286 * @brief Independent WATCHDOG 287 */ 288 289 typedef struct 290 { 291 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 292 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 293 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 294 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 295 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 296 } IWDG_TypeDef; 297 298 /** 299 * @brief Power Control 300 */ 301 302 typedef struct 303 { 304 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 305 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 306 } PWR_TypeDef; 307 308 /** 309 * @brief Reset and Clock Control 310 */ 311 312 typedef struct 313 { 314 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 315 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 316 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 317 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 318 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 319 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 320 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 321 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 322 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 323 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 324 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 325 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 326 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 327 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ 328 } RCC_TypeDef; 329 330 /** 331 * @brief Real-Time Clock 332 */ 333 typedef struct 334 { 335 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 336 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 337 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 338 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 339 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 340 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 341 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ 342 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 343 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ 344 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 345 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 346 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 347 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 348 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 349 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 350 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 351 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 352 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 353 } RTC_TypeDef; 354 355 /** 356 * @brief Serial Peripheral Interface 357 */ 358 359 typedef struct 360 { 361 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 362 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 363 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 364 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 365 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 366 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 367 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 368 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 369 } SPI_TypeDef; 370 371 /** 372 * @brief TIM 373 */ 374 typedef struct 375 { 376 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 377 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 378 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 379 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 380 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 381 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 382 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 383 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 384 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 385 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 386 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 387 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 388 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 389 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 390 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 391 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 392 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 393 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 394 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 395 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 396 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 397 } TIM_TypeDef; 398 399 /** 400 * @brief Universal Synchronous Asynchronous Receiver Transmitter 401 */ 402 403 typedef struct 404 { 405 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 406 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 407 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 408 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 409 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 410 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 411 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 412 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 413 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 414 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 415 uint16_t RESERVED1; /*!< Reserved, 0x26 */ 416 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 417 uint16_t RESERVED2; /*!< Reserved, 0x2A */ 418 } USART_TypeDef; 419 420 /** 421 * @brief Window WATCHDOG 422 */ 423 typedef struct 424 { 425 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 426 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 427 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 428 } WWDG_TypeDef; 429 430 /** 431 * @} 432 */ 433 434 /** @addtogroup Peripheral_memory_map 435 * @{ 436 */ 437 438 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 439 #define FLASH_BANK1_END 0x0803FFFFUL /*!< FLASH END address of bank1 */ 440 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 441 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 442 443 /*!< Peripheral memory map */ 444 #define APBPERIPH_BASE PERIPH_BASE 445 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 446 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 447 448 /*!< APB peripherals */ 449 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 450 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) 451 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) 452 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) 453 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 454 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 455 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 456 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 457 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 458 #define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) 459 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) 460 #define USART5_BASE (APBPERIPH_BASE + 0x00005000UL) 461 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 462 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) 463 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 464 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 465 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 466 #define USART6_BASE (APBPERIPH_BASE + 0x00011400UL) 467 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 468 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 469 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) 470 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 471 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 472 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) 473 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) 474 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) 475 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 476 477 /*!< AHB peripherals */ 478 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 479 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 480 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 481 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 482 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 483 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 484 485 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 486 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 487 #define OB_BASE 0x1FFFF800UL /*!< FLASH Option Bytes base address */ 488 #define FLASHSIZE_BASE 0x1FFFF7CCUL /*!< FLASH Size register base address */ 489 #define UID_BASE 0x1FFFF7ACUL /*!< Unique device ID register base address */ 490 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 491 492 /*!< AHB2 peripherals */ 493 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL) 494 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL) 495 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL) 496 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL) 497 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL) 498 499 /** 500 * @} 501 */ 502 503 /** @addtogroup Peripheral_declaration 504 * @{ 505 */ 506 507 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 508 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 509 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 510 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 511 #define RTC ((RTC_TypeDef *) RTC_BASE) 512 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 513 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 514 #define USART2 ((USART_TypeDef *) USART2_BASE) 515 #define USART3 ((USART_TypeDef *) USART3_BASE) 516 #define USART4 ((USART_TypeDef *) USART4_BASE) 517 #define USART5 ((USART_TypeDef *) USART5_BASE) 518 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 519 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 520 #define PWR ((PWR_TypeDef *) PWR_BASE) 521 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 522 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 523 #define USART6 ((USART_TypeDef *) USART6_BASE) 524 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 525 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 526 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ 527 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 528 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 529 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 530 #define USART1 ((USART_TypeDef *) USART1_BASE) 531 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 532 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 533 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 534 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 535 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 536 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 537 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 538 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 539 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 540 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 541 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 542 #define OB ((OB_TypeDef *) OB_BASE) 543 #define RCC ((RCC_TypeDef *) RCC_BASE) 544 #define CRC ((CRC_TypeDef *) CRC_BASE) 545 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 546 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 547 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 548 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 549 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 550 /** 551 * @} 552 */ 553 554 /** @addtogroup Exported_constants 555 * @{ 556 */ 557 558 /** @addtogroup Hardware_Constant_Definition 559 * @{ 560 */ 561 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 562 563 /** 564 * @} 565 */ 566 567 /** @addtogroup Peripheral_Registers_Bits_Definition 568 * @{ 569 */ 570 571 /******************************************************************************/ 572 /* Peripheral Registers Bits Definition */ 573 /******************************************************************************/ 574 575 /******************************************************************************/ 576 /* */ 577 /* Analog to Digital Converter (ADC) */ 578 /* */ 579 /******************************************************************************/ 580 581 /* 582 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 583 */ 584 /* Note: No specific macro feature on this device */ 585 586 /******************** Bits definition for ADC_ISR register ******************/ 587 #define ADC_ISR_ADRDY_Pos (0U) 588 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 589 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 590 #define ADC_ISR_EOSMP_Pos (1U) 591 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 592 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 593 #define ADC_ISR_EOC_Pos (2U) 594 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 595 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 596 #define ADC_ISR_EOS_Pos (3U) 597 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 598 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 599 #define ADC_ISR_OVR_Pos (4U) 600 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 601 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 602 #define ADC_ISR_AWD1_Pos (7U) 603 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 604 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 605 606 /* Legacy defines */ 607 #define ADC_ISR_AWD (ADC_ISR_AWD1) 608 #define ADC_ISR_EOSEQ (ADC_ISR_EOS) 609 610 /******************** Bits definition for ADC_IER register ******************/ 611 #define ADC_IER_ADRDYIE_Pos (0U) 612 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 613 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 614 #define ADC_IER_EOSMPIE_Pos (1U) 615 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 616 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 617 #define ADC_IER_EOCIE_Pos (2U) 618 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 619 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 620 #define ADC_IER_EOSIE_Pos (3U) 621 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 622 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 623 #define ADC_IER_OVRIE_Pos (4U) 624 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 625 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 626 #define ADC_IER_AWD1IE_Pos (7U) 627 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 628 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 629 630 /* Legacy defines */ 631 #define ADC_IER_AWDIE (ADC_IER_AWD1IE) 632 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE) 633 634 /******************** Bits definition for ADC_CR register *******************/ 635 #define ADC_CR_ADEN_Pos (0U) 636 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 637 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 638 #define ADC_CR_ADDIS_Pos (1U) 639 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 640 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 641 #define ADC_CR_ADSTART_Pos (2U) 642 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 643 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 644 #define ADC_CR_ADSTP_Pos (4U) 645 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 646 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 647 #define ADC_CR_ADCAL_Pos (31U) 648 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 649 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 650 651 /******************* Bits definition for ADC_CFGR1 register *****************/ 652 #define ADC_CFGR1_DMAEN_Pos (0U) 653 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 654 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ 655 #define ADC_CFGR1_DMACFG_Pos (1U) 656 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 657 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ 658 #define ADC_CFGR1_SCANDIR_Pos (2U) 659 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 660 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ 661 662 #define ADC_CFGR1_RES_Pos (3U) 663 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 664 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ 665 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 666 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 667 668 #define ADC_CFGR1_ALIGN_Pos (5U) 669 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 670 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ 671 672 #define ADC_CFGR1_EXTSEL_Pos (6U) 673 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 674 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ 675 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 676 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 677 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 678 679 #define ADC_CFGR1_EXTEN_Pos (10U) 680 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 681 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 682 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 683 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 684 685 #define ADC_CFGR1_OVRMOD_Pos (12U) 686 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 687 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 688 #define ADC_CFGR1_CONT_Pos (13U) 689 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 690 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ 691 #define ADC_CFGR1_WAIT_Pos (14U) 692 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 693 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ 694 #define ADC_CFGR1_AUTOFF_Pos (15U) 695 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 696 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ 697 #define ADC_CFGR1_DISCEN_Pos (16U) 698 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 699 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 700 701 #define ADC_CFGR1_AWD1SGL_Pos (22U) 702 #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ 703 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 704 #define ADC_CFGR1_AWD1EN_Pos (23U) 705 #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ 706 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 707 708 #define ADC_CFGR1_AWD1CH_Pos (26U) 709 #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ 710 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 711 #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ 712 #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ 713 #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ 714 #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ 715 #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ 716 717 /* Legacy defines */ 718 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) 719 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL) 720 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN) 721 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH) 722 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0) 723 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1) 724 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2) 725 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3) 726 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4) 727 728 /******************* Bits definition for ADC_CFGR2 register *****************/ 729 #define ADC_CFGR2_CKMODE_Pos (30U) 730 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 731 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ 732 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 733 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 734 735 /* Legacy defines */ 736 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */ 737 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */ 738 739 /****************** Bit definition for ADC_SMPR register ********************/ 740 #define ADC_SMPR_SMP_Pos (0U) 741 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 742 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ 743 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 744 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 745 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 746 747 /* Legacy defines */ 748 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */ 749 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */ 750 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */ 751 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */ 752 753 /******************* Bit definition for ADC_TR register ********************/ 754 #define ADC_TR1_LT1_Pos (0U) 755 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 756 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 757 #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ 758 #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ 759 #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ 760 #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ 761 #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ 762 #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ 763 #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ 764 #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ 765 #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ 766 #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ 767 #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ 768 #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ 769 770 #define ADC_TR1_HT1_Pos (16U) 771 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 772 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ 773 #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ 774 #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ 775 #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ 776 #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ 777 #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ 778 #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ 779 #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ 780 #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ 781 #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ 782 #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ 783 #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ 784 #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ 785 786 /* Legacy defines */ 787 #define ADC_TR_HT (ADC_TR1_HT1) 788 #define ADC_TR_LT (ADC_TR1_LT1) 789 #define ADC_HTR_HT (ADC_TR1_HT1) 790 #define ADC_LTR_LT (ADC_TR1_LT1) 791 792 /****************** Bit definition for ADC_CHSELR register ******************/ 793 #define ADC_CHSELR_CHSEL_Pos (0U) 794 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 795 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ 796 #define ADC_CHSELR_CHSEL18_Pos (18U) 797 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 798 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ 799 #define ADC_CHSELR_CHSEL17_Pos (17U) 800 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 801 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ 802 #define ADC_CHSELR_CHSEL16_Pos (16U) 803 #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ 804 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ 805 #define ADC_CHSELR_CHSEL15_Pos (15U) 806 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 807 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ 808 #define ADC_CHSELR_CHSEL14_Pos (14U) 809 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 810 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ 811 #define ADC_CHSELR_CHSEL13_Pos (13U) 812 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 813 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ 814 #define ADC_CHSELR_CHSEL12_Pos (12U) 815 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 816 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ 817 #define ADC_CHSELR_CHSEL11_Pos (11U) 818 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 819 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ 820 #define ADC_CHSELR_CHSEL10_Pos (10U) 821 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 822 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ 823 #define ADC_CHSELR_CHSEL9_Pos (9U) 824 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 825 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ 826 #define ADC_CHSELR_CHSEL8_Pos (8U) 827 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 828 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ 829 #define ADC_CHSELR_CHSEL7_Pos (7U) 830 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 831 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ 832 #define ADC_CHSELR_CHSEL6_Pos (6U) 833 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 834 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ 835 #define ADC_CHSELR_CHSEL5_Pos (5U) 836 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 837 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ 838 #define ADC_CHSELR_CHSEL4_Pos (4U) 839 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 840 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ 841 #define ADC_CHSELR_CHSEL3_Pos (3U) 842 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 843 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ 844 #define ADC_CHSELR_CHSEL2_Pos (2U) 845 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 846 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ 847 #define ADC_CHSELR_CHSEL1_Pos (1U) 848 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 849 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ 850 #define ADC_CHSELR_CHSEL0_Pos (0U) 851 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 852 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ 853 854 /******************** Bit definition for ADC_DR register ********************/ 855 #define ADC_DR_DATA_Pos (0U) 856 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 857 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 858 #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ 859 #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ 860 #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ 861 #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ 862 #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ 863 #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ 864 #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ 865 #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ 866 #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ 867 #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ 868 #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ 869 #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ 870 #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ 871 #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ 872 #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ 873 #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ 874 875 /************************* ADC Common registers *****************************/ 876 /******************* Bit definition for ADC_CCR register ********************/ 877 #define ADC_CCR_VREFEN_Pos (22U) 878 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 879 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 880 #define ADC_CCR_TSEN_Pos (23U) 881 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 882 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ 883 884 885 /******************************************************************************/ 886 /* */ 887 /* CRC calculation unit (CRC) */ 888 /* */ 889 /******************************************************************************/ 890 /******************* Bit definition for CRC_DR register *********************/ 891 #define CRC_DR_DR_Pos (0U) 892 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 893 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 894 895 /******************* Bit definition for CRC_IDR register ********************/ 896 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 897 898 /******************** Bit definition for CRC_CR register ********************/ 899 #define CRC_CR_RESET_Pos (0U) 900 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 901 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 902 #define CRC_CR_REV_IN_Pos (5U) 903 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 904 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 905 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 906 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 907 #define CRC_CR_REV_OUT_Pos (7U) 908 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 909 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 910 911 /******************* Bit definition for CRC_INIT register *******************/ 912 #define CRC_INIT_INIT_Pos (0U) 913 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 914 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 915 916 /******************************************************************************/ 917 /* */ 918 /* Debug MCU (DBGMCU) */ 919 /* */ 920 /******************************************************************************/ 921 922 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 923 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 924 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 925 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 926 927 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 928 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 929 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 930 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 931 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 932 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 933 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 934 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 935 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 936 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 937 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 938 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 939 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 940 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 941 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 942 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 943 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 944 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 945 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 946 947 /****************** Bit definition for DBGMCU_CR register *******************/ 948 #define DBGMCU_CR_DBG_STOP_Pos (1U) 949 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 950 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 951 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 952 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 953 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 954 955 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 956 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 957 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 958 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 959 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 960 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 961 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 962 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 963 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 964 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 965 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 966 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ 967 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */ 968 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 969 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 970 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 971 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 972 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 973 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 974 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 975 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 976 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 977 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 978 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 979 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 980 981 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 982 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U) 983 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ 984 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 985 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U) 986 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ 987 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */ 988 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U) 989 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ 990 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */ 991 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U) 992 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ 993 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */ 994 995 /******************************************************************************/ 996 /* */ 997 /* DMA Controller (DMA) */ 998 /* */ 999 /******************************************************************************/ 1000 /******************* Bit definition for DMA_ISR register ********************/ 1001 #define DMA_ISR_GIF1_Pos (0U) 1002 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1003 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1004 #define DMA_ISR_TCIF1_Pos (1U) 1005 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1006 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1007 #define DMA_ISR_HTIF1_Pos (2U) 1008 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1009 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1010 #define DMA_ISR_TEIF1_Pos (3U) 1011 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1012 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1013 #define DMA_ISR_GIF2_Pos (4U) 1014 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1015 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1016 #define DMA_ISR_TCIF2_Pos (5U) 1017 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1018 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1019 #define DMA_ISR_HTIF2_Pos (6U) 1020 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1021 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1022 #define DMA_ISR_TEIF2_Pos (7U) 1023 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1024 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1025 #define DMA_ISR_GIF3_Pos (8U) 1026 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1027 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1028 #define DMA_ISR_TCIF3_Pos (9U) 1029 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1030 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1031 #define DMA_ISR_HTIF3_Pos (10U) 1032 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1033 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1034 #define DMA_ISR_TEIF3_Pos (11U) 1035 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1036 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1037 #define DMA_ISR_GIF4_Pos (12U) 1038 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1039 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1040 #define DMA_ISR_TCIF4_Pos (13U) 1041 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1042 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1043 #define DMA_ISR_HTIF4_Pos (14U) 1044 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1045 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1046 #define DMA_ISR_TEIF4_Pos (15U) 1047 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1048 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1049 #define DMA_ISR_GIF5_Pos (16U) 1050 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1051 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1052 #define DMA_ISR_TCIF5_Pos (17U) 1053 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1054 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1055 #define DMA_ISR_HTIF5_Pos (18U) 1056 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1057 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1058 #define DMA_ISR_TEIF5_Pos (19U) 1059 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1060 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1061 1062 /******************* Bit definition for DMA_IFCR register *******************/ 1063 #define DMA_IFCR_CGIF1_Pos (0U) 1064 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1065 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1066 #define DMA_IFCR_CTCIF1_Pos (1U) 1067 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1068 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1069 #define DMA_IFCR_CHTIF1_Pos (2U) 1070 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1071 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1072 #define DMA_IFCR_CTEIF1_Pos (3U) 1073 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1074 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1075 #define DMA_IFCR_CGIF2_Pos (4U) 1076 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1077 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1078 #define DMA_IFCR_CTCIF2_Pos (5U) 1079 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1080 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1081 #define DMA_IFCR_CHTIF2_Pos (6U) 1082 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1083 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1084 #define DMA_IFCR_CTEIF2_Pos (7U) 1085 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1086 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1087 #define DMA_IFCR_CGIF3_Pos (8U) 1088 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1089 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1090 #define DMA_IFCR_CTCIF3_Pos (9U) 1091 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1092 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1093 #define DMA_IFCR_CHTIF3_Pos (10U) 1094 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1095 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1096 #define DMA_IFCR_CTEIF3_Pos (11U) 1097 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1098 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1099 #define DMA_IFCR_CGIF4_Pos (12U) 1100 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1101 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1102 #define DMA_IFCR_CTCIF4_Pos (13U) 1103 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1104 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1105 #define DMA_IFCR_CHTIF4_Pos (14U) 1106 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1107 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1108 #define DMA_IFCR_CTEIF4_Pos (15U) 1109 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1110 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1111 #define DMA_IFCR_CGIF5_Pos (16U) 1112 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1113 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1114 #define DMA_IFCR_CTCIF5_Pos (17U) 1115 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1116 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1117 #define DMA_IFCR_CHTIF5_Pos (18U) 1118 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1119 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1120 #define DMA_IFCR_CTEIF5_Pos (19U) 1121 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1122 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1123 1124 /******************* Bit definition for DMA_CCR register ********************/ 1125 #define DMA_CCR_EN_Pos (0U) 1126 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1127 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1128 #define DMA_CCR_TCIE_Pos (1U) 1129 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1130 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1131 #define DMA_CCR_HTIE_Pos (2U) 1132 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1133 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1134 #define DMA_CCR_TEIE_Pos (3U) 1135 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1136 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1137 #define DMA_CCR_DIR_Pos (4U) 1138 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1139 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1140 #define DMA_CCR_CIRC_Pos (5U) 1141 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1142 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1143 #define DMA_CCR_PINC_Pos (6U) 1144 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1145 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1146 #define DMA_CCR_MINC_Pos (7U) 1147 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1148 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1149 1150 #define DMA_CCR_PSIZE_Pos (8U) 1151 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1152 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1153 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1154 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1155 1156 #define DMA_CCR_MSIZE_Pos (10U) 1157 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1158 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1159 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1160 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1161 1162 #define DMA_CCR_PL_Pos (12U) 1163 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1164 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1165 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1166 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1167 1168 #define DMA_CCR_MEM2MEM_Pos (14U) 1169 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1170 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1171 1172 /****************** Bit definition for DMA_CNDTR register *******************/ 1173 #define DMA_CNDTR_NDT_Pos (0U) 1174 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1175 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1176 1177 /****************** Bit definition for DMA_CPAR register ********************/ 1178 #define DMA_CPAR_PA_Pos (0U) 1179 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1180 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1181 1182 /****************** Bit definition for DMA_CMAR register ********************/ 1183 #define DMA_CMAR_MA_Pos (0U) 1184 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1185 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1186 1187 /****************** Bit definition for DMA1_CSELR register ********************/ 1188 #define DMA_CSELR_C1S_Pos (0U) 1189 #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ 1190 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ 1191 #define DMA_CSELR_C2S_Pos (4U) 1192 #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ 1193 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ 1194 #define DMA_CSELR_C3S_Pos (8U) 1195 #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ 1196 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ 1197 #define DMA_CSELR_C4S_Pos (12U) 1198 #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ 1199 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ 1200 #define DMA_CSELR_C5S_Pos (16U) 1201 #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ 1202 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ 1203 #define DMA_CSELR_C6S_Pos (20U) 1204 #define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ 1205 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ 1206 #define DMA_CSELR_C7S_Pos (24U) 1207 #define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ 1208 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ 1209 1210 #define DMA1_CSELR_DEFAULT (0x00000000U) /*!< Default remap position for DMA1 */ 1211 #define DMA1_CSELR_CH1_ADC_Pos (0U) 1212 #define DMA1_CSELR_CH1_ADC_Msk (0x1UL << DMA1_CSELR_CH1_ADC_Pos) /*!< 0x00000001 */ 1213 #define DMA1_CSELR_CH1_ADC DMA1_CSELR_CH1_ADC_Msk /*!< Remap ADC on DMA1 Channel 1*/ 1214 #define DMA1_CSELR_CH1_TIM17_CH1_Pos (0U) 1215 #define DMA1_CSELR_CH1_TIM17_CH1_Msk (0x7UL << DMA1_CSELR_CH1_TIM17_CH1_Pos) /*!< 0x00000007 */ 1216 #define DMA1_CSELR_CH1_TIM17_CH1 DMA1_CSELR_CH1_TIM17_CH1_Msk /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ 1217 #define DMA1_CSELR_CH1_TIM17_UP_Pos (0U) 1218 #define DMA1_CSELR_CH1_TIM17_UP_Msk (0x7UL << DMA1_CSELR_CH1_TIM17_UP_Pos) /*!< 0x00000007 */ 1219 #define DMA1_CSELR_CH1_TIM17_UP DMA1_CSELR_CH1_TIM17_UP_Msk /*!< Remap TIM17 up on DMA1 channel 1 */ 1220 #define DMA1_CSELR_CH1_USART1_RX_Pos (3U) 1221 #define DMA1_CSELR_CH1_USART1_RX_Msk (0x1UL << DMA1_CSELR_CH1_USART1_RX_Pos) /*!< 0x00000008 */ 1222 #define DMA1_CSELR_CH1_USART1_RX DMA1_CSELR_CH1_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 1 */ 1223 #define DMA1_CSELR_CH1_USART2_RX_Pos (0U) 1224 #define DMA1_CSELR_CH1_USART2_RX_Msk (0x9UL << DMA1_CSELR_CH1_USART2_RX_Pos) /*!< 0x00000009 */ 1225 #define DMA1_CSELR_CH1_USART2_RX DMA1_CSELR_CH1_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 1 */ 1226 #define DMA1_CSELR_CH1_USART3_RX_Pos (1U) 1227 #define DMA1_CSELR_CH1_USART3_RX_Msk (0x5UL << DMA1_CSELR_CH1_USART3_RX_Pos) /*!< 0x0000000A */ 1228 #define DMA1_CSELR_CH1_USART3_RX DMA1_CSELR_CH1_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 1 */ 1229 #define DMA1_CSELR_CH1_USART4_RX_Pos (0U) 1230 #define DMA1_CSELR_CH1_USART4_RX_Msk (0xBUL << DMA1_CSELR_CH1_USART4_RX_Pos) /*!< 0x0000000B */ 1231 #define DMA1_CSELR_CH1_USART4_RX DMA1_CSELR_CH1_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 1 */ 1232 #define DMA1_CSELR_CH1_USART5_RX_Pos (2U) 1233 #define DMA1_CSELR_CH1_USART5_RX_Msk (0x3UL << DMA1_CSELR_CH1_USART5_RX_Pos) /*!< 0x0000000C */ 1234 #define DMA1_CSELR_CH1_USART5_RX DMA1_CSELR_CH1_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 1 */ 1235 #define DMA1_CSELR_CH1_USART6_RX_Pos (0U) 1236 #define DMA1_CSELR_CH1_USART6_RX_Msk (0xDUL << DMA1_CSELR_CH1_USART6_RX_Pos) /*!< 0x0000000D */ 1237 #define DMA1_CSELR_CH1_USART6_RX DMA1_CSELR_CH1_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 1 */ 1238 #define DMA1_CSELR_CH2_ADC_Pos (4U) 1239 #define DMA1_CSELR_CH2_ADC_Msk (0x1UL << DMA1_CSELR_CH2_ADC_Pos) /*!< 0x00000010 */ 1240 #define DMA1_CSELR_CH2_ADC DMA1_CSELR_CH2_ADC_Msk /*!< Remap ADC on DMA1 channel 2 */ 1241 #define DMA1_CSELR_CH2_I2C1_TX_Pos (5U) 1242 #define DMA1_CSELR_CH2_I2C1_TX_Msk (0x1UL << DMA1_CSELR_CH2_I2C1_TX_Pos) /*!< 0x00000020 */ 1243 #define DMA1_CSELR_CH2_I2C1_TX DMA1_CSELR_CH2_I2C1_TX_Msk /*!< Remap I2C1 Tx on DMA1 channel 2 */ 1244 #define DMA1_CSELR_CH2_SPI1_RX_Pos (4U) 1245 #define DMA1_CSELR_CH2_SPI1_RX_Msk (0x3UL << DMA1_CSELR_CH2_SPI1_RX_Pos) /*!< 0x00000030 */ 1246 #define DMA1_CSELR_CH2_SPI1_RX DMA1_CSELR_CH2_SPI1_RX_Msk /*!< Remap SPI1 Rx on DMA1 channel 2 */ 1247 #define DMA1_CSELR_CH2_TIM1_CH1_Pos (6U) 1248 #define DMA1_CSELR_CH2_TIM1_CH1_Msk (0x1UL << DMA1_CSELR_CH2_TIM1_CH1_Pos) /*!< 0x00000040 */ 1249 #define DMA1_CSELR_CH2_TIM1_CH1 DMA1_CSELR_CH2_TIM1_CH1_Msk /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ 1250 #define DMA1_CSELR_CH2_TIM17_CH1_Pos (4U) 1251 #define DMA1_CSELR_CH2_TIM17_CH1_Msk (0x7UL << DMA1_CSELR_CH2_TIM17_CH1_Pos) /*!< 0x00000070 */ 1252 #define DMA1_CSELR_CH2_TIM17_CH1 DMA1_CSELR_CH2_TIM17_CH1_Msk /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ 1253 #define DMA1_CSELR_CH2_TIM17_UP_Pos (4U) 1254 #define DMA1_CSELR_CH2_TIM17_UP_Msk (0x7UL << DMA1_CSELR_CH2_TIM17_UP_Pos) /*!< 0x00000070 */ 1255 #define DMA1_CSELR_CH2_TIM17_UP DMA1_CSELR_CH2_TIM17_UP_Msk /*!< Remap TIM17 up on DMA1 channel 2 */ 1256 #define DMA1_CSELR_CH2_USART1_TX_Pos (7U) 1257 #define DMA1_CSELR_CH2_USART1_TX_Msk (0x1UL << DMA1_CSELR_CH2_USART1_TX_Pos) /*!< 0x00000080 */ 1258 #define DMA1_CSELR_CH2_USART1_TX DMA1_CSELR_CH2_USART1_TX_Msk /*!< Remap USART1 Tx on DMA1 channel 2 */ 1259 #define DMA1_CSELR_CH2_USART2_TX_Pos (4U) 1260 #define DMA1_CSELR_CH2_USART2_TX_Msk (0x9UL << DMA1_CSELR_CH2_USART2_TX_Pos) /*!< 0x00000090 */ 1261 #define DMA1_CSELR_CH2_USART2_TX DMA1_CSELR_CH2_USART2_TX_Msk /*!< Remap USART2 Tx on DMA1 channel 2 */ 1262 #define DMA1_CSELR_CH2_USART3_TX_Pos (5U) 1263 #define DMA1_CSELR_CH2_USART3_TX_Msk (0x5UL << DMA1_CSELR_CH2_USART3_TX_Pos) /*!< 0x000000A0 */ 1264 #define DMA1_CSELR_CH2_USART3_TX DMA1_CSELR_CH2_USART3_TX_Msk /*!< Remap USART3 Tx on DMA1 channel 2 */ 1265 #define DMA1_CSELR_CH2_USART4_TX_Pos (4U) 1266 #define DMA1_CSELR_CH2_USART4_TX_Msk (0xBUL << DMA1_CSELR_CH2_USART4_TX_Pos) /*!< 0x000000B0 */ 1267 #define DMA1_CSELR_CH2_USART4_TX DMA1_CSELR_CH2_USART4_TX_Msk /*!< Remap USART4 Tx on DMA1 channel 2 */ 1268 #define DMA1_CSELR_CH2_USART5_TX_Pos (6U) 1269 #define DMA1_CSELR_CH2_USART5_TX_Msk (0x3UL << DMA1_CSELR_CH2_USART5_TX_Pos) /*!< 0x000000C0 */ 1270 #define DMA1_CSELR_CH2_USART5_TX DMA1_CSELR_CH2_USART5_TX_Msk /*!< Remap USART5 Tx on DMA1 channel 2 */ 1271 #define DMA1_CSELR_CH2_USART6_TX_Pos (4U) 1272 #define DMA1_CSELR_CH2_USART6_TX_Msk (0xDUL << DMA1_CSELR_CH2_USART6_TX_Pos) /*!< 0x000000D0 */ 1273 #define DMA1_CSELR_CH2_USART6_TX DMA1_CSELR_CH2_USART6_TX_Msk /*!< Remap USART6 Tx on DMA1 channel 2 */ 1274 #define DMA1_CSELR_CH3_TIM6_UP_Pos (8U) 1275 #define DMA1_CSELR_CH3_TIM6_UP_Msk (0x1UL << DMA1_CSELR_CH3_TIM6_UP_Pos) /*!< 0x00000100 */ 1276 #define DMA1_CSELR_CH3_TIM6_UP DMA1_CSELR_CH3_TIM6_UP_Msk /*!< Remap TIM6 up on DMA1 channel 3 */ 1277 #define DMA1_CSELR_CH3_I2C1_RX_Pos (9U) 1278 #define DMA1_CSELR_CH3_I2C1_RX_Msk (0x1UL << DMA1_CSELR_CH3_I2C1_RX_Pos) /*!< 0x00000200 */ 1279 #define DMA1_CSELR_CH3_I2C1_RX DMA1_CSELR_CH3_I2C1_RX_Msk /*!< Remap I2C1 Rx on DMA1 channel 3 */ 1280 #define DMA1_CSELR_CH3_SPI1_TX_Pos (8U) 1281 #define DMA1_CSELR_CH3_SPI1_TX_Msk (0x3UL << DMA1_CSELR_CH3_SPI1_TX_Pos) /*!< 0x00000300 */ 1282 #define DMA1_CSELR_CH3_SPI1_TX DMA1_CSELR_CH3_SPI1_TX_Msk /*!< Remap SPI1 Tx on DMA1 channel 3 */ 1283 #define DMA1_CSELR_CH3_TIM1_CH2_Pos (10U) 1284 #define DMA1_CSELR_CH3_TIM1_CH2_Msk (0x1UL << DMA1_CSELR_CH3_TIM1_CH2_Pos) /*!< 0x00000400 */ 1285 #define DMA1_CSELR_CH3_TIM1_CH2 DMA1_CSELR_CH3_TIM1_CH2_Msk /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ 1286 #define DMA1_CSELR_CH3_TIM16_CH1_Pos (8U) 1287 #define DMA1_CSELR_CH3_TIM16_CH1_Msk (0x7UL << DMA1_CSELR_CH3_TIM16_CH1_Pos) /*!< 0x00000700 */ 1288 #define DMA1_CSELR_CH3_TIM16_CH1 DMA1_CSELR_CH3_TIM16_CH1_Msk /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ 1289 #define DMA1_CSELR_CH3_TIM16_UP_Pos (8U) 1290 #define DMA1_CSELR_CH3_TIM16_UP_Msk (0x7UL << DMA1_CSELR_CH3_TIM16_UP_Pos) /*!< 0x00000700 */ 1291 #define DMA1_CSELR_CH3_TIM16_UP DMA1_CSELR_CH3_TIM16_UP_Msk /*!< Remap TIM16 up on DMA1 channel 3 */ 1292 #define DMA1_CSELR_CH3_USART1_RX_Pos (11U) 1293 #define DMA1_CSELR_CH3_USART1_RX_Msk (0x1UL << DMA1_CSELR_CH3_USART1_RX_Pos) /*!< 0x00000800 */ 1294 #define DMA1_CSELR_CH3_USART1_RX DMA1_CSELR_CH3_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 3 */ 1295 #define DMA1_CSELR_CH3_USART2_RX_Pos (8U) 1296 #define DMA1_CSELR_CH3_USART2_RX_Msk (0x9UL << DMA1_CSELR_CH3_USART2_RX_Pos) /*!< 0x00000900 */ 1297 #define DMA1_CSELR_CH3_USART2_RX DMA1_CSELR_CH3_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 3 */ 1298 #define DMA1_CSELR_CH3_USART3_RX_Pos (9U) 1299 #define DMA1_CSELR_CH3_USART3_RX_Msk (0x5UL << DMA1_CSELR_CH3_USART3_RX_Pos) /*!< 0x00000A00 */ 1300 #define DMA1_CSELR_CH3_USART3_RX DMA1_CSELR_CH3_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 3 */ 1301 #define DMA1_CSELR_CH3_USART4_RX_Pos (8U) 1302 #define DMA1_CSELR_CH3_USART4_RX_Msk (0xBUL << DMA1_CSELR_CH3_USART4_RX_Pos) /*!< 0x00000B00 */ 1303 #define DMA1_CSELR_CH3_USART4_RX DMA1_CSELR_CH3_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 3 */ 1304 #define DMA1_CSELR_CH3_USART5_RX_Pos (10U) 1305 #define DMA1_CSELR_CH3_USART5_RX_Msk (0x3UL << DMA1_CSELR_CH3_USART5_RX_Pos) /*!< 0x00000C00 */ 1306 #define DMA1_CSELR_CH3_USART5_RX DMA1_CSELR_CH3_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 3 */ 1307 #define DMA1_CSELR_CH3_USART6_RX_Pos (8U) 1308 #define DMA1_CSELR_CH3_USART6_RX_Msk (0xDUL << DMA1_CSELR_CH3_USART6_RX_Pos) /*!< 0x00000D00 */ 1309 #define DMA1_CSELR_CH3_USART6_RX DMA1_CSELR_CH3_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 3 */ 1310 #define DMA1_CSELR_CH4_TIM7_UP_Pos (12U) 1311 #define DMA1_CSELR_CH4_TIM7_UP_Msk (0x1UL << DMA1_CSELR_CH4_TIM7_UP_Pos) /*!< 0x00001000 */ 1312 #define DMA1_CSELR_CH4_TIM7_UP DMA1_CSELR_CH4_TIM7_UP_Msk /*!< Remap TIM7 up on DMA1 channel 4 */ 1313 #define DMA1_CSELR_CH4_I2C2_TX_Pos (13U) 1314 #define DMA1_CSELR_CH4_I2C2_TX_Msk (0x1UL << DMA1_CSELR_CH4_I2C2_TX_Pos) /*!< 0x00002000 */ 1315 #define DMA1_CSELR_CH4_I2C2_TX DMA1_CSELR_CH4_I2C2_TX_Msk /*!< Remap I2C2 Tx on DMA1 channel 4 */ 1316 #define DMA1_CSELR_CH4_SPI2_RX_Pos (12U) 1317 #define DMA1_CSELR_CH4_SPI2_RX_Msk (0x3UL << DMA1_CSELR_CH4_SPI2_RX_Pos) /*!< 0x00003000 */ 1318 #define DMA1_CSELR_CH4_SPI2_RX DMA1_CSELR_CH4_SPI2_RX_Msk /*!< Remap SPI2 Rx on DMA1 channel 4 */ 1319 #define DMA1_CSELR_CH4_TIM2_CH4_Pos (12U) 1320 #define DMA1_CSELR_CH4_TIM2_CH4_Msk (0x5UL << DMA1_CSELR_CH4_TIM2_CH4_Pos) /*!< 0x00005000 */ 1321 #define DMA1_CSELR_CH4_TIM2_CH4 DMA1_CSELR_CH4_TIM2_CH4_Msk /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ 1322 #define DMA1_CSELR_CH4_TIM3_CH1_Pos (13U) 1323 #define DMA1_CSELR_CH4_TIM3_CH1_Msk (0x3UL << DMA1_CSELR_CH4_TIM3_CH1_Pos) /*!< 0x00006000 */ 1324 #define DMA1_CSELR_CH4_TIM3_CH1 DMA1_CSELR_CH4_TIM3_CH1_Msk /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ 1325 #define DMA1_CSELR_CH4_TIM3_TRIG_Pos (13U) 1326 #define DMA1_CSELR_CH4_TIM3_TRIG_Msk (0x3UL << DMA1_CSELR_CH4_TIM3_TRIG_Pos) /*!< 0x00006000 */ 1327 #define DMA1_CSELR_CH4_TIM3_TRIG DMA1_CSELR_CH4_TIM3_TRIG_Msk /*!< Remap TIM3 Trig on DMA1 channel 4 */ 1328 #define DMA1_CSELR_CH4_TIM16_CH1_Pos (12U) 1329 #define DMA1_CSELR_CH4_TIM16_CH1_Msk (0x7UL << DMA1_CSELR_CH4_TIM16_CH1_Pos) /*!< 0x00007000 */ 1330 #define DMA1_CSELR_CH4_TIM16_CH1 DMA1_CSELR_CH4_TIM16_CH1_Msk /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ 1331 #define DMA1_CSELR_CH4_TIM16_UP_Pos (12U) 1332 #define DMA1_CSELR_CH4_TIM16_UP_Msk (0x7UL << DMA1_CSELR_CH4_TIM16_UP_Pos) /*!< 0x00007000 */ 1333 #define DMA1_CSELR_CH4_TIM16_UP DMA1_CSELR_CH4_TIM16_UP_Msk /*!< Remap TIM16 up on DMA1 channel 4 */ 1334 #define DMA1_CSELR_CH4_USART1_TX_Pos (15U) 1335 #define DMA1_CSELR_CH4_USART1_TX_Msk (0x1UL << DMA1_CSELR_CH4_USART1_TX_Pos) /*!< 0x00008000 */ 1336 #define DMA1_CSELR_CH4_USART1_TX DMA1_CSELR_CH4_USART1_TX_Msk /*!< Remap USART1 Tx on DMA1 channel 4 */ 1337 #define DMA1_CSELR_CH4_USART2_TX_Pos (12U) 1338 #define DMA1_CSELR_CH4_USART2_TX_Msk (0x9UL << DMA1_CSELR_CH4_USART2_TX_Pos) /*!< 0x00009000 */ 1339 #define DMA1_CSELR_CH4_USART2_TX DMA1_CSELR_CH4_USART2_TX_Msk /*!< Remap USART2 Tx on DMA1 channel 4 */ 1340 #define DMA1_CSELR_CH4_USART3_TX_Pos (13U) 1341 #define DMA1_CSELR_CH4_USART3_TX_Msk (0x5UL << DMA1_CSELR_CH4_USART3_TX_Pos) /*!< 0x0000A000 */ 1342 #define DMA1_CSELR_CH4_USART3_TX DMA1_CSELR_CH4_USART3_TX_Msk /*!< Remap USART3 Tx on DMA1 channel 4 */ 1343 #define DMA1_CSELR_CH4_USART4_TX_Pos (12U) 1344 #define DMA1_CSELR_CH4_USART4_TX_Msk (0xBUL << DMA1_CSELR_CH4_USART4_TX_Pos) /*!< 0x0000B000 */ 1345 #define DMA1_CSELR_CH4_USART4_TX DMA1_CSELR_CH4_USART4_TX_Msk /*!< Remap USART4 Tx on DMA1 channel 4 */ 1346 #define DMA1_CSELR_CH4_USART5_TX_Pos (14U) 1347 #define DMA1_CSELR_CH4_USART5_TX_Msk (0x3UL << DMA1_CSELR_CH4_USART5_TX_Pos) /*!< 0x0000C000 */ 1348 #define DMA1_CSELR_CH4_USART5_TX DMA1_CSELR_CH4_USART5_TX_Msk /*!< Remap USART5 Tx on DMA1 channel 4 */ 1349 #define DMA1_CSELR_CH4_USART6_TX_Pos (12U) 1350 #define DMA1_CSELR_CH4_USART6_TX_Msk (0xDUL << DMA1_CSELR_CH4_USART6_TX_Pos) /*!< 0x0000D000 */ 1351 #define DMA1_CSELR_CH4_USART6_TX DMA1_CSELR_CH4_USART6_TX_Msk /*!< Remap USART6 Tx on DMA1 channel 4 */ 1352 #define DMA1_CSELR_CH5_I2C2_RX_Pos (17U) 1353 #define DMA1_CSELR_CH5_I2C2_RX_Msk (0x1UL << DMA1_CSELR_CH5_I2C2_RX_Pos) /*!< 0x00020000 */ 1354 #define DMA1_CSELR_CH5_I2C2_RX DMA1_CSELR_CH5_I2C2_RX_Msk /*!< Remap I2C2 Rx on DMA1 channel 5 */ 1355 #define DMA1_CSELR_CH5_SPI2_TX_Pos (16U) 1356 #define DMA1_CSELR_CH5_SPI2_TX_Msk (0x3UL << DMA1_CSELR_CH5_SPI2_TX_Pos) /*!< 0x00030000 */ 1357 #define DMA1_CSELR_CH5_SPI2_TX DMA1_CSELR_CH5_SPI2_TX_Msk /*!< Remap SPI1 Tx on DMA1 channel 5 */ 1358 #define DMA1_CSELR_CH5_TIM1_CH3_Pos (18U) 1359 #define DMA1_CSELR_CH5_TIM1_CH3_Msk (0x1UL << DMA1_CSELR_CH5_TIM1_CH3_Pos) /*!< 0x00040000 */ 1360 #define DMA1_CSELR_CH5_TIM1_CH3 DMA1_CSELR_CH5_TIM1_CH3_Msk /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ 1361 #define DMA1_CSELR_CH5_USART1_RX_Pos (19U) 1362 #define DMA1_CSELR_CH5_USART1_RX_Msk (0x1UL << DMA1_CSELR_CH5_USART1_RX_Pos) /*!< 0x00080000 */ 1363 #define DMA1_CSELR_CH5_USART1_RX DMA1_CSELR_CH5_USART1_RX_Msk /*!< Remap USART1 Rx on DMA1 channel 5 */ 1364 #define DMA1_CSELR_CH5_USART2_RX_Pos (16U) 1365 #define DMA1_CSELR_CH5_USART2_RX_Msk (0x9UL << DMA1_CSELR_CH5_USART2_RX_Pos) /*!< 0x00090000 */ 1366 #define DMA1_CSELR_CH5_USART2_RX DMA1_CSELR_CH5_USART2_RX_Msk /*!< Remap USART2 Rx on DMA1 channel 5 */ 1367 #define DMA1_CSELR_CH5_USART3_RX_Pos (17U) 1368 #define DMA1_CSELR_CH5_USART3_RX_Msk (0x5UL << DMA1_CSELR_CH5_USART3_RX_Pos) /*!< 0x000A0000 */ 1369 #define DMA1_CSELR_CH5_USART3_RX DMA1_CSELR_CH5_USART3_RX_Msk /*!< Remap USART3 Rx on DMA1 channel 5 */ 1370 #define DMA1_CSELR_CH5_USART4_RX_Pos (16U) 1371 #define DMA1_CSELR_CH5_USART4_RX_Msk (0xBUL << DMA1_CSELR_CH5_USART4_RX_Pos) /*!< 0x000B0000 */ 1372 #define DMA1_CSELR_CH5_USART4_RX DMA1_CSELR_CH5_USART4_RX_Msk /*!< Remap USART4 Rx on DMA1 channel 5 */ 1373 #define DMA1_CSELR_CH5_USART5_RX_Pos (18U) 1374 #define DMA1_CSELR_CH5_USART5_RX_Msk (0x3UL << DMA1_CSELR_CH5_USART5_RX_Pos) /*!< 0x000C0000 */ 1375 #define DMA1_CSELR_CH5_USART5_RX DMA1_CSELR_CH5_USART5_RX_Msk /*!< Remap USART5 Rx on DMA1 channel 5 */ 1376 #define DMA1_CSELR_CH5_USART6_RX_Pos (16U) 1377 #define DMA1_CSELR_CH5_USART6_RX_Msk (0xDUL << DMA1_CSELR_CH5_USART6_RX_Pos) /*!< 0x000D0000 */ 1378 #define DMA1_CSELR_CH5_USART6_RX DMA1_CSELR_CH5_USART6_RX_Msk /*!< Remap USART6 Rx on DMA1 channel 5 */ 1379 /******************************************************************************/ 1380 /* */ 1381 /* External Interrupt/Event Controller (EXTI) */ 1382 /* */ 1383 /******************************************************************************/ 1384 /******************* Bit definition for EXTI_IMR register *******************/ 1385 #define EXTI_IMR_MR0_Pos (0U) 1386 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 1387 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 1388 #define EXTI_IMR_MR1_Pos (1U) 1389 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 1390 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 1391 #define EXTI_IMR_MR2_Pos (2U) 1392 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 1393 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 1394 #define EXTI_IMR_MR3_Pos (3U) 1395 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 1396 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 1397 #define EXTI_IMR_MR4_Pos (4U) 1398 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 1399 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 1400 #define EXTI_IMR_MR5_Pos (5U) 1401 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 1402 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 1403 #define EXTI_IMR_MR6_Pos (6U) 1404 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 1405 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 1406 #define EXTI_IMR_MR7_Pos (7U) 1407 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 1408 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 1409 #define EXTI_IMR_MR8_Pos (8U) 1410 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 1411 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 1412 #define EXTI_IMR_MR9_Pos (9U) 1413 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 1414 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 1415 #define EXTI_IMR_MR10_Pos (10U) 1416 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 1417 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 1418 #define EXTI_IMR_MR11_Pos (11U) 1419 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 1420 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 1421 #define EXTI_IMR_MR12_Pos (12U) 1422 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 1423 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 1424 #define EXTI_IMR_MR13_Pos (13U) 1425 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 1426 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 1427 #define EXTI_IMR_MR14_Pos (14U) 1428 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 1429 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 1430 #define EXTI_IMR_MR15_Pos (15U) 1431 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 1432 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 1433 #define EXTI_IMR_MR17_Pos (17U) 1434 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 1435 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 1436 #define EXTI_IMR_MR19_Pos (19U) 1437 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 1438 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 1439 #define EXTI_IMR_MR20_Pos (20U) 1440 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 1441 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 1442 1443 /* References Defines */ 1444 #define EXTI_IMR_IM0 EXTI_IMR_MR0 1445 #define EXTI_IMR_IM1 EXTI_IMR_MR1 1446 #define EXTI_IMR_IM2 EXTI_IMR_MR2 1447 #define EXTI_IMR_IM3 EXTI_IMR_MR3 1448 #define EXTI_IMR_IM4 EXTI_IMR_MR4 1449 #define EXTI_IMR_IM5 EXTI_IMR_MR5 1450 #define EXTI_IMR_IM6 EXTI_IMR_MR6 1451 #define EXTI_IMR_IM7 EXTI_IMR_MR7 1452 #define EXTI_IMR_IM8 EXTI_IMR_MR8 1453 #define EXTI_IMR_IM9 EXTI_IMR_MR9 1454 #define EXTI_IMR_IM10 EXTI_IMR_MR10 1455 #define EXTI_IMR_IM11 EXTI_IMR_MR11 1456 #define EXTI_IMR_IM12 EXTI_IMR_MR12 1457 #define EXTI_IMR_IM13 EXTI_IMR_MR13 1458 #define EXTI_IMR_IM14 EXTI_IMR_MR14 1459 #define EXTI_IMR_IM15 EXTI_IMR_MR15 1460 #define EXTI_IMR_IM17 EXTI_IMR_MR17 1461 #define EXTI_IMR_IM19 EXTI_IMR_MR19 1462 #define EXTI_IMR_IM20 EXTI_IMR_MR20 1463 1464 #define EXTI_IMR_IM_Pos (0U) 1465 #define EXTI_IMR_IM_Msk (0x9EFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x009EFFFF */ 1466 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1467 1468 1469 /****************** Bit definition for EXTI_EMR register ********************/ 1470 #define EXTI_EMR_MR0_Pos (0U) 1471 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 1472 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 1473 #define EXTI_EMR_MR1_Pos (1U) 1474 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 1475 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 1476 #define EXTI_EMR_MR2_Pos (2U) 1477 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 1478 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 1479 #define EXTI_EMR_MR3_Pos (3U) 1480 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 1481 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 1482 #define EXTI_EMR_MR4_Pos (4U) 1483 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 1484 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 1485 #define EXTI_EMR_MR5_Pos (5U) 1486 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 1487 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 1488 #define EXTI_EMR_MR6_Pos (6U) 1489 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 1490 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 1491 #define EXTI_EMR_MR7_Pos (7U) 1492 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 1493 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 1494 #define EXTI_EMR_MR8_Pos (8U) 1495 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 1496 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 1497 #define EXTI_EMR_MR9_Pos (9U) 1498 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 1499 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 1500 #define EXTI_EMR_MR10_Pos (10U) 1501 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 1502 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 1503 #define EXTI_EMR_MR11_Pos (11U) 1504 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 1505 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 1506 #define EXTI_EMR_MR12_Pos (12U) 1507 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 1508 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 1509 #define EXTI_EMR_MR13_Pos (13U) 1510 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 1511 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 1512 #define EXTI_EMR_MR14_Pos (14U) 1513 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 1514 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 1515 #define EXTI_EMR_MR15_Pos (15U) 1516 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 1517 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 1518 #define EXTI_EMR_MR17_Pos (17U) 1519 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 1520 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 1521 #define EXTI_EMR_MR19_Pos (19U) 1522 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 1523 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 1524 #define EXTI_EMR_MR20_Pos (20U) 1525 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 1526 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 1527 1528 /* References Defines */ 1529 #define EXTI_EMR_EM0 EXTI_EMR_MR0 1530 #define EXTI_EMR_EM1 EXTI_EMR_MR1 1531 #define EXTI_EMR_EM2 EXTI_EMR_MR2 1532 #define EXTI_EMR_EM3 EXTI_EMR_MR3 1533 #define EXTI_EMR_EM4 EXTI_EMR_MR4 1534 #define EXTI_EMR_EM5 EXTI_EMR_MR5 1535 #define EXTI_EMR_EM6 EXTI_EMR_MR6 1536 #define EXTI_EMR_EM7 EXTI_EMR_MR7 1537 #define EXTI_EMR_EM8 EXTI_EMR_MR8 1538 #define EXTI_EMR_EM9 EXTI_EMR_MR9 1539 #define EXTI_EMR_EM10 EXTI_EMR_MR10 1540 #define EXTI_EMR_EM11 EXTI_EMR_MR11 1541 #define EXTI_EMR_EM12 EXTI_EMR_MR12 1542 #define EXTI_EMR_EM13 EXTI_EMR_MR13 1543 #define EXTI_EMR_EM14 EXTI_EMR_MR14 1544 #define EXTI_EMR_EM15 EXTI_EMR_MR15 1545 #define EXTI_EMR_EM17 EXTI_EMR_MR17 1546 #define EXTI_EMR_EM19 EXTI_EMR_MR19 1547 #define EXTI_EMR_EM20 EXTI_EMR_MR20 1548 1549 /******************* Bit definition for EXTI_RTSR register ******************/ 1550 #define EXTI_RTSR_TR0_Pos (0U) 1551 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 1552 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1553 #define EXTI_RTSR_TR1_Pos (1U) 1554 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 1555 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1556 #define EXTI_RTSR_TR2_Pos (2U) 1557 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 1558 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1559 #define EXTI_RTSR_TR3_Pos (3U) 1560 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 1561 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1562 #define EXTI_RTSR_TR4_Pos (4U) 1563 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 1564 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1565 #define EXTI_RTSR_TR5_Pos (5U) 1566 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 1567 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1568 #define EXTI_RTSR_TR6_Pos (6U) 1569 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 1570 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1571 #define EXTI_RTSR_TR7_Pos (7U) 1572 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 1573 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1574 #define EXTI_RTSR_TR8_Pos (8U) 1575 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 1576 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1577 #define EXTI_RTSR_TR9_Pos (9U) 1578 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 1579 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1580 #define EXTI_RTSR_TR10_Pos (10U) 1581 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 1582 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1583 #define EXTI_RTSR_TR11_Pos (11U) 1584 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 1585 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1586 #define EXTI_RTSR_TR12_Pos (12U) 1587 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 1588 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1589 #define EXTI_RTSR_TR13_Pos (13U) 1590 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 1591 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1592 #define EXTI_RTSR_TR14_Pos (14U) 1593 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 1594 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1595 #define EXTI_RTSR_TR15_Pos (15U) 1596 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 1597 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1598 #define EXTI_RTSR_TR16_Pos (16U) 1599 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 1600 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1601 #define EXTI_RTSR_TR17_Pos (17U) 1602 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 1603 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1604 #define EXTI_RTSR_TR19_Pos (19U) 1605 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 1606 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1607 #define EXTI_RTSR_TR20_Pos (20U) 1608 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 1609 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 1610 1611 /* References Defines */ 1612 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 1613 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 1614 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 1615 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 1616 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 1617 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 1618 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 1619 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 1620 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 1621 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 1622 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 1623 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 1624 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 1625 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 1626 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 1627 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 1628 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 1629 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 1630 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 1631 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 1632 1633 /******************* Bit definition for EXTI_FTSR register *******************/ 1634 #define EXTI_FTSR_TR0_Pos (0U) 1635 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 1636 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1637 #define EXTI_FTSR_TR1_Pos (1U) 1638 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 1639 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1640 #define EXTI_FTSR_TR2_Pos (2U) 1641 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 1642 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1643 #define EXTI_FTSR_TR3_Pos (3U) 1644 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 1645 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1646 #define EXTI_FTSR_TR4_Pos (4U) 1647 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 1648 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1649 #define EXTI_FTSR_TR5_Pos (5U) 1650 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 1651 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1652 #define EXTI_FTSR_TR6_Pos (6U) 1653 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 1654 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1655 #define EXTI_FTSR_TR7_Pos (7U) 1656 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 1657 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1658 #define EXTI_FTSR_TR8_Pos (8U) 1659 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 1660 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1661 #define EXTI_FTSR_TR9_Pos (9U) 1662 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 1663 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1664 #define EXTI_FTSR_TR10_Pos (10U) 1665 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 1666 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1667 #define EXTI_FTSR_TR11_Pos (11U) 1668 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 1669 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1670 #define EXTI_FTSR_TR12_Pos (12U) 1671 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 1672 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1673 #define EXTI_FTSR_TR13_Pos (13U) 1674 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 1675 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1676 #define EXTI_FTSR_TR14_Pos (14U) 1677 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 1678 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1679 #define EXTI_FTSR_TR15_Pos (15U) 1680 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 1681 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1682 #define EXTI_FTSR_TR16_Pos (16U) 1683 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 1684 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1685 #define EXTI_FTSR_TR17_Pos (17U) 1686 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 1687 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1688 #define EXTI_FTSR_TR19_Pos (19U) 1689 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 1690 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1691 #define EXTI_FTSR_TR20_Pos (20U) 1692 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 1693 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 1694 1695 /* References Defines */ 1696 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 1697 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 1698 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 1699 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 1700 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 1701 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 1702 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 1703 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 1704 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 1705 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 1706 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 1707 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 1708 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 1709 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 1710 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 1711 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 1712 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 1713 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 1714 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 1715 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 1716 1717 /******************* Bit definition for EXTI_SWIER register *******************/ 1718 #define EXTI_SWIER_SWIER0_Pos (0U) 1719 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 1720 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 1721 #define EXTI_SWIER_SWIER1_Pos (1U) 1722 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 1723 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 1724 #define EXTI_SWIER_SWIER2_Pos (2U) 1725 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 1726 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 1727 #define EXTI_SWIER_SWIER3_Pos (3U) 1728 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 1729 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 1730 #define EXTI_SWIER_SWIER4_Pos (4U) 1731 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 1732 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 1733 #define EXTI_SWIER_SWIER5_Pos (5U) 1734 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 1735 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 1736 #define EXTI_SWIER_SWIER6_Pos (6U) 1737 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 1738 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 1739 #define EXTI_SWIER_SWIER7_Pos (7U) 1740 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 1741 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 1742 #define EXTI_SWIER_SWIER8_Pos (8U) 1743 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 1744 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 1745 #define EXTI_SWIER_SWIER9_Pos (9U) 1746 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 1747 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 1748 #define EXTI_SWIER_SWIER10_Pos (10U) 1749 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 1750 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 1751 #define EXTI_SWIER_SWIER11_Pos (11U) 1752 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 1753 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 1754 #define EXTI_SWIER_SWIER12_Pos (12U) 1755 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 1756 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 1757 #define EXTI_SWIER_SWIER13_Pos (13U) 1758 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 1759 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 1760 #define EXTI_SWIER_SWIER14_Pos (14U) 1761 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 1762 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 1763 #define EXTI_SWIER_SWIER15_Pos (15U) 1764 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 1765 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 1766 #define EXTI_SWIER_SWIER16_Pos (16U) 1767 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 1768 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 1769 #define EXTI_SWIER_SWIER17_Pos (17U) 1770 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 1771 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 1772 #define EXTI_SWIER_SWIER19_Pos (19U) 1773 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 1774 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 1775 #define EXTI_SWIER_SWIER20_Pos (20U) 1776 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 1777 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 1778 1779 /* References Defines */ 1780 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 1781 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 1782 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 1783 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 1784 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 1785 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 1786 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 1787 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 1788 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 1789 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 1790 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 1791 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 1792 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 1793 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 1794 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 1795 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 1796 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 1797 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 1798 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 1799 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 1800 1801 /****************** Bit definition for EXTI_PR register *********************/ 1802 #define EXTI_PR_PR0_Pos (0U) 1803 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 1804 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */ 1805 #define EXTI_PR_PR1_Pos (1U) 1806 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 1807 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */ 1808 #define EXTI_PR_PR2_Pos (2U) 1809 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 1810 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */ 1811 #define EXTI_PR_PR3_Pos (3U) 1812 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 1813 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */ 1814 #define EXTI_PR_PR4_Pos (4U) 1815 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 1816 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */ 1817 #define EXTI_PR_PR5_Pos (5U) 1818 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 1819 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */ 1820 #define EXTI_PR_PR6_Pos (6U) 1821 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 1822 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */ 1823 #define EXTI_PR_PR7_Pos (7U) 1824 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 1825 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */ 1826 #define EXTI_PR_PR8_Pos (8U) 1827 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 1828 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */ 1829 #define EXTI_PR_PR9_Pos (9U) 1830 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 1831 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */ 1832 #define EXTI_PR_PR10_Pos (10U) 1833 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 1834 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */ 1835 #define EXTI_PR_PR11_Pos (11U) 1836 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 1837 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */ 1838 #define EXTI_PR_PR12_Pos (12U) 1839 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 1840 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */ 1841 #define EXTI_PR_PR13_Pos (13U) 1842 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 1843 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */ 1844 #define EXTI_PR_PR14_Pos (14U) 1845 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 1846 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */ 1847 #define EXTI_PR_PR15_Pos (15U) 1848 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 1849 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */ 1850 #define EXTI_PR_PR16_Pos (16U) 1851 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 1852 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */ 1853 #define EXTI_PR_PR17_Pos (17U) 1854 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 1855 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */ 1856 #define EXTI_PR_PR19_Pos (19U) 1857 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 1858 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */ 1859 #define EXTI_PR_PR20_Pos (20U) 1860 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 1861 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit 20 */ 1862 1863 /* References Defines */ 1864 #define EXTI_PR_PIF0 EXTI_PR_PR0 1865 #define EXTI_PR_PIF1 EXTI_PR_PR1 1866 #define EXTI_PR_PIF2 EXTI_PR_PR2 1867 #define EXTI_PR_PIF3 EXTI_PR_PR3 1868 #define EXTI_PR_PIF4 EXTI_PR_PR4 1869 #define EXTI_PR_PIF5 EXTI_PR_PR5 1870 #define EXTI_PR_PIF6 EXTI_PR_PR6 1871 #define EXTI_PR_PIF7 EXTI_PR_PR7 1872 #define EXTI_PR_PIF8 EXTI_PR_PR8 1873 #define EXTI_PR_PIF9 EXTI_PR_PR9 1874 #define EXTI_PR_PIF10 EXTI_PR_PR10 1875 #define EXTI_PR_PIF11 EXTI_PR_PR11 1876 #define EXTI_PR_PIF12 EXTI_PR_PR12 1877 #define EXTI_PR_PIF13 EXTI_PR_PR13 1878 #define EXTI_PR_PIF14 EXTI_PR_PR14 1879 #define EXTI_PR_PIF15 EXTI_PR_PR15 1880 #define EXTI_PR_PIF16 EXTI_PR_PR16 1881 #define EXTI_PR_PIF17 EXTI_PR_PR17 1882 #define EXTI_PR_PIF19 EXTI_PR_PR19 1883 #define EXTI_PR_PIF20 EXTI_PR_PR20 1884 1885 /******************************************************************************/ 1886 /* */ 1887 /* FLASH and Option Bytes Registers */ 1888 /* */ 1889 /******************************************************************************/ 1890 1891 /******************* Bit definition for FLASH_ACR register ******************/ 1892 #define FLASH_ACR_LATENCY_Pos (0U) 1893 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 1894 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 1895 1896 #define FLASH_ACR_PRFTBE_Pos (4U) 1897 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 1898 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 1899 #define FLASH_ACR_PRFTBS_Pos (5U) 1900 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 1901 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 1902 1903 /****************** Bit definition for FLASH_KEYR register ******************/ 1904 #define FLASH_KEYR_FKEYR_Pos (0U) 1905 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 1906 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 1907 1908 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 1909 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 1910 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 1911 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 1912 1913 /****************** FLASH Keys **********************************************/ 1914 #define FLASH_KEY1_Pos (0U) 1915 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 1916 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */ 1917 #define FLASH_KEY2_Pos (0U) 1918 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 1919 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1 1920 to unlock the write access to the FPEC. */ 1921 1922 #define FLASH_OPTKEY1_Pos (0U) 1923 #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */ 1924 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */ 1925 #define FLASH_OPTKEY2_Pos (0U) 1926 #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */ 1927 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to 1928 unlock the write access to the option byte block */ 1929 1930 /****************** Bit definition for FLASH_SR register *******************/ 1931 #define FLASH_SR_BSY_Pos (0U) 1932 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 1933 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 1934 #define FLASH_SR_PGERR_Pos (2U) 1935 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 1936 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 1937 #define FLASH_SR_WRPRTERR_Pos (4U) 1938 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 1939 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 1940 #define FLASH_SR_EOP_Pos (5U) 1941 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 1942 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 1943 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ 1944 1945 /******************* Bit definition for FLASH_CR register *******************/ 1946 #define FLASH_CR_PG_Pos (0U) 1947 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 1948 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 1949 #define FLASH_CR_PER_Pos (1U) 1950 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 1951 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 1952 #define FLASH_CR_MER_Pos (2U) 1953 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 1954 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 1955 #define FLASH_CR_OPTPG_Pos (4U) 1956 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 1957 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 1958 #define FLASH_CR_OPTER_Pos (5U) 1959 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 1960 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 1961 #define FLASH_CR_STRT_Pos (6U) 1962 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 1963 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 1964 #define FLASH_CR_LOCK_Pos (7U) 1965 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 1966 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 1967 #define FLASH_CR_OPTWRE_Pos (9U) 1968 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 1969 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 1970 #define FLASH_CR_ERRIE_Pos (10U) 1971 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 1972 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 1973 #define FLASH_CR_EOPIE_Pos (12U) 1974 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 1975 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 1976 #define FLASH_CR_OBL_LAUNCH_Pos (13U) 1977 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */ 1978 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */ 1979 1980 /******************* Bit definition for FLASH_AR register *******************/ 1981 #define FLASH_AR_FAR_Pos (0U) 1982 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 1983 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 1984 1985 /****************** Bit definition for FLASH_OBR register *******************/ 1986 #define FLASH_OBR_OPTERR_Pos (0U) 1987 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 1988 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 1989 #define FLASH_OBR_RDPRT1_Pos (1U) 1990 #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */ 1991 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */ 1992 #define FLASH_OBR_RDPRT2_Pos (2U) 1993 #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */ 1994 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */ 1995 1996 #define FLASH_OBR_USER_Pos (8U) 1997 #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos) /*!< 0x00007700 */ 1998 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 1999 #define FLASH_OBR_IWDG_SW_Pos (8U) 2000 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */ 2001 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 2002 #define FLASH_OBR_nRST_STOP_Pos (9U) 2003 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */ 2004 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 2005 #define FLASH_OBR_nRST_STDBY_Pos (10U) 2006 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */ 2007 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2008 #define FLASH_OBR_nBOOT1_Pos (12U) 2009 #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */ 2010 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */ 2011 #define FLASH_OBR_VDDA_MONITOR_Pos (13U) 2012 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */ 2013 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */ 2014 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U) 2015 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */ 2016 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */ 2017 #define FLASH_OBR_DATA0_Pos (16U) 2018 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */ 2019 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 2020 #define FLASH_OBR_DATA1_Pos (24U) 2021 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */ 2022 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 2023 2024 /* Old BOOT1 bit definition, maintained for legacy purpose */ 2025 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 2026 2027 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ 2028 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR 2029 2030 /****************** Bit definition for FLASH_WRPR register ******************/ 2031 #define FLASH_WRPR_WRP_Pos (0U) 2032 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 2033 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 2034 2035 /*----------------------------------------------------------------------------*/ 2036 2037 /****************** Bit definition for OB_RDP register **********************/ 2038 #define OB_RDP_RDP_Pos (0U) 2039 #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos) /*!< 0x000000FF */ 2040 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */ 2041 #define OB_RDP_nRDP_Pos (8U) 2042 #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 2043 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 2044 2045 /****************** Bit definition for OB_USER register *********************/ 2046 #define OB_USER_USER_Pos (16U) 2047 #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos) /*!< 0x00FF0000 */ 2048 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */ 2049 #define OB_USER_nUSER_Pos (24U) 2050 #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos) /*!< 0xFF000000 */ 2051 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */ 2052 2053 /****************** Bit definition for OB_WRP0 register *********************/ 2054 #define OB_WRP0_WRP0_Pos (0U) 2055 #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */ 2056 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 2057 #define OB_WRP0_nWRP0_Pos (8U) 2058 #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 2059 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 2060 2061 /****************** Bit definition for OB_WRP1 register *********************/ 2062 #define OB_WRP1_WRP1_Pos (16U) 2063 #define OB_WRP1_WRP1_Msk (0xFFUL << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 2064 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 2065 #define OB_WRP1_nWRP1_Pos (24U) 2066 #define OB_WRP1_nWRP1_Msk (0xFFUL << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 2067 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 2068 2069 /****************** Bit definition for OB_WRP2 register *********************/ 2070 #define OB_WRP2_WRP2_Pos (0U) 2071 #define OB_WRP2_WRP2_Msk (0xFFUL << OB_WRP2_WRP2_Pos) /*!< 0x000000FF */ 2072 #define OB_WRP2_WRP2 OB_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ 2073 #define OB_WRP2_nWRP2_Pos (8U) 2074 #define OB_WRP2_nWRP2_Msk (0xFFUL << OB_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ 2075 #define OB_WRP2_nWRP2 OB_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ 2076 2077 /****************** Bit definition for OB_WRP3 register *********************/ 2078 #define OB_WRP3_WRP3_Pos (16U) 2079 #define OB_WRP3_WRP3_Msk (0xFFUL << OB_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ 2080 #define OB_WRP3_WRP3 OB_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ 2081 #define OB_WRP3_nWRP3_Pos (24U) 2082 #define OB_WRP3_nWRP3_Msk (0xFFUL << OB_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ 2083 #define OB_WRP3_nWRP3 OB_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ 2084 2085 /******************************************************************************/ 2086 /* */ 2087 /* General Purpose IOs (GPIO) */ 2088 /* */ 2089 /******************************************************************************/ 2090 /******************* Bit definition for GPIO_MODER register *****************/ 2091 #define GPIO_MODER_MODER0_Pos (0U) 2092 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 2093 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 2094 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 2095 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 2096 #define GPIO_MODER_MODER1_Pos (2U) 2097 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 2098 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 2099 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 2100 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 2101 #define GPIO_MODER_MODER2_Pos (4U) 2102 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 2103 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 2104 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 2105 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 2106 #define GPIO_MODER_MODER3_Pos (6U) 2107 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 2108 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 2109 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 2110 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 2111 #define GPIO_MODER_MODER4_Pos (8U) 2112 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 2113 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 2114 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 2115 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 2116 #define GPIO_MODER_MODER5_Pos (10U) 2117 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 2118 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 2119 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 2120 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 2121 #define GPIO_MODER_MODER6_Pos (12U) 2122 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 2123 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 2124 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 2125 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 2126 #define GPIO_MODER_MODER7_Pos (14U) 2127 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 2128 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 2129 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 2130 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 2131 #define GPIO_MODER_MODER8_Pos (16U) 2132 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 2133 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 2134 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 2135 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 2136 #define GPIO_MODER_MODER9_Pos (18U) 2137 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 2138 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 2139 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 2140 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 2141 #define GPIO_MODER_MODER10_Pos (20U) 2142 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 2143 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 2144 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 2145 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 2146 #define GPIO_MODER_MODER11_Pos (22U) 2147 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 2148 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 2149 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 2150 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 2151 #define GPIO_MODER_MODER12_Pos (24U) 2152 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 2153 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 2154 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 2155 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 2156 #define GPIO_MODER_MODER13_Pos (26U) 2157 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 2158 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 2159 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 2160 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 2161 #define GPIO_MODER_MODER14_Pos (28U) 2162 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 2163 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 2164 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 2165 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 2166 #define GPIO_MODER_MODER15_Pos (30U) 2167 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 2168 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 2169 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 2170 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 2171 2172 /****************** Bit definition for GPIO_OTYPER register *****************/ 2173 #define GPIO_OTYPER_OT_0 (0x00000001U) 2174 #define GPIO_OTYPER_OT_1 (0x00000002U) 2175 #define GPIO_OTYPER_OT_2 (0x00000004U) 2176 #define GPIO_OTYPER_OT_3 (0x00000008U) 2177 #define GPIO_OTYPER_OT_4 (0x00000010U) 2178 #define GPIO_OTYPER_OT_5 (0x00000020U) 2179 #define GPIO_OTYPER_OT_6 (0x00000040U) 2180 #define GPIO_OTYPER_OT_7 (0x00000080U) 2181 #define GPIO_OTYPER_OT_8 (0x00000100U) 2182 #define GPIO_OTYPER_OT_9 (0x00000200U) 2183 #define GPIO_OTYPER_OT_10 (0x00000400U) 2184 #define GPIO_OTYPER_OT_11 (0x00000800U) 2185 #define GPIO_OTYPER_OT_12 (0x00001000U) 2186 #define GPIO_OTYPER_OT_13 (0x00002000U) 2187 #define GPIO_OTYPER_OT_14 (0x00004000U) 2188 #define GPIO_OTYPER_OT_15 (0x00008000U) 2189 2190 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 2191 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U) 2192 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */ 2193 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk 2194 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */ 2195 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */ 2196 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U) 2197 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */ 2198 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk 2199 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */ 2200 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */ 2201 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U) 2202 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */ 2203 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk 2204 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */ 2205 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */ 2206 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U) 2207 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */ 2208 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk 2209 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */ 2210 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */ 2211 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U) 2212 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */ 2213 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk 2214 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */ 2215 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */ 2216 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U) 2217 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */ 2218 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk 2219 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */ 2220 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */ 2221 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U) 2222 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */ 2223 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk 2224 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */ 2225 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */ 2226 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U) 2227 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */ 2228 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk 2229 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */ 2230 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */ 2231 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U) 2232 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */ 2233 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk 2234 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */ 2235 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */ 2236 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U) 2237 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */ 2238 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk 2239 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */ 2240 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */ 2241 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U) 2242 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */ 2243 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk 2244 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */ 2245 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */ 2246 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U) 2247 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */ 2248 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk 2249 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */ 2250 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */ 2251 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U) 2252 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */ 2253 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk 2254 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */ 2255 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */ 2256 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U) 2257 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */ 2258 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk 2259 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */ 2260 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */ 2261 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U) 2262 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */ 2263 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk 2264 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */ 2265 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */ 2266 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U) 2267 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */ 2268 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk 2269 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */ 2270 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */ 2271 2272 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ 2273 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 2274 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 2275 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 2276 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 2277 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 2278 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 2279 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 2280 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 2281 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 2282 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 2283 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 2284 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 2285 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 2286 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 2287 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 2288 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 2289 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 2290 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 2291 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 2292 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 2293 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 2294 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 2295 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 2296 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 2297 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 2298 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 2299 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 2300 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 2301 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 2302 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 2303 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 2304 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 2305 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 2306 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 2307 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 2308 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 2309 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 2310 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 2311 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 2312 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 2313 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 2314 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 2315 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 2316 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 2317 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 2318 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 2319 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 2320 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 2321 2322 /******************* Bit definition for GPIO_PUPDR register ******************/ 2323 #define GPIO_PUPDR_PUPDR0_Pos (0U) 2324 #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 2325 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 2326 #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 2327 #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 2328 #define GPIO_PUPDR_PUPDR1_Pos (2U) 2329 #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 2330 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 2331 #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 2332 #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 2333 #define GPIO_PUPDR_PUPDR2_Pos (4U) 2334 #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 2335 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 2336 #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 2337 #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 2338 #define GPIO_PUPDR_PUPDR3_Pos (6U) 2339 #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 2340 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 2341 #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 2342 #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 2343 #define GPIO_PUPDR_PUPDR4_Pos (8U) 2344 #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 2345 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 2346 #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 2347 #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 2348 #define GPIO_PUPDR_PUPDR5_Pos (10U) 2349 #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 2350 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 2351 #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 2352 #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 2353 #define GPIO_PUPDR_PUPDR6_Pos (12U) 2354 #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 2355 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 2356 #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 2357 #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 2358 #define GPIO_PUPDR_PUPDR7_Pos (14U) 2359 #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 2360 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 2361 #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 2362 #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 2363 #define GPIO_PUPDR_PUPDR8_Pos (16U) 2364 #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 2365 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 2366 #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 2367 #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 2368 #define GPIO_PUPDR_PUPDR9_Pos (18U) 2369 #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 2370 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 2371 #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 2372 #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 2373 #define GPIO_PUPDR_PUPDR10_Pos (20U) 2374 #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 2375 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 2376 #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 2377 #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 2378 #define GPIO_PUPDR_PUPDR11_Pos (22U) 2379 #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 2380 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 2381 #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 2382 #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 2383 #define GPIO_PUPDR_PUPDR12_Pos (24U) 2384 #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 2385 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 2386 #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 2387 #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 2388 #define GPIO_PUPDR_PUPDR13_Pos (26U) 2389 #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 2390 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 2391 #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 2392 #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 2393 #define GPIO_PUPDR_PUPDR14_Pos (28U) 2394 #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 2395 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 2396 #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 2397 #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 2398 #define GPIO_PUPDR_PUPDR15_Pos (30U) 2399 #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 2400 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 2401 #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 2402 #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 2403 2404 /******************* Bit definition for GPIO_IDR register *******************/ 2405 #define GPIO_IDR_0 (0x00000001U) 2406 #define GPIO_IDR_1 (0x00000002U) 2407 #define GPIO_IDR_2 (0x00000004U) 2408 #define GPIO_IDR_3 (0x00000008U) 2409 #define GPIO_IDR_4 (0x00000010U) 2410 #define GPIO_IDR_5 (0x00000020U) 2411 #define GPIO_IDR_6 (0x00000040U) 2412 #define GPIO_IDR_7 (0x00000080U) 2413 #define GPIO_IDR_8 (0x00000100U) 2414 #define GPIO_IDR_9 (0x00000200U) 2415 #define GPIO_IDR_10 (0x00000400U) 2416 #define GPIO_IDR_11 (0x00000800U) 2417 #define GPIO_IDR_12 (0x00001000U) 2418 #define GPIO_IDR_13 (0x00002000U) 2419 #define GPIO_IDR_14 (0x00004000U) 2420 #define GPIO_IDR_15 (0x00008000U) 2421 2422 /****************** Bit definition for GPIO_ODR register ********************/ 2423 #define GPIO_ODR_0 (0x00000001U) 2424 #define GPIO_ODR_1 (0x00000002U) 2425 #define GPIO_ODR_2 (0x00000004U) 2426 #define GPIO_ODR_3 (0x00000008U) 2427 #define GPIO_ODR_4 (0x00000010U) 2428 #define GPIO_ODR_5 (0x00000020U) 2429 #define GPIO_ODR_6 (0x00000040U) 2430 #define GPIO_ODR_7 (0x00000080U) 2431 #define GPIO_ODR_8 (0x00000100U) 2432 #define GPIO_ODR_9 (0x00000200U) 2433 #define GPIO_ODR_10 (0x00000400U) 2434 #define GPIO_ODR_11 (0x00000800U) 2435 #define GPIO_ODR_12 (0x00001000U) 2436 #define GPIO_ODR_13 (0x00002000U) 2437 #define GPIO_ODR_14 (0x00004000U) 2438 #define GPIO_ODR_15 (0x00008000U) 2439 2440 /****************** Bit definition for GPIO_BSRR register ********************/ 2441 #define GPIO_BSRR_BS_0 (0x00000001U) 2442 #define GPIO_BSRR_BS_1 (0x00000002U) 2443 #define GPIO_BSRR_BS_2 (0x00000004U) 2444 #define GPIO_BSRR_BS_3 (0x00000008U) 2445 #define GPIO_BSRR_BS_4 (0x00000010U) 2446 #define GPIO_BSRR_BS_5 (0x00000020U) 2447 #define GPIO_BSRR_BS_6 (0x00000040U) 2448 #define GPIO_BSRR_BS_7 (0x00000080U) 2449 #define GPIO_BSRR_BS_8 (0x00000100U) 2450 #define GPIO_BSRR_BS_9 (0x00000200U) 2451 #define GPIO_BSRR_BS_10 (0x00000400U) 2452 #define GPIO_BSRR_BS_11 (0x00000800U) 2453 #define GPIO_BSRR_BS_12 (0x00001000U) 2454 #define GPIO_BSRR_BS_13 (0x00002000U) 2455 #define GPIO_BSRR_BS_14 (0x00004000U) 2456 #define GPIO_BSRR_BS_15 (0x00008000U) 2457 #define GPIO_BSRR_BR_0 (0x00010000U) 2458 #define GPIO_BSRR_BR_1 (0x00020000U) 2459 #define GPIO_BSRR_BR_2 (0x00040000U) 2460 #define GPIO_BSRR_BR_3 (0x00080000U) 2461 #define GPIO_BSRR_BR_4 (0x00100000U) 2462 #define GPIO_BSRR_BR_5 (0x00200000U) 2463 #define GPIO_BSRR_BR_6 (0x00400000U) 2464 #define GPIO_BSRR_BR_7 (0x00800000U) 2465 #define GPIO_BSRR_BR_8 (0x01000000U) 2466 #define GPIO_BSRR_BR_9 (0x02000000U) 2467 #define GPIO_BSRR_BR_10 (0x04000000U) 2468 #define GPIO_BSRR_BR_11 (0x08000000U) 2469 #define GPIO_BSRR_BR_12 (0x10000000U) 2470 #define GPIO_BSRR_BR_13 (0x20000000U) 2471 #define GPIO_BSRR_BR_14 (0x40000000U) 2472 #define GPIO_BSRR_BR_15 (0x80000000U) 2473 2474 /****************** Bit definition for GPIO_LCKR register ********************/ 2475 #define GPIO_LCKR_LCK0_Pos (0U) 2476 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2477 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2478 #define GPIO_LCKR_LCK1_Pos (1U) 2479 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2480 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2481 #define GPIO_LCKR_LCK2_Pos (2U) 2482 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2483 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2484 #define GPIO_LCKR_LCK3_Pos (3U) 2485 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2486 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2487 #define GPIO_LCKR_LCK4_Pos (4U) 2488 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2489 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2490 #define GPIO_LCKR_LCK5_Pos (5U) 2491 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2492 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2493 #define GPIO_LCKR_LCK6_Pos (6U) 2494 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2495 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2496 #define GPIO_LCKR_LCK7_Pos (7U) 2497 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2498 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2499 #define GPIO_LCKR_LCK8_Pos (8U) 2500 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2501 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2502 #define GPIO_LCKR_LCK9_Pos (9U) 2503 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2504 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2505 #define GPIO_LCKR_LCK10_Pos (10U) 2506 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2507 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2508 #define GPIO_LCKR_LCK11_Pos (11U) 2509 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2510 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2511 #define GPIO_LCKR_LCK12_Pos (12U) 2512 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2513 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2514 #define GPIO_LCKR_LCK13_Pos (13U) 2515 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2516 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2517 #define GPIO_LCKR_LCK14_Pos (14U) 2518 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2519 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2520 #define GPIO_LCKR_LCK15_Pos (15U) 2521 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2522 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2523 #define GPIO_LCKR_LCKK_Pos (16U) 2524 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2525 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2526 2527 /****************** Bit definition for GPIO_AFRL register ********************/ 2528 #define GPIO_AFRL_AFSEL0_Pos (0U) 2529 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 2530 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 2531 #define GPIO_AFRL_AFSEL1_Pos (4U) 2532 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 2533 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 2534 #define GPIO_AFRL_AFSEL2_Pos (8U) 2535 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 2536 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 2537 #define GPIO_AFRL_AFSEL3_Pos (12U) 2538 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 2539 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 2540 #define GPIO_AFRL_AFSEL4_Pos (16U) 2541 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 2542 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 2543 #define GPIO_AFRL_AFSEL5_Pos (20U) 2544 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 2545 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 2546 #define GPIO_AFRL_AFSEL6_Pos (24U) 2547 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 2548 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 2549 #define GPIO_AFRL_AFSEL7_Pos (28U) 2550 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 2551 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 2552 2553 /* Legacy aliases */ 2554 #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos 2555 #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk 2556 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 2557 #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos 2558 #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk 2559 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 2560 #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos 2561 #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk 2562 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 2563 #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos 2564 #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk 2565 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 2566 #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos 2567 #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk 2568 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 2569 #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos 2570 #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk 2571 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 2572 #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos 2573 #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk 2574 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 2575 #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos 2576 #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk 2577 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 2578 2579 /****************** Bit definition for GPIO_AFRH register ********************/ 2580 #define GPIO_AFRH_AFSEL8_Pos (0U) 2581 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 2582 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 2583 #define GPIO_AFRH_AFSEL9_Pos (4U) 2584 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 2585 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 2586 #define GPIO_AFRH_AFSEL10_Pos (8U) 2587 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 2588 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 2589 #define GPIO_AFRH_AFSEL11_Pos (12U) 2590 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 2591 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 2592 #define GPIO_AFRH_AFSEL12_Pos (16U) 2593 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 2594 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 2595 #define GPIO_AFRH_AFSEL13_Pos (20U) 2596 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 2597 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 2598 #define GPIO_AFRH_AFSEL14_Pos (24U) 2599 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 2600 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 2601 #define GPIO_AFRH_AFSEL15_Pos (28U) 2602 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 2603 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 2604 2605 /* Legacy aliases */ 2606 #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos 2607 #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk 2608 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 2609 #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos 2610 #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk 2611 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 2612 #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos 2613 #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk 2614 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 2615 #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos 2616 #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk 2617 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 2618 #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos 2619 #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk 2620 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 2621 #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos 2622 #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk 2623 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 2624 #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos 2625 #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk 2626 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 2627 #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos 2628 #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk 2629 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 2630 2631 /****************** Bit definition for GPIO_BRR register *********************/ 2632 #define GPIO_BRR_BR_0 (0x00000001U) 2633 #define GPIO_BRR_BR_1 (0x00000002U) 2634 #define GPIO_BRR_BR_2 (0x00000004U) 2635 #define GPIO_BRR_BR_3 (0x00000008U) 2636 #define GPIO_BRR_BR_4 (0x00000010U) 2637 #define GPIO_BRR_BR_5 (0x00000020U) 2638 #define GPIO_BRR_BR_6 (0x00000040U) 2639 #define GPIO_BRR_BR_7 (0x00000080U) 2640 #define GPIO_BRR_BR_8 (0x00000100U) 2641 #define GPIO_BRR_BR_9 (0x00000200U) 2642 #define GPIO_BRR_BR_10 (0x00000400U) 2643 #define GPIO_BRR_BR_11 (0x00000800U) 2644 #define GPIO_BRR_BR_12 (0x00001000U) 2645 #define GPIO_BRR_BR_13 (0x00002000U) 2646 #define GPIO_BRR_BR_14 (0x00004000U) 2647 #define GPIO_BRR_BR_15 (0x00008000U) 2648 2649 /******************************************************************************/ 2650 /* */ 2651 /* Inter-integrated Circuit Interface (I2C) */ 2652 /* */ 2653 /******************************************************************************/ 2654 2655 /******************* Bit definition for I2C_CR1 register *******************/ 2656 #define I2C_CR1_PE_Pos (0U) 2657 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2658 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2659 #define I2C_CR1_TXIE_Pos (1U) 2660 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2661 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2662 #define I2C_CR1_RXIE_Pos (2U) 2663 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2664 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2665 #define I2C_CR1_ADDRIE_Pos (3U) 2666 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2667 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2668 #define I2C_CR1_NACKIE_Pos (4U) 2669 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2670 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2671 #define I2C_CR1_STOPIE_Pos (5U) 2672 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2673 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2674 #define I2C_CR1_TCIE_Pos (6U) 2675 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2676 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2677 #define I2C_CR1_ERRIE_Pos (7U) 2678 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2679 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2680 #define I2C_CR1_DNF_Pos (8U) 2681 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2682 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2683 #define I2C_CR1_ANFOFF_Pos (12U) 2684 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2685 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2686 #define I2C_CR1_SWRST_Pos (13U) 2687 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 2688 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 2689 #define I2C_CR1_TXDMAEN_Pos (14U) 2690 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2691 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2692 #define I2C_CR1_RXDMAEN_Pos (15U) 2693 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2694 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2695 #define I2C_CR1_SBC_Pos (16U) 2696 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2697 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2698 #define I2C_CR1_NOSTRETCH_Pos (17U) 2699 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2700 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2701 #define I2C_CR1_GCEN_Pos (19U) 2702 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2703 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2704 #define I2C_CR1_SMBHEN_Pos (20U) 2705 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2706 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2707 #define I2C_CR1_SMBDEN_Pos (21U) 2708 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2709 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2710 #define I2C_CR1_ALERTEN_Pos (22U) 2711 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2712 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2713 #define I2C_CR1_PECEN_Pos (23U) 2714 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2715 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2716 2717 /****************** Bit definition for I2C_CR2 register ********************/ 2718 #define I2C_CR2_SADD_Pos (0U) 2719 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2720 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2721 #define I2C_CR2_RD_WRN_Pos (10U) 2722 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2723 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2724 #define I2C_CR2_ADD10_Pos (11U) 2725 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2726 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2727 #define I2C_CR2_HEAD10R_Pos (12U) 2728 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2729 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2730 #define I2C_CR2_START_Pos (13U) 2731 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2732 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 2733 #define I2C_CR2_STOP_Pos (14U) 2734 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 2735 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 2736 #define I2C_CR2_NACK_Pos (15U) 2737 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 2738 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 2739 #define I2C_CR2_NBYTES_Pos (16U) 2740 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 2741 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 2742 #define I2C_CR2_RELOAD_Pos (24U) 2743 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 2744 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 2745 #define I2C_CR2_AUTOEND_Pos (25U) 2746 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 2747 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 2748 #define I2C_CR2_PECBYTE_Pos (26U) 2749 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 2750 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 2751 2752 /******************* Bit definition for I2C_OAR1 register ******************/ 2753 #define I2C_OAR1_OA1_Pos (0U) 2754 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 2755 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 2756 #define I2C_OAR1_OA1MODE_Pos (10U) 2757 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 2758 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 2759 #define I2C_OAR1_OA1EN_Pos (15U) 2760 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 2761 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 2762 2763 /******************* Bit definition for I2C_OAR2 register ******************/ 2764 #define I2C_OAR2_OA2_Pos (1U) 2765 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 2766 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 2767 #define I2C_OAR2_OA2MSK_Pos (8U) 2768 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 2769 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 2770 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 2771 #define I2C_OAR2_OA2MASK01_Pos (8U) 2772 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 2773 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 2774 #define I2C_OAR2_OA2MASK02_Pos (9U) 2775 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 2776 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 2777 #define I2C_OAR2_OA2MASK03_Pos (8U) 2778 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 2779 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 2780 #define I2C_OAR2_OA2MASK04_Pos (10U) 2781 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 2782 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 2783 #define I2C_OAR2_OA2MASK05_Pos (8U) 2784 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 2785 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 2786 #define I2C_OAR2_OA2MASK06_Pos (9U) 2787 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 2788 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 2789 #define I2C_OAR2_OA2MASK07_Pos (8U) 2790 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 2791 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 2792 #define I2C_OAR2_OA2EN_Pos (15U) 2793 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 2794 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 2795 2796 /******************* Bit definition for I2C_TIMINGR register ****************/ 2797 #define I2C_TIMINGR_SCLL_Pos (0U) 2798 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 2799 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 2800 #define I2C_TIMINGR_SCLH_Pos (8U) 2801 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 2802 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 2803 #define I2C_TIMINGR_SDADEL_Pos (16U) 2804 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 2805 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 2806 #define I2C_TIMINGR_SCLDEL_Pos (20U) 2807 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 2808 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 2809 #define I2C_TIMINGR_PRESC_Pos (28U) 2810 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 2811 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 2812 2813 /******************* Bit definition for I2C_TIMEOUTR register ****************/ 2814 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 2815 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 2816 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 2817 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 2818 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 2819 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 2820 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 2821 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 2822 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 2823 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 2824 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 2825 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 2826 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 2827 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 2828 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 2829 2830 /****************** Bit definition for I2C_ISR register ********************/ 2831 #define I2C_ISR_TXE_Pos (0U) 2832 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 2833 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 2834 #define I2C_ISR_TXIS_Pos (1U) 2835 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 2836 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 2837 #define I2C_ISR_RXNE_Pos (2U) 2838 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 2839 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 2840 #define I2C_ISR_ADDR_Pos (3U) 2841 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 2842 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 2843 #define I2C_ISR_NACKF_Pos (4U) 2844 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 2845 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 2846 #define I2C_ISR_STOPF_Pos (5U) 2847 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 2848 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 2849 #define I2C_ISR_TC_Pos (6U) 2850 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 2851 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 2852 #define I2C_ISR_TCR_Pos (7U) 2853 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 2854 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 2855 #define I2C_ISR_BERR_Pos (8U) 2856 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 2857 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 2858 #define I2C_ISR_ARLO_Pos (9U) 2859 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 2860 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 2861 #define I2C_ISR_OVR_Pos (10U) 2862 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 2863 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 2864 #define I2C_ISR_PECERR_Pos (11U) 2865 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 2866 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 2867 #define I2C_ISR_TIMEOUT_Pos (12U) 2868 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 2869 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 2870 #define I2C_ISR_ALERT_Pos (13U) 2871 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 2872 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 2873 #define I2C_ISR_BUSY_Pos (15U) 2874 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 2875 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 2876 #define I2C_ISR_DIR_Pos (16U) 2877 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 2878 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 2879 #define I2C_ISR_ADDCODE_Pos (17U) 2880 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 2881 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 2882 2883 /****************** Bit definition for I2C_ICR register ********************/ 2884 #define I2C_ICR_ADDRCF_Pos (3U) 2885 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 2886 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 2887 #define I2C_ICR_NACKCF_Pos (4U) 2888 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 2889 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 2890 #define I2C_ICR_STOPCF_Pos (5U) 2891 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 2892 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 2893 #define I2C_ICR_BERRCF_Pos (8U) 2894 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 2895 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 2896 #define I2C_ICR_ARLOCF_Pos (9U) 2897 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 2898 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 2899 #define I2C_ICR_OVRCF_Pos (10U) 2900 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 2901 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 2902 #define I2C_ICR_PECCF_Pos (11U) 2903 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 2904 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 2905 #define I2C_ICR_TIMOUTCF_Pos (12U) 2906 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 2907 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 2908 #define I2C_ICR_ALERTCF_Pos (13U) 2909 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 2910 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 2911 2912 /****************** Bit definition for I2C_PECR register *******************/ 2913 #define I2C_PECR_PEC_Pos (0U) 2914 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 2915 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 2916 2917 /****************** Bit definition for I2C_RXDR register *********************/ 2918 #define I2C_RXDR_RXDATA_Pos (0U) 2919 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 2920 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 2921 2922 /****************** Bit definition for I2C_TXDR register *******************/ 2923 #define I2C_TXDR_TXDATA_Pos (0U) 2924 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 2925 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 2926 2927 /*****************************************************************************/ 2928 /* */ 2929 /* Independent WATCHDOG (IWDG) */ 2930 /* */ 2931 /*****************************************************************************/ 2932 /******************* Bit definition for IWDG_KR register *******************/ 2933 #define IWDG_KR_KEY_Pos (0U) 2934 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 2935 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 2936 2937 /******************* Bit definition for IWDG_PR register *******************/ 2938 #define IWDG_PR_PR_Pos (0U) 2939 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 2940 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 2941 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */ 2942 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */ 2943 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */ 2944 2945 /******************* Bit definition for IWDG_RLR register ******************/ 2946 #define IWDG_RLR_RL_Pos (0U) 2947 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 2948 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 2949 2950 /******************* Bit definition for IWDG_SR register *******************/ 2951 #define IWDG_SR_PVU_Pos (0U) 2952 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 2953 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 2954 #define IWDG_SR_RVU_Pos (1U) 2955 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 2956 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 2957 #define IWDG_SR_WVU_Pos (2U) 2958 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 2959 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 2960 2961 /******************* Bit definition for IWDG_KR register *******************/ 2962 #define IWDG_WINR_WIN_Pos (0U) 2963 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 2964 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 2965 2966 /*****************************************************************************/ 2967 /* */ 2968 /* Power Control (PWR) */ 2969 /* */ 2970 /*****************************************************************************/ 2971 2972 /* Note: No specific macro feature on this device */ 2973 2974 2975 /******************** Bit definition for PWR_CR register *******************/ 2976 #define PWR_CR_LPDS_Pos (0U) 2977 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 2978 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */ 2979 #define PWR_CR_PDDS_Pos (1U) 2980 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 2981 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 2982 #define PWR_CR_CWUF_Pos (2U) 2983 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 2984 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 2985 #define PWR_CR_CSBF_Pos (3U) 2986 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 2987 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 2988 #define PWR_CR_DBP_Pos (8U) 2989 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 2990 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 2991 2992 /******************* Bit definition for PWR_CSR register *******************/ 2993 #define PWR_CSR_WUF_Pos (0U) 2994 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 2995 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 2996 #define PWR_CSR_SBF_Pos (1U) 2997 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 2998 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 2999 3000 #define PWR_CSR_EWUP1_Pos (8U) 3001 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3002 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3003 #define PWR_CSR_EWUP2_Pos (9U) 3004 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 3005 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3006 #define PWR_CSR_EWUP4_Pos (11U) 3007 #define PWR_CSR_EWUP4_Msk (0x1UL << PWR_CSR_EWUP4_Pos) /*!< 0x00000800 */ 3008 #define PWR_CSR_EWUP4 PWR_CSR_EWUP4_Msk /*!< Enable WKUP pin 4 */ 3009 #define PWR_CSR_EWUP5_Pos (12U) 3010 #define PWR_CSR_EWUP5_Msk (0x1UL << PWR_CSR_EWUP5_Pos) /*!< 0x00001000 */ 3011 #define PWR_CSR_EWUP5 PWR_CSR_EWUP5_Msk /*!< Enable WKUP pin 5 */ 3012 #define PWR_CSR_EWUP6_Pos (13U) 3013 #define PWR_CSR_EWUP6_Msk (0x1UL << PWR_CSR_EWUP6_Pos) /*!< 0x00002000 */ 3014 #define PWR_CSR_EWUP6 PWR_CSR_EWUP6_Msk /*!< Enable WKUP pin 6 */ 3015 #define PWR_CSR_EWUP7_Pos (14U) 3016 #define PWR_CSR_EWUP7_Msk (0x1UL << PWR_CSR_EWUP7_Pos) /*!< 0x00004000 */ 3017 #define PWR_CSR_EWUP7 PWR_CSR_EWUP7_Msk /*!< Enable WKUP pin 7 */ 3018 3019 /*****************************************************************************/ 3020 /* */ 3021 /* Reset and Clock Control */ 3022 /* */ 3023 /*****************************************************************************/ 3024 /* 3025 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3026 */ 3027 #define RCC_PLLSRC_PREDIV1_SUPPORT /*!< PREDIV support used as PLL source input */ 3028 3029 /******************** Bit definition for RCC_CR register *******************/ 3030 #define RCC_CR_HSION_Pos (0U) 3031 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3032 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3033 #define RCC_CR_HSIRDY_Pos (1U) 3034 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 3035 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3036 3037 #define RCC_CR_HSITRIM_Pos (3U) 3038 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 3039 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3040 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ 3041 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ 3042 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ 3043 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ 3044 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ 3045 3046 #define RCC_CR_HSICAL_Pos (8U) 3047 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 3048 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3049 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ 3050 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ 3051 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ 3052 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ 3053 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ 3054 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ 3055 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ 3056 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ 3057 3058 #define RCC_CR_HSEON_Pos (16U) 3059 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3060 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3061 #define RCC_CR_HSERDY_Pos (17U) 3062 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3063 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3064 #define RCC_CR_HSEBYP_Pos (18U) 3065 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3066 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3067 #define RCC_CR_CSSON_Pos (19U) 3068 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 3069 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 3070 #define RCC_CR_PLLON_Pos (24U) 3071 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3072 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3073 #define RCC_CR_PLLRDY_Pos (25U) 3074 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3075 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3076 3077 /******************** Bit definition for RCC_CFGR register *****************/ 3078 /*!< SW configuration */ 3079 #define RCC_CFGR_SW_Pos (0U) 3080 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3081 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3082 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3083 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3084 3085 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */ 3086 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */ 3087 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */ 3088 3089 /*!< SWS configuration */ 3090 #define RCC_CFGR_SWS_Pos (2U) 3091 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3092 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3093 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3094 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3095 3096 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */ 3097 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */ 3098 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */ 3099 3100 /*!< HPRE configuration */ 3101 #define RCC_CFGR_HPRE_Pos (4U) 3102 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3103 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3104 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3105 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3106 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3107 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3108 3109 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3110 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3111 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3112 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3113 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3114 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3115 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3116 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3117 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3118 3119 /*!< PPRE configuration */ 3120 #define RCC_CFGR_PPRE_Pos (8U) 3121 #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */ 3122 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */ 3123 #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */ 3124 #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */ 3125 #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */ 3126 3127 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */ 3128 #define RCC_CFGR_PPRE_DIV2_Pos (10U) 3129 #define RCC_CFGR_PPRE_DIV2_Msk (0x1UL << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */ 3130 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */ 3131 #define RCC_CFGR_PPRE_DIV4_Pos (8U) 3132 #define RCC_CFGR_PPRE_DIV4_Msk (0x5UL << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */ 3133 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */ 3134 #define RCC_CFGR_PPRE_DIV8_Pos (9U) 3135 #define RCC_CFGR_PPRE_DIV8_Msk (0x3UL << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */ 3136 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ 3137 #define RCC_CFGR_PPRE_DIV16_Pos (8U) 3138 #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ 3139 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ 3140 3141 #define RCC_CFGR_PLLSRC_Pos (15U) 3142 #define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */ 3143 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3144 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 3145 #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ 3146 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ 3147 3148 #define RCC_CFGR_PLLXTPRE_Pos (17U) 3149 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 3150 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 3151 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */ 3152 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ 3153 3154 /*!< PLLMUL configuration */ 3155 #define RCC_CFGR_PLLMUL_Pos (18U) 3156 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3157 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3158 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3159 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 3160 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 3161 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 3162 3163 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */ 3164 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */ 3165 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */ 3166 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */ 3167 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */ 3168 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */ 3169 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */ 3170 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */ 3171 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */ 3172 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */ 3173 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */ 3174 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */ 3175 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */ 3176 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */ 3177 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */ 3178 3179 /*!< MCO configuration */ 3180 #define RCC_CFGR_MCO_Pos (24U) 3181 #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ 3182 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 3183 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 3184 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 3185 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 3186 3187 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */ 3188 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */ 3189 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */ 3190 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */ 3191 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */ 3192 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */ 3193 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */ 3194 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */ 3195 3196 #define RCC_CFGR_MCOPRE_Pos (28U) 3197 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 3198 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 3199 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 3200 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 3201 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 3202 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 3203 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 3204 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */ 3205 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */ 3206 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */ 3207 3208 #define RCC_CFGR_PLLNODIV_Pos (31U) 3209 #define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */ 3210 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */ 3211 3212 /* Reference defines */ 3213 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 3214 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 3215 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 3216 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 3217 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 3218 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14 3219 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI 3220 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE 3221 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 3222 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 3223 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 3224 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL 3225 3226 /*!<****************** Bit definition for RCC_CIR register *****************/ 3227 #define RCC_CIR_LSIRDYF_Pos (0U) 3228 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 3229 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 3230 #define RCC_CIR_LSERDYF_Pos (1U) 3231 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 3232 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 3233 #define RCC_CIR_HSIRDYF_Pos (2U) 3234 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 3235 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 3236 #define RCC_CIR_HSERDYF_Pos (3U) 3237 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 3238 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 3239 #define RCC_CIR_PLLRDYF_Pos (4U) 3240 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 3241 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 3242 #define RCC_CIR_HSI14RDYF_Pos (5U) 3243 #define RCC_CIR_HSI14RDYF_Msk (0x1UL << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */ 3244 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */ 3245 #define RCC_CIR_CSSF_Pos (7U) 3246 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 3247 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 3248 #define RCC_CIR_LSIRDYIE_Pos (8U) 3249 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 3250 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 3251 #define RCC_CIR_LSERDYIE_Pos (9U) 3252 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 3253 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 3254 #define RCC_CIR_HSIRDYIE_Pos (10U) 3255 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 3256 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 3257 #define RCC_CIR_HSERDYIE_Pos (11U) 3258 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 3259 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 3260 #define RCC_CIR_PLLRDYIE_Pos (12U) 3261 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 3262 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 3263 #define RCC_CIR_HSI14RDYIE_Pos (13U) 3264 #define RCC_CIR_HSI14RDYIE_Msk (0x1UL << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */ 3265 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */ 3266 #define RCC_CIR_LSIRDYC_Pos (16U) 3267 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 3268 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 3269 #define RCC_CIR_LSERDYC_Pos (17U) 3270 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 3271 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 3272 #define RCC_CIR_HSIRDYC_Pos (18U) 3273 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 3274 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3275 #define RCC_CIR_HSERDYC_Pos (19U) 3276 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 3277 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3278 #define RCC_CIR_PLLRDYC_Pos (20U) 3279 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 3280 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3281 #define RCC_CIR_HSI14RDYC_Pos (21U) 3282 #define RCC_CIR_HSI14RDYC_Msk (0x1UL << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */ 3283 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */ 3284 #define RCC_CIR_CSSC_Pos (23U) 3285 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 3286 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 3287 3288 /***************** Bit definition for RCC_APB2RSTR register ****************/ 3289 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3290 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3291 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 3292 #define RCC_APB2RSTR_USART6RST_Pos (5U) 3293 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ 3294 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */ 3295 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3296 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3297 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */ 3298 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 3299 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 3300 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */ 3301 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3302 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3303 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 3304 #define RCC_APB2RSTR_USART1RST_Pos (14U) 3305 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 3306 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 3307 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 3308 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 3309 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */ 3310 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 3311 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 3312 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */ 3313 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 3314 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 3315 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */ 3316 #define RCC_APB2RSTR_DBGMCURST_Pos (22U) 3317 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */ 3318 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */ 3319 3320 /*!< Old ADC1 reset bit definition maintained for legacy purpose */ 3321 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST 3322 3323 /***************** Bit definition for RCC_APB1RSTR register ****************/ 3324 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 3325 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 3326 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 3327 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 3328 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 3329 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 3330 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 3331 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 3332 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 3333 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 3334 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ 3335 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */ 3336 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3337 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3338 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 3339 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 3340 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 3341 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 3342 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3343 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3344 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 3345 #define RCC_APB1RSTR_USART3RST_Pos (18U) 3346 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 3347 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 3348 #define RCC_APB1RSTR_USART4RST_Pos (19U) 3349 #define RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ 3350 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART 4 reset */ 3351 #define RCC_APB1RSTR_USART5RST_Pos (20U) 3352 #define RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ 3353 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART 5 reset */ 3354 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3355 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3356 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 3357 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 3358 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 3359 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 3360 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3361 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3362 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 3363 3364 /****************** Bit definition for RCC_AHBENR register *****************/ 3365 #define RCC_AHBENR_DMAEN_Pos (0U) 3366 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3367 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3368 #define RCC_AHBENR_SRAMEN_Pos (2U) 3369 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 3370 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 3371 #define RCC_AHBENR_FLITFEN_Pos (4U) 3372 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 3373 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 3374 #define RCC_AHBENR_CRCEN_Pos (6U) 3375 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 3376 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3377 #define RCC_AHBENR_GPIOAEN_Pos (17U) 3378 #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */ 3379 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */ 3380 #define RCC_AHBENR_GPIOBEN_Pos (18U) 3381 #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */ 3382 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */ 3383 #define RCC_AHBENR_GPIOCEN_Pos (19U) 3384 #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */ 3385 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */ 3386 #define RCC_AHBENR_GPIODEN_Pos (20U) 3387 #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */ 3388 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */ 3389 #define RCC_AHBENR_GPIOFEN_Pos (22U) 3390 #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */ 3391 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */ 3392 3393 /* Old Bit definition maintained for legacy purpose */ 3394 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3395 3396 /***************** Bit definition for RCC_APB2ENR register *****************/ 3397 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U) 3398 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */ 3399 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */ 3400 #define RCC_APB2ENR_USART6EN_Pos (5U) 3401 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ 3402 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 clock enable */ 3403 #define RCC_APB2ENR_ADCEN_Pos (9U) 3404 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3405 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3406 #define RCC_APB2ENR_TIM1EN_Pos (11U) 3407 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 3408 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */ 3409 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3410 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3411 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3412 #define RCC_APB2ENR_USART1EN_Pos (14U) 3413 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 3414 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 3415 #define RCC_APB2ENR_TIM15EN_Pos (16U) 3416 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 3417 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */ 3418 #define RCC_APB2ENR_TIM16EN_Pos (17U) 3419 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 3420 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */ 3421 #define RCC_APB2ENR_TIM17EN_Pos (18U) 3422 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 3423 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */ 3424 #define RCC_APB2ENR_DBGMCUEN_Pos (22U) 3425 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */ 3426 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */ 3427 3428 /* Old Bit definition maintained for legacy purpose */ 3429 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ 3430 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3431 3432 /***************** Bit definition for RCC_APB1ENR register *****************/ 3433 #define RCC_APB1ENR_TIM3EN_Pos (1U) 3434 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 3435 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 3436 #define RCC_APB1ENR_TIM6EN_Pos (4U) 3437 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 3438 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 3439 #define RCC_APB1ENR_TIM7EN_Pos (5U) 3440 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 3441 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 3442 #define RCC_APB1ENR_TIM14EN_Pos (8U) 3443 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ 3444 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */ 3445 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3446 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3447 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3448 #define RCC_APB1ENR_SPI2EN_Pos (14U) 3449 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 3450 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 3451 #define RCC_APB1ENR_USART2EN_Pos (17U) 3452 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3453 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3454 #define RCC_APB1ENR_USART3EN_Pos (18U) 3455 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 3456 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART3 clock enable */ 3457 #define RCC_APB1ENR_USART4EN_Pos (19U) 3458 #define RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */ 3459 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */ 3460 #define RCC_APB1ENR_USART5EN_Pos (20U) 3461 #define RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */ 3462 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */ 3463 #define RCC_APB1ENR_I2C1EN_Pos (21U) 3464 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 3465 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 3466 #define RCC_APB1ENR_I2C2EN_Pos (22U) 3467 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 3468 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ 3469 #define RCC_APB1ENR_PWREN_Pos (28U) 3470 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 3471 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 3472 3473 /******************* Bit definition for RCC_BDCR register ******************/ 3474 #define RCC_BDCR_LSEON_Pos (0U) 3475 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 3476 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 3477 #define RCC_BDCR_LSERDY_Pos (1U) 3478 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 3479 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 3480 #define RCC_BDCR_LSEBYP_Pos (2U) 3481 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 3482 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 3483 3484 #define RCC_BDCR_LSEDRV_Pos (3U) 3485 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 3486 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 3487 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 3488 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 3489 3490 #define RCC_BDCR_RTCSEL_Pos (8U) 3491 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 3492 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 3493 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 3494 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 3495 3496 /*!< RTC configuration */ 3497 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3498 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */ 3499 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */ 3500 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */ 3501 3502 #define RCC_BDCR_RTCEN_Pos (15U) 3503 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 3504 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 3505 #define RCC_BDCR_BDRST_Pos (16U) 3506 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 3507 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 3508 3509 /******************* Bit definition for RCC_CSR register *******************/ 3510 #define RCC_CSR_LSION_Pos (0U) 3511 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 3512 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 3513 #define RCC_CSR_LSIRDY_Pos (1U) 3514 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 3515 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 3516 #define RCC_CSR_V18PWRRSTF_Pos (23U) 3517 #define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */ 3518 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */ 3519 #define RCC_CSR_RMVF_Pos (24U) 3520 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 3521 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 3522 #define RCC_CSR_OBLRSTF_Pos (25U) 3523 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 3524 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 3525 #define RCC_CSR_PINRSTF_Pos (26U) 3526 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 3527 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 3528 #define RCC_CSR_PORRSTF_Pos (27U) 3529 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 3530 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 3531 #define RCC_CSR_SFTRSTF_Pos (28U) 3532 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 3533 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 3534 #define RCC_CSR_IWDGRSTF_Pos (29U) 3535 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 3536 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 3537 #define RCC_CSR_WWDGRSTF_Pos (30U) 3538 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 3539 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 3540 #define RCC_CSR_LPWRRSTF_Pos (31U) 3541 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 3542 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 3543 3544 /* Old Bit definition maintained for legacy purpose */ 3545 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 3546 3547 /******************* Bit definition for RCC_AHBRSTR register ***************/ 3548 #define RCC_AHBRSTR_GPIOARST_Pos (17U) 3549 #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */ 3550 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */ 3551 #define RCC_AHBRSTR_GPIOBRST_Pos (18U) 3552 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */ 3553 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */ 3554 #define RCC_AHBRSTR_GPIOCRST_Pos (19U) 3555 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */ 3556 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */ 3557 #define RCC_AHBRSTR_GPIODRST_Pos (20U) 3558 #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */ 3559 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */ 3560 #define RCC_AHBRSTR_GPIOFRST_Pos (22U) 3561 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */ 3562 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */ 3563 3564 /******************* Bit definition for RCC_CFGR2 register *****************/ 3565 /*!< PREDIV configuration */ 3566 #define RCC_CFGR2_PREDIV_Pos (0U) 3567 #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */ 3568 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */ 3569 #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */ 3570 #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */ 3571 #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */ 3572 #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */ 3573 3574 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */ 3575 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */ 3576 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */ 3577 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */ 3578 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */ 3579 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */ 3580 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */ 3581 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */ 3582 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */ 3583 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */ 3584 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */ 3585 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */ 3586 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */ 3587 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */ 3588 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */ 3589 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */ 3590 3591 /******************* Bit definition for RCC_CFGR3 register *****************/ 3592 /*!< USART1 Clock source selection */ 3593 #define RCC_CFGR3_USART1SW_Pos (0U) 3594 #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */ 3595 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */ 3596 #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */ 3597 #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */ 3598 3599 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */ 3600 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */ 3601 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */ 3602 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */ 3603 3604 /*!< I2C1 Clock source selection */ 3605 #define RCC_CFGR3_I2C1SW_Pos (4U) 3606 #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */ 3607 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */ 3608 3609 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */ 3610 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U) 3611 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */ 3612 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */ 3613 3614 /******************* Bit definition for RCC_CR2 register *******************/ 3615 #define RCC_CR2_HSI14ON_Pos (0U) 3616 #define RCC_CR2_HSI14ON_Msk (0x1UL << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */ 3617 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */ 3618 #define RCC_CR2_HSI14RDY_Pos (1U) 3619 #define RCC_CR2_HSI14RDY_Msk (0x1UL << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */ 3620 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */ 3621 #define RCC_CR2_HSI14DIS_Pos (2U) 3622 #define RCC_CR2_HSI14DIS_Msk (0x1UL << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */ 3623 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */ 3624 #define RCC_CR2_HSI14TRIM_Pos (3U) 3625 #define RCC_CR2_HSI14TRIM_Msk (0x1FUL << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */ 3626 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */ 3627 #define RCC_CR2_HSI14CAL_Pos (8U) 3628 #define RCC_CR2_HSI14CAL_Msk (0xFFUL << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */ 3629 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */ 3630 3631 /*****************************************************************************/ 3632 /* */ 3633 /* Real-Time Clock (RTC) */ 3634 /* */ 3635 /*****************************************************************************/ 3636 /* 3637 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 3638 */ 3639 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 3640 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 3641 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 3642 3643 /******************** Bits definition for RTC_TR register ******************/ 3644 #define RTC_TR_PM_Pos (22U) 3645 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 3646 #define RTC_TR_PM RTC_TR_PM_Msk 3647 #define RTC_TR_HT_Pos (20U) 3648 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 3649 #define RTC_TR_HT RTC_TR_HT_Msk 3650 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 3651 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 3652 #define RTC_TR_HU_Pos (16U) 3653 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 3654 #define RTC_TR_HU RTC_TR_HU_Msk 3655 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 3656 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 3657 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 3658 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 3659 #define RTC_TR_MNT_Pos (12U) 3660 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 3661 #define RTC_TR_MNT RTC_TR_MNT_Msk 3662 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 3663 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 3664 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 3665 #define RTC_TR_MNU_Pos (8U) 3666 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 3667 #define RTC_TR_MNU RTC_TR_MNU_Msk 3668 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 3669 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 3670 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 3671 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 3672 #define RTC_TR_ST_Pos (4U) 3673 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 3674 #define RTC_TR_ST RTC_TR_ST_Msk 3675 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 3676 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 3677 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 3678 #define RTC_TR_SU_Pos (0U) 3679 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 3680 #define RTC_TR_SU RTC_TR_SU_Msk 3681 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 3682 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 3683 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 3684 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 3685 3686 /******************** Bits definition for RTC_DR register ******************/ 3687 #define RTC_DR_YT_Pos (20U) 3688 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 3689 #define RTC_DR_YT RTC_DR_YT_Msk 3690 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 3691 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 3692 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 3693 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 3694 #define RTC_DR_YU_Pos (16U) 3695 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 3696 #define RTC_DR_YU RTC_DR_YU_Msk 3697 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 3698 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 3699 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 3700 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 3701 #define RTC_DR_WDU_Pos (13U) 3702 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 3703 #define RTC_DR_WDU RTC_DR_WDU_Msk 3704 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 3705 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 3706 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 3707 #define RTC_DR_MT_Pos (12U) 3708 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 3709 #define RTC_DR_MT RTC_DR_MT_Msk 3710 #define RTC_DR_MU_Pos (8U) 3711 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 3712 #define RTC_DR_MU RTC_DR_MU_Msk 3713 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 3714 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 3715 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 3716 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 3717 #define RTC_DR_DT_Pos (4U) 3718 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 3719 #define RTC_DR_DT RTC_DR_DT_Msk 3720 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 3721 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 3722 #define RTC_DR_DU_Pos (0U) 3723 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 3724 #define RTC_DR_DU RTC_DR_DU_Msk 3725 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 3726 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 3727 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 3728 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 3729 3730 /******************** Bits definition for RTC_CR register ******************/ 3731 #define RTC_CR_COE_Pos (23U) 3732 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 3733 #define RTC_CR_COE RTC_CR_COE_Msk 3734 #define RTC_CR_OSEL_Pos (21U) 3735 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 3736 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 3737 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 3738 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 3739 #define RTC_CR_POL_Pos (20U) 3740 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 3741 #define RTC_CR_POL RTC_CR_POL_Msk 3742 #define RTC_CR_COSEL_Pos (19U) 3743 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 3744 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 3745 #define RTC_CR_BKP_Pos (18U) 3746 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 3747 #define RTC_CR_BKP RTC_CR_BKP_Msk 3748 #define RTC_CR_SUB1H_Pos (17U) 3749 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 3750 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 3751 #define RTC_CR_ADD1H_Pos (16U) 3752 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 3753 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 3754 #define RTC_CR_TSIE_Pos (15U) 3755 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 3756 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 3757 #define RTC_CR_WUTIE_Pos (14U) 3758 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 3759 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 3760 #define RTC_CR_ALRAIE_Pos (12U) 3761 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 3762 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 3763 #define RTC_CR_TSE_Pos (11U) 3764 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 3765 #define RTC_CR_TSE RTC_CR_TSE_Msk 3766 #define RTC_CR_WUTE_Pos (10U) 3767 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 3768 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 3769 #define RTC_CR_ALRAE_Pos (8U) 3770 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 3771 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 3772 #define RTC_CR_FMT_Pos (6U) 3773 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 3774 #define RTC_CR_FMT RTC_CR_FMT_Msk 3775 #define RTC_CR_BYPSHAD_Pos (5U) 3776 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 3777 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 3778 #define RTC_CR_REFCKON_Pos (4U) 3779 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 3780 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 3781 #define RTC_CR_TSEDGE_Pos (3U) 3782 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 3783 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 3784 #define RTC_CR_WUCKSEL_Pos (0U) 3785 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 3786 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 3787 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 3788 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 3789 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 3790 3791 /* Legacy defines */ 3792 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 3793 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 3794 #define RTC_CR_BCK RTC_CR_BKP 3795 3796 /******************** Bits definition for RTC_ISR register *****************/ 3797 #define RTC_ISR_RECALPF_Pos (16U) 3798 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 3799 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 3800 #define RTC_ISR_TAMP2F_Pos (14U) 3801 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 3802 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 3803 #define RTC_ISR_TAMP1F_Pos (13U) 3804 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 3805 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 3806 #define RTC_ISR_TSOVF_Pos (12U) 3807 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 3808 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 3809 #define RTC_ISR_TSF_Pos (11U) 3810 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 3811 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 3812 #define RTC_ISR_WUTF_Pos (10U) 3813 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 3814 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 3815 #define RTC_ISR_ALRAF_Pos (8U) 3816 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 3817 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 3818 #define RTC_ISR_INIT_Pos (7U) 3819 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 3820 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 3821 #define RTC_ISR_INITF_Pos (6U) 3822 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 3823 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 3824 #define RTC_ISR_RSF_Pos (5U) 3825 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 3826 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 3827 #define RTC_ISR_INITS_Pos (4U) 3828 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 3829 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 3830 #define RTC_ISR_SHPF_Pos (3U) 3831 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 3832 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 3833 #define RTC_ISR_WUTWF_Pos (2U) 3834 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 3835 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 3836 #define RTC_ISR_ALRAWF_Pos (0U) 3837 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 3838 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 3839 3840 /******************** Bits definition for RTC_PRER register ****************/ 3841 #define RTC_PRER_PREDIV_A_Pos (16U) 3842 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 3843 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 3844 #define RTC_PRER_PREDIV_S_Pos (0U) 3845 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 3846 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 3847 3848 /******************** Bits definition for RTC_WUTR register ****************/ 3849 #define RTC_WUTR_WUT_Pos (0U) 3850 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 3851 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 3852 3853 /******************** Bits definition for RTC_ALRMAR register **************/ 3854 #define RTC_ALRMAR_MSK4_Pos (31U) 3855 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 3856 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 3857 #define RTC_ALRMAR_WDSEL_Pos (30U) 3858 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 3859 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 3860 #define RTC_ALRMAR_DT_Pos (28U) 3861 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 3862 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 3863 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 3864 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 3865 #define RTC_ALRMAR_DU_Pos (24U) 3866 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 3867 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 3868 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 3869 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 3870 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 3871 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 3872 #define RTC_ALRMAR_MSK3_Pos (23U) 3873 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 3874 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 3875 #define RTC_ALRMAR_PM_Pos (22U) 3876 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 3877 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 3878 #define RTC_ALRMAR_HT_Pos (20U) 3879 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 3880 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 3881 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 3882 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 3883 #define RTC_ALRMAR_HU_Pos (16U) 3884 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 3885 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 3886 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 3887 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 3888 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 3889 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 3890 #define RTC_ALRMAR_MSK2_Pos (15U) 3891 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 3892 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 3893 #define RTC_ALRMAR_MNT_Pos (12U) 3894 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 3895 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 3896 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 3897 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 3898 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 3899 #define RTC_ALRMAR_MNU_Pos (8U) 3900 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 3901 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 3902 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 3903 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 3904 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 3905 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 3906 #define RTC_ALRMAR_MSK1_Pos (7U) 3907 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 3908 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 3909 #define RTC_ALRMAR_ST_Pos (4U) 3910 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 3911 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 3912 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 3913 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 3914 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 3915 #define RTC_ALRMAR_SU_Pos (0U) 3916 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 3917 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 3918 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 3919 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 3920 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 3921 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 3922 3923 /******************** Bits definition for RTC_WPR register *****************/ 3924 #define RTC_WPR_KEY_Pos (0U) 3925 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 3926 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 3927 3928 /******************** Bits definition for RTC_SSR register *****************/ 3929 #define RTC_SSR_SS_Pos (0U) 3930 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 3931 #define RTC_SSR_SS RTC_SSR_SS_Msk 3932 3933 /******************** Bits definition for RTC_SHIFTR register **************/ 3934 #define RTC_SHIFTR_SUBFS_Pos (0U) 3935 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 3936 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 3937 #define RTC_SHIFTR_ADD1S_Pos (31U) 3938 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 3939 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 3940 3941 /******************** Bits definition for RTC_TSTR register ****************/ 3942 #define RTC_TSTR_PM_Pos (22U) 3943 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 3944 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 3945 #define RTC_TSTR_HT_Pos (20U) 3946 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 3947 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 3948 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 3949 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 3950 #define RTC_TSTR_HU_Pos (16U) 3951 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 3952 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 3953 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 3954 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 3955 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 3956 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 3957 #define RTC_TSTR_MNT_Pos (12U) 3958 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 3959 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 3960 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 3961 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 3962 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 3963 #define RTC_TSTR_MNU_Pos (8U) 3964 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 3965 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 3966 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 3967 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 3968 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 3969 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 3970 #define RTC_TSTR_ST_Pos (4U) 3971 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 3972 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 3973 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 3974 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 3975 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 3976 #define RTC_TSTR_SU_Pos (0U) 3977 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 3978 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 3979 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 3980 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 3981 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 3982 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 3983 3984 /******************** Bits definition for RTC_TSDR register ****************/ 3985 #define RTC_TSDR_WDU_Pos (13U) 3986 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 3987 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 3988 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 3989 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 3990 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 3991 #define RTC_TSDR_MT_Pos (12U) 3992 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 3993 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 3994 #define RTC_TSDR_MU_Pos (8U) 3995 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 3996 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 3997 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 3998 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 3999 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4000 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4001 #define RTC_TSDR_DT_Pos (4U) 4002 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4003 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 4004 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4005 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4006 #define RTC_TSDR_DU_Pos (0U) 4007 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4008 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 4009 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4010 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4011 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4012 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4013 4014 /******************** Bits definition for RTC_TSSSR register ***************/ 4015 #define RTC_TSSSR_SS_Pos (0U) 4016 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4017 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 4018 4019 /******************** Bits definition for RTC_CALR register ****************/ 4020 #define RTC_CALR_CALP_Pos (15U) 4021 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4022 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 4023 #define RTC_CALR_CALW8_Pos (14U) 4024 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4025 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 4026 #define RTC_CALR_CALW16_Pos (13U) 4027 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4028 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 4029 #define RTC_CALR_CALM_Pos (0U) 4030 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4031 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 4032 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4033 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4034 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4035 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4036 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4037 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4038 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4039 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4040 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4041 4042 /******************** Bits definition for RTC_TAFCR register ***************/ 4043 #define RTC_TAFCR_PC15MODE_Pos (23U) 4044 #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */ 4045 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk 4046 #define RTC_TAFCR_PC15VALUE_Pos (22U) 4047 #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */ 4048 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk 4049 #define RTC_TAFCR_PC14MODE_Pos (21U) 4050 #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */ 4051 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk 4052 #define RTC_TAFCR_PC14VALUE_Pos (20U) 4053 #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */ 4054 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk 4055 #define RTC_TAFCR_PC13MODE_Pos (19U) 4056 #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */ 4057 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk 4058 #define RTC_TAFCR_PC13VALUE_Pos (18U) 4059 #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */ 4060 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk 4061 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 4062 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 4063 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 4064 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 4065 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 4066 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 4067 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 4068 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 4069 #define RTC_TAFCR_TAMPFLT_Pos (11U) 4070 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 4071 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 4072 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 4073 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 4074 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 4075 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 4076 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 4077 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 4078 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 4079 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 4080 #define RTC_TAFCR_TAMPTS_Pos (7U) 4081 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 4082 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 4083 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 4084 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 4085 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 4086 #define RTC_TAFCR_TAMP2E_Pos (3U) 4087 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 4088 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 4089 #define RTC_TAFCR_TAMPIE_Pos (2U) 4090 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 4091 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 4092 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 4093 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 4094 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 4095 #define RTC_TAFCR_TAMP1E_Pos (0U) 4096 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 4097 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 4098 4099 /* Reference defines */ 4100 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 4101 4102 /******************** Bits definition for RTC_ALRMASSR register ************/ 4103 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4104 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4105 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4106 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4107 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4108 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4109 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4110 #define RTC_ALRMASSR_SS_Pos (0U) 4111 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4112 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4113 4114 /*****************************************************************************/ 4115 /* */ 4116 /* Serial Peripheral Interface (SPI) */ 4117 /* */ 4118 /*****************************************************************************/ 4119 4120 /* 4121 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 4122 */ 4123 /* Note: No specific macro feature on this device */ 4124 4125 /******************* Bit definition for SPI_CR1 register *******************/ 4126 #define SPI_CR1_CPHA_Pos (0U) 4127 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4128 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4129 #define SPI_CR1_CPOL_Pos (1U) 4130 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4131 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4132 #define SPI_CR1_MSTR_Pos (2U) 4133 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4134 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4135 #define SPI_CR1_BR_Pos (3U) 4136 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4137 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4138 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4139 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4140 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4141 #define SPI_CR1_SPE_Pos (6U) 4142 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4143 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4144 #define SPI_CR1_LSBFIRST_Pos (7U) 4145 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4146 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4147 #define SPI_CR1_SSI_Pos (8U) 4148 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4149 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4150 #define SPI_CR1_SSM_Pos (9U) 4151 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4152 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4153 #define SPI_CR1_RXONLY_Pos (10U) 4154 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4155 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4156 #define SPI_CR1_CRCL_Pos (11U) 4157 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 4158 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 4159 #define SPI_CR1_CRCNEXT_Pos (12U) 4160 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4161 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4162 #define SPI_CR1_CRCEN_Pos (13U) 4163 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4164 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4165 #define SPI_CR1_BIDIOE_Pos (14U) 4166 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4167 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4168 #define SPI_CR1_BIDIMODE_Pos (15U) 4169 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4170 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4171 4172 /******************* Bit definition for SPI_CR2 register *******************/ 4173 #define SPI_CR2_RXDMAEN_Pos (0U) 4174 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4175 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4176 #define SPI_CR2_TXDMAEN_Pos (1U) 4177 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4178 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4179 #define SPI_CR2_SSOE_Pos (2U) 4180 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4181 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4182 #define SPI_CR2_NSSP_Pos (3U) 4183 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 4184 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 4185 #define SPI_CR2_FRF_Pos (4U) 4186 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4187 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4188 #define SPI_CR2_ERRIE_Pos (5U) 4189 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4190 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4191 #define SPI_CR2_RXNEIE_Pos (6U) 4192 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4193 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4194 #define SPI_CR2_TXEIE_Pos (7U) 4195 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4196 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4197 #define SPI_CR2_DS_Pos (8U) 4198 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 4199 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 4200 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 4201 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 4202 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 4203 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 4204 #define SPI_CR2_FRXTH_Pos (12U) 4205 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 4206 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 4207 #define SPI_CR2_LDMARX_Pos (13U) 4208 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 4209 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 4210 #define SPI_CR2_LDMATX_Pos (14U) 4211 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 4212 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 4213 4214 /******************** Bit definition for SPI_SR register *******************/ 4215 #define SPI_SR_RXNE_Pos (0U) 4216 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4217 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4218 #define SPI_SR_TXE_Pos (1U) 4219 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4220 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4221 #define SPI_SR_CRCERR_Pos (4U) 4222 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4223 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4224 #define SPI_SR_MODF_Pos (5U) 4225 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4226 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4227 #define SPI_SR_OVR_Pos (6U) 4228 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4229 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 4230 #define SPI_SR_BSY_Pos (7U) 4231 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 4232 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 4233 #define SPI_SR_FRE_Pos (8U) 4234 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 4235 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 4236 #define SPI_SR_FRLVL_Pos (9U) 4237 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 4238 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 4239 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 4240 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 4241 #define SPI_SR_FTLVL_Pos (11U) 4242 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 4243 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 4244 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 4245 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 4246 4247 /******************** Bit definition for SPI_DR register *******************/ 4248 #define SPI_DR_DR_Pos (0U) 4249 #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ 4250 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 4251 4252 /******************* Bit definition for SPI_CRCPR register *****************/ 4253 #define SPI_CRCPR_CRCPOLY_Pos (0U) 4254 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ 4255 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 4256 4257 /****************** Bit definition for SPI_RXCRCR register *****************/ 4258 #define SPI_RXCRCR_RXCRC_Pos (0U) 4259 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ 4260 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 4261 4262 /****************** Bit definition for SPI_TXCRCR register *****************/ 4263 #define SPI_TXCRCR_TXCRC_Pos (0U) 4264 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ 4265 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 4266 4267 /****************** Bit definition for SPI_I2SCFGR register ****************/ 4268 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 4269 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 4270 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */ 4271 4272 /*****************************************************************************/ 4273 /* */ 4274 /* System Configuration (SYSCFG) */ 4275 /* */ 4276 /*****************************************************************************/ 4277 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 4278 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 4279 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 4280 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 4281 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 4282 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 4283 4284 4285 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U) 4286 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */ 4287 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */ 4288 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U) 4289 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */ 4290 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */ 4291 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U) 4292 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */ 4293 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */ 4294 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U) 4295 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */ 4296 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */ 4297 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U) 4298 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */ 4299 #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */ 4300 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U) 4301 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */ 4302 #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk /*!< Enable Fast Mode Plus on PA9 */ 4303 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U) 4304 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */ 4305 #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk /*!< Enable Fast Mode Plus on PA10 */ 4306 4307 /***************** Bit definition for SYSCFG_EXTICR1 register **************/ 4308 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 4309 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 4310 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 4311 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 4312 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 4313 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 4314 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 4315 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 4316 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 4317 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 4318 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 4319 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 4320 4321 /** 4322 * @brief EXTI0 configuration 4323 */ 4324 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 4325 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 4326 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 4327 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 4328 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 4329 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */ 4330 4331 /** 4332 * @brief EXTI1 configuration 4333 */ 4334 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 4335 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 4336 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 4337 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 4338 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 4339 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */ 4340 4341 /** 4342 * @brief EXTI2 configuration 4343 */ 4344 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 4345 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 4346 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 4347 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 4348 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 4349 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */ 4350 4351 /** 4352 * @brief EXTI3 configuration 4353 */ 4354 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 4355 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 4356 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 4357 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 4358 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 4359 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */ 4360 4361 /***************** Bit definition for SYSCFG_EXTICR2 register **************/ 4362 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 4363 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 4364 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 4365 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 4366 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 4367 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 4368 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 4369 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 4370 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 4371 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 4372 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 4373 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 4374 4375 /** 4376 * @brief EXTI4 configuration 4377 */ 4378 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 4379 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 4380 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 4381 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 4382 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 4383 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */ 4384 4385 /** 4386 * @brief EXTI5 configuration 4387 */ 4388 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 4389 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 4390 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 4391 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 4392 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 4393 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */ 4394 4395 /** 4396 * @brief EXTI6 configuration 4397 */ 4398 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 4399 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 4400 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 4401 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 4402 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 4403 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */ 4404 4405 /** 4406 * @brief EXTI7 configuration 4407 */ 4408 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 4409 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 4410 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 4411 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 4412 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 4413 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */ 4414 4415 /***************** Bit definition for SYSCFG_EXTICR3 register **************/ 4416 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 4417 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 4418 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 4419 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 4420 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 4421 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 4422 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 4423 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 4424 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 4425 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 4426 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 4427 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 4428 4429 /** 4430 * @brief EXTI8 configuration 4431 */ 4432 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 4433 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 4434 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 4435 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 4436 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 4437 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */ 4438 4439 4440 /** 4441 * @brief EXTI9 configuration 4442 */ 4443 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 4444 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 4445 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 4446 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 4447 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 4448 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */ 4449 4450 /** 4451 * @brief EXTI10 configuration 4452 */ 4453 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 4454 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 4455 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 4456 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 4457 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 4458 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */ 4459 4460 /** 4461 * @brief EXTI11 configuration 4462 */ 4463 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 4464 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 4465 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 4466 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 4467 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 4468 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */ 4469 4470 /***************** Bit definition for SYSCFG_EXTICR4 register **************/ 4471 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 4472 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 4473 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 4474 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 4475 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 4476 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 4477 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 4478 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 4479 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 4480 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 4481 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 4482 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 4483 4484 /** 4485 * @brief EXTI12 configuration 4486 */ 4487 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 4488 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 4489 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 4490 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 4491 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 4492 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */ 4493 4494 /** 4495 * @brief EXTI13 configuration 4496 */ 4497 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 4498 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 4499 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 4500 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 4501 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 4502 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */ 4503 4504 /** 4505 * @brief EXTI14 configuration 4506 */ 4507 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 4508 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 4509 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 4510 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 4511 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 4512 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */ 4513 4514 /** 4515 * @brief EXTI15 configuration 4516 */ 4517 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 4518 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 4519 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 4520 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 4521 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 4522 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */ 4523 4524 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 4525 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U) 4526 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */ 4527 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 4528 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U) 4529 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */ 4530 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 4531 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U) 4532 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */ 4533 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */ 4534 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */ 4535 4536 /*****************************************************************************/ 4537 /* */ 4538 /* Timers (TIM) */ 4539 /* */ 4540 /*****************************************************************************/ 4541 /******************* Bit definition for TIM_CR1 register *******************/ 4542 #define TIM_CR1_CEN_Pos (0U) 4543 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4544 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4545 #define TIM_CR1_UDIS_Pos (1U) 4546 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4547 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4548 #define TIM_CR1_URS_Pos (2U) 4549 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4550 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4551 #define TIM_CR1_OPM_Pos (3U) 4552 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4553 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4554 #define TIM_CR1_DIR_Pos (4U) 4555 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4556 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4557 4558 #define TIM_CR1_CMS_Pos (5U) 4559 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4560 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4561 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4562 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4563 4564 #define TIM_CR1_ARPE_Pos (7U) 4565 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4566 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4567 4568 #define TIM_CR1_CKD_Pos (8U) 4569 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4570 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4571 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4572 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4573 4574 /******************* Bit definition for TIM_CR2 register *******************/ 4575 #define TIM_CR2_CCPC_Pos (0U) 4576 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 4577 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 4578 #define TIM_CR2_CCUS_Pos (2U) 4579 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 4580 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 4581 #define TIM_CR2_CCDS_Pos (3U) 4582 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4583 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4584 4585 #define TIM_CR2_MMS_Pos (4U) 4586 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4587 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4588 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4589 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4590 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4591 4592 #define TIM_CR2_TI1S_Pos (7U) 4593 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4594 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4595 #define TIM_CR2_OIS1_Pos (8U) 4596 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 4597 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 4598 #define TIM_CR2_OIS1N_Pos (9U) 4599 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 4600 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 4601 #define TIM_CR2_OIS2_Pos (10U) 4602 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 4603 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 4604 #define TIM_CR2_OIS2N_Pos (11U) 4605 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 4606 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 4607 #define TIM_CR2_OIS3_Pos (12U) 4608 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 4609 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 4610 #define TIM_CR2_OIS3N_Pos (13U) 4611 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 4612 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 4613 #define TIM_CR2_OIS4_Pos (14U) 4614 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 4615 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 4616 4617 /******************* Bit definition for TIM_SMCR register ******************/ 4618 #define TIM_SMCR_SMS_Pos (0U) 4619 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4620 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4621 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4622 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4623 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4624 4625 #define TIM_SMCR_OCCS_Pos (3U) 4626 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 4627 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 4628 4629 #define TIM_SMCR_TS_Pos (4U) 4630 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4631 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4632 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4633 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4634 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4635 4636 #define TIM_SMCR_MSM_Pos (7U) 4637 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4638 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4639 4640 #define TIM_SMCR_ETF_Pos (8U) 4641 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4642 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4643 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4644 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4645 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4646 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 4647 4648 #define TIM_SMCR_ETPS_Pos (12U) 4649 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 4650 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 4651 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 4652 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 4653 4654 #define TIM_SMCR_ECE_Pos (14U) 4655 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 4656 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 4657 #define TIM_SMCR_ETP_Pos (15U) 4658 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 4659 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 4660 4661 /******************* Bit definition for TIM_DIER register ******************/ 4662 #define TIM_DIER_UIE_Pos (0U) 4663 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 4664 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 4665 #define TIM_DIER_CC1IE_Pos (1U) 4666 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 4667 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 4668 #define TIM_DIER_CC2IE_Pos (2U) 4669 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 4670 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 4671 #define TIM_DIER_CC3IE_Pos (3U) 4672 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 4673 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 4674 #define TIM_DIER_CC4IE_Pos (4U) 4675 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 4676 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 4677 #define TIM_DIER_COMIE_Pos (5U) 4678 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 4679 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 4680 #define TIM_DIER_TIE_Pos (6U) 4681 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 4682 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 4683 #define TIM_DIER_BIE_Pos (7U) 4684 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 4685 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 4686 #define TIM_DIER_UDE_Pos (8U) 4687 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 4688 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 4689 #define TIM_DIER_CC1DE_Pos (9U) 4690 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 4691 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 4692 #define TIM_DIER_CC2DE_Pos (10U) 4693 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 4694 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 4695 #define TIM_DIER_CC3DE_Pos (11U) 4696 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 4697 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 4698 #define TIM_DIER_CC4DE_Pos (12U) 4699 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 4700 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 4701 #define TIM_DIER_COMDE_Pos (13U) 4702 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 4703 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 4704 #define TIM_DIER_TDE_Pos (14U) 4705 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 4706 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 4707 4708 /******************** Bit definition for TIM_SR register *******************/ 4709 #define TIM_SR_UIF_Pos (0U) 4710 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 4711 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 4712 #define TIM_SR_CC1IF_Pos (1U) 4713 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 4714 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 4715 #define TIM_SR_CC2IF_Pos (2U) 4716 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 4717 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 4718 #define TIM_SR_CC3IF_Pos (3U) 4719 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 4720 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 4721 #define TIM_SR_CC4IF_Pos (4U) 4722 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 4723 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 4724 #define TIM_SR_COMIF_Pos (5U) 4725 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 4726 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 4727 #define TIM_SR_TIF_Pos (6U) 4728 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 4729 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 4730 #define TIM_SR_BIF_Pos (7U) 4731 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 4732 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 4733 #define TIM_SR_CC1OF_Pos (9U) 4734 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 4735 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 4736 #define TIM_SR_CC2OF_Pos (10U) 4737 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 4738 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 4739 #define TIM_SR_CC3OF_Pos (11U) 4740 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 4741 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 4742 #define TIM_SR_CC4OF_Pos (12U) 4743 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 4744 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 4745 4746 /******************* Bit definition for TIM_EGR register *******************/ 4747 #define TIM_EGR_UG_Pos (0U) 4748 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 4749 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 4750 #define TIM_EGR_CC1G_Pos (1U) 4751 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 4752 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 4753 #define TIM_EGR_CC2G_Pos (2U) 4754 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 4755 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 4756 #define TIM_EGR_CC3G_Pos (3U) 4757 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 4758 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 4759 #define TIM_EGR_CC4G_Pos (4U) 4760 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 4761 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 4762 #define TIM_EGR_COMG_Pos (5U) 4763 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 4764 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 4765 #define TIM_EGR_TG_Pos (6U) 4766 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 4767 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 4768 #define TIM_EGR_BG_Pos (7U) 4769 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 4770 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 4771 4772 /****************** Bit definition for TIM_CCMR1 register ******************/ 4773 #define TIM_CCMR1_CC1S_Pos (0U) 4774 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 4775 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 4776 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 4777 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 4778 4779 #define TIM_CCMR1_OC1FE_Pos (2U) 4780 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 4781 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 4782 #define TIM_CCMR1_OC1PE_Pos (3U) 4783 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 4784 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 4785 4786 #define TIM_CCMR1_OC1M_Pos (4U) 4787 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 4788 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 4789 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 4790 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 4791 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 4792 4793 #define TIM_CCMR1_OC1CE_Pos (7U) 4794 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 4795 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 4796 4797 #define TIM_CCMR1_CC2S_Pos (8U) 4798 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 4799 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 4800 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 4801 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 4802 4803 #define TIM_CCMR1_OC2FE_Pos (10U) 4804 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 4805 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 4806 #define TIM_CCMR1_OC2PE_Pos (11U) 4807 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 4808 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 4809 4810 #define TIM_CCMR1_OC2M_Pos (12U) 4811 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 4812 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 4813 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 4814 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 4815 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 4816 4817 #define TIM_CCMR1_OC2CE_Pos (15U) 4818 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 4819 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 4820 4821 /*---------------------------------------------------------------------------*/ 4822 4823 #define TIM_CCMR1_IC1PSC_Pos (2U) 4824 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 4825 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 4826 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 4827 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 4828 4829 #define TIM_CCMR1_IC1F_Pos (4U) 4830 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 4831 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 4832 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 4833 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 4834 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 4835 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 4836 4837 #define TIM_CCMR1_IC2PSC_Pos (10U) 4838 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 4839 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 4840 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 4841 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 4842 4843 #define TIM_CCMR1_IC2F_Pos (12U) 4844 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 4845 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 4846 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 4847 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 4848 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 4849 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 4850 4851 /****************** Bit definition for TIM_CCMR2 register ******************/ 4852 #define TIM_CCMR2_CC3S_Pos (0U) 4853 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 4854 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 4855 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 4856 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 4857 4858 #define TIM_CCMR2_OC3FE_Pos (2U) 4859 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 4860 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 4861 #define TIM_CCMR2_OC3PE_Pos (3U) 4862 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 4863 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 4864 4865 #define TIM_CCMR2_OC3M_Pos (4U) 4866 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 4867 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 4868 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 4869 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 4870 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 4871 4872 #define TIM_CCMR2_OC3CE_Pos (7U) 4873 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 4874 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 4875 4876 #define TIM_CCMR2_CC4S_Pos (8U) 4877 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 4878 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 4879 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 4880 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 4881 4882 #define TIM_CCMR2_OC4FE_Pos (10U) 4883 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 4884 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 4885 #define TIM_CCMR2_OC4PE_Pos (11U) 4886 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 4887 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 4888 4889 #define TIM_CCMR2_OC4M_Pos (12U) 4890 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 4891 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 4892 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 4893 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 4894 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 4895 4896 #define TIM_CCMR2_OC4CE_Pos (15U) 4897 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 4898 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 4899 4900 /*---------------------------------------------------------------------------*/ 4901 4902 #define TIM_CCMR2_IC3PSC_Pos (2U) 4903 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 4904 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 4905 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 4906 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 4907 4908 #define TIM_CCMR2_IC3F_Pos (4U) 4909 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 4910 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 4911 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 4912 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 4913 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 4914 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 4915 4916 #define TIM_CCMR2_IC4PSC_Pos (10U) 4917 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 4918 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 4919 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 4920 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 4921 4922 #define TIM_CCMR2_IC4F_Pos (12U) 4923 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 4924 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 4925 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 4926 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 4927 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 4928 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 4929 4930 /******************* Bit definition for TIM_CCER register ******************/ 4931 #define TIM_CCER_CC1E_Pos (0U) 4932 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 4933 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 4934 #define TIM_CCER_CC1P_Pos (1U) 4935 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 4936 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 4937 #define TIM_CCER_CC1NE_Pos (2U) 4938 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 4939 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 4940 #define TIM_CCER_CC1NP_Pos (3U) 4941 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 4942 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 4943 #define TIM_CCER_CC2E_Pos (4U) 4944 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 4945 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 4946 #define TIM_CCER_CC2P_Pos (5U) 4947 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 4948 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 4949 #define TIM_CCER_CC2NE_Pos (6U) 4950 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 4951 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 4952 #define TIM_CCER_CC2NP_Pos (7U) 4953 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 4954 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 4955 #define TIM_CCER_CC3E_Pos (8U) 4956 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 4957 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 4958 #define TIM_CCER_CC3P_Pos (9U) 4959 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 4960 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 4961 #define TIM_CCER_CC3NE_Pos (10U) 4962 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 4963 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 4964 #define TIM_CCER_CC3NP_Pos (11U) 4965 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 4966 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 4967 #define TIM_CCER_CC4E_Pos (12U) 4968 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 4969 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 4970 #define TIM_CCER_CC4P_Pos (13U) 4971 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 4972 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 4973 #define TIM_CCER_CC4NP_Pos (15U) 4974 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 4975 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 4976 4977 /******************* Bit definition for TIM_CNT register *******************/ 4978 #define TIM_CNT_CNT_Pos (0U) 4979 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 4980 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 4981 4982 /******************* Bit definition for TIM_PSC register *******************/ 4983 #define TIM_PSC_PSC_Pos (0U) 4984 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 4985 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 4986 4987 /******************* Bit definition for TIM_ARR register *******************/ 4988 #define TIM_ARR_ARR_Pos (0U) 4989 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 4990 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 4991 4992 /******************* Bit definition for TIM_RCR register *******************/ 4993 #define TIM_RCR_REP_Pos (0U) 4994 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 4995 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 4996 4997 /******************* Bit definition for TIM_CCR1 register ******************/ 4998 #define TIM_CCR1_CCR1_Pos (0U) 4999 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 5000 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5001 5002 /******************* Bit definition for TIM_CCR2 register ******************/ 5003 #define TIM_CCR2_CCR2_Pos (0U) 5004 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 5005 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5006 5007 /******************* Bit definition for TIM_CCR3 register ******************/ 5008 #define TIM_CCR3_CCR3_Pos (0U) 5009 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 5010 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5011 5012 /******************* Bit definition for TIM_CCR4 register ******************/ 5013 #define TIM_CCR4_CCR4_Pos (0U) 5014 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 5015 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5016 5017 /******************* Bit definition for TIM_BDTR register ******************/ 5018 #define TIM_BDTR_DTG_Pos (0U) 5019 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 5020 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 5021 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 5022 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 5023 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 5024 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 5025 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 5026 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 5027 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 5028 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 5029 5030 #define TIM_BDTR_LOCK_Pos (8U) 5031 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 5032 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 5033 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 5034 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 5035 5036 #define TIM_BDTR_OSSI_Pos (10U) 5037 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 5038 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 5039 #define TIM_BDTR_OSSR_Pos (11U) 5040 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 5041 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 5042 #define TIM_BDTR_BKE_Pos (12U) 5043 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 5044 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 5045 #define TIM_BDTR_BKP_Pos (13U) 5046 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 5047 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 5048 #define TIM_BDTR_AOE_Pos (14U) 5049 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 5050 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 5051 #define TIM_BDTR_MOE_Pos (15U) 5052 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 5053 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 5054 5055 /******************* Bit definition for TIM_DCR register *******************/ 5056 #define TIM_DCR_DBA_Pos (0U) 5057 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5058 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5059 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5060 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5061 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5062 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5063 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5064 5065 #define TIM_DCR_DBL_Pos (8U) 5066 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5067 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5068 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5069 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5070 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5071 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5072 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5073 5074 /******************* Bit definition for TIM_DMAR register ******************/ 5075 #define TIM_DMAR_DMAB_Pos (0U) 5076 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5077 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5078 5079 /******************* Bit definition for TIM14_OR register ********************/ 5080 #define TIM14_OR_TI1_RMP_Pos (0U) 5081 #define TIM14_OR_TI1_RMP_Msk (0x3UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */ 5082 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ 5083 #define TIM14_OR_TI1_RMP_0 (0x1UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */ 5084 #define TIM14_OR_TI1_RMP_1 (0x2UL << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */ 5085 5086 /******************************************************************************/ 5087 /* */ 5088 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5089 /* */ 5090 /******************************************************************************/ 5091 5092 /* 5093 * @brief Specific device feature definitions (not present on all devices in the STM32F0 series) 5094 */ 5095 5096 /* Support of 7 bits data length feature */ 5097 #define USART_7BITS_SUPPORT 5098 5099 /* Support of Full Auto Baud rate feature (4 modes) activation */ 5100 #define USART_FABR_SUPPORT 5101 5102 /****************** Bit definition for USART_CR1 register *******************/ 5103 #define USART_CR1_UE_Pos (0U) 5104 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 5105 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5106 #define USART_CR1_RE_Pos (2U) 5107 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5108 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5109 #define USART_CR1_TE_Pos (3U) 5110 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5111 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5112 #define USART_CR1_IDLEIE_Pos (4U) 5113 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5114 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5115 #define USART_CR1_RXNEIE_Pos (5U) 5116 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5117 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5118 #define USART_CR1_TCIE_Pos (6U) 5119 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5120 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5121 #define USART_CR1_TXEIE_Pos (7U) 5122 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5123 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 5124 #define USART_CR1_PEIE_Pos (8U) 5125 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5126 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5127 #define USART_CR1_PS_Pos (9U) 5128 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5129 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5130 #define USART_CR1_PCE_Pos (10U) 5131 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5132 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5133 #define USART_CR1_WAKE_Pos (11U) 5134 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5135 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 5136 #define USART_CR1_M0_Pos (12U) 5137 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 5138 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length bit 0 */ 5139 #define USART_CR1_MME_Pos (13U) 5140 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 5141 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 5142 #define USART_CR1_CMIE_Pos (14U) 5143 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 5144 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 5145 #define USART_CR1_OVER8_Pos (15U) 5146 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5147 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 5148 #define USART_CR1_DEDT_Pos (16U) 5149 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 5150 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 5151 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 5152 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 5153 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 5154 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 5155 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 5156 #define USART_CR1_DEAT_Pos (21U) 5157 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 5158 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 5159 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 5160 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 5161 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 5162 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 5163 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 5164 #define USART_CR1_RTOIE_Pos (26U) 5165 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 5166 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 5167 #define USART_CR1_EOBIE_Pos (27U) 5168 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 5169 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 5170 #define USART_CR1_M1_Pos (28U) 5171 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 5172 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length bit 1 */ 5173 #define USART_CR1_M_Pos (12U) 5174 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 5175 #define USART_CR1_M USART_CR1_M_Msk /*!< [M1:M0] Word length */ 5176 5177 /****************** Bit definition for USART_CR2 register *******************/ 5178 #define USART_CR2_ADDM7_Pos (4U) 5179 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 5180 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 5181 #define USART_CR2_LBCL_Pos (8U) 5182 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5183 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5184 #define USART_CR2_CPHA_Pos (9U) 5185 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5186 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5187 #define USART_CR2_CPOL_Pos (10U) 5188 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5189 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5190 #define USART_CR2_CLKEN_Pos (11U) 5191 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5192 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5193 #define USART_CR2_STOP_Pos (12U) 5194 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5195 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5196 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5197 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5198 #define USART_CR2_SWAP_Pos (15U) 5199 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 5200 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 5201 #define USART_CR2_RXINV_Pos (16U) 5202 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 5203 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 5204 #define USART_CR2_TXINV_Pos (17U) 5205 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 5206 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 5207 #define USART_CR2_DATAINV_Pos (18U) 5208 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 5209 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 5210 #define USART_CR2_MSBFIRST_Pos (19U) 5211 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 5212 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 5213 #define USART_CR2_ABREN_Pos (20U) 5214 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 5215 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 5216 #define USART_CR2_ABRMODE_Pos (21U) 5217 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 5218 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 5219 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 5220 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 5221 #define USART_CR2_RTOEN_Pos (23U) 5222 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 5223 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 5224 #define USART_CR2_ADD_Pos (24U) 5225 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 5226 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 5227 5228 /****************** Bit definition for USART_CR3 register *******************/ 5229 #define USART_CR3_EIE_Pos (0U) 5230 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 5231 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 5232 #define USART_CR3_HDSEL_Pos (3U) 5233 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 5234 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 5235 #define USART_CR3_DMAR_Pos (6U) 5236 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 5237 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 5238 #define USART_CR3_DMAT_Pos (7U) 5239 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 5240 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 5241 #define USART_CR3_RTSE_Pos (8U) 5242 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 5243 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 5244 #define USART_CR3_CTSE_Pos (9U) 5245 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 5246 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 5247 #define USART_CR3_CTSIE_Pos (10U) 5248 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 5249 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 5250 #define USART_CR3_ONEBIT_Pos (11U) 5251 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 5252 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 5253 #define USART_CR3_OVRDIS_Pos (12U) 5254 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 5255 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 5256 #define USART_CR3_DDRE_Pos (13U) 5257 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 5258 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 5259 #define USART_CR3_DEM_Pos (14U) 5260 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 5261 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 5262 #define USART_CR3_DEP_Pos (15U) 5263 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 5264 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 5265 5266 /****************** Bit definition for USART_BRR register *******************/ 5267 #define USART_BRR_DIV_FRACTION_Pos (0U) 5268 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 5269 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 5270 #define USART_BRR_DIV_MANTISSA_Pos (4U) 5271 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 5272 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 5273 5274 /****************** Bit definition for USART_GTPR register ******************/ 5275 #define USART_GTPR_PSC_Pos (0U) 5276 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 5277 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 5278 #define USART_GTPR_GT_Pos (8U) 5279 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 5280 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 5281 5282 5283 /******************* Bit definition for USART_RTOR register *****************/ 5284 #define USART_RTOR_RTO_Pos (0U) 5285 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 5286 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 5287 #define USART_RTOR_BLEN_Pos (24U) 5288 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 5289 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 5290 5291 /******************* Bit definition for USART_RQR register ******************/ 5292 #define USART_RQR_ABRRQ_Pos (0U) 5293 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 5294 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 5295 #define USART_RQR_SBKRQ_Pos (1U) 5296 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 5297 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 5298 #define USART_RQR_MMRQ_Pos (2U) 5299 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 5300 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 5301 #define USART_RQR_RXFRQ_Pos (3U) 5302 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 5303 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 5304 5305 /******************* Bit definition for USART_ISR register ******************/ 5306 #define USART_ISR_PE_Pos (0U) 5307 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 5308 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 5309 #define USART_ISR_FE_Pos (1U) 5310 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 5311 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 5312 #define USART_ISR_NE_Pos (2U) 5313 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 5314 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 5315 #define USART_ISR_ORE_Pos (3U) 5316 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 5317 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 5318 #define USART_ISR_IDLE_Pos (4U) 5319 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 5320 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 5321 #define USART_ISR_RXNE_Pos (5U) 5322 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 5323 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 5324 #define USART_ISR_TC_Pos (6U) 5325 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 5326 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 5327 #define USART_ISR_TXE_Pos (7U) 5328 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 5329 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 5330 #define USART_ISR_CTSIF_Pos (9U) 5331 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 5332 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 5333 #define USART_ISR_CTS_Pos (10U) 5334 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 5335 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 5336 #define USART_ISR_RTOF_Pos (11U) 5337 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 5338 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 5339 #define USART_ISR_ABRE_Pos (14U) 5340 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 5341 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 5342 #define USART_ISR_ABRF_Pos (15U) 5343 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 5344 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 5345 #define USART_ISR_BUSY_Pos (16U) 5346 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 5347 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 5348 #define USART_ISR_CMF_Pos (17U) 5349 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 5350 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 5351 #define USART_ISR_SBKF_Pos (18U) 5352 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 5353 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 5354 #define USART_ISR_RWU_Pos (19U) 5355 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 5356 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 5357 #define USART_ISR_TEACK_Pos (21U) 5358 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 5359 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 5360 #define USART_ISR_REACK_Pos (22U) 5361 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 5362 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 5363 5364 /******************* Bit definition for USART_ICR register ******************/ 5365 #define USART_ICR_PECF_Pos (0U) 5366 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 5367 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 5368 #define USART_ICR_FECF_Pos (1U) 5369 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 5370 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 5371 #define USART_ICR_NCF_Pos (2U) 5372 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 5373 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 5374 #define USART_ICR_ORECF_Pos (3U) 5375 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 5376 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 5377 #define USART_ICR_IDLECF_Pos (4U) 5378 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 5379 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 5380 #define USART_ICR_TCCF_Pos (6U) 5381 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 5382 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 5383 #define USART_ICR_CTSCF_Pos (9U) 5384 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 5385 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 5386 #define USART_ICR_RTOCF_Pos (11U) 5387 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 5388 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 5389 #define USART_ICR_CMCF_Pos (17U) 5390 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 5391 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 5392 5393 /******************* Bit definition for USART_RDR register ******************/ 5394 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */ 5395 5396 /******************* Bit definition for USART_TDR register ******************/ 5397 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */ 5398 5399 /******************************************************************************/ 5400 /* */ 5401 /* Window WATCHDOG (WWDG) */ 5402 /* */ 5403 /******************************************************************************/ 5404 5405 /******************* Bit definition for WWDG_CR register ********************/ 5406 #define WWDG_CR_T_Pos (0U) 5407 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 5408 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 5409 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 5410 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 5411 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 5412 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 5413 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 5414 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 5415 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 5416 5417 /* Legacy defines */ 5418 #define WWDG_CR_T0 WWDG_CR_T_0 5419 #define WWDG_CR_T1 WWDG_CR_T_1 5420 #define WWDG_CR_T2 WWDG_CR_T_2 5421 #define WWDG_CR_T3 WWDG_CR_T_3 5422 #define WWDG_CR_T4 WWDG_CR_T_4 5423 #define WWDG_CR_T5 WWDG_CR_T_5 5424 #define WWDG_CR_T6 WWDG_CR_T_6 5425 5426 #define WWDG_CR_WDGA_Pos (7U) 5427 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 5428 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 5429 5430 /******************* Bit definition for WWDG_CFR register *******************/ 5431 #define WWDG_CFR_W_Pos (0U) 5432 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 5433 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 5434 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 5435 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 5436 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 5437 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 5438 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 5439 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 5440 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 5441 5442 /* Legacy defines */ 5443 #define WWDG_CFR_W0 WWDG_CFR_W_0 5444 #define WWDG_CFR_W1 WWDG_CFR_W_1 5445 #define WWDG_CFR_W2 WWDG_CFR_W_2 5446 #define WWDG_CFR_W3 WWDG_CFR_W_3 5447 #define WWDG_CFR_W4 WWDG_CFR_W_4 5448 #define WWDG_CFR_W5 WWDG_CFR_W_5 5449 #define WWDG_CFR_W6 WWDG_CFR_W_6 5450 5451 #define WWDG_CFR_WDGTB_Pos (7U) 5452 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 5453 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 5454 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 5455 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 5456 5457 /* Legacy defines */ 5458 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 5459 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 5460 5461 #define WWDG_CFR_EWI_Pos (9U) 5462 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 5463 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 5464 5465 /******************* Bit definition for WWDG_SR register ********************/ 5466 #define WWDG_SR_EWIF_Pos (0U) 5467 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 5468 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 5469 5470 /** 5471 * @} 5472 */ 5473 5474 /** 5475 * @} 5476 */ 5477 5478 5479 /** @addtogroup Exported_macro 5480 * @{ 5481 */ 5482 5483 /****************************** ADC Instances *********************************/ 5484 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 5485 5486 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC) 5487 5488 /****************************** CRC Instances *********************************/ 5489 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 5490 5491 /******************************* DMA Instances ********************************/ 5492 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 5493 ((INSTANCE) == DMA1_Channel2) || \ 5494 ((INSTANCE) == DMA1_Channel3) || \ 5495 ((INSTANCE) == DMA1_Channel4) || \ 5496 ((INSTANCE) == DMA1_Channel5)) 5497 5498 /****************************** GPIO Instances ********************************/ 5499 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5500 ((INSTANCE) == GPIOB) || \ 5501 ((INSTANCE) == GPIOC) || \ 5502 ((INSTANCE) == GPIOD) || \ 5503 ((INSTANCE) == GPIOF)) 5504 5505 /**************************** GPIO Alternate Function Instances ***************/ 5506 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5507 ((INSTANCE) == GPIOB) || \ 5508 ((INSTANCE) == GPIOC) || \ 5509 ((INSTANCE) == GPIOD) || \ 5510 ((INSTANCE) == GPIOF)) 5511 5512 /****************************** GPIO Lock Instances ***************************/ 5513 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5514 ((INSTANCE) == GPIOB)) 5515 5516 /****************************** I2C Instances *********************************/ 5517 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 5518 ((INSTANCE) == I2C2)) 5519 5520 5521 /****************************** IWDG Instances ********************************/ 5522 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 5523 5524 /****************************** RTC Instances *********************************/ 5525 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 5526 5527 /****************************** SMBUS Instances *********************************/ 5528 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 5529 5530 /****************************** SPI Instances *********************************/ 5531 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 5532 ((INSTANCE) == SPI2)) 5533 5534 /****************************** TIM Instances *********************************/ 5535 #define IS_TIM_INSTANCE(INSTANCE)\ 5536 (((INSTANCE) == TIM1) || \ 5537 ((INSTANCE) == TIM3) || \ 5538 ((INSTANCE) == TIM6) || \ 5539 ((INSTANCE) == TIM7) || \ 5540 ((INSTANCE) == TIM14) || \ 5541 ((INSTANCE) == TIM15) || \ 5542 ((INSTANCE) == TIM16) || \ 5543 ((INSTANCE) == TIM17)) 5544 5545 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 5546 (((INSTANCE) == TIM1) || \ 5547 ((INSTANCE) == TIM3) || \ 5548 ((INSTANCE) == TIM14) || \ 5549 ((INSTANCE) == TIM15) || \ 5550 ((INSTANCE) == TIM16) || \ 5551 ((INSTANCE) == TIM17)) 5552 5553 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 5554 (((INSTANCE) == TIM1) || \ 5555 ((INSTANCE) == TIM3) || \ 5556 ((INSTANCE) == TIM15)) 5557 5558 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 5559 (((INSTANCE) == TIM1) || \ 5560 ((INSTANCE) == TIM3)) 5561 5562 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 5563 (((INSTANCE) == TIM1) || \ 5564 ((INSTANCE) == TIM3)) 5565 5566 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 5567 (((INSTANCE) == TIM1) || \ 5568 ((INSTANCE) == TIM3)) 5569 5570 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 5571 (((INSTANCE) == TIM1) || \ 5572 ((INSTANCE) == TIM3)) 5573 5574 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 5575 (((INSTANCE) == TIM1) || \ 5576 ((INSTANCE) == TIM3) || \ 5577 ((INSTANCE) == TIM15)) 5578 5579 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 5580 (((INSTANCE) == TIM1) || \ 5581 ((INSTANCE) == TIM3) || \ 5582 ((INSTANCE) == TIM15)) 5583 5584 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 5585 (((INSTANCE) == TIM1) || \ 5586 ((INSTANCE) == TIM3)) 5587 5588 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 5589 (((INSTANCE) == TIM1) || \ 5590 ((INSTANCE) == TIM3)) 5591 5592 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ 5593 (((INSTANCE) == TIM1)) 5594 5595 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\ 5596 (((INSTANCE) == TIM1)) 5597 5598 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 5599 (((INSTANCE) == TIM1) || \ 5600 ((INSTANCE) == TIM3)) 5601 5602 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 5603 (((INSTANCE) == TIM1) || \ 5604 ((INSTANCE) == TIM3) || \ 5605 ((INSTANCE) == TIM6) || \ 5606 ((INSTANCE) == TIM7) || \ 5607 ((INSTANCE) == TIM15)) 5608 5609 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 5610 (((INSTANCE) == TIM1) || \ 5611 ((INSTANCE) == TIM3) || \ 5612 ((INSTANCE) == TIM15)) 5613 5614 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(0) 5615 5616 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 5617 (((INSTANCE) == TIM1) || \ 5618 ((INSTANCE) == TIM3) || \ 5619 ((INSTANCE) == TIM15) || \ 5620 ((INSTANCE) == TIM16) || \ 5621 ((INSTANCE) == TIM17)) 5622 5623 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 5624 (((INSTANCE) == TIM1) || \ 5625 ((INSTANCE) == TIM15) || \ 5626 ((INSTANCE) == TIM16) || \ 5627 ((INSTANCE) == TIM17)) 5628 5629 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 5630 ((((INSTANCE) == TIM1) && \ 5631 (((CHANNEL) == TIM_CHANNEL_1) || \ 5632 ((CHANNEL) == TIM_CHANNEL_2) || \ 5633 ((CHANNEL) == TIM_CHANNEL_3) || \ 5634 ((CHANNEL) == TIM_CHANNEL_4))) \ 5635 || \ 5636 (((INSTANCE) == TIM3) && \ 5637 (((CHANNEL) == TIM_CHANNEL_1) || \ 5638 ((CHANNEL) == TIM_CHANNEL_2) || \ 5639 ((CHANNEL) == TIM_CHANNEL_3) || \ 5640 ((CHANNEL) == TIM_CHANNEL_4))) \ 5641 || \ 5642 (((INSTANCE) == TIM14) && \ 5643 (((CHANNEL) == TIM_CHANNEL_1))) \ 5644 || \ 5645 (((INSTANCE) == TIM15) && \ 5646 (((CHANNEL) == TIM_CHANNEL_1) || \ 5647 ((CHANNEL) == TIM_CHANNEL_2))) \ 5648 || \ 5649 (((INSTANCE) == TIM16) && \ 5650 (((CHANNEL) == TIM_CHANNEL_1))) \ 5651 || \ 5652 (((INSTANCE) == TIM17) && \ 5653 (((CHANNEL) == TIM_CHANNEL_1)))) 5654 5655 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 5656 ((((INSTANCE) == TIM1) && \ 5657 (((CHANNEL) == TIM_CHANNEL_1) || \ 5658 ((CHANNEL) == TIM_CHANNEL_2) || \ 5659 ((CHANNEL) == TIM_CHANNEL_3))) \ 5660 || \ 5661 (((INSTANCE) == TIM15) && \ 5662 ((CHANNEL) == TIM_CHANNEL_1)) \ 5663 || \ 5664 (((INSTANCE) == TIM16) && \ 5665 ((CHANNEL) == TIM_CHANNEL_1)) \ 5666 || \ 5667 (((INSTANCE) == TIM17) && \ 5668 ((CHANNEL) == TIM_CHANNEL_1))) 5669 5670 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 5671 (((INSTANCE) == TIM1) || \ 5672 ((INSTANCE) == TIM3)) 5673 5674 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 5675 (((INSTANCE) == TIM1) || \ 5676 ((INSTANCE) == TIM15) || \ 5677 ((INSTANCE) == TIM16) || \ 5678 ((INSTANCE) == TIM17)) 5679 5680 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 5681 (((INSTANCE) == TIM1) || \ 5682 ((INSTANCE) == TIM3) || \ 5683 ((INSTANCE) == TIM14) || \ 5684 ((INSTANCE) == TIM15) || \ 5685 ((INSTANCE) == TIM16) || \ 5686 ((INSTANCE) == TIM17)) 5687 5688 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 5689 (((INSTANCE) == TIM1) || \ 5690 ((INSTANCE) == TIM3) || \ 5691 ((INSTANCE) == TIM6) || \ 5692 ((INSTANCE) == TIM7) || \ 5693 ((INSTANCE) == TIM15) || \ 5694 ((INSTANCE) == TIM16) || \ 5695 ((INSTANCE) == TIM17)) 5696 5697 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 5698 (((INSTANCE) == TIM1) || \ 5699 ((INSTANCE) == TIM3) || \ 5700 ((INSTANCE) == TIM15) || \ 5701 ((INSTANCE) == TIM16) || \ 5702 ((INSTANCE) == TIM17)) 5703 5704 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 5705 (((INSTANCE) == TIM1) || \ 5706 ((INSTANCE) == TIM15) || \ 5707 ((INSTANCE) == TIM16) || \ 5708 ((INSTANCE) == TIM17)) 5709 5710 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ 5711 ((INSTANCE) == TIM14) 5712 5713 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\ 5714 ((INSTANCE) == TIM1) 5715 5716 /******************** USART Instances : Synchronous mode **********************/ 5717 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5718 ((INSTANCE) == USART2) || \ 5719 ((INSTANCE) == USART3) || \ 5720 ((INSTANCE) == USART4) || \ 5721 ((INSTANCE) == USART5)) 5722 5723 /******************** USART Instances : auto Baud rate detection **************/ 5724 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5725 ((INSTANCE) == USART2) || \ 5726 ((INSTANCE) == USART3)) 5727 5728 /******************** UART Instances : Asynchronous mode **********************/ 5729 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5730 ((INSTANCE) == USART2) || \ 5731 ((INSTANCE) == USART3) || \ 5732 ((INSTANCE) == USART4) || \ 5733 ((INSTANCE) == USART5) || \ 5734 ((INSTANCE) == USART6)) 5735 5736 /******************** UART Instances : Half-Duplex mode **********************/ 5737 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5738 ((INSTANCE) == USART2) || \ 5739 ((INSTANCE) == USART3) || \ 5740 ((INSTANCE) == USART4) || \ 5741 ((INSTANCE) == USART5) || \ 5742 ((INSTANCE) == USART6)) 5743 5744 /****************** UART Instances : Hardware Flow control ********************/ 5745 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5746 ((INSTANCE) == USART2) || \ 5747 ((INSTANCE) == USART3) || \ 5748 ((INSTANCE) == USART4)) 5749 5750 /****************** UART Instances : Driver enable detection ********************/ 5751 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5752 ((INSTANCE) == USART2) || \ 5753 ((INSTANCE) == USART3) || \ 5754 ((INSTANCE) == USART4) || \ 5755 ((INSTANCE) == USART5) || \ 5756 ((INSTANCE) == USART6)) 5757 5758 /****************************** WWDG Instances ********************************/ 5759 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 5760 5761 /** 5762 * @} 5763 */ 5764 5765 5766 /******************************************************************************/ 5767 /* For a painless codes migration between the STM32F0xx device product */ 5768 /* lines, the aliases defined below are put in place to overcome the */ 5769 /* differences in the interrupt handlers and IRQn definitions. */ 5770 /* No need to update developed interrupt code when moving across */ 5771 /* product lines within the same STM32F0 Family */ 5772 /******************************************************************************/ 5773 5774 /* Aliases for __IRQn */ 5775 #define ADC1_COMP_IRQn ADC1_IRQn 5776 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5777 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5778 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5779 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5780 #define RCC_CRS_IRQn RCC_IRQn 5781 #define TIM6_DAC_IRQn TIM6_IRQn 5782 #define USART3_8_IRQn USART3_6_IRQn 5783 #define USART3_4_IRQn USART3_6_IRQn 5784 5785 #define SVC_IRQn SVCall_IRQn 5786 5787 /* Aliases for __IRQHandler */ 5788 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5789 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5790 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5791 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5792 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5793 #define RCC_CRS_IRQHandler RCC_IRQHandler 5794 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 5795 #define USART3_8_IRQHandler USART3_6_IRQHandler 5796 #define USART3_4_IRQHandler USART3_6_IRQHandler 5797 5798 5799 #ifdef __cplusplus 5800 } 5801 #endif /* __cplusplus */ 5802 5803 #endif /* __STM32F030xC_H */ 5804 5805 /** 5806 * @} 5807 */ 5808 5809 /** 5810 * @} 5811 */ 5812 5813
