1 /** 2 ****************************************************************************** 3 * @file stm32l081xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32l081xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2016 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 /** @addtogroup CMSIS 28 * @{ 29 */ 30 31 /** @addtogroup stm32l081xx 32 * @{ 33 */ 34 35 #ifndef __STM32L081xx_H 36 #define __STM32L081xx_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 /** @addtogroup Configuration_section_for_CMSIS 44 * @{ 45 */ 46 /** 47 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 48 */ 49 #define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ 50 #define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */ 51 #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ 52 #define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief stm32l081xx Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ 74 SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ 75 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ 76 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ 77 78 /****** STM32L-0 specific Interrupt Numbers *********************************************************/ 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ 81 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 82 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 83 RCC_IRQn = 4, /*!< RCC Interrupt */ 84 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 85 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 86 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 87 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 88 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 89 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ 90 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ 91 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ 92 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ 93 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 94 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 95 TIM6_IRQn = 17, /*!< TIM6 Interrupt */ 96 TIM7_IRQn = 18, /*!< TIM7 Interrupt */ 97 TIM21_IRQn = 20, /*!< TIM21 Interrupt */ 98 I2C3_IRQn = 21, /*!< I2C3 Interrupt */ 99 TIM22_IRQn = 22, /*!< TIM22 Interrupt */ 100 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 101 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 102 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 103 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 104 USART1_IRQn = 27, /*!< USART1 Interrupt */ 105 USART2_IRQn = 28, /*!< USART2 Interrupt */ 106 AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ 107 } IRQn_Type; 108 109 /** 110 * @} 111 */ 112 113 #include "core_cm0plus.h" 114 #include "system_stm32l0xx.h" 115 #include <stdint.h> 116 117 /** @addtogroup Peripheral_registers_structures 118 * @{ 119 */ 120 121 /** 122 * @brief Analog to Digital Converter 123 */ 124 125 typedef struct 126 { 127 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ 128 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ 129 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ 130 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ 131 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ 132 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ 133 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 134 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 135 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ 136 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 137 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ 138 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 139 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ 140 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ 141 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ 142 } ADC_TypeDef; 143 144 typedef struct 145 { 146 __IO uint32_t CCR; 147 } ADC_Common_TypeDef; 148 149 /** 150 * @brief AES hardware accelerator 151 */ 152 153 typedef struct 154 { 155 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 156 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 157 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 158 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 159 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 160 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 161 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 162 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 163 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 164 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 165 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 166 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 167 } AES_TypeDef; 168 169 /** 170 * @brief Comparator 171 */ 172 173 typedef struct 174 { 175 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ 176 } COMP_TypeDef; 177 178 typedef struct 179 { 180 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 181 } COMP_Common_TypeDef; 182 183 184 /** 185 * @brief CRC calculation unit 186 */ 187 188 typedef struct 189 { 190 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 191 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 192 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 193 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 194 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 195 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 196 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 197 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 198 } CRC_TypeDef; 199 200 /** 201 * @brief Debug MCU 202 */ 203 204 typedef struct 205 { 206 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 207 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 208 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 209 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 210 }DBGMCU_TypeDef; 211 212 /** 213 * @brief DMA Controller 214 */ 215 216 typedef struct 217 { 218 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 219 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 220 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 221 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 222 } DMA_Channel_TypeDef; 223 224 typedef struct 225 { 226 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 227 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 228 } DMA_TypeDef; 229 230 typedef struct 231 { 232 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ 233 } DMA_Request_TypeDef; 234 235 /** 236 * @brief External Interrupt/Event Controller 237 */ 238 239 typedef struct 240 { 241 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 242 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 243 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 244 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 245 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 246 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 247 }EXTI_TypeDef; 248 249 /** 250 * @brief FLASH Registers 251 */ 252 typedef struct 253 { 254 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 255 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 256 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 257 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 258 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 259 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 260 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 261 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */ 262 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ 263 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */ 264 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ 265 } FLASH_TypeDef; 266 267 268 /** 269 * @brief Option Bytes Registers 270 */ 271 typedef struct 272 { 273 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 274 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 275 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */ 276 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */ 277 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */ 278 } OB_TypeDef; 279 280 281 /** 282 * @brief General Purpose IO 283 */ 284 285 typedef struct 286 { 287 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 288 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 289 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 290 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 291 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 292 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 293 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 294 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 295 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 296 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 297 }GPIO_TypeDef; 298 299 /** 300 * @brief LPTIMIMER 301 */ 302 typedef struct 303 { 304 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 305 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 306 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 307 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 308 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 309 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 310 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 311 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 312 } LPTIM_TypeDef; 313 314 /** 315 * @brief SysTem Configuration 316 */ 317 318 typedef struct 319 { 320 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 321 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */ 322 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 323 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 324 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */ 325 } SYSCFG_TypeDef; 326 327 328 329 /** 330 * @brief Inter-integrated Circuit Interface 331 */ 332 333 typedef struct 334 { 335 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 336 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 337 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 338 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 339 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 340 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 341 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 342 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 343 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 344 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 345 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 346 }I2C_TypeDef; 347 348 349 /** 350 * @brief Independent WATCHDOG 351 */ 352 typedef struct 353 { 354 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 355 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 356 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 357 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 358 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 359 } IWDG_TypeDef; 360 361 /** 362 * @brief MIFARE Firewall 363 */ 364 typedef struct 365 { 366 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ 367 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ 368 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ 369 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ 370 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ 371 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ 372 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */ 373 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */ 374 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ 375 376 } FIREWALL_TypeDef; 377 378 /** 379 * @brief Power Control 380 */ 381 typedef struct 382 { 383 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 384 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 385 } PWR_TypeDef; 386 387 /** 388 * @brief Reset and Clock Control 389 */ 390 typedef struct 391 { 392 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 393 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 394 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */ 395 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */ 396 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */ 397 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */ 398 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */ 399 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */ 400 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */ 401 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ 402 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */ 403 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */ 404 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */ 405 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */ 406 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */ 407 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */ 408 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */ 409 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */ 410 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */ 411 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */ 412 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ 413 } RCC_TypeDef; 414 415 /** 416 * @brief Real-Time Clock 417 */ 418 typedef struct 419 { 420 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 421 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 422 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 423 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 424 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 425 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 426 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ 427 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 428 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 429 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 430 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 431 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 432 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 433 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 434 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 435 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 436 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ 437 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 438 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 439 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ 440 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 441 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 442 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 443 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 444 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 445 } RTC_TypeDef; 446 447 448 /** 449 * @brief Serial Peripheral Interface 450 */ 451 typedef struct 452 { 453 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 454 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 455 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 456 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 457 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 458 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 459 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 460 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 461 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 462 } SPI_TypeDef; 463 464 /** 465 * @brief TIM 466 */ 467 typedef struct 468 { 469 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 470 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 471 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 472 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 473 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 474 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 475 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 476 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 477 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 478 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 479 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 480 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 481 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */ 482 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 483 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 484 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 485 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 486 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */ 487 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 488 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 489 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 490 } TIM_TypeDef; 491 492 /** 493 * @brief Universal Synchronous Asynchronous Receiver Transmitter 494 */ 495 typedef struct 496 { 497 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 498 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 499 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 500 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 501 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 502 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 503 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 504 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 505 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 506 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 507 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 508 } USART_TypeDef; 509 510 /** 511 * @brief Window WATCHDOG 512 */ 513 typedef struct 514 { 515 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 516 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 517 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 518 } WWDG_TypeDef; 519 520 521 /** 522 * @} 523 */ 524 525 /** @addtogroup Peripheral_memory_map 526 * @{ 527 */ 528 #define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ 529 530 #define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */ 531 #define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */ 532 #define DATA_EEPROM_BANK1_END (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */ 533 #define DATA_EEPROM_BANK2_END (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */ 534 #define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ 535 #define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */ 536 537 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ 538 539 /*!< Peripheral memory map */ 540 #define APBPERIPH_BASE PERIPH_BASE 541 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 542 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL) 543 544 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) 545 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) 546 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) 547 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) 548 #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) 549 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) 550 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) 551 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) 552 #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) 553 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL) 554 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) 555 #define USART5_BASE (APBPERIPH_BASE + 0x00005000UL) 556 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) 557 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) 558 #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) 559 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) 560 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800UL) 561 562 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) 563 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL) 564 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL) 565 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) 566 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL) 567 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL) 568 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL) 569 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL) 570 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) 571 #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) 572 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) 573 #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) 574 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) 575 576 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 577 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) 578 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) 579 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) 580 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) 581 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) 582 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) 583 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) 584 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL) 585 586 587 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 588 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ 589 #define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ 590 #define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */ 591 #define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */ 592 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 593 #define AES_BASE (AHBPERIPH_BASE + 0x00006000UL) 594 595 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL) 596 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL) 597 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL) 598 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL) 599 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL) 600 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL) 601 602 /** 603 * @} 604 */ 605 606 /** @addtogroup Peripheral_declaration 607 * @{ 608 */ 609 610 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 611 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 612 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 613 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 614 #define RTC ((RTC_TypeDef *) RTC_BASE) 615 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 616 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 617 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 618 #define USART2 ((USART_TypeDef *) USART2_BASE) 619 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 620 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 621 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 622 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 623 #define PWR ((PWR_TypeDef *) PWR_BASE) 624 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 625 #define USART4 ((USART_TypeDef *) USART4_BASE) 626 #define USART5 ((USART_TypeDef *) USART5_BASE) 627 628 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 629 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 630 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 631 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 632 #define TIM21 ((TIM_TypeDef *) TIM21_BASE) 633 #define TIM22 ((TIM_TypeDef *) TIM22_BASE) 634 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) 635 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 636 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 637 /* Legacy defines */ 638 #define ADC ADC1_COMMON 639 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 640 #define USART1 ((USART_TypeDef *) USART1_BASE) 641 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 642 643 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 644 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 645 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 646 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 647 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 648 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 649 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 650 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 651 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) 652 653 654 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 655 #define OB ((OB_TypeDef *) OB_BASE) 656 #define RCC ((RCC_TypeDef *) RCC_BASE) 657 #define CRC ((CRC_TypeDef *) CRC_BASE) 658 #define AES ((AES_TypeDef *) AES_BASE) 659 660 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 661 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 662 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 663 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 664 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 665 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 666 667 /** 668 * @} 669 */ 670 671 /** @addtogroup Exported_constants 672 * @{ 673 */ 674 675 /** @addtogroup Hardware_Constant_Definition 676 * @{ 677 */ 678 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */ 679 680 /** 681 * @} 682 */ 683 684 /** @addtogroup Peripheral_Registers_Bits_Definition 685 * @{ 686 */ 687 688 /******************************************************************************/ 689 /* Peripheral Registers Bits Definition */ 690 /******************************************************************************/ 691 /******************************************************************************/ 692 /* */ 693 /* Analog to Digital Converter (ADC) */ 694 /* */ 695 /******************************************************************************/ 696 /******************** Bits definition for ADC_ISR register ******************/ 697 #define ADC_ISR_EOCAL_Pos (11U) 698 #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 699 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ 700 #define ADC_ISR_AWD_Pos (7U) 701 #define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ 702 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ 703 #define ADC_ISR_OVR_Pos (4U) 704 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 705 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ 706 #define ADC_ISR_EOSEQ_Pos (3U) 707 #define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ 708 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ 709 #define ADC_ISR_EOC_Pos (2U) 710 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 711 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ 712 #define ADC_ISR_EOSMP_Pos (1U) 713 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 714 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ 715 #define ADC_ISR_ADRDY_Pos (0U) 716 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 717 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ 718 719 /* Old EOSEQ bit definition, maintained for legacy purpose */ 720 #define ADC_ISR_EOS ADC_ISR_EOSEQ 721 722 /******************** Bits definition for ADC_IER register ******************/ 723 #define ADC_IER_EOCALIE_Pos (11U) 724 #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 725 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ 726 #define ADC_IER_AWDIE_Pos (7U) 727 #define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ 728 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ 729 #define ADC_IER_OVRIE_Pos (4U) 730 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 731 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ 732 #define ADC_IER_EOSEQIE_Pos (3U) 733 #define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ 734 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ 735 #define ADC_IER_EOCIE_Pos (2U) 736 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 737 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ 738 #define ADC_IER_EOSMPIE_Pos (1U) 739 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 740 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ 741 #define ADC_IER_ADRDYIE_Pos (0U) 742 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 743 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ 744 745 /* Old EOSEQIE bit definition, maintained for legacy purpose */ 746 #define ADC_IER_EOSIE ADC_IER_EOSEQIE 747 748 /******************** Bits definition for ADC_CR register *******************/ 749 #define ADC_CR_ADCAL_Pos (31U) 750 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 751 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 752 #define ADC_CR_ADVREGEN_Pos (28U) 753 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 754 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ 755 #define ADC_CR_ADSTP_Pos (4U) 756 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 757 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ 758 #define ADC_CR_ADSTART_Pos (2U) 759 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 760 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ 761 #define ADC_CR_ADDIS_Pos (1U) 762 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 763 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ 764 #define ADC_CR_ADEN_Pos (0U) 765 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 766 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ 767 768 /******************* Bits definition for ADC_CFGR1 register *****************/ 769 #define ADC_CFGR1_AWDCH_Pos (26U) 770 #define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ 771 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ 772 #define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ 773 #define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ 774 #define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ 775 #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ 776 #define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ 777 #define ADC_CFGR1_AWDEN_Pos (23U) 778 #define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ 779 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ 780 #define ADC_CFGR1_AWDSGL_Pos (22U) 781 #define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ 782 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ 783 #define ADC_CFGR1_DISCEN_Pos (16U) 784 #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 785 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ 786 #define ADC_CFGR1_AUTOFF_Pos (15U) 787 #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 788 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ 789 #define ADC_CFGR1_WAIT_Pos (14U) 790 #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 791 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ 792 #define ADC_CFGR1_CONT_Pos (13U) 793 #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 794 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ 795 #define ADC_CFGR1_OVRMOD_Pos (12U) 796 #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 797 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ 798 #define ADC_CFGR1_EXTEN_Pos (10U) 799 #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 800 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ 801 #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 802 #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 803 #define ADC_CFGR1_EXTSEL_Pos (6U) 804 #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 805 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ 806 #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 807 #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 808 #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 809 #define ADC_CFGR1_ALIGN_Pos (5U) 810 #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 811 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ 812 #define ADC_CFGR1_RES_Pos (3U) 813 #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 814 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ 815 #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 816 #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 817 #define ADC_CFGR1_SCANDIR_Pos (2U) 818 #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 819 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ 820 #define ADC_CFGR1_DMACFG_Pos (1U) 821 #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 822 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ 823 #define ADC_CFGR1_DMAEN_Pos (0U) 824 #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 825 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ 826 827 /* Old WAIT bit definition, maintained for legacy purpose */ 828 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT 829 830 /******************* Bits definition for ADC_CFGR2 register *****************/ 831 #define ADC_CFGR2_TOVS_Pos (9U) 832 #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ 833 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ 834 #define ADC_CFGR2_OVSS_Pos (5U) 835 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 836 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ 837 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 838 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 839 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 840 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 841 #define ADC_CFGR2_OVSR_Pos (2U) 842 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 843 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ 844 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 845 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 846 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 847 #define ADC_CFGR2_OVSE_Pos (0U) 848 #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 849 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ 850 #define ADC_CFGR2_CKMODE_Pos (30U) 851 #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 852 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ 853 #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 854 #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 855 856 857 /****************** Bit definition for ADC_SMPR register ********************/ 858 #define ADC_SMPR_SMP_Pos (0U) 859 #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 860 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ 861 #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 862 #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 863 #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 864 865 /* Legacy defines */ 866 #define ADC_SMPR_SMPR ADC_SMPR_SMP 867 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0 868 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1 869 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 870 871 /******************* Bit definition for ADC_TR register ********************/ 872 #define ADC_TR_HT_Pos (16U) 873 #define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ 874 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ 875 #define ADC_TR_LT_Pos (0U) 876 #define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */ 877 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ 878 879 /****************** Bit definition for ADC_CHSELR register ******************/ 880 #define ADC_CHSELR_CHSEL_Pos (0U) 881 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 882 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ 883 #define ADC_CHSELR_CHSEL18_Pos (18U) 884 #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 885 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ 886 #define ADC_CHSELR_CHSEL17_Pos (17U) 887 #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 888 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ 889 #define ADC_CHSELR_CHSEL15_Pos (15U) 890 #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 891 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ 892 #define ADC_CHSELR_CHSEL14_Pos (14U) 893 #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 894 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ 895 #define ADC_CHSELR_CHSEL13_Pos (13U) 896 #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 897 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ 898 #define ADC_CHSELR_CHSEL12_Pos (12U) 899 #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 900 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ 901 #define ADC_CHSELR_CHSEL11_Pos (11U) 902 #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 903 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ 904 #define ADC_CHSELR_CHSEL10_Pos (10U) 905 #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 906 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ 907 #define ADC_CHSELR_CHSEL9_Pos (9U) 908 #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 909 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ 910 #define ADC_CHSELR_CHSEL8_Pos (8U) 911 #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 912 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ 913 #define ADC_CHSELR_CHSEL7_Pos (7U) 914 #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 915 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ 916 #define ADC_CHSELR_CHSEL6_Pos (6U) 917 #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 918 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ 919 #define ADC_CHSELR_CHSEL5_Pos (5U) 920 #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 921 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ 922 #define ADC_CHSELR_CHSEL4_Pos (4U) 923 #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 924 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ 925 #define ADC_CHSELR_CHSEL3_Pos (3U) 926 #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 927 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ 928 #define ADC_CHSELR_CHSEL2_Pos (2U) 929 #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 930 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ 931 #define ADC_CHSELR_CHSEL1_Pos (1U) 932 #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 933 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ 934 #define ADC_CHSELR_CHSEL0_Pos (0U) 935 #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 936 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ 937 938 /******************** Bit definition for ADC_DR register ********************/ 939 #define ADC_DR_DATA_Pos (0U) 940 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 941 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ 942 943 /******************** Bit definition for ADC_CALFACT register ********************/ 944 #define ADC_CALFACT_CALFACT_Pos (0U) 945 #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 946 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ 947 948 /******************* Bit definition for ADC_CCR register ********************/ 949 #define ADC_CCR_LFMEN_Pos (25U) 950 #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ 951 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ 952 #define ADC_CCR_TSEN_Pos (23U) 953 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 954 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ 955 #define ADC_CCR_VREFEN_Pos (22U) 956 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 957 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ 958 #define ADC_CCR_PRESC_Pos (18U) 959 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 960 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ 961 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 962 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 963 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 964 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 965 966 /******************************************************************************/ 967 /* */ 968 /* Advanced Encryption Standard (AES) */ 969 /* */ 970 /******************************************************************************/ 971 /******************* Bit definition for AES_CR register *********************/ 972 #define AES_CR_EN_Pos (0U) 973 #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ 974 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 975 #define AES_CR_DATATYPE_Pos (1U) 976 #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 977 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 978 #define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 979 #define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 980 981 #define AES_CR_MODE_Pos (3U) 982 #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ 983 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 984 #define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ 985 #define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ 986 987 #define AES_CR_CHMOD_Pos (5U) 988 #define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */ 989 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 990 #define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 991 #define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 992 993 #define AES_CR_CCFC_Pos (7U) 994 #define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 995 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 996 #define AES_CR_ERRC_Pos (8U) 997 #define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 998 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 999 #define AES_CR_CCIE_Pos (9U) 1000 #define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */ 1001 #define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */ 1002 #define AES_CR_ERRIE_Pos (10U) 1003 #define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 1004 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 1005 #define AES_CR_DMAINEN_Pos (11U) 1006 #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 1007 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */ 1008 #define AES_CR_DMAOUTEN_Pos (12U) 1009 #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 1010 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */ 1011 1012 /******************* Bit definition for AES_SR register *********************/ 1013 #define AES_SR_CCF_Pos (0U) 1014 #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ 1015 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 1016 #define AES_SR_RDERR_Pos (1U) 1017 #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 1018 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 1019 #define AES_SR_WRERR_Pos (2U) 1020 #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 1021 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 1022 1023 /******************* Bit definition for AES_DINR register *******************/ 1024 #define AES_DINR_Pos (0U) 1025 #define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */ 1026 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 1027 1028 /******************* Bit definition for AES_DOUTR register ******************/ 1029 #define AES_DOUTR_Pos (0U) 1030 #define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */ 1031 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 1032 1033 /******************* Bit definition for AES_KEYR0 register ******************/ 1034 #define AES_KEYR0_Pos (0U) 1035 #define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */ 1036 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 1037 1038 /******************* Bit definition for AES_KEYR1 register ******************/ 1039 #define AES_KEYR1_Pos (0U) 1040 #define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */ 1041 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 1042 1043 /******************* Bit definition for AES_KEYR2 register ******************/ 1044 #define AES_KEYR2_Pos (0U) 1045 #define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */ 1046 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 1047 1048 /******************* Bit definition for AES_KEYR3 register ******************/ 1049 #define AES_KEYR3_Pos (0U) 1050 #define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */ 1051 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 1052 1053 /******************* Bit definition for AES_IVR0 register *******************/ 1054 #define AES_IVR0_Pos (0U) 1055 #define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */ 1056 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 1057 1058 /******************* Bit definition for AES_IVR1 register *******************/ 1059 #define AES_IVR1_Pos (0U) 1060 #define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */ 1061 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 1062 1063 /******************* Bit definition for AES_IVR2 register *******************/ 1064 #define AES_IVR2_Pos (0U) 1065 #define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */ 1066 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 1067 1068 /******************* Bit definition for AES_IVR3 register *******************/ 1069 #define AES_IVR3_Pos (0U) 1070 #define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */ 1071 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 1072 1073 /******************************************************************************/ 1074 /* */ 1075 /* Analog Comparators (COMP) */ 1076 /* */ 1077 /******************************************************************************/ 1078 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ 1079 /* COMP1 bits definition */ 1080 #define COMP_CSR_COMP1EN_Pos (0U) 1081 #define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ 1082 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ 1083 #define COMP_CSR_COMP1INNSEL_Pos (4U) 1084 #define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ 1085 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ 1086 #define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ 1087 #define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ 1088 #define COMP_CSR_COMP1WM_Pos (8U) 1089 #define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ 1090 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ 1091 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) 1092 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ 1093 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ 1094 #define COMP_CSR_COMP1POLARITY_Pos (15U) 1095 #define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ 1096 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ 1097 #define COMP_CSR_COMP1VALUE_Pos (30U) 1098 #define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ 1099 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ 1100 #define COMP_CSR_COMP1LOCK_Pos (31U) 1101 #define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ 1102 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ 1103 /* COMP2 bits definition */ 1104 #define COMP_CSR_COMP2EN_Pos (0U) 1105 #define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ 1106 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ 1107 #define COMP_CSR_COMP2SPEED_Pos (3U) 1108 #define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ 1109 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ 1110 #define COMP_CSR_COMP2INNSEL_Pos (4U) 1111 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ 1112 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ 1113 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ 1114 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ 1115 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ 1116 #define COMP_CSR_COMP2INPSEL_Pos (8U) 1117 #define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ 1118 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ 1119 #define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ 1120 #define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ 1121 #define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ 1122 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) 1123 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ 1124 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ 1125 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) 1126 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ 1127 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ 1128 #define COMP_CSR_COMP2POLARITY_Pos (15U) 1129 #define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ 1130 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ 1131 #define COMP_CSR_COMP2VALUE_Pos (30U) 1132 #define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ 1133 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ 1134 #define COMP_CSR_COMP2LOCK_Pos (31U) 1135 #define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 1136 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 1137 1138 /********************** Bit definition for COMP_CSR register common ****************/ 1139 #define COMP_CSR_COMPxEN_Pos (0U) 1140 #define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 1141 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 1142 #define COMP_CSR_COMPxPOLARITY_Pos (15U) 1143 #define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ 1144 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ 1145 #define COMP_CSR_COMPxOUTVALUE_Pos (30U) 1146 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ 1147 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ 1148 #define COMP_CSR_COMPxLOCK_Pos (31U) 1149 #define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ 1150 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 1151 1152 /* Reference defines */ 1153 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1154 1155 /******************************************************************************/ 1156 /* */ 1157 /* CRC calculation unit (CRC) */ 1158 /* */ 1159 /******************************************************************************/ 1160 /******************* Bit definition for CRC_DR register *********************/ 1161 #define CRC_DR_DR_Pos (0U) 1162 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1163 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1164 1165 /******************* Bit definition for CRC_IDR register ********************/ 1166 #define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */ 1167 1168 /******************** Bit definition for CRC_CR register ********************/ 1169 #define CRC_CR_RESET_Pos (0U) 1170 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1171 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1172 #define CRC_CR_POLYSIZE_Pos (3U) 1173 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 1174 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 1175 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 1176 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 1177 #define CRC_CR_REV_IN_Pos (5U) 1178 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1179 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1180 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1181 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1182 #define CRC_CR_REV_OUT_Pos (7U) 1183 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1184 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1185 1186 /******************* Bit definition for CRC_INIT register *******************/ 1187 #define CRC_INIT_INIT_Pos (0U) 1188 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1189 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1190 1191 /******************* Bit definition for CRC_POL register ********************/ 1192 #define CRC_POL_POL_Pos (0U) 1193 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 1194 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 1195 1196 /******************************************************************************/ 1197 /* */ 1198 /* Debug MCU (DBGMCU) */ 1199 /* */ 1200 /******************************************************************************/ 1201 1202 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 1203 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 1204 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1205 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 1206 1207 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 1208 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1209 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 1210 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 1211 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 1212 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 1213 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 1214 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 1215 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 1216 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 1217 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 1218 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 1219 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 1220 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 1221 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 1222 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 1223 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 1224 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 1225 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 1226 1227 /****************** Bit definition for DBGMCU_CR register *******************/ 1228 #define DBGMCU_CR_DBG_Pos (0U) 1229 #define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ 1230 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ 1231 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 1232 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 1233 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 1234 #define DBGMCU_CR_DBG_STOP_Pos (1U) 1235 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1236 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 1237 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 1238 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1239 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 1240 1241 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 1242 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 1243 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 1244 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 1245 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 1246 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 1247 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 1248 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 1249 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 1250 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 1251 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 1252 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 1253 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 1254 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 1255 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 1256 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 1257 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 1258 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1259 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 1260 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 1261 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1262 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 1263 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) 1264 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 1265 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 1266 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U) 1267 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ 1268 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 1269 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U) 1270 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ 1271 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ 1272 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) 1273 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ 1274 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ 1275 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 1276 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) 1277 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ 1278 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ 1279 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) 1280 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ 1281 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ 1282 1283 /******************************************************************************/ 1284 /* */ 1285 /* DMA Controller (DMA) */ 1286 /* */ 1287 /******************************************************************************/ 1288 1289 /******************* Bit definition for DMA_ISR register ********************/ 1290 #define DMA_ISR_GIF1_Pos (0U) 1291 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1292 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1293 #define DMA_ISR_TCIF1_Pos (1U) 1294 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1295 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1296 #define DMA_ISR_HTIF1_Pos (2U) 1297 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1298 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1299 #define DMA_ISR_TEIF1_Pos (3U) 1300 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1301 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1302 #define DMA_ISR_GIF2_Pos (4U) 1303 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1304 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1305 #define DMA_ISR_TCIF2_Pos (5U) 1306 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1307 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1308 #define DMA_ISR_HTIF2_Pos (6U) 1309 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1310 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1311 #define DMA_ISR_TEIF2_Pos (7U) 1312 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1313 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1314 #define DMA_ISR_GIF3_Pos (8U) 1315 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1316 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1317 #define DMA_ISR_TCIF3_Pos (9U) 1318 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1319 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1320 #define DMA_ISR_HTIF3_Pos (10U) 1321 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1322 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1323 #define DMA_ISR_TEIF3_Pos (11U) 1324 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1325 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1326 #define DMA_ISR_GIF4_Pos (12U) 1327 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1328 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1329 #define DMA_ISR_TCIF4_Pos (13U) 1330 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1331 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1332 #define DMA_ISR_HTIF4_Pos (14U) 1333 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1334 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1335 #define DMA_ISR_TEIF4_Pos (15U) 1336 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1337 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1338 #define DMA_ISR_GIF5_Pos (16U) 1339 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1340 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1341 #define DMA_ISR_TCIF5_Pos (17U) 1342 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1343 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1344 #define DMA_ISR_HTIF5_Pos (18U) 1345 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1346 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1347 #define DMA_ISR_TEIF5_Pos (19U) 1348 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1349 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1350 #define DMA_ISR_GIF6_Pos (20U) 1351 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 1352 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 1353 #define DMA_ISR_TCIF6_Pos (21U) 1354 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 1355 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 1356 #define DMA_ISR_HTIF6_Pos (22U) 1357 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 1358 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 1359 #define DMA_ISR_TEIF6_Pos (23U) 1360 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 1361 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 1362 #define DMA_ISR_GIF7_Pos (24U) 1363 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 1364 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 1365 #define DMA_ISR_TCIF7_Pos (25U) 1366 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 1367 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 1368 #define DMA_ISR_HTIF7_Pos (26U) 1369 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 1370 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 1371 #define DMA_ISR_TEIF7_Pos (27U) 1372 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 1373 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 1374 1375 /******************* Bit definition for DMA_IFCR register *******************/ 1376 #define DMA_IFCR_CGIF1_Pos (0U) 1377 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1378 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1379 #define DMA_IFCR_CTCIF1_Pos (1U) 1380 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1381 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1382 #define DMA_IFCR_CHTIF1_Pos (2U) 1383 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1384 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1385 #define DMA_IFCR_CTEIF1_Pos (3U) 1386 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1387 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1388 #define DMA_IFCR_CGIF2_Pos (4U) 1389 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1390 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1391 #define DMA_IFCR_CTCIF2_Pos (5U) 1392 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1393 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1394 #define DMA_IFCR_CHTIF2_Pos (6U) 1395 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1396 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1397 #define DMA_IFCR_CTEIF2_Pos (7U) 1398 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1399 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1400 #define DMA_IFCR_CGIF3_Pos (8U) 1401 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1402 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1403 #define DMA_IFCR_CTCIF3_Pos (9U) 1404 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1405 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1406 #define DMA_IFCR_CHTIF3_Pos (10U) 1407 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1408 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1409 #define DMA_IFCR_CTEIF3_Pos (11U) 1410 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1411 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1412 #define DMA_IFCR_CGIF4_Pos (12U) 1413 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1414 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1415 #define DMA_IFCR_CTCIF4_Pos (13U) 1416 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1417 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1418 #define DMA_IFCR_CHTIF4_Pos (14U) 1419 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1420 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1421 #define DMA_IFCR_CTEIF4_Pos (15U) 1422 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1423 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1424 #define DMA_IFCR_CGIF5_Pos (16U) 1425 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1426 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1427 #define DMA_IFCR_CTCIF5_Pos (17U) 1428 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1429 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1430 #define DMA_IFCR_CHTIF5_Pos (18U) 1431 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1432 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1433 #define DMA_IFCR_CTEIF5_Pos (19U) 1434 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1435 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1436 #define DMA_IFCR_CGIF6_Pos (20U) 1437 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 1438 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 1439 #define DMA_IFCR_CTCIF6_Pos (21U) 1440 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 1441 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 1442 #define DMA_IFCR_CHTIF6_Pos (22U) 1443 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 1444 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 1445 #define DMA_IFCR_CTEIF6_Pos (23U) 1446 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 1447 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 1448 #define DMA_IFCR_CGIF7_Pos (24U) 1449 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 1450 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 1451 #define DMA_IFCR_CTCIF7_Pos (25U) 1452 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 1453 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 1454 #define DMA_IFCR_CHTIF7_Pos (26U) 1455 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 1456 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 1457 #define DMA_IFCR_CTEIF7_Pos (27U) 1458 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 1459 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 1460 1461 /******************* Bit definition for DMA_CCR register ********************/ 1462 #define DMA_CCR_EN_Pos (0U) 1463 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1464 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1465 #define DMA_CCR_TCIE_Pos (1U) 1466 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1467 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1468 #define DMA_CCR_HTIE_Pos (2U) 1469 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1470 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1471 #define DMA_CCR_TEIE_Pos (3U) 1472 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1473 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1474 #define DMA_CCR_DIR_Pos (4U) 1475 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1476 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1477 #define DMA_CCR_CIRC_Pos (5U) 1478 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1479 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1480 #define DMA_CCR_PINC_Pos (6U) 1481 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1482 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1483 #define DMA_CCR_MINC_Pos (7U) 1484 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1485 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1486 1487 #define DMA_CCR_PSIZE_Pos (8U) 1488 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1489 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1490 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1491 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1492 1493 #define DMA_CCR_MSIZE_Pos (10U) 1494 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1495 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1496 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1497 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1498 1499 #define DMA_CCR_PL_Pos (12U) 1500 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1501 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1502 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1503 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1504 1505 #define DMA_CCR_MEM2MEM_Pos (14U) 1506 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1507 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1508 1509 /****************** Bit definition for DMA_CNDTR register *******************/ 1510 #define DMA_CNDTR_NDT_Pos (0U) 1511 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1512 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1513 1514 /****************** Bit definition for DMA_CPAR register ********************/ 1515 #define DMA_CPAR_PA_Pos (0U) 1516 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1517 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1518 1519 /****************** Bit definition for DMA_CMAR register ********************/ 1520 #define DMA_CMAR_MA_Pos (0U) 1521 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1522 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1523 1524 1525 /******************* Bit definition for DMA_CSELR register *******************/ 1526 #define DMA_CSELR_C1S_Pos (0U) 1527 #define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ 1528 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ 1529 #define DMA_CSELR_C2S_Pos (4U) 1530 #define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ 1531 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ 1532 #define DMA_CSELR_C3S_Pos (8U) 1533 #define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ 1534 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ 1535 #define DMA_CSELR_C4S_Pos (12U) 1536 #define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ 1537 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ 1538 #define DMA_CSELR_C5S_Pos (16U) 1539 #define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ 1540 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ 1541 #define DMA_CSELR_C6S_Pos (20U) 1542 #define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ 1543 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ 1544 #define DMA_CSELR_C7S_Pos (24U) 1545 #define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ 1546 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ 1547 1548 /******************************************************************************/ 1549 /* */ 1550 /* External Interrupt/Event Controller (EXTI) */ 1551 /* */ 1552 /******************************************************************************/ 1553 1554 /******************* Bit definition for EXTI_IMR register *******************/ 1555 #define EXTI_IMR_IM0_Pos (0U) 1556 #define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ 1557 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ 1558 #define EXTI_IMR_IM1_Pos (1U) 1559 #define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ 1560 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ 1561 #define EXTI_IMR_IM2_Pos (2U) 1562 #define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ 1563 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ 1564 #define EXTI_IMR_IM3_Pos (3U) 1565 #define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ 1566 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ 1567 #define EXTI_IMR_IM4_Pos (4U) 1568 #define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ 1569 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ 1570 #define EXTI_IMR_IM5_Pos (5U) 1571 #define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ 1572 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ 1573 #define EXTI_IMR_IM6_Pos (6U) 1574 #define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ 1575 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ 1576 #define EXTI_IMR_IM7_Pos (7U) 1577 #define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ 1578 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ 1579 #define EXTI_IMR_IM8_Pos (8U) 1580 #define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ 1581 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ 1582 #define EXTI_IMR_IM9_Pos (9U) 1583 #define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ 1584 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ 1585 #define EXTI_IMR_IM10_Pos (10U) 1586 #define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ 1587 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ 1588 #define EXTI_IMR_IM11_Pos (11U) 1589 #define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ 1590 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ 1591 #define EXTI_IMR_IM12_Pos (12U) 1592 #define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ 1593 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ 1594 #define EXTI_IMR_IM13_Pos (13U) 1595 #define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ 1596 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ 1597 #define EXTI_IMR_IM14_Pos (14U) 1598 #define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ 1599 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ 1600 #define EXTI_IMR_IM15_Pos (15U) 1601 #define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ 1602 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ 1603 #define EXTI_IMR_IM16_Pos (16U) 1604 #define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ 1605 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ 1606 #define EXTI_IMR_IM17_Pos (17U) 1607 #define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ 1608 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ 1609 #define EXTI_IMR_IM18_Pos (18U) 1610 #define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ 1611 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ 1612 #define EXTI_IMR_IM19_Pos (19U) 1613 #define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ 1614 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ 1615 #define EXTI_IMR_IM20_Pos (20U) 1616 #define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ 1617 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ 1618 #define EXTI_IMR_IM21_Pos (21U) 1619 #define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ 1620 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ 1621 #define EXTI_IMR_IM22_Pos (22U) 1622 #define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ 1623 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ 1624 #define EXTI_IMR_IM23_Pos (23U) 1625 #define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ 1626 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ 1627 #define EXTI_IMR_IM24_Pos (24U) 1628 #define EXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */ 1629 #define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */ 1630 #define EXTI_IMR_IM25_Pos (25U) 1631 #define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ 1632 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ 1633 #define EXTI_IMR_IM26_Pos (26U) 1634 #define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ 1635 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ 1636 #define EXTI_IMR_IM28_Pos (28U) 1637 #define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ 1638 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ 1639 #define EXTI_IMR_IM29_Pos (29U) 1640 #define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ 1641 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ 1642 1643 #define EXTI_IMR_IM_Pos (0U) 1644 #define EXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */ 1645 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1646 1647 /****************** Bit definition for EXTI_EMR register ********************/ 1648 #define EXTI_EMR_EM0_Pos (0U) 1649 #define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ 1650 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ 1651 #define EXTI_EMR_EM1_Pos (1U) 1652 #define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ 1653 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ 1654 #define EXTI_EMR_EM2_Pos (2U) 1655 #define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ 1656 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ 1657 #define EXTI_EMR_EM3_Pos (3U) 1658 #define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ 1659 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ 1660 #define EXTI_EMR_EM4_Pos (4U) 1661 #define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ 1662 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ 1663 #define EXTI_EMR_EM5_Pos (5U) 1664 #define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ 1665 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ 1666 #define EXTI_EMR_EM6_Pos (6U) 1667 #define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ 1668 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ 1669 #define EXTI_EMR_EM7_Pos (7U) 1670 #define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ 1671 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ 1672 #define EXTI_EMR_EM8_Pos (8U) 1673 #define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ 1674 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ 1675 #define EXTI_EMR_EM9_Pos (9U) 1676 #define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ 1677 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ 1678 #define EXTI_EMR_EM10_Pos (10U) 1679 #define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ 1680 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ 1681 #define EXTI_EMR_EM11_Pos (11U) 1682 #define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ 1683 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ 1684 #define EXTI_EMR_EM12_Pos (12U) 1685 #define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ 1686 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ 1687 #define EXTI_EMR_EM13_Pos (13U) 1688 #define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ 1689 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ 1690 #define EXTI_EMR_EM14_Pos (14U) 1691 #define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ 1692 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ 1693 #define EXTI_EMR_EM15_Pos (15U) 1694 #define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ 1695 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ 1696 #define EXTI_EMR_EM16_Pos (16U) 1697 #define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ 1698 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ 1699 #define EXTI_EMR_EM17_Pos (17U) 1700 #define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ 1701 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ 1702 #define EXTI_EMR_EM18_Pos (18U) 1703 #define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ 1704 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ 1705 #define EXTI_EMR_EM19_Pos (19U) 1706 #define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ 1707 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ 1708 #define EXTI_EMR_EM20_Pos (20U) 1709 #define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ 1710 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ 1711 #define EXTI_EMR_EM21_Pos (21U) 1712 #define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ 1713 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ 1714 #define EXTI_EMR_EM22_Pos (22U) 1715 #define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ 1716 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ 1717 #define EXTI_EMR_EM23_Pos (23U) 1718 #define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ 1719 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ 1720 #define EXTI_EMR_EM24_Pos (24U) 1721 #define EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */ 1722 #define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */ 1723 #define EXTI_EMR_EM25_Pos (25U) 1724 #define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ 1725 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ 1726 #define EXTI_EMR_EM26_Pos (26U) 1727 #define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ 1728 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ 1729 #define EXTI_EMR_EM28_Pos (28U) 1730 #define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ 1731 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ 1732 #define EXTI_EMR_EM29_Pos (29U) 1733 #define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ 1734 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ 1735 1736 /******************* Bit definition for EXTI_RTSR register ******************/ 1737 #define EXTI_RTSR_RT0_Pos (0U) 1738 #define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ 1739 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1740 #define EXTI_RTSR_RT1_Pos (1U) 1741 #define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ 1742 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1743 #define EXTI_RTSR_RT2_Pos (2U) 1744 #define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ 1745 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1746 #define EXTI_RTSR_RT3_Pos (3U) 1747 #define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ 1748 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1749 #define EXTI_RTSR_RT4_Pos (4U) 1750 #define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ 1751 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1752 #define EXTI_RTSR_RT5_Pos (5U) 1753 #define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ 1754 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1755 #define EXTI_RTSR_RT6_Pos (6U) 1756 #define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ 1757 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1758 #define EXTI_RTSR_RT7_Pos (7U) 1759 #define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ 1760 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1761 #define EXTI_RTSR_RT8_Pos (8U) 1762 #define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ 1763 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1764 #define EXTI_RTSR_RT9_Pos (9U) 1765 #define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ 1766 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1767 #define EXTI_RTSR_RT10_Pos (10U) 1768 #define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ 1769 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1770 #define EXTI_RTSR_RT11_Pos (11U) 1771 #define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ 1772 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1773 #define EXTI_RTSR_RT12_Pos (12U) 1774 #define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ 1775 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1776 #define EXTI_RTSR_RT13_Pos (13U) 1777 #define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ 1778 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1779 #define EXTI_RTSR_RT14_Pos (14U) 1780 #define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ 1781 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1782 #define EXTI_RTSR_RT15_Pos (15U) 1783 #define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ 1784 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1785 #define EXTI_RTSR_RT16_Pos (16U) 1786 #define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ 1787 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1788 #define EXTI_RTSR_RT17_Pos (17U) 1789 #define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ 1790 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1791 #define EXTI_RTSR_RT19_Pos (19U) 1792 #define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ 1793 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1794 #define EXTI_RTSR_RT20_Pos (20U) 1795 #define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ 1796 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 1797 #define EXTI_RTSR_RT21_Pos (21U) 1798 #define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ 1799 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 1800 #define EXTI_RTSR_RT22_Pos (22U) 1801 #define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ 1802 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 1803 1804 /* Legacy defines */ 1805 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 1806 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1 1807 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2 1808 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3 1809 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4 1810 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5 1811 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6 1812 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7 1813 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8 1814 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9 1815 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10 1816 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11 1817 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12 1818 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13 1819 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14 1820 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15 1821 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16 1822 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17 1823 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19 1824 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20 1825 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21 1826 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 1827 1828 /******************* Bit definition for EXTI_FTSR register *******************/ 1829 #define EXTI_FTSR_FT0_Pos (0U) 1830 #define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ 1831 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1832 #define EXTI_FTSR_FT1_Pos (1U) 1833 #define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ 1834 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1835 #define EXTI_FTSR_FT2_Pos (2U) 1836 #define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ 1837 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1838 #define EXTI_FTSR_FT3_Pos (3U) 1839 #define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ 1840 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1841 #define EXTI_FTSR_FT4_Pos (4U) 1842 #define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ 1843 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1844 #define EXTI_FTSR_FT5_Pos (5U) 1845 #define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ 1846 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1847 #define EXTI_FTSR_FT6_Pos (6U) 1848 #define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ 1849 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1850 #define EXTI_FTSR_FT7_Pos (7U) 1851 #define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ 1852 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1853 #define EXTI_FTSR_FT8_Pos (8U) 1854 #define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ 1855 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1856 #define EXTI_FTSR_FT9_Pos (9U) 1857 #define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ 1858 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1859 #define EXTI_FTSR_FT10_Pos (10U) 1860 #define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ 1861 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1862 #define EXTI_FTSR_FT11_Pos (11U) 1863 #define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ 1864 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1865 #define EXTI_FTSR_FT12_Pos (12U) 1866 #define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ 1867 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1868 #define EXTI_FTSR_FT13_Pos (13U) 1869 #define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ 1870 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1871 #define EXTI_FTSR_FT14_Pos (14U) 1872 #define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ 1873 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1874 #define EXTI_FTSR_FT15_Pos (15U) 1875 #define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ 1876 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1877 #define EXTI_FTSR_FT16_Pos (16U) 1878 #define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ 1879 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1880 #define EXTI_FTSR_FT17_Pos (17U) 1881 #define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ 1882 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1883 #define EXTI_FTSR_FT19_Pos (19U) 1884 #define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ 1885 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1886 #define EXTI_FTSR_FT20_Pos (20U) 1887 #define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ 1888 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 1889 #define EXTI_FTSR_FT21_Pos (21U) 1890 #define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ 1891 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 1892 #define EXTI_FTSR_FT22_Pos (22U) 1893 #define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ 1894 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 1895 1896 /* Legacy defines */ 1897 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 1898 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1 1899 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2 1900 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3 1901 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4 1902 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5 1903 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6 1904 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7 1905 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8 1906 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9 1907 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10 1908 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11 1909 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12 1910 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13 1911 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14 1912 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15 1913 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16 1914 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17 1915 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19 1916 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20 1917 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21 1918 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 1919 1920 /******************* Bit definition for EXTI_SWIER register *******************/ 1921 #define EXTI_SWIER_SWI0_Pos (0U) 1922 #define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ 1923 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ 1924 #define EXTI_SWIER_SWI1_Pos (1U) 1925 #define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ 1926 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ 1927 #define EXTI_SWIER_SWI2_Pos (2U) 1928 #define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ 1929 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ 1930 #define EXTI_SWIER_SWI3_Pos (3U) 1931 #define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ 1932 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ 1933 #define EXTI_SWIER_SWI4_Pos (4U) 1934 #define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ 1935 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ 1936 #define EXTI_SWIER_SWI5_Pos (5U) 1937 #define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ 1938 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ 1939 #define EXTI_SWIER_SWI6_Pos (6U) 1940 #define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ 1941 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ 1942 #define EXTI_SWIER_SWI7_Pos (7U) 1943 #define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ 1944 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ 1945 #define EXTI_SWIER_SWI8_Pos (8U) 1946 #define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ 1947 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ 1948 #define EXTI_SWIER_SWI9_Pos (9U) 1949 #define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ 1950 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ 1951 #define EXTI_SWIER_SWI10_Pos (10U) 1952 #define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ 1953 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ 1954 #define EXTI_SWIER_SWI11_Pos (11U) 1955 #define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ 1956 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ 1957 #define EXTI_SWIER_SWI12_Pos (12U) 1958 #define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ 1959 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ 1960 #define EXTI_SWIER_SWI13_Pos (13U) 1961 #define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ 1962 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ 1963 #define EXTI_SWIER_SWI14_Pos (14U) 1964 #define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ 1965 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ 1966 #define EXTI_SWIER_SWI15_Pos (15U) 1967 #define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ 1968 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ 1969 #define EXTI_SWIER_SWI16_Pos (16U) 1970 #define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ 1971 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ 1972 #define EXTI_SWIER_SWI17_Pos (17U) 1973 #define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ 1974 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ 1975 #define EXTI_SWIER_SWI19_Pos (19U) 1976 #define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ 1977 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ 1978 #define EXTI_SWIER_SWI20_Pos (20U) 1979 #define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ 1980 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ 1981 #define EXTI_SWIER_SWI21_Pos (21U) 1982 #define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ 1983 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ 1984 #define EXTI_SWIER_SWI22_Pos (22U) 1985 #define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ 1986 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ 1987 1988 /* Legacy defines */ 1989 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 1990 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1 1991 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2 1992 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3 1993 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4 1994 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5 1995 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6 1996 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7 1997 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8 1998 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9 1999 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10 2000 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11 2001 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12 2002 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13 2003 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14 2004 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15 2005 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16 2006 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17 2007 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19 2008 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20 2009 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21 2010 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 2011 2012 /****************** Bit definition for EXTI_PR register *********************/ 2013 #define EXTI_PR_PIF0_Pos (0U) 2014 #define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ 2015 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ 2016 #define EXTI_PR_PIF1_Pos (1U) 2017 #define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ 2018 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ 2019 #define EXTI_PR_PIF2_Pos (2U) 2020 #define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ 2021 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ 2022 #define EXTI_PR_PIF3_Pos (3U) 2023 #define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ 2024 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ 2025 #define EXTI_PR_PIF4_Pos (4U) 2026 #define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ 2027 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ 2028 #define EXTI_PR_PIF5_Pos (5U) 2029 #define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ 2030 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ 2031 #define EXTI_PR_PIF6_Pos (6U) 2032 #define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ 2033 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ 2034 #define EXTI_PR_PIF7_Pos (7U) 2035 #define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ 2036 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ 2037 #define EXTI_PR_PIF8_Pos (8U) 2038 #define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ 2039 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ 2040 #define EXTI_PR_PIF9_Pos (9U) 2041 #define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ 2042 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ 2043 #define EXTI_PR_PIF10_Pos (10U) 2044 #define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ 2045 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ 2046 #define EXTI_PR_PIF11_Pos (11U) 2047 #define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ 2048 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ 2049 #define EXTI_PR_PIF12_Pos (12U) 2050 #define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ 2051 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ 2052 #define EXTI_PR_PIF13_Pos (13U) 2053 #define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ 2054 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ 2055 #define EXTI_PR_PIF14_Pos (14U) 2056 #define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ 2057 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ 2058 #define EXTI_PR_PIF15_Pos (15U) 2059 #define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ 2060 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ 2061 #define EXTI_PR_PIF16_Pos (16U) 2062 #define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ 2063 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ 2064 #define EXTI_PR_PIF17_Pos (17U) 2065 #define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ 2066 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ 2067 #define EXTI_PR_PIF19_Pos (19U) 2068 #define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ 2069 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ 2070 #define EXTI_PR_PIF20_Pos (20U) 2071 #define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ 2072 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ 2073 #define EXTI_PR_PIF21_Pos (21U) 2074 #define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ 2075 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ 2076 #define EXTI_PR_PIF22_Pos (22U) 2077 #define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ 2078 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ 2079 2080 /* Legacy defines */ 2081 #define EXTI_PR_PR0 EXTI_PR_PIF0 2082 #define EXTI_PR_PR1 EXTI_PR_PIF1 2083 #define EXTI_PR_PR2 EXTI_PR_PIF2 2084 #define EXTI_PR_PR3 EXTI_PR_PIF3 2085 #define EXTI_PR_PR4 EXTI_PR_PIF4 2086 #define EXTI_PR_PR5 EXTI_PR_PIF5 2087 #define EXTI_PR_PR6 EXTI_PR_PIF6 2088 #define EXTI_PR_PR7 EXTI_PR_PIF7 2089 #define EXTI_PR_PR8 EXTI_PR_PIF8 2090 #define EXTI_PR_PR9 EXTI_PR_PIF9 2091 #define EXTI_PR_PR10 EXTI_PR_PIF10 2092 #define EXTI_PR_PR11 EXTI_PR_PIF11 2093 #define EXTI_PR_PR12 EXTI_PR_PIF12 2094 #define EXTI_PR_PR13 EXTI_PR_PIF13 2095 #define EXTI_PR_PR14 EXTI_PR_PIF14 2096 #define EXTI_PR_PR15 EXTI_PR_PIF15 2097 #define EXTI_PR_PR16 EXTI_PR_PIF16 2098 #define EXTI_PR_PR17 EXTI_PR_PIF17 2099 #define EXTI_PR_PR19 EXTI_PR_PIF19 2100 #define EXTI_PR_PR20 EXTI_PR_PIF20 2101 #define EXTI_PR_PR21 EXTI_PR_PIF21 2102 #define EXTI_PR_PR22 EXTI_PR_PIF22 2103 2104 /******************************************************************************/ 2105 /* */ 2106 /* FLASH and Option Bytes Registers */ 2107 /* */ 2108 /******************************************************************************/ 2109 2110 /******************* Bit definition for FLASH_ACR register ******************/ 2111 #define FLASH_ACR_LATENCY_Pos (0U) 2112 #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2113 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 2114 #define FLASH_ACR_PRFTEN_Pos (1U) 2115 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 2116 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 2117 #define FLASH_ACR_SLEEP_PD_Pos (3U) 2118 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 2119 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 2120 #define FLASH_ACR_RUN_PD_Pos (4U) 2121 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 2122 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 2123 #define FLASH_ACR_DISAB_BUF_Pos (5U) 2124 #define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ 2125 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ 2126 #define FLASH_ACR_PRE_READ_Pos (6U) 2127 #define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ 2128 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ 2129 2130 /******************* Bit definition for FLASH_PECR register ******************/ 2131 #define FLASH_PECR_PELOCK_Pos (0U) 2132 #define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 2133 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 2134 #define FLASH_PECR_PRGLOCK_Pos (1U) 2135 #define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 2136 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 2137 #define FLASH_PECR_OPTLOCK_Pos (2U) 2138 #define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 2139 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 2140 #define FLASH_PECR_PROG_Pos (3U) 2141 #define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 2142 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 2143 #define FLASH_PECR_DATA_Pos (4U) 2144 #define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 2145 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 2146 #define FLASH_PECR_FIX_Pos (8U) 2147 #define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ 2148 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 2149 #define FLASH_PECR_ERASE_Pos (9U) 2150 #define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 2151 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 2152 #define FLASH_PECR_FPRG_Pos (10U) 2153 #define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 2154 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 2155 #define FLASH_PECR_PARALLBANK_Pos (15U) 2156 #define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ 2157 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ 2158 #define FLASH_PECR_EOPIE_Pos (16U) 2159 #define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 2160 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 2161 #define FLASH_PECR_ERRIE_Pos (17U) 2162 #define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 2163 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 2164 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 2165 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 2166 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 2167 #define FLASH_PECR_HALF_ARRAY_Pos (19U) 2168 #define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ 2169 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ 2170 #define FLASH_PECR_NZDISABLE_Pos (22U) 2171 #define FLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */ 2172 #define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */ 2173 2174 /****************** Bit definition for FLASH_PDKEYR register ******************/ 2175 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 2176 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 2177 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2178 2179 /****************** Bit definition for FLASH_PEKEYR register ******************/ 2180 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 2181 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 2182 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2183 2184 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 2185 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 2186 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 2187 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 2188 2189 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 2190 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 2191 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 2192 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 2193 2194 /****************** Bit definition for FLASH_SR register *******************/ 2195 #define FLASH_SR_BSY_Pos (0U) 2196 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 2197 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 2198 #define FLASH_SR_EOP_Pos (1U) 2199 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 2200 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 2201 #define FLASH_SR_HVOFF_Pos (2U) 2202 #define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ 2203 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ 2204 #define FLASH_SR_READY_Pos (3U) 2205 #define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 2206 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 2207 2208 #define FLASH_SR_WRPERR_Pos (8U) 2209 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 2210 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ 2211 #define FLASH_SR_PGAERR_Pos (9U) 2212 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 2213 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 2214 #define FLASH_SR_SIZERR_Pos (10U) 2215 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 2216 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 2217 #define FLASH_SR_OPTVERR_Pos (11U) 2218 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 2219 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ 2220 #define FLASH_SR_RDERR_Pos (13U) 2221 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ 2222 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ 2223 #define FLASH_SR_NOTZEROERR_Pos (16U) 2224 #define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ 2225 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ 2226 #define FLASH_SR_FWWERR_Pos (17U) 2227 #define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ 2228 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ 2229 2230 /* Legacy defines */ 2231 #define FLASH_SR_FWWER FLASH_SR_FWWERR 2232 #define FLASH_SR_ENHV FLASH_SR_HVOFF 2233 #define FLASH_SR_ENDHV FLASH_SR_HVOFF 2234 2235 /****************** Bit definition for FLASH_OPTR register *******************/ 2236 #define FLASH_OPTR_RDPROT_Pos (0U) 2237 #define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ 2238 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ 2239 #define FLASH_OPTR_WPRMOD_Pos (8U) 2240 #define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ 2241 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ 2242 #define FLASH_OPTR_BOR_LEV_Pos (16U) 2243 #define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ 2244 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 2245 #define FLASH_OPTR_IWDG_SW_Pos (20U) 2246 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ 2247 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ 2248 #define FLASH_OPTR_nRST_STOP_Pos (21U) 2249 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ 2250 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ 2251 #define FLASH_OPTR_nRST_STDBY_Pos (22U) 2252 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ 2253 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2254 #define FLASH_OPTR_BFB2_Pos (23U) 2255 #define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */ 2256 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */ 2257 #define FLASH_OPTR_USER_Pos (20U) 2258 #define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ 2259 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ 2260 #define FLASH_OPTR_BOOT1_Pos (31U) 2261 #define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ 2262 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ 2263 2264 /****************** Bit definition for FLASH_WRPR register ******************/ 2265 #define FLASH_WRPR_WRP_Pos (0U) 2266 #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 2267 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ 2268 2269 /******************************************************************************/ 2270 /* */ 2271 /* General Purpose IOs (GPIO) */ 2272 /* */ 2273 /******************************************************************************/ 2274 /******************* Bit definition for GPIO_MODER register *****************/ 2275 #define GPIO_MODER_MODE0_Pos (0U) 2276 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 2277 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 2278 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 2279 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 2280 #define GPIO_MODER_MODE1_Pos (2U) 2281 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 2282 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 2283 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 2284 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 2285 #define GPIO_MODER_MODE2_Pos (4U) 2286 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 2287 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 2288 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 2289 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 2290 #define GPIO_MODER_MODE3_Pos (6U) 2291 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 2292 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 2293 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 2294 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 2295 #define GPIO_MODER_MODE4_Pos (8U) 2296 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 2297 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 2298 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 2299 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 2300 #define GPIO_MODER_MODE5_Pos (10U) 2301 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 2302 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 2303 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 2304 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 2305 #define GPIO_MODER_MODE6_Pos (12U) 2306 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 2307 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 2308 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 2309 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 2310 #define GPIO_MODER_MODE7_Pos (14U) 2311 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 2312 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 2313 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 2314 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 2315 #define GPIO_MODER_MODE8_Pos (16U) 2316 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 2317 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 2318 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 2319 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 2320 #define GPIO_MODER_MODE9_Pos (18U) 2321 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 2322 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 2323 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 2324 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 2325 #define GPIO_MODER_MODE10_Pos (20U) 2326 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 2327 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 2328 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 2329 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 2330 #define GPIO_MODER_MODE11_Pos (22U) 2331 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 2332 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 2333 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 2334 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 2335 #define GPIO_MODER_MODE12_Pos (24U) 2336 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 2337 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 2338 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 2339 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 2340 #define GPIO_MODER_MODE13_Pos (26U) 2341 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 2342 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 2343 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 2344 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 2345 #define GPIO_MODER_MODE14_Pos (28U) 2346 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 2347 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 2348 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 2349 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 2350 #define GPIO_MODER_MODE15_Pos (30U) 2351 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 2352 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 2353 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 2354 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 2355 2356 /****************** Bit definition for GPIO_OTYPER register *****************/ 2357 #define GPIO_OTYPER_OT_0 (0x00000001U) 2358 #define GPIO_OTYPER_OT_1 (0x00000002U) 2359 #define GPIO_OTYPER_OT_2 (0x00000004U) 2360 #define GPIO_OTYPER_OT_3 (0x00000008U) 2361 #define GPIO_OTYPER_OT_4 (0x00000010U) 2362 #define GPIO_OTYPER_OT_5 (0x00000020U) 2363 #define GPIO_OTYPER_OT_6 (0x00000040U) 2364 #define GPIO_OTYPER_OT_7 (0x00000080U) 2365 #define GPIO_OTYPER_OT_8 (0x00000100U) 2366 #define GPIO_OTYPER_OT_9 (0x00000200U) 2367 #define GPIO_OTYPER_OT_10 (0x00000400U) 2368 #define GPIO_OTYPER_OT_11 (0x00000800U) 2369 #define GPIO_OTYPER_OT_12 (0x00001000U) 2370 #define GPIO_OTYPER_OT_13 (0x00002000U) 2371 #define GPIO_OTYPER_OT_14 (0x00004000U) 2372 #define GPIO_OTYPER_OT_15 (0x00008000U) 2373 2374 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 2375 #define GPIO_OSPEEDER_OSPEED0_Pos (0U) 2376 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ 2377 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk 2378 #define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ 2379 #define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ 2380 #define GPIO_OSPEEDER_OSPEED1_Pos (2U) 2381 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ 2382 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk 2383 #define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ 2384 #define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ 2385 #define GPIO_OSPEEDER_OSPEED2_Pos (4U) 2386 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ 2387 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk 2388 #define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ 2389 #define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ 2390 #define GPIO_OSPEEDER_OSPEED3_Pos (6U) 2391 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ 2392 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk 2393 #define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ 2394 #define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ 2395 #define GPIO_OSPEEDER_OSPEED4_Pos (8U) 2396 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ 2397 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk 2398 #define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ 2399 #define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ 2400 #define GPIO_OSPEEDER_OSPEED5_Pos (10U) 2401 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ 2402 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk 2403 #define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ 2404 #define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ 2405 #define GPIO_OSPEEDER_OSPEED6_Pos (12U) 2406 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ 2407 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk 2408 #define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ 2409 #define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ 2410 #define GPIO_OSPEEDER_OSPEED7_Pos (14U) 2411 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ 2412 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk 2413 #define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ 2414 #define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ 2415 #define GPIO_OSPEEDER_OSPEED8_Pos (16U) 2416 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ 2417 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk 2418 #define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ 2419 #define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ 2420 #define GPIO_OSPEEDER_OSPEED9_Pos (18U) 2421 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ 2422 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk 2423 #define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ 2424 #define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ 2425 #define GPIO_OSPEEDER_OSPEED10_Pos (20U) 2426 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ 2427 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk 2428 #define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ 2429 #define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ 2430 #define GPIO_OSPEEDER_OSPEED11_Pos (22U) 2431 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ 2432 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk 2433 #define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ 2434 #define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ 2435 #define GPIO_OSPEEDER_OSPEED12_Pos (24U) 2436 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ 2437 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk 2438 #define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ 2439 #define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ 2440 #define GPIO_OSPEEDER_OSPEED13_Pos (26U) 2441 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ 2442 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk 2443 #define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ 2444 #define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ 2445 #define GPIO_OSPEEDER_OSPEED14_Pos (28U) 2446 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ 2447 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk 2448 #define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ 2449 #define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ 2450 #define GPIO_OSPEEDER_OSPEED15_Pos (30U) 2451 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ 2452 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk 2453 #define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ 2454 #define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ 2455 2456 /******************* Bit definition for GPIO_PUPDR register ******************/ 2457 #define GPIO_PUPDR_PUPD0_Pos (0U) 2458 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 2459 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 2460 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 2461 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 2462 #define GPIO_PUPDR_PUPD1_Pos (2U) 2463 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 2464 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 2465 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 2466 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 2467 #define GPIO_PUPDR_PUPD2_Pos (4U) 2468 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 2469 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 2470 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 2471 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 2472 #define GPIO_PUPDR_PUPD3_Pos (6U) 2473 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 2474 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 2475 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 2476 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 2477 #define GPIO_PUPDR_PUPD4_Pos (8U) 2478 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 2479 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 2480 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 2481 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 2482 #define GPIO_PUPDR_PUPD5_Pos (10U) 2483 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 2484 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 2485 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 2486 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 2487 #define GPIO_PUPDR_PUPD6_Pos (12U) 2488 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 2489 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 2490 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 2491 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 2492 #define GPIO_PUPDR_PUPD7_Pos (14U) 2493 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 2494 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 2495 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 2496 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 2497 #define GPIO_PUPDR_PUPD8_Pos (16U) 2498 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 2499 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 2500 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 2501 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 2502 #define GPIO_PUPDR_PUPD9_Pos (18U) 2503 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 2504 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 2505 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 2506 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 2507 #define GPIO_PUPDR_PUPD10_Pos (20U) 2508 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 2509 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 2510 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 2511 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 2512 #define GPIO_PUPDR_PUPD11_Pos (22U) 2513 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 2514 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 2515 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 2516 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 2517 #define GPIO_PUPDR_PUPD12_Pos (24U) 2518 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 2519 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 2520 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 2521 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 2522 #define GPIO_PUPDR_PUPD13_Pos (26U) 2523 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 2524 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 2525 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 2526 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 2527 #define GPIO_PUPDR_PUPD14_Pos (28U) 2528 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 2529 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 2530 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 2531 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 2532 #define GPIO_PUPDR_PUPD15_Pos (30U) 2533 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 2534 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 2535 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 2536 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 2537 2538 /******************* Bit definition for GPIO_IDR register *******************/ 2539 #define GPIO_IDR_ID0_Pos (0U) 2540 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 2541 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 2542 #define GPIO_IDR_ID1_Pos (1U) 2543 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 2544 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 2545 #define GPIO_IDR_ID2_Pos (2U) 2546 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 2547 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 2548 #define GPIO_IDR_ID3_Pos (3U) 2549 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 2550 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 2551 #define GPIO_IDR_ID4_Pos (4U) 2552 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 2553 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 2554 #define GPIO_IDR_ID5_Pos (5U) 2555 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 2556 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 2557 #define GPIO_IDR_ID6_Pos (6U) 2558 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 2559 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 2560 #define GPIO_IDR_ID7_Pos (7U) 2561 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 2562 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 2563 #define GPIO_IDR_ID8_Pos (8U) 2564 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 2565 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 2566 #define GPIO_IDR_ID9_Pos (9U) 2567 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 2568 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 2569 #define GPIO_IDR_ID10_Pos (10U) 2570 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 2571 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 2572 #define GPIO_IDR_ID11_Pos (11U) 2573 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 2574 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 2575 #define GPIO_IDR_ID12_Pos (12U) 2576 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 2577 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 2578 #define GPIO_IDR_ID13_Pos (13U) 2579 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 2580 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 2581 #define GPIO_IDR_ID14_Pos (14U) 2582 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 2583 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 2584 #define GPIO_IDR_ID15_Pos (15U) 2585 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 2586 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 2587 2588 /****************** Bit definition for GPIO_ODR register ********************/ 2589 #define GPIO_ODR_OD0_Pos (0U) 2590 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 2591 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 2592 #define GPIO_ODR_OD1_Pos (1U) 2593 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 2594 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 2595 #define GPIO_ODR_OD2_Pos (2U) 2596 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 2597 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 2598 #define GPIO_ODR_OD3_Pos (3U) 2599 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 2600 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 2601 #define GPIO_ODR_OD4_Pos (4U) 2602 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 2603 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 2604 #define GPIO_ODR_OD5_Pos (5U) 2605 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 2606 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 2607 #define GPIO_ODR_OD6_Pos (6U) 2608 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 2609 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 2610 #define GPIO_ODR_OD7_Pos (7U) 2611 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 2612 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 2613 #define GPIO_ODR_OD8_Pos (8U) 2614 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 2615 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 2616 #define GPIO_ODR_OD9_Pos (9U) 2617 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 2618 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 2619 #define GPIO_ODR_OD10_Pos (10U) 2620 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 2621 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 2622 #define GPIO_ODR_OD11_Pos (11U) 2623 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 2624 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 2625 #define GPIO_ODR_OD12_Pos (12U) 2626 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 2627 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 2628 #define GPIO_ODR_OD13_Pos (13U) 2629 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 2630 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 2631 #define GPIO_ODR_OD14_Pos (14U) 2632 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 2633 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 2634 #define GPIO_ODR_OD15_Pos (15U) 2635 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 2636 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 2637 2638 /****************** Bit definition for GPIO_BSRR register ********************/ 2639 #define GPIO_BSRR_BS_0 (0x00000001U) 2640 #define GPIO_BSRR_BS_1 (0x00000002U) 2641 #define GPIO_BSRR_BS_2 (0x00000004U) 2642 #define GPIO_BSRR_BS_3 (0x00000008U) 2643 #define GPIO_BSRR_BS_4 (0x00000010U) 2644 #define GPIO_BSRR_BS_5 (0x00000020U) 2645 #define GPIO_BSRR_BS_6 (0x00000040U) 2646 #define GPIO_BSRR_BS_7 (0x00000080U) 2647 #define GPIO_BSRR_BS_8 (0x00000100U) 2648 #define GPIO_BSRR_BS_9 (0x00000200U) 2649 #define GPIO_BSRR_BS_10 (0x00000400U) 2650 #define GPIO_BSRR_BS_11 (0x00000800U) 2651 #define GPIO_BSRR_BS_12 (0x00001000U) 2652 #define GPIO_BSRR_BS_13 (0x00002000U) 2653 #define GPIO_BSRR_BS_14 (0x00004000U) 2654 #define GPIO_BSRR_BS_15 (0x00008000U) 2655 #define GPIO_BSRR_BR_0 (0x00010000U) 2656 #define GPIO_BSRR_BR_1 (0x00020000U) 2657 #define GPIO_BSRR_BR_2 (0x00040000U) 2658 #define GPIO_BSRR_BR_3 (0x00080000U) 2659 #define GPIO_BSRR_BR_4 (0x00100000U) 2660 #define GPIO_BSRR_BR_5 (0x00200000U) 2661 #define GPIO_BSRR_BR_6 (0x00400000U) 2662 #define GPIO_BSRR_BR_7 (0x00800000U) 2663 #define GPIO_BSRR_BR_8 (0x01000000U) 2664 #define GPIO_BSRR_BR_9 (0x02000000U) 2665 #define GPIO_BSRR_BR_10 (0x04000000U) 2666 #define GPIO_BSRR_BR_11 (0x08000000U) 2667 #define GPIO_BSRR_BR_12 (0x10000000U) 2668 #define GPIO_BSRR_BR_13 (0x20000000U) 2669 #define GPIO_BSRR_BR_14 (0x40000000U) 2670 #define GPIO_BSRR_BR_15 (0x80000000U) 2671 2672 /****************** Bit definition for GPIO_LCKR register ********************/ 2673 #define GPIO_LCKR_LCK0_Pos (0U) 2674 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2675 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2676 #define GPIO_LCKR_LCK1_Pos (1U) 2677 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2678 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2679 #define GPIO_LCKR_LCK2_Pos (2U) 2680 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2681 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2682 #define GPIO_LCKR_LCK3_Pos (3U) 2683 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2684 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2685 #define GPIO_LCKR_LCK4_Pos (4U) 2686 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2687 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2688 #define GPIO_LCKR_LCK5_Pos (5U) 2689 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2690 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2691 #define GPIO_LCKR_LCK6_Pos (6U) 2692 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2693 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2694 #define GPIO_LCKR_LCK7_Pos (7U) 2695 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2696 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2697 #define GPIO_LCKR_LCK8_Pos (8U) 2698 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2699 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2700 #define GPIO_LCKR_LCK9_Pos (9U) 2701 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2702 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2703 #define GPIO_LCKR_LCK10_Pos (10U) 2704 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2705 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2706 #define GPIO_LCKR_LCK11_Pos (11U) 2707 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2708 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2709 #define GPIO_LCKR_LCK12_Pos (12U) 2710 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2711 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2712 #define GPIO_LCKR_LCK13_Pos (13U) 2713 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2714 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2715 #define GPIO_LCKR_LCK14_Pos (14U) 2716 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2717 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2718 #define GPIO_LCKR_LCK15_Pos (15U) 2719 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2720 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2721 #define GPIO_LCKR_LCKK_Pos (16U) 2722 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2723 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2724 2725 /****************** Bit definition for GPIO_AFRL register ********************/ 2726 #define GPIO_AFRL_AFSEL0_Pos (0U) 2727 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 2728 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 2729 #define GPIO_AFRL_AFSEL1_Pos (4U) 2730 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 2731 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 2732 #define GPIO_AFRL_AFSEL2_Pos (8U) 2733 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 2734 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 2735 #define GPIO_AFRL_AFSEL3_Pos (12U) 2736 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 2737 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 2738 #define GPIO_AFRL_AFSEL4_Pos (16U) 2739 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 2740 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 2741 #define GPIO_AFRL_AFSEL5_Pos (20U) 2742 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 2743 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 2744 #define GPIO_AFRL_AFSEL6_Pos (24U) 2745 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 2746 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 2747 #define GPIO_AFRL_AFSEL7_Pos (28U) 2748 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 2749 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 2750 2751 /****************** Bit definition for GPIO_AFRH register ********************/ 2752 #define GPIO_AFRH_AFSEL8_Pos (0U) 2753 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 2754 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 2755 #define GPIO_AFRH_AFSEL9_Pos (4U) 2756 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 2757 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 2758 #define GPIO_AFRH_AFSEL10_Pos (8U) 2759 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 2760 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 2761 #define GPIO_AFRH_AFSEL11_Pos (12U) 2762 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 2763 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 2764 #define GPIO_AFRH_AFSEL12_Pos (16U) 2765 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 2766 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 2767 #define GPIO_AFRH_AFSEL13_Pos (20U) 2768 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 2769 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 2770 #define GPIO_AFRH_AFSEL14_Pos (24U) 2771 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 2772 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 2773 #define GPIO_AFRH_AFSEL15_Pos (28U) 2774 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 2775 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 2776 2777 /****************** Bit definition for GPIO_BRR register *********************/ 2778 #define GPIO_BRR_BR_0 (0x00000001U) 2779 #define GPIO_BRR_BR_1 (0x00000002U) 2780 #define GPIO_BRR_BR_2 (0x00000004U) 2781 #define GPIO_BRR_BR_3 (0x00000008U) 2782 #define GPIO_BRR_BR_4 (0x00000010U) 2783 #define GPIO_BRR_BR_5 (0x00000020U) 2784 #define GPIO_BRR_BR_6 (0x00000040U) 2785 #define GPIO_BRR_BR_7 (0x00000080U) 2786 #define GPIO_BRR_BR_8 (0x00000100U) 2787 #define GPIO_BRR_BR_9 (0x00000200U) 2788 #define GPIO_BRR_BR_10 (0x00000400U) 2789 #define GPIO_BRR_BR_11 (0x00000800U) 2790 #define GPIO_BRR_BR_12 (0x00001000U) 2791 #define GPIO_BRR_BR_13 (0x00002000U) 2792 #define GPIO_BRR_BR_14 (0x00004000U) 2793 #define GPIO_BRR_BR_15 (0x00008000U) 2794 2795 /******************************************************************************/ 2796 /* */ 2797 /* Inter-integrated Circuit Interface (I2C) */ 2798 /* */ 2799 /******************************************************************************/ 2800 2801 /******************* Bit definition for I2C_CR1 register *******************/ 2802 #define I2C_CR1_PE_Pos (0U) 2803 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2804 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2805 #define I2C_CR1_TXIE_Pos (1U) 2806 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2807 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2808 #define I2C_CR1_RXIE_Pos (2U) 2809 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2810 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2811 #define I2C_CR1_ADDRIE_Pos (3U) 2812 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2813 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2814 #define I2C_CR1_NACKIE_Pos (4U) 2815 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2816 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2817 #define I2C_CR1_STOPIE_Pos (5U) 2818 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2819 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2820 #define I2C_CR1_TCIE_Pos (6U) 2821 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2822 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2823 #define I2C_CR1_ERRIE_Pos (7U) 2824 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2825 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2826 #define I2C_CR1_DNF_Pos (8U) 2827 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2828 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2829 #define I2C_CR1_ANFOFF_Pos (12U) 2830 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2831 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2832 #define I2C_CR1_TXDMAEN_Pos (14U) 2833 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2834 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2835 #define I2C_CR1_RXDMAEN_Pos (15U) 2836 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2837 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2838 #define I2C_CR1_SBC_Pos (16U) 2839 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2840 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2841 #define I2C_CR1_NOSTRETCH_Pos (17U) 2842 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2843 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2844 #define I2C_CR1_WUPEN_Pos (18U) 2845 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 2846 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 2847 #define I2C_CR1_GCEN_Pos (19U) 2848 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2849 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2850 #define I2C_CR1_SMBHEN_Pos (20U) 2851 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2852 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2853 #define I2C_CR1_SMBDEN_Pos (21U) 2854 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2855 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2856 #define I2C_CR1_ALERTEN_Pos (22U) 2857 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2858 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2859 #define I2C_CR1_PECEN_Pos (23U) 2860 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2861 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2862 2863 /****************** Bit definition for I2C_CR2 register ********************/ 2864 #define I2C_CR2_SADD_Pos (0U) 2865 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2866 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2867 #define I2C_CR2_RD_WRN_Pos (10U) 2868 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2869 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2870 #define I2C_CR2_ADD10_Pos (11U) 2871 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2872 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2873 #define I2C_CR2_HEAD10R_Pos (12U) 2874 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2875 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2876 #define I2C_CR2_START_Pos (13U) 2877 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2878 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 2879 #define I2C_CR2_STOP_Pos (14U) 2880 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 2881 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 2882 #define I2C_CR2_NACK_Pos (15U) 2883 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 2884 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 2885 #define I2C_CR2_NBYTES_Pos (16U) 2886 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 2887 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 2888 #define I2C_CR2_RELOAD_Pos (24U) 2889 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 2890 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 2891 #define I2C_CR2_AUTOEND_Pos (25U) 2892 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 2893 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 2894 #define I2C_CR2_PECBYTE_Pos (26U) 2895 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 2896 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 2897 2898 /******************* Bit definition for I2C_OAR1 register ******************/ 2899 #define I2C_OAR1_OA1_Pos (0U) 2900 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 2901 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 2902 #define I2C_OAR1_OA1MODE_Pos (10U) 2903 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 2904 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 2905 #define I2C_OAR1_OA1EN_Pos (15U) 2906 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 2907 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 2908 2909 /******************* Bit definition for I2C_OAR2 register ******************/ 2910 #define I2C_OAR2_OA2_Pos (1U) 2911 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 2912 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 2913 #define I2C_OAR2_OA2MSK_Pos (8U) 2914 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 2915 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 2916 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 2917 #define I2C_OAR2_OA2MASK01_Pos (8U) 2918 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 2919 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 2920 #define I2C_OAR2_OA2MASK02_Pos (9U) 2921 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 2922 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 2923 #define I2C_OAR2_OA2MASK03_Pos (8U) 2924 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 2925 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 2926 #define I2C_OAR2_OA2MASK04_Pos (10U) 2927 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 2928 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 2929 #define I2C_OAR2_OA2MASK05_Pos (8U) 2930 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 2931 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 2932 #define I2C_OAR2_OA2MASK06_Pos (9U) 2933 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 2934 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 2935 #define I2C_OAR2_OA2MASK07_Pos (8U) 2936 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 2937 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 2938 #define I2C_OAR2_OA2EN_Pos (15U) 2939 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 2940 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 2941 2942 /******************* Bit definition for I2C_TIMINGR register *******************/ 2943 #define I2C_TIMINGR_SCLL_Pos (0U) 2944 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 2945 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 2946 #define I2C_TIMINGR_SCLH_Pos (8U) 2947 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 2948 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 2949 #define I2C_TIMINGR_SDADEL_Pos (16U) 2950 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 2951 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 2952 #define I2C_TIMINGR_SCLDEL_Pos (20U) 2953 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 2954 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 2955 #define I2C_TIMINGR_PRESC_Pos (28U) 2956 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 2957 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 2958 2959 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 2960 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 2961 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 2962 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 2963 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 2964 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 2965 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 2966 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 2967 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 2968 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 2969 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 2970 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 2971 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 2972 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 2973 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 2974 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 2975 2976 /****************** Bit definition for I2C_ISR register *********************/ 2977 #define I2C_ISR_TXE_Pos (0U) 2978 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 2979 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 2980 #define I2C_ISR_TXIS_Pos (1U) 2981 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 2982 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 2983 #define I2C_ISR_RXNE_Pos (2U) 2984 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 2985 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 2986 #define I2C_ISR_ADDR_Pos (3U) 2987 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 2988 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 2989 #define I2C_ISR_NACKF_Pos (4U) 2990 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 2991 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 2992 #define I2C_ISR_STOPF_Pos (5U) 2993 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 2994 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 2995 #define I2C_ISR_TC_Pos (6U) 2996 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 2997 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 2998 #define I2C_ISR_TCR_Pos (7U) 2999 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 3000 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 3001 #define I2C_ISR_BERR_Pos (8U) 3002 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 3003 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 3004 #define I2C_ISR_ARLO_Pos (9U) 3005 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 3006 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 3007 #define I2C_ISR_OVR_Pos (10U) 3008 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 3009 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 3010 #define I2C_ISR_PECERR_Pos (11U) 3011 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 3012 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 3013 #define I2C_ISR_TIMEOUT_Pos (12U) 3014 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 3015 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 3016 #define I2C_ISR_ALERT_Pos (13U) 3017 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 3018 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 3019 #define I2C_ISR_BUSY_Pos (15U) 3020 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 3021 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 3022 #define I2C_ISR_DIR_Pos (16U) 3023 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 3024 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 3025 #define I2C_ISR_ADDCODE_Pos (17U) 3026 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 3027 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 3028 3029 /****************** Bit definition for I2C_ICR register *********************/ 3030 #define I2C_ICR_ADDRCF_Pos (3U) 3031 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 3032 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 3033 #define I2C_ICR_NACKCF_Pos (4U) 3034 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 3035 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 3036 #define I2C_ICR_STOPCF_Pos (5U) 3037 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 3038 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 3039 #define I2C_ICR_BERRCF_Pos (8U) 3040 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 3041 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 3042 #define I2C_ICR_ARLOCF_Pos (9U) 3043 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 3044 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 3045 #define I2C_ICR_OVRCF_Pos (10U) 3046 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 3047 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 3048 #define I2C_ICR_PECCF_Pos (11U) 3049 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 3050 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 3051 #define I2C_ICR_TIMOUTCF_Pos (12U) 3052 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 3053 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 3054 #define I2C_ICR_ALERTCF_Pos (13U) 3055 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 3056 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 3057 3058 /****************** Bit definition for I2C_PECR register *********************/ 3059 #define I2C_PECR_PEC_Pos (0U) 3060 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 3061 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 3062 3063 /****************** Bit definition for I2C_RXDR register *********************/ 3064 #define I2C_RXDR_RXDATA_Pos (0U) 3065 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 3066 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 3067 3068 /****************** Bit definition for I2C_TXDR register *********************/ 3069 #define I2C_TXDR_TXDATA_Pos (0U) 3070 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 3071 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 3072 3073 /******************************************************************************/ 3074 /* */ 3075 /* Independent WATCHDOG (IWDG) */ 3076 /* */ 3077 /******************************************************************************/ 3078 /******************* Bit definition for IWDG_KR register ********************/ 3079 #define IWDG_KR_KEY_Pos (0U) 3080 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3081 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 3082 3083 /******************* Bit definition for IWDG_PR register ********************/ 3084 #define IWDG_PR_PR_Pos (0U) 3085 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3086 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 3087 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3088 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3089 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3090 3091 /******************* Bit definition for IWDG_RLR register *******************/ 3092 #define IWDG_RLR_RL_Pos (0U) 3093 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3094 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 3095 3096 /******************* Bit definition for IWDG_SR register ********************/ 3097 #define IWDG_SR_PVU_Pos (0U) 3098 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3099 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3100 #define IWDG_SR_RVU_Pos (1U) 3101 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3102 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3103 #define IWDG_SR_WVU_Pos (2U) 3104 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 3105 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 3106 3107 /******************* Bit definition for IWDG_KR register ********************/ 3108 #define IWDG_WINR_WIN_Pos (0U) 3109 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 3110 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 3111 3112 /******************************************************************************/ 3113 /* */ 3114 /* Low Power Timer (LPTTIM) */ 3115 /* */ 3116 /******************************************************************************/ 3117 /****************** Bit definition for LPTIM_ISR register *******************/ 3118 #define LPTIM_ISR_CMPM_Pos (0U) 3119 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 3120 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 3121 #define LPTIM_ISR_ARRM_Pos (1U) 3122 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 3123 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 3124 #define LPTIM_ISR_EXTTRIG_Pos (2U) 3125 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 3126 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 3127 #define LPTIM_ISR_CMPOK_Pos (3U) 3128 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 3129 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 3130 #define LPTIM_ISR_ARROK_Pos (4U) 3131 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 3132 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 3133 #define LPTIM_ISR_UP_Pos (5U) 3134 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 3135 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 3136 #define LPTIM_ISR_DOWN_Pos (6U) 3137 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 3138 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 3139 3140 /****************** Bit definition for LPTIM_ICR register *******************/ 3141 #define LPTIM_ICR_CMPMCF_Pos (0U) 3142 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 3143 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 3144 #define LPTIM_ICR_ARRMCF_Pos (1U) 3145 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 3146 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 3147 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 3148 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 3149 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 3150 #define LPTIM_ICR_CMPOKCF_Pos (3U) 3151 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 3152 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 3153 #define LPTIM_ICR_ARROKCF_Pos (4U) 3154 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 3155 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 3156 #define LPTIM_ICR_UPCF_Pos (5U) 3157 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 3158 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 3159 #define LPTIM_ICR_DOWNCF_Pos (6U) 3160 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 3161 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 3162 3163 /****************** Bit definition for LPTIM_IER register ********************/ 3164 #define LPTIM_IER_CMPMIE_Pos (0U) 3165 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 3166 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 3167 #define LPTIM_IER_ARRMIE_Pos (1U) 3168 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 3169 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 3170 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 3171 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 3172 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 3173 #define LPTIM_IER_CMPOKIE_Pos (3U) 3174 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 3175 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 3176 #define LPTIM_IER_ARROKIE_Pos (4U) 3177 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 3178 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 3179 #define LPTIM_IER_UPIE_Pos (5U) 3180 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 3181 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 3182 #define LPTIM_IER_DOWNIE_Pos (6U) 3183 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 3184 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 3185 3186 /****************** Bit definition for LPTIM_CFGR register *******************/ 3187 #define LPTIM_CFGR_CKSEL_Pos (0U) 3188 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 3189 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 3190 3191 #define LPTIM_CFGR_CKPOL_Pos (1U) 3192 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 3193 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 3194 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 3195 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 3196 3197 #define LPTIM_CFGR_CKFLT_Pos (3U) 3198 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 3199 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 3200 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 3201 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 3202 3203 #define LPTIM_CFGR_TRGFLT_Pos (6U) 3204 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 3205 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 3206 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 3207 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 3208 3209 #define LPTIM_CFGR_PRESC_Pos (9U) 3210 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 3211 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 3212 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 3213 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 3214 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 3215 3216 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 3217 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 3218 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 3219 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 3220 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 3221 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 3222 3223 #define LPTIM_CFGR_TRIGEN_Pos (17U) 3224 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 3225 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 3226 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 3227 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 3228 3229 #define LPTIM_CFGR_TIMOUT_Pos (19U) 3230 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 3231 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 3232 #define LPTIM_CFGR_WAVE_Pos (20U) 3233 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 3234 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 3235 #define LPTIM_CFGR_WAVPOL_Pos (21U) 3236 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 3237 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 3238 #define LPTIM_CFGR_PRELOAD_Pos (22U) 3239 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 3240 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 3241 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 3242 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 3243 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 3244 #define LPTIM_CFGR_ENC_Pos (24U) 3245 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 3246 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 3247 3248 /****************** Bit definition for LPTIM_CR register ********************/ 3249 #define LPTIM_CR_ENABLE_Pos (0U) 3250 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 3251 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 3252 #define LPTIM_CR_SNGSTRT_Pos (1U) 3253 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 3254 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 3255 #define LPTIM_CR_CNTSTRT_Pos (2U) 3256 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 3257 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 3258 3259 /****************** Bit definition for LPTIM_CMP register *******************/ 3260 #define LPTIM_CMP_CMP_Pos (0U) 3261 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 3262 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 3263 3264 /****************** Bit definition for LPTIM_ARR register *******************/ 3265 #define LPTIM_ARR_ARR_Pos (0U) 3266 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 3267 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 3268 3269 /****************** Bit definition for LPTIM_CNT register *******************/ 3270 #define LPTIM_CNT_CNT_Pos (0U) 3271 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 3272 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 3273 3274 /******************************************************************************/ 3275 /* */ 3276 /* MIFARE Firewall */ 3277 /* */ 3278 /******************************************************************************/ 3279 3280 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ 3281 #define FW_CSSA_ADD_Pos (8U) 3282 #define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ 3283 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ 3284 #define FW_CSL_LENG_Pos (8U) 3285 #define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ 3286 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ 3287 #define FW_NVDSSA_ADD_Pos (8U) 3288 #define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ 3289 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ 3290 #define FW_NVDSL_LENG_Pos (8U) 3291 #define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ 3292 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ 3293 #define FW_VDSSA_ADD_Pos (6U) 3294 #define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */ 3295 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ 3296 #define FW_VDSL_LENG_Pos (6U) 3297 #define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */ 3298 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ 3299 3300 /**************************Bit definition for CR register *********************/ 3301 #define FW_CR_FPA_Pos (0U) 3302 #define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */ 3303 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ 3304 #define FW_CR_VDS_Pos (1U) 3305 #define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */ 3306 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ 3307 #define FW_CR_VDE_Pos (2U) 3308 #define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */ 3309 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ 3310 3311 /******************************************************************************/ 3312 /* */ 3313 /* Power Control (PWR) */ 3314 /* */ 3315 /******************************************************************************/ 3316 3317 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ 3318 3319 /******************** Bit definition for PWR_CR register ********************/ 3320 #define PWR_CR_LPSDSR_Pos (0U) 3321 #define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 3322 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 3323 #define PWR_CR_PDDS_Pos (1U) 3324 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 3325 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 3326 #define PWR_CR_CWUF_Pos (2U) 3327 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 3328 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 3329 #define PWR_CR_CSBF_Pos (3U) 3330 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 3331 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 3332 #define PWR_CR_PVDE_Pos (4U) 3333 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 3334 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 3335 3336 #define PWR_CR_PLS_Pos (5U) 3337 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 3338 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 3339 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 3340 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 3341 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 3342 3343 /*!< PVD level configuration */ 3344 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 3345 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 3346 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 3347 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 3348 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 3349 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 3350 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 3351 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 3352 3353 #define PWR_CR_DBP_Pos (8U) 3354 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 3355 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 3356 #define PWR_CR_ULP_Pos (9U) 3357 #define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 3358 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 3359 #define PWR_CR_FWU_Pos (10U) 3360 #define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 3361 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 3362 3363 #define PWR_CR_VOS_Pos (11U) 3364 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 3365 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 3366 #define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 3367 #define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 3368 #define PWR_CR_DSEEKOFF_Pos (13U) 3369 #define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ 3370 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ 3371 #define PWR_CR_LPRUN_Pos (14U) 3372 #define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 3373 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 3374 3375 /******************* Bit definition for PWR_CSR register ********************/ 3376 #define PWR_CSR_WUF_Pos (0U) 3377 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 3378 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 3379 #define PWR_CSR_SBF_Pos (1U) 3380 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 3381 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 3382 #define PWR_CSR_PVDO_Pos (2U) 3383 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 3384 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 3385 #define PWR_CSR_VREFINTRDYF_Pos (3U) 3386 #define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 3387 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 3388 #define PWR_CSR_VOSF_Pos (4U) 3389 #define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 3390 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 3391 #define PWR_CSR_REGLPF_Pos (5U) 3392 #define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 3393 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 3394 3395 #define PWR_CSR_EWUP1_Pos (8U) 3396 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3397 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3398 #define PWR_CSR_EWUP2_Pos (9U) 3399 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 3400 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3401 #define PWR_CSR_EWUP3_Pos (10U) 3402 #define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 3403 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 3404 3405 /******************************************************************************/ 3406 /* */ 3407 /* Reset and Clock Control */ 3408 /* */ 3409 /******************************************************************************/ 3410 /* 3411 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 3412 */ 3413 #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ 3414 #define RCC_MCO3_SUPPORT /*!<Support MCO3 */ 3415 #define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */ 3416 3417 /******************** Bit definition for RCC_CR register ********************/ 3418 #define RCC_CR_HSION_Pos (0U) 3419 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3420 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3421 #define RCC_CR_HSIKERON_Pos (1U) 3422 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ 3423 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ 3424 #define RCC_CR_HSIRDY_Pos (2U) 3425 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ 3426 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3427 #define RCC_CR_HSIDIVEN_Pos (3U) 3428 #define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ 3429 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ 3430 #define RCC_CR_HSIDIVF_Pos (4U) 3431 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ 3432 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ 3433 #define RCC_CR_HSIOUTEN_Pos (5U) 3434 #define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ 3435 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ 3436 #define RCC_CR_MSION_Pos (8U) 3437 #define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 3438 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 3439 #define RCC_CR_MSIRDY_Pos (9U) 3440 #define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 3441 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 3442 #define RCC_CR_HSEON_Pos (16U) 3443 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3444 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3445 #define RCC_CR_HSERDY_Pos (17U) 3446 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3447 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3448 #define RCC_CR_HSEBYP_Pos (18U) 3449 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3450 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3451 #define RCC_CR_CSSHSEON_Pos (19U) 3452 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ 3453 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ 3454 #define RCC_CR_RTCPRE_Pos (20U) 3455 #define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ 3456 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */ 3457 #define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ 3458 #define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ 3459 #define RCC_CR_PLLON_Pos (24U) 3460 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3461 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3462 #define RCC_CR_PLLRDY_Pos (25U) 3463 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3464 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3465 3466 /* Reference defines */ 3467 #define RCC_CR_CSSON RCC_CR_CSSHSEON 3468 3469 /******************** Bit definition for RCC_ICSCR register *****************/ 3470 #define RCC_ICSCR_HSICAL_Pos (0U) 3471 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 3472 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3473 #define RCC_ICSCR_HSITRIM_Pos (8U) 3474 #define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 3475 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3476 3477 #define RCC_ICSCR_MSIRANGE_Pos (13U) 3478 #define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 3479 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 3480 #define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 3481 #define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 3482 #define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 3483 #define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 3484 #define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 3485 #define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 3486 #define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 3487 #define RCC_ICSCR_MSICAL_Pos (16U) 3488 #define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 3489 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 3490 #define RCC_ICSCR_MSITRIM_Pos (24U) 3491 #define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 3492 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 3493 3494 3495 /******************* Bit definition for RCC_CFGR register *******************/ 3496 /*!< SW configuration */ 3497 #define RCC_CFGR_SW_Pos (0U) 3498 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3499 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3500 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3501 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3502 3503 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 3504 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 3505 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 3506 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 3507 3508 /*!< SWS configuration */ 3509 #define RCC_CFGR_SWS_Pos (2U) 3510 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3511 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3512 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3513 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3514 3515 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 3516 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 3517 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 3518 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 3519 3520 /*!< HPRE configuration */ 3521 #define RCC_CFGR_HPRE_Pos (4U) 3522 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3523 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3524 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3525 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3526 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3527 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3528 3529 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3530 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3531 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3532 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3533 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3534 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3535 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3536 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3537 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3538 3539 /*!< PPRE1 configuration */ 3540 #define RCC_CFGR_PPRE1_Pos (8U) 3541 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 3542 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 3543 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 3544 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 3545 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 3546 3547 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 3548 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 3549 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 3550 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 3551 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 3552 3553 /*!< PPRE2 configuration */ 3554 #define RCC_CFGR_PPRE2_Pos (11U) 3555 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 3556 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 3557 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 3558 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 3559 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 3560 3561 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 3562 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 3563 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 3564 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 3565 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 3566 3567 #define RCC_CFGR_STOPWUCK_Pos (15U) 3568 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 3569 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ 3570 3571 /*!< PLL entry clock source*/ 3572 #define RCC_CFGR_PLLSRC_Pos (16U) 3573 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 3574 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3575 3576 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 3577 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 3578 3579 3580 /*!< PLLMUL configuration */ 3581 #define RCC_CFGR_PLLMUL_Pos (18U) 3582 #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3583 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3584 #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3585 #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 3586 #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 3587 #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 3588 3589 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 3590 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 3591 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 3592 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 3593 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 3594 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 3595 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 3596 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 3597 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 3598 3599 /*!< PLLDIV configuration */ 3600 #define RCC_CFGR_PLLDIV_Pos (22U) 3601 #define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 3602 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 3603 #define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 3604 #define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 3605 3606 #define RCC_CFGR_PLLDIV2_Pos (22U) 3607 #define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 3608 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 3609 #define RCC_CFGR_PLLDIV3_Pos (23U) 3610 #define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 3611 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 3612 #define RCC_CFGR_PLLDIV4_Pos (22U) 3613 #define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 3614 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 3615 3616 /*!< MCO configuration */ 3617 #define RCC_CFGR_MCOSEL_Pos (24U) 3618 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 3619 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 3620 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 3621 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 3622 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 3623 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 3624 3625 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3626 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 3627 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 3628 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ 3629 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 3630 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 3631 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 3632 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 3633 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 3634 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 3635 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 3636 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 3637 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 3638 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 3639 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 3640 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 3641 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 3642 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 3643 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 3644 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 3645 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 3646 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 3647 3648 #define RCC_CFGR_MCOPRE_Pos (28U) 3649 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 3650 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 3651 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 3652 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 3653 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 3654 3655 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 3656 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 3657 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 3658 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 3659 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 3660 3661 /* Legacy defines */ 3662 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 3663 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 3664 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 3665 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 3666 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 3667 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 3668 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 3669 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 3670 #ifdef RCC_CFGR_MCOSEL_HSI48 3671 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 3672 #endif 3673 3674 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ 3675 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ 3676 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ 3677 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */ 3678 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */ 3679 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ 3680 3681 /*!<****************** Bit definition for RCC_CIER register ********************/ 3682 #define RCC_CIER_LSIRDYIE_Pos (0U) 3683 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 3684 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 3685 #define RCC_CIER_LSERDYIE_Pos (1U) 3686 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 3687 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 3688 #define RCC_CIER_HSIRDYIE_Pos (2U) 3689 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ 3690 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 3691 #define RCC_CIER_HSERDYIE_Pos (3U) 3692 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ 3693 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 3694 #define RCC_CIER_PLLRDYIE_Pos (4U) 3695 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ 3696 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 3697 #define RCC_CIER_MSIRDYIE_Pos (5U) 3698 #define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ 3699 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 3700 #define RCC_CIER_CSSLSE_Pos (7U) 3701 #define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ 3702 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ 3703 3704 /* Reference defines */ 3705 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE 3706 3707 /*!<****************** Bit definition for RCC_CIFR register ********************/ 3708 #define RCC_CIFR_LSIRDYF_Pos (0U) 3709 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 3710 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 3711 #define RCC_CIFR_LSERDYF_Pos (1U) 3712 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 3713 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 3714 #define RCC_CIFR_HSIRDYF_Pos (2U) 3715 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ 3716 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 3717 #define RCC_CIFR_HSERDYF_Pos (3U) 3718 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ 3719 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 3720 #define RCC_CIFR_PLLRDYF_Pos (4U) 3721 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ 3722 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 3723 #define RCC_CIFR_MSIRDYF_Pos (5U) 3724 #define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ 3725 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 3726 #define RCC_CIFR_CSSLSEF_Pos (7U) 3727 #define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ 3728 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ 3729 #define RCC_CIFR_CSSHSEF_Pos (8U) 3730 #define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ 3731 #define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ 3732 3733 /* Reference defines */ 3734 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF 3735 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF 3736 3737 /*!<****************** Bit definition for RCC_CICR register ********************/ 3738 #define RCC_CICR_LSIRDYC_Pos (0U) 3739 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 3740 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 3741 #define RCC_CICR_LSERDYC_Pos (1U) 3742 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 3743 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 3744 #define RCC_CICR_HSIRDYC_Pos (2U) 3745 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ 3746 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3747 #define RCC_CICR_HSERDYC_Pos (3U) 3748 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ 3749 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3750 #define RCC_CICR_PLLRDYC_Pos (4U) 3751 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ 3752 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3753 #define RCC_CICR_MSIRDYC_Pos (5U) 3754 #define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ 3755 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 3756 #define RCC_CICR_CSSLSEC_Pos (7U) 3757 #define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ 3758 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ 3759 #define RCC_CICR_CSSHSEC_Pos (8U) 3760 #define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ 3761 #define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ 3762 3763 /* Reference defines */ 3764 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC 3765 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC 3766 /***************** Bit definition for RCC_IOPRSTR register ******************/ 3767 #define RCC_IOPRSTR_IOPARST_Pos (0U) 3768 #define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ 3769 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ 3770 #define RCC_IOPRSTR_IOPBRST_Pos (1U) 3771 #define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ 3772 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ 3773 #define RCC_IOPRSTR_IOPCRST_Pos (2U) 3774 #define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ 3775 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ 3776 #define RCC_IOPRSTR_IOPDRST_Pos (3U) 3777 #define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */ 3778 #define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */ 3779 #define RCC_IOPRSTR_IOPERST_Pos (4U) 3780 #define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */ 3781 #define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */ 3782 #define RCC_IOPRSTR_IOPHRST_Pos (7U) 3783 #define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ 3784 #define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ 3785 3786 /* Reference defines */ 3787 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ 3788 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */ 3789 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */ 3790 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */ 3791 #define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */ 3792 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */ 3793 3794 3795 /****************** Bit definition for RCC_AHBRST register ******************/ 3796 #define RCC_AHBRSTR_DMARST_Pos (0U) 3797 #define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ 3798 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ 3799 #define RCC_AHBRSTR_MIFRST_Pos (8U) 3800 #define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ 3801 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */ 3802 #define RCC_AHBRSTR_CRCRST_Pos (12U) 3803 #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 3804 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 3805 #define RCC_AHBRSTR_CRYPRST_Pos (24U) 3806 #define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */ 3807 #define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */ 3808 3809 /* Reference defines */ 3810 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ 3811 3812 /***************** Bit definition for RCC_APB2RSTR register *****************/ 3813 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3814 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3815 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */ 3816 #define RCC_APB2RSTR_TIM21RST_Pos (2U) 3817 #define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ 3818 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */ 3819 #define RCC_APB2RSTR_TIM22RST_Pos (5U) 3820 #define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ 3821 #define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */ 3822 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3823 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3824 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */ 3825 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3826 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3827 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 3828 #define RCC_APB2RSTR_USART1RST_Pos (14U) 3829 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 3830 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 3831 #define RCC_APB2RSTR_DBGRST_Pos (22U) 3832 #define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ 3833 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */ 3834 3835 /* Reference defines */ 3836 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */ 3837 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */ 3838 3839 /***************** Bit definition for RCC_APB1RSTR register *****************/ 3840 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 3841 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 3842 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 3843 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 3844 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 3845 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 3846 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 3847 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 3848 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 3849 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 3850 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 3851 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 3852 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3853 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3854 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 3855 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 3856 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 3857 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */ 3858 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3859 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3860 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 3861 #define RCC_APB1RSTR_LPUART1RST_Pos (18U) 3862 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ 3863 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */ 3864 #define RCC_APB1RSTR_USART4RST_Pos (19U) 3865 #define RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ 3866 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 reset */ 3867 #define RCC_APB1RSTR_USART5RST_Pos (20U) 3868 #define RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ 3869 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 reset */ 3870 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3871 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3872 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 3873 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 3874 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 3875 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 3876 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3877 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3878 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */ 3879 #define RCC_APB1RSTR_I2C3RST_Pos (30U) 3880 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */ 3881 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C3 reset */ 3882 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U) 3883 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ 3884 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */ 3885 3886 /***************** Bit definition for RCC_IOPENR register ******************/ 3887 #define RCC_IOPENR_IOPAEN_Pos (0U) 3888 #define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ 3889 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ 3890 #define RCC_IOPENR_IOPBEN_Pos (1U) 3891 #define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ 3892 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ 3893 #define RCC_IOPENR_IOPCEN_Pos (2U) 3894 #define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ 3895 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ 3896 #define RCC_IOPENR_IOPDEN_Pos (3U) 3897 #define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */ 3898 #define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */ 3899 #define RCC_IOPENR_IOPEEN_Pos (4U) 3900 #define RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */ 3901 #define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */ 3902 #define RCC_IOPENR_IOPHEN_Pos (7U) 3903 #define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ 3904 #define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ 3905 3906 /* Reference defines */ 3907 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ 3908 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */ 3909 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */ 3910 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */ 3911 #define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */ 3912 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ 3913 3914 /***************** Bit definition for RCC_AHBENR register ******************/ 3915 #define RCC_AHBENR_DMAEN_Pos (0U) 3916 #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3917 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3918 #define RCC_AHBENR_MIFEN_Pos (8U) 3919 #define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ 3920 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ 3921 #define RCC_AHBENR_CRCEN_Pos (12U) 3922 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 3923 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3924 #define RCC_AHBENR_CRYPEN_Pos (24U) 3925 #define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */ 3926 #define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/ 3927 3928 /* Reference defines */ 3929 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3930 3931 /***************** Bit definition for RCC_APB2ENR register ******************/ 3932 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 3933 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 3934 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ 3935 #define RCC_APB2ENR_TIM21EN_Pos (2U) 3936 #define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ 3937 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ 3938 #define RCC_APB2ENR_TIM22EN_Pos (5U) 3939 #define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ 3940 #define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ 3941 #define RCC_APB2ENR_FWEN_Pos (7U) 3942 #define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ 3943 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ 3944 #define RCC_APB2ENR_ADCEN_Pos (9U) 3945 #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3946 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3947 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3948 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3949 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3950 #define RCC_APB2ENR_USART1EN_Pos (14U) 3951 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 3952 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 3953 #define RCC_APB2ENR_DBGEN_Pos (22U) 3954 #define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ 3955 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ 3956 3957 /* Reference defines */ 3958 3959 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */ 3960 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3961 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ 3962 3963 /***************** Bit definition for RCC_APB1ENR register ******************/ 3964 #define RCC_APB1ENR_TIM2EN_Pos (0U) 3965 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 3966 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 3967 #define RCC_APB1ENR_TIM3EN_Pos (1U) 3968 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 3969 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 3970 #define RCC_APB1ENR_TIM6EN_Pos (4U) 3971 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 3972 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 3973 #define RCC_APB1ENR_TIM7EN_Pos (5U) 3974 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 3975 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 3976 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3977 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3978 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3979 #define RCC_APB1ENR_SPI2EN_Pos (14U) 3980 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 3981 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 3982 #define RCC_APB1ENR_USART2EN_Pos (17U) 3983 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3984 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3985 #define RCC_APB1ENR_LPUART1EN_Pos (18U) 3986 #define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ 3987 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ 3988 #define RCC_APB1ENR_USART4EN_Pos (19U) 3989 #define RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */ 3990 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */ 3991 #define RCC_APB1ENR_USART5EN_Pos (20U) 3992 #define RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */ 3993 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */ 3994 #define RCC_APB1ENR_I2C1EN_Pos (21U) 3995 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 3996 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 3997 #define RCC_APB1ENR_I2C2EN_Pos (22U) 3998 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 3999 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ 4000 #define RCC_APB1ENR_PWREN_Pos (28U) 4001 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 4002 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 4003 #define RCC_APB1ENR_I2C3EN_Pos (30U) 4004 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */ 4005 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */ 4006 #define RCC_APB1ENR_LPTIM1EN_Pos (31U) 4007 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ 4008 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ 4009 4010 /****************** Bit definition for RCC_IOPSMENR register ****************/ 4011 #define RCC_IOPSMENR_IOPASMEN_Pos (0U) 4012 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ 4013 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 4014 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U) 4015 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ 4016 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 4017 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U) 4018 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ 4019 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 4020 #define RCC_IOPSMENR_IOPDSMEN_Pos (3U) 4021 #define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */ 4022 #define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 4023 #define RCC_IOPSMENR_IOPESMEN_Pos (4U) 4024 #define RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */ 4025 #define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 4026 #define RCC_IOPSMENR_IOPHSMEN_Pos (7U) 4027 #define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ 4028 #define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 4029 4030 /* Reference defines */ 4031 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ 4032 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */ 4033 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */ 4034 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */ 4035 #define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */ 4036 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ 4037 4038 /***************** Bit definition for RCC_AHBSMENR register ******************/ 4039 #define RCC_AHBSMENR_DMASMEN_Pos (0U) 4040 #define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ 4041 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ 4042 #define RCC_AHBSMENR_MIFSMEN_Pos (8U) 4043 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ 4044 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ 4045 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U) 4046 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ 4047 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ 4048 #define RCC_AHBSMENR_CRCSMEN_Pos (12U) 4049 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 4050 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ 4051 #define RCC_AHBSMENR_CRYPSMEN_Pos (24U) 4052 #define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */ 4053 #define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */ 4054 4055 /* Reference defines */ 4056 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ 4057 4058 /***************** Bit definition for RCC_APB2SMENR register ******************/ 4059 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) 4060 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 4061 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ 4062 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U) 4063 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ 4064 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ 4065 #define RCC_APB2SMENR_TIM22SMEN_Pos (5U) 4066 #define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ 4067 #define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ 4068 #define RCC_APB2SMENR_ADCSMEN_Pos (9U) 4069 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ 4070 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ 4071 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 4072 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 4073 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ 4074 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 4075 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ 4076 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */ 4077 #define RCC_APB2SMENR_DBGSMEN_Pos (22U) 4078 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ 4079 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ 4080 4081 /* Reference defines */ 4082 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ 4083 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ 4084 4085 /***************** Bit definition for RCC_APB1SMENR register ******************/ 4086 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U) 4087 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ 4088 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 4089 #define RCC_APB1SMENR_TIM3SMEN_Pos (1U) 4090 #define RCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */ 4091 #define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 4092 #define RCC_APB1SMENR_TIM6SMEN_Pos (4U) 4093 #define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */ 4094 #define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 4095 #define RCC_APB1SMENR_TIM7SMEN_Pos (5U) 4096 #define RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */ 4097 #define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 4098 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U) 4099 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ 4100 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 4101 #define RCC_APB1SMENR_SPI2SMEN_Pos (14U) 4102 #define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */ 4103 #define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */ 4104 #define RCC_APB1SMENR_USART2SMEN_Pos (17U) 4105 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ 4106 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ 4107 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) 4108 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ 4109 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ 4110 #define RCC_APB1SMENR_USART4SMEN_Pos (19U) 4111 #define RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */ 4112 #define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */ 4113 #define RCC_APB1SMENR_USART5SMEN_Pos (20U) 4114 #define RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */ 4115 #define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */ 4116 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U) 4117 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ 4118 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ 4119 #define RCC_APB1SMENR_I2C2SMEN_Pos (22U) 4120 #define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ 4121 #define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ 4122 #define RCC_APB1SMENR_PWRSMEN_Pos (28U) 4123 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ 4124 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ 4125 #define RCC_APB1SMENR_I2C3SMEN_Pos (30U) 4126 #define RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */ 4127 #define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */ 4128 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) 4129 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 4130 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ 4131 4132 /******************* Bit definition for RCC_CCIPR register *******************/ 4133 /*!< USART1 Clock source selection */ 4134 #define RCC_CCIPR_USART1SEL_Pos (0U) 4135 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 4136 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */ 4137 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 4138 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 4139 4140 /*!< USART2 Clock source selection */ 4141 #define RCC_CCIPR_USART2SEL_Pos (2U) 4142 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ 4143 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ 4144 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ 4145 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ 4146 4147 /*!< LPUART1 Clock source selection */ 4148 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 4149 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ 4150 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ 4151 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ 4152 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ 4153 4154 /*!< I2C1 Clock source selection */ 4155 #define RCC_CCIPR_I2C1SEL_Pos (12U) 4156 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 4157 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ 4158 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 4159 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 4160 4161 /*!< I2C3 Clock source selection */ 4162 #define RCC_CCIPR_I2C3SEL_Pos (16U) 4163 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ 4164 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */ 4165 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ 4166 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ 4167 4168 /*!< LPTIM1 Clock source selection */ 4169 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 4170 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 4171 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ 4172 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 4173 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 4174 4175 /******************* Bit definition for RCC_CSR register *******************/ 4176 #define RCC_CSR_LSION_Pos (0U) 4177 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 4178 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 4179 #define RCC_CSR_LSIRDY_Pos (1U) 4180 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 4181 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 4182 4183 #define RCC_CSR_LSEON_Pos (8U) 4184 #define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 4185 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 4186 #define RCC_CSR_LSERDY_Pos (9U) 4187 #define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 4188 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 4189 #define RCC_CSR_LSEBYP_Pos (10U) 4190 #define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 4191 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 4192 4193 #define RCC_CSR_LSEDRV_Pos (11U) 4194 #define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ 4195 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 4196 #define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ 4197 #define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ 4198 4199 #define RCC_CSR_LSECSSON_Pos (13U) 4200 #define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ 4201 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 4202 #define RCC_CSR_LSECSSD_Pos (14U) 4203 #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ 4204 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 4205 4206 /*!< RTC configuration */ 4207 #define RCC_CSR_RTCSEL_Pos (16U) 4208 #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 4209 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 4210 #define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 4211 #define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 4212 4213 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4214 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 4215 #define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 4216 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 4217 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 4218 #define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 4219 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 4220 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 4221 #define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 4222 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ 4223 4224 #define RCC_CSR_RTCEN_Pos (18U) 4225 #define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ 4226 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 4227 #define RCC_CSR_RTCRST_Pos (19U) 4228 #define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ 4229 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ 4230 4231 #define RCC_CSR_RMVF_Pos (23U) 4232 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 4233 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 4234 #define RCC_CSR_FWRSTF_Pos (24U) 4235 #define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ 4236 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ 4237 #define RCC_CSR_OBLRSTF_Pos (25U) 4238 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 4239 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 4240 #define RCC_CSR_PINRSTF_Pos (26U) 4241 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 4242 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 4243 #define RCC_CSR_PORRSTF_Pos (27U) 4244 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 4245 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 4246 #define RCC_CSR_SFTRSTF_Pos (28U) 4247 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 4248 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 4249 #define RCC_CSR_IWDGRSTF_Pos (29U) 4250 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 4251 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 4252 #define RCC_CSR_WWDGRSTF_Pos (30U) 4253 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 4254 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 4255 #define RCC_CSR_LPWRRSTF_Pos (31U) 4256 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 4257 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 4258 4259 /* Reference defines */ 4260 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 4261 4262 4263 /******************************************************************************/ 4264 /* */ 4265 /* Real-Time Clock (RTC) */ 4266 /* */ 4267 /******************************************************************************/ 4268 /* 4269 * @brief Specific device feature definitions 4270 */ 4271 #define RTC_TAMPER1_SUPPORT 4272 #define RTC_TAMPER2_SUPPORT 4273 #define RTC_TAMPER3_SUPPORT 4274 #define RTC_WAKEUP_SUPPORT 4275 #define RTC_BACKUP_SUPPORT 4276 4277 /******************** Bits definition for RTC_TR register *******************/ 4278 #define RTC_TR_PM_Pos (22U) 4279 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4280 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */ 4281 #define RTC_TR_HT_Pos (20U) 4282 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4283 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */ 4284 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4285 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4286 #define RTC_TR_HU_Pos (16U) 4287 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4288 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */ 4289 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4290 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4291 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4292 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4293 #define RTC_TR_MNT_Pos (12U) 4294 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4295 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ 4296 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4297 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4298 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4299 #define RTC_TR_MNU_Pos (8U) 4300 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 4301 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ 4302 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 4303 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 4304 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 4305 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 4306 #define RTC_TR_ST_Pos (4U) 4307 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 4308 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */ 4309 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 4310 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 4311 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 4312 #define RTC_TR_SU_Pos (0U) 4313 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 4314 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */ 4315 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 4316 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 4317 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 4318 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 4319 4320 /******************** Bits definition for RTC_DR register *******************/ 4321 #define RTC_DR_YT_Pos (20U) 4322 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 4323 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */ 4324 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 4325 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 4326 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 4327 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 4328 #define RTC_DR_YU_Pos (16U) 4329 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 4330 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */ 4331 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 4332 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 4333 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 4334 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 4335 #define RTC_DR_WDU_Pos (13U) 4336 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 4337 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ 4338 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 4339 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 4340 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 4341 #define RTC_DR_MT_Pos (12U) 4342 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 4343 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */ 4344 #define RTC_DR_MU_Pos (8U) 4345 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 4346 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */ 4347 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4348 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4349 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4350 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4351 #define RTC_DR_DT_Pos (4U) 4352 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4353 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */ 4354 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4355 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4356 #define RTC_DR_DU_Pos (0U) 4357 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4358 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */ 4359 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4360 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4361 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4362 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4363 4364 /******************** Bits definition for RTC_CR register *******************/ 4365 #define RTC_CR_COE_Pos (23U) 4366 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4367 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */ 4368 #define RTC_CR_OSEL_Pos (21U) 4369 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4370 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ 4371 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4372 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4373 #define RTC_CR_POL_Pos (20U) 4374 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4375 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */ 4376 #define RTC_CR_COSEL_Pos (19U) 4377 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4378 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ 4379 #define RTC_CR_BKP_Pos (18U) 4380 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 4381 #define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */ 4382 #define RTC_CR_SUB1H_Pos (17U) 4383 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4384 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ 4385 #define RTC_CR_ADD1H_Pos (16U) 4386 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4387 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ 4388 #define RTC_CR_TSIE_Pos (15U) 4389 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4390 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ 4391 #define RTC_CR_WUTIE_Pos (14U) 4392 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 4393 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ 4394 #define RTC_CR_ALRBIE_Pos (13U) 4395 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 4396 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ 4397 #define RTC_CR_ALRAIE_Pos (12U) 4398 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4399 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ 4400 #define RTC_CR_TSE_Pos (11U) 4401 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4402 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ 4403 #define RTC_CR_WUTE_Pos (10U) 4404 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 4405 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ 4406 #define RTC_CR_ALRBE_Pos (9U) 4407 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 4408 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ 4409 #define RTC_CR_ALRAE_Pos (8U) 4410 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4411 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ 4412 #define RTC_CR_FMT_Pos (6U) 4413 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4414 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ 4415 #define RTC_CR_BYPSHAD_Pos (5U) 4416 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4417 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ 4418 #define RTC_CR_REFCKON_Pos (4U) 4419 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4420 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ 4421 #define RTC_CR_TSEDGE_Pos (3U) 4422 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4423 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ 4424 #define RTC_CR_WUCKSEL_Pos (0U) 4425 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 4426 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ 4427 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 4428 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 4429 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 4430 4431 /******************** Bits definition for RTC_ISR register ******************/ 4432 #define RTC_ISR_RECALPF_Pos (16U) 4433 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 4434 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ 4435 #define RTC_ISR_TAMP3F_Pos (15U) 4436 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 4437 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ 4438 #define RTC_ISR_TAMP2F_Pos (14U) 4439 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 4440 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ 4441 #define RTC_ISR_TAMP1F_Pos (13U) 4442 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 4443 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ 4444 #define RTC_ISR_TSOVF_Pos (12U) 4445 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 4446 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ 4447 #define RTC_ISR_TSF_Pos (11U) 4448 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 4449 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ 4450 #define RTC_ISR_WUTF_Pos (10U) 4451 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 4452 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ 4453 #define RTC_ISR_ALRBF_Pos (9U) 4454 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 4455 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ 4456 #define RTC_ISR_ALRAF_Pos (8U) 4457 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 4458 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ 4459 #define RTC_ISR_INIT_Pos (7U) 4460 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 4461 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ 4462 #define RTC_ISR_INITF_Pos (6U) 4463 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 4464 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ 4465 #define RTC_ISR_RSF_Pos (5U) 4466 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 4467 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ 4468 #define RTC_ISR_INITS_Pos (4U) 4469 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 4470 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ 4471 #define RTC_ISR_SHPF_Pos (3U) 4472 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 4473 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ 4474 #define RTC_ISR_WUTWF_Pos (2U) 4475 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 4476 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ 4477 #define RTC_ISR_ALRBWF_Pos (1U) 4478 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 4479 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ 4480 #define RTC_ISR_ALRAWF_Pos (0U) 4481 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 4482 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ 4483 4484 /******************** Bits definition for RTC_PRER register *****************/ 4485 #define RTC_PRER_PREDIV_A_Pos (16U) 4486 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4487 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ 4488 #define RTC_PRER_PREDIV_S_Pos (0U) 4489 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4490 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ 4491 4492 /******************** Bits definition for RTC_WUTR register *****************/ 4493 #define RTC_WUTR_WUT_Pos (0U) 4494 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 4495 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 4496 4497 /******************** Bits definition for RTC_ALRMAR register ***************/ 4498 #define RTC_ALRMAR_MSK4_Pos (31U) 4499 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4500 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ 4501 #define RTC_ALRMAR_WDSEL_Pos (30U) 4502 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4503 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ 4504 #define RTC_ALRMAR_DT_Pos (28U) 4505 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4506 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ 4507 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4508 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4509 #define RTC_ALRMAR_DU_Pos (24U) 4510 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4511 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ 4512 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4513 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4514 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4515 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4516 #define RTC_ALRMAR_MSK3_Pos (23U) 4517 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4518 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ 4519 #define RTC_ALRMAR_PM_Pos (22U) 4520 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4521 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ 4522 #define RTC_ALRMAR_HT_Pos (20U) 4523 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4524 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ 4525 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4526 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4527 #define RTC_ALRMAR_HU_Pos (16U) 4528 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4529 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ 4530 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4531 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4532 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4533 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4534 #define RTC_ALRMAR_MSK2_Pos (15U) 4535 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4536 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ 4537 #define RTC_ALRMAR_MNT_Pos (12U) 4538 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4539 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ 4540 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4541 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4542 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4543 #define RTC_ALRMAR_MNU_Pos (8U) 4544 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4545 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ 4546 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4547 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4548 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4549 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4550 #define RTC_ALRMAR_MSK1_Pos (7U) 4551 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4552 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ 4553 #define RTC_ALRMAR_ST_Pos (4U) 4554 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4555 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ 4556 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4557 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4558 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4559 #define RTC_ALRMAR_SU_Pos (0U) 4560 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4561 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ 4562 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4563 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4564 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4565 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4566 4567 /******************** Bits definition for RTC_ALRMBR register ***************/ 4568 #define RTC_ALRMBR_MSK4_Pos (31U) 4569 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 4570 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ 4571 #define RTC_ALRMBR_WDSEL_Pos (30U) 4572 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 4573 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ 4574 #define RTC_ALRMBR_DT_Pos (28U) 4575 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 4576 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ 4577 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 4578 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 4579 #define RTC_ALRMBR_DU_Pos (24U) 4580 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 4581 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ 4582 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 4583 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 4584 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 4585 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 4586 #define RTC_ALRMBR_MSK3_Pos (23U) 4587 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 4588 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ 4589 #define RTC_ALRMBR_PM_Pos (22U) 4590 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 4591 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ 4592 #define RTC_ALRMBR_HT_Pos (20U) 4593 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 4594 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ 4595 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 4596 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 4597 #define RTC_ALRMBR_HU_Pos (16U) 4598 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 4599 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ 4600 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 4601 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 4602 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 4603 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 4604 #define RTC_ALRMBR_MSK2_Pos (15U) 4605 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 4606 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ 4607 #define RTC_ALRMBR_MNT_Pos (12U) 4608 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 4609 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ 4610 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 4611 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 4612 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 4613 #define RTC_ALRMBR_MNU_Pos (8U) 4614 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 4615 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ 4616 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 4617 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 4618 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 4619 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 4620 #define RTC_ALRMBR_MSK1_Pos (7U) 4621 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 4622 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ 4623 #define RTC_ALRMBR_ST_Pos (4U) 4624 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 4625 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ 4626 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 4627 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 4628 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 4629 #define RTC_ALRMBR_SU_Pos (0U) 4630 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 4631 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ 4632 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 4633 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 4634 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 4635 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 4636 4637 /******************** Bits definition for RTC_WPR register ******************/ 4638 #define RTC_WPR_KEY_Pos (0U) 4639 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4640 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ 4641 4642 /******************** Bits definition for RTC_SSR register ******************/ 4643 #define RTC_SSR_SS_Pos (0U) 4644 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4645 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ 4646 4647 /******************** Bits definition for RTC_SHIFTR register ***************/ 4648 #define RTC_SHIFTR_SUBFS_Pos (0U) 4649 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4650 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ 4651 #define RTC_SHIFTR_ADD1S_Pos (31U) 4652 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4653 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ 4654 4655 /******************** Bits definition for RTC_TSTR register *****************/ 4656 #define RTC_TSTR_PM_Pos (22U) 4657 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4658 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ 4659 #define RTC_TSTR_HT_Pos (20U) 4660 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4661 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ 4662 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4663 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4664 #define RTC_TSTR_HU_Pos (16U) 4665 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4666 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ 4667 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4668 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4669 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4670 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4671 #define RTC_TSTR_MNT_Pos (12U) 4672 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4673 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ 4674 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4675 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4676 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4677 #define RTC_TSTR_MNU_Pos (8U) 4678 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4679 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ 4680 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4681 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4682 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4683 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4684 #define RTC_TSTR_ST_Pos (4U) 4685 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4686 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ 4687 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4688 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4689 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4690 #define RTC_TSTR_SU_Pos (0U) 4691 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4692 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ 4693 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4694 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4695 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4696 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4697 4698 /******************** Bits definition for RTC_TSDR register *****************/ 4699 #define RTC_TSDR_WDU_Pos (13U) 4700 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4701 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ 4702 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4703 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4704 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4705 #define RTC_TSDR_MT_Pos (12U) 4706 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4707 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ 4708 #define RTC_TSDR_MU_Pos (8U) 4709 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4710 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ 4711 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4712 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4713 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4714 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4715 #define RTC_TSDR_DT_Pos (4U) 4716 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4717 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ 4718 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4719 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4720 #define RTC_TSDR_DU_Pos (0U) 4721 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4722 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ 4723 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4724 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4725 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4726 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4727 4728 /******************** Bits definition for RTC_TSSSR register ****************/ 4729 #define RTC_TSSSR_SS_Pos (0U) 4730 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4731 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 4732 4733 /******************** Bits definition for RTC_CALR register *****************/ 4734 #define RTC_CALR_CALP_Pos (15U) 4735 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4736 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ 4737 #define RTC_CALR_CALW8_Pos (14U) 4738 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4739 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ 4740 #define RTC_CALR_CALW16_Pos (13U) 4741 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4742 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ 4743 #define RTC_CALR_CALM_Pos (0U) 4744 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4745 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ 4746 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4747 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4748 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4749 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4750 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4751 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4752 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4753 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4754 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4755 4756 /* Legacy defines */ 4757 #define RTC_CAL_CALP RTC_CALR_CALP 4758 #define RTC_CAL_CALW8 RTC_CALR_CALW8 4759 #define RTC_CAL_CALW16 RTC_CALR_CALW16 4760 #define RTC_CAL_CALM RTC_CALR_CALM 4761 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0 4762 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1 4763 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2 4764 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3 4765 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4 4766 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5 4767 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6 4768 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7 4769 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 4770 4771 /******************** Bits definition for RTC_TAMPCR register ****************/ 4772 #define RTC_TAMPCR_TAMP3MF_Pos (24U) 4773 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ 4774 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ 4775 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) 4776 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ 4777 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ 4778 #define RTC_TAMPCR_TAMP3IE_Pos (22U) 4779 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ 4780 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ 4781 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 4782 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ 4783 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ 4784 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 4785 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ 4786 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ 4787 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 4788 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ 4789 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ 4790 #define RTC_TAMPCR_TAMP1MF_Pos (18U) 4791 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ 4792 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ 4793 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) 4794 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ 4795 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ 4796 #define RTC_TAMPCR_TAMP1IE_Pos (16U) 4797 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ 4798 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ 4799 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 4800 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 4801 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ 4802 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 4803 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 4804 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ 4805 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 4806 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 4807 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 4808 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ 4809 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ 4810 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ 4811 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ 4812 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 4813 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 4814 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ 4815 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 4816 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 4817 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 4818 #define RTC_TAMPCR_TAMPTS_Pos (7U) 4819 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ 4820 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ 4821 #define RTC_TAMPCR_TAMP3TRG_Pos (6U) 4822 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 4823 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ 4824 #define RTC_TAMPCR_TAMP3E_Pos (5U) 4825 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ 4826 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ 4827 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 4828 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 4829 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ 4830 #define RTC_TAMPCR_TAMP2E_Pos (3U) 4831 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ 4832 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ 4833 #define RTC_TAMPCR_TAMPIE_Pos (2U) 4834 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ 4835 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ 4836 #define RTC_TAMPCR_TAMP1TRG_Pos (1U) 4837 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 4838 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ 4839 #define RTC_TAMPCR_TAMP1E_Pos (0U) 4840 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ 4841 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ 4842 4843 /******************** Bits definition for RTC_ALRMASSR register *************/ 4844 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4845 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4846 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4847 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4848 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4849 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4850 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4851 #define RTC_ALRMASSR_SS_Pos (0U) 4852 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4853 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4854 4855 /******************** Bits definition for RTC_ALRMBSSR register *************/ 4856 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 4857 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 4858 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 4859 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 4860 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 4861 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 4862 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 4863 #define RTC_ALRMBSSR_SS_Pos (0U) 4864 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 4865 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 4866 4867 /******************** Bits definition for RTC_OR register ****************/ 4868 #define RTC_OR_OUT_RMP_Pos (1U) 4869 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ 4870 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ 4871 #define RTC_OR_ALARMOUTTYPE_Pos (0U) 4872 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ 4873 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ 4874 4875 /* Legacy defines */ 4876 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP 4877 4878 /******************** Bits definition for RTC_BKP0R register ****************/ 4879 #define RTC_BKP0R_Pos (0U) 4880 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 4881 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */ 4882 4883 /******************** Bits definition for RTC_BKP1R register ****************/ 4884 #define RTC_BKP1R_Pos (0U) 4885 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 4886 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */ 4887 4888 /******************** Bits definition for RTC_BKP2R register ****************/ 4889 #define RTC_BKP2R_Pos (0U) 4890 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 4891 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */ 4892 4893 /******************** Bits definition for RTC_BKP3R register ****************/ 4894 #define RTC_BKP3R_Pos (0U) 4895 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 4896 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */ 4897 4898 /******************** Bits definition for RTC_BKP4R register ****************/ 4899 #define RTC_BKP4R_Pos (0U) 4900 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 4901 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */ 4902 4903 /******************** Number of backup registers ******************************/ 4904 #define RTC_BKP_NUMBER (0x00000005U) /*!< */ 4905 4906 /******************************************************************************/ 4907 /* */ 4908 /* Serial Peripheral Interface (SPI) */ 4909 /* */ 4910 /******************************************************************************/ 4911 4912 /* 4913 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 4914 */ 4915 #define SPI_I2S_SUPPORT /*!< I2S support */ 4916 4917 /******************* Bit definition for SPI_CR1 register ********************/ 4918 #define SPI_CR1_CPHA_Pos (0U) 4919 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4920 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4921 #define SPI_CR1_CPOL_Pos (1U) 4922 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4923 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4924 #define SPI_CR1_MSTR_Pos (2U) 4925 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4926 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4927 #define SPI_CR1_BR_Pos (3U) 4928 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4929 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4930 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4931 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4932 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4933 #define SPI_CR1_SPE_Pos (6U) 4934 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4935 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4936 #define SPI_CR1_LSBFIRST_Pos (7U) 4937 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4938 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4939 #define SPI_CR1_SSI_Pos (8U) 4940 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4941 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4942 #define SPI_CR1_SSM_Pos (9U) 4943 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4944 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4945 #define SPI_CR1_RXONLY_Pos (10U) 4946 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4947 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4948 #define SPI_CR1_DFF_Pos (11U) 4949 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 4950 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 4951 #define SPI_CR1_CRCNEXT_Pos (12U) 4952 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4953 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4954 #define SPI_CR1_CRCEN_Pos (13U) 4955 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4956 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4957 #define SPI_CR1_BIDIOE_Pos (14U) 4958 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4959 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4960 #define SPI_CR1_BIDIMODE_Pos (15U) 4961 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4962 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4963 4964 /******************* Bit definition for SPI_CR2 register ********************/ 4965 #define SPI_CR2_RXDMAEN_Pos (0U) 4966 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4967 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4968 #define SPI_CR2_TXDMAEN_Pos (1U) 4969 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4970 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4971 #define SPI_CR2_SSOE_Pos (2U) 4972 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4973 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4974 #define SPI_CR2_FRF_Pos (4U) 4975 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4976 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4977 #define SPI_CR2_ERRIE_Pos (5U) 4978 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4979 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4980 #define SPI_CR2_RXNEIE_Pos (6U) 4981 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4982 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4983 #define SPI_CR2_TXEIE_Pos (7U) 4984 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4985 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4986 4987 /******************** Bit definition for SPI_SR register ********************/ 4988 #define SPI_SR_RXNE_Pos (0U) 4989 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4990 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4991 #define SPI_SR_TXE_Pos (1U) 4992 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4993 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4994 #define SPI_SR_CHSIDE_Pos (2U) 4995 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4996 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4997 #define SPI_SR_UDR_Pos (3U) 4998 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4999 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5000 #define SPI_SR_CRCERR_Pos (4U) 5001 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5002 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5003 #define SPI_SR_MODF_Pos (5U) 5004 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5005 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5006 #define SPI_SR_OVR_Pos (6U) 5007 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5008 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5009 #define SPI_SR_BSY_Pos (7U) 5010 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5011 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5012 #define SPI_SR_FRE_Pos (8U) 5013 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5014 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 5015 5016 /******************** Bit definition for SPI_DR register ********************/ 5017 #define SPI_DR_DR_Pos (0U) 5018 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5019 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 5020 5021 /******************* Bit definition for SPI_CRCPR register ******************/ 5022 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5023 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5024 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 5025 5026 /****************** Bit definition for SPI_RXCRCR register ******************/ 5027 #define SPI_RXCRCR_RXCRC_Pos (0U) 5028 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5029 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 5030 5031 /****************** Bit definition for SPI_TXCRCR register ******************/ 5032 #define SPI_TXCRCR_TXCRC_Pos (0U) 5033 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5034 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 5035 5036 /****************** Bit definition for SPI_I2SCFGR register *****************/ 5037 #define SPI_I2SCFGR_CHLEN_Pos (0U) 5038 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 5039 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 5040 #define SPI_I2SCFGR_DATLEN_Pos (1U) 5041 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 5042 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 5043 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 5044 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 5045 #define SPI_I2SCFGR_CKPOL_Pos (3U) 5046 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 5047 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 5048 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 5049 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 5050 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 5051 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 5052 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 5053 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 5054 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 5055 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 5056 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 5057 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 5058 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 5059 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 5060 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 5061 #define SPI_I2SCFGR_I2SE_Pos (10U) 5062 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 5063 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 5064 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 5065 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 5066 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 5067 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 5068 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 5069 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 5070 /****************** Bit definition for SPI_I2SPR register *******************/ 5071 #define SPI_I2SPR_I2SDIV_Pos (0U) 5072 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 5073 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 5074 #define SPI_I2SPR_ODD_Pos (8U) 5075 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 5076 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 5077 #define SPI_I2SPR_MCKOE_Pos (9U) 5078 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 5079 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 5080 5081 /******************************************************************************/ 5082 /* */ 5083 /* System Configuration (SYSCFG) */ 5084 /* */ 5085 /******************************************************************************/ 5086 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 5087 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 5088 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 5089 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5090 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 5091 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 5092 #define SYSCFG_CFGR1_UFB_Pos (3U) 5093 #define SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */ 5094 #define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */ 5095 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U) 5096 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */ 5097 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */ 5098 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */ 5099 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */ 5100 5101 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 5102 #define SYSCFG_CFGR2_FWDISEN_Pos (0U) 5103 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */ 5104 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */ 5105 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U) 5106 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */ 5107 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 5108 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U) 5109 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */ 5110 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 5111 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U) 5112 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */ 5113 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 5114 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U) 5115 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */ 5116 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 5117 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U) 5118 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */ 5119 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 5120 #define SYSCFG_CFGR2_I2C2_FMP_Pos (13U) 5121 #define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */ 5122 #define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ 5123 #define SYSCFG_CFGR2_I2C3_FMP_Pos (14U) 5124 #define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */ 5125 #define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ 5126 5127 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 5128 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 5129 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 5130 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 5131 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 5132 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 5133 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 5134 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 5135 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 5136 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 5137 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 5138 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 5139 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 5140 5141 /** 5142 * @brief EXTI0 configuration 5143 */ 5144 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 5145 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 5146 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 5147 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 5148 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 5149 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 5150 5151 /** 5152 * @brief EXTI1 configuration 5153 */ 5154 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 5155 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 5156 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 5157 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 5158 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 5159 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 5160 5161 /** 5162 * @brief EXTI2 configuration 5163 */ 5164 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 5165 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 5166 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 5167 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 5168 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 5169 5170 /** 5171 * @brief EXTI3 configuration 5172 */ 5173 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 5174 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 5175 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 5176 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 5177 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 5178 5179 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 5180 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 5181 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 5182 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 5183 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 5184 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 5185 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 5186 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 5187 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 5188 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 5189 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 5190 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 5191 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 5192 5193 /** 5194 * @brief EXTI4 configuration 5195 */ 5196 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 5197 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 5198 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 5199 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 5200 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 5201 5202 /** 5203 * @brief EXTI5 configuration 5204 */ 5205 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 5206 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 5207 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 5208 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 5209 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 5210 5211 /** 5212 * @brief EXTI6 configuration 5213 */ 5214 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 5215 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 5216 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 5217 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 5218 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 5219 5220 /** 5221 * @brief EXTI7 configuration 5222 */ 5223 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 5224 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 5225 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 5226 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 5227 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 5228 5229 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 5230 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 5231 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 5232 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 5233 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 5234 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 5235 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 5236 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 5237 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 5238 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 5239 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 5240 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 5241 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 5242 5243 /** 5244 * @brief EXTI8 configuration 5245 */ 5246 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 5247 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 5248 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 5249 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 5250 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 5251 5252 /** 5253 * @brief EXTI9 configuration 5254 */ 5255 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 5256 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 5257 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 5258 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 5259 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 5260 #define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */ 5261 5262 /** 5263 * @brief EXTI10 configuration 5264 */ 5265 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 5266 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 5267 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 5268 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 5269 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 5270 #define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */ 5271 5272 /** 5273 * @brief EXTI11 configuration 5274 */ 5275 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 5276 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 5277 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 5278 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 5279 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 5280 5281 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 5282 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 5283 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 5284 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 5285 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 5286 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 5287 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 5288 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 5289 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 5290 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 5291 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 5292 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 5293 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 5294 5295 /** 5296 * @brief EXTI12 configuration 5297 */ 5298 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 5299 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 5300 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 5301 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 5302 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 5303 5304 /** 5305 * @brief EXTI13 configuration 5306 */ 5307 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 5308 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 5309 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 5310 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 5311 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 5312 5313 /** 5314 * @brief EXTI14 configuration 5315 */ 5316 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 5317 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 5318 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 5319 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 5320 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 5321 5322 /** 5323 * @brief EXTI15 configuration 5324 */ 5325 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 5326 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 5327 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 5328 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 5329 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 5330 5331 5332 /***************** Bit definition for SYSCFG_CFGR3 register ****************/ 5333 #define SYSCFG_CFGR3_EN_VREFINT_Pos (0U) 5334 #define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */ 5335 #define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */ 5336 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U) 5337 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */ 5338 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */ 5339 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */ 5340 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */ 5341 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U) 5342 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */ 5343 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */ 5344 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U) 5345 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */ 5346 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */ 5347 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) 5348 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ 5349 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ 5350 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) 5351 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ 5352 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ 5353 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U) 5354 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */ 5355 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */ 5356 5357 /* Legacy defines */ 5358 5359 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT 5360 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC 5361 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP 5362 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5363 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5364 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5365 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5366 5367 /******************************************************************************/ 5368 /* */ 5369 /* Timers (TIM)*/ 5370 /* */ 5371 /******************************************************************************/ 5372 /* 5373 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 5374 */ 5375 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */ 5376 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */ 5377 5378 /******************* Bit definition for TIM_CR1 register ********************/ 5379 #define TIM_CR1_CEN_Pos (0U) 5380 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 5381 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 5382 #define TIM_CR1_UDIS_Pos (1U) 5383 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 5384 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 5385 #define TIM_CR1_URS_Pos (2U) 5386 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 5387 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 5388 #define TIM_CR1_OPM_Pos (3U) 5389 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 5390 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 5391 #define TIM_CR1_DIR_Pos (4U) 5392 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 5393 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 5394 5395 #define TIM_CR1_CMS_Pos (5U) 5396 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 5397 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 5398 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 5399 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 5400 5401 #define TIM_CR1_ARPE_Pos (7U) 5402 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 5403 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 5404 5405 #define TIM_CR1_CKD_Pos (8U) 5406 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 5407 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 5408 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 5409 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 5410 5411 /******************* Bit definition for TIM_CR2 register ********************/ 5412 #define TIM_CR2_CCDS_Pos (3U) 5413 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 5414 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 5415 5416 #define TIM_CR2_MMS_Pos (4U) 5417 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 5418 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5419 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 5420 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 5421 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 5422 5423 #define TIM_CR2_TI1S_Pos (7U) 5424 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 5425 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 5426 5427 /******************* Bit definition for TIM_SMCR register *******************/ 5428 #define TIM_SMCR_SMS_Pos (0U) 5429 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 5430 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 5431 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 5432 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 5433 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 5434 5435 #define TIM_SMCR_TS_Pos (4U) 5436 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 5437 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 5438 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 5439 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 5440 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 5441 5442 #define TIM_SMCR_MSM_Pos (7U) 5443 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 5444 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 5445 5446 #define TIM_SMCR_ETF_Pos (8U) 5447 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 5448 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 5449 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 5450 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 5451 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 5452 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5453 5454 #define TIM_SMCR_ETPS_Pos (12U) 5455 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5456 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5457 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5458 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5459 5460 #define TIM_SMCR_ECE_Pos (14U) 5461 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5462 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5463 #define TIM_SMCR_ETP_Pos (15U) 5464 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5465 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5466 5467 /******************* Bit definition for TIM_DIER register *******************/ 5468 #define TIM_DIER_UIE_Pos (0U) 5469 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5470 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5471 #define TIM_DIER_CC1IE_Pos (1U) 5472 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5473 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5474 #define TIM_DIER_CC2IE_Pos (2U) 5475 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5476 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5477 #define TIM_DIER_CC3IE_Pos (3U) 5478 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5479 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5480 #define TIM_DIER_CC4IE_Pos (4U) 5481 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5482 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5483 #define TIM_DIER_TIE_Pos (6U) 5484 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5485 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5486 #define TIM_DIER_UDE_Pos (8U) 5487 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5488 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5489 #define TIM_DIER_CC1DE_Pos (9U) 5490 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5491 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5492 #define TIM_DIER_CC2DE_Pos (10U) 5493 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5494 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5495 #define TIM_DIER_CC3DE_Pos (11U) 5496 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5497 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5498 #define TIM_DIER_CC4DE_Pos (12U) 5499 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5500 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5501 #define TIM_DIER_TDE_Pos (14U) 5502 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5503 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5504 5505 /******************** Bit definition for TIM_SR register ********************/ 5506 #define TIM_SR_UIF_Pos (0U) 5507 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5508 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5509 #define TIM_SR_CC1IF_Pos (1U) 5510 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5511 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5512 #define TIM_SR_CC2IF_Pos (2U) 5513 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5514 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5515 #define TIM_SR_CC3IF_Pos (3U) 5516 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5517 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5518 #define TIM_SR_CC4IF_Pos (4U) 5519 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5520 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5521 #define TIM_SR_TIF_Pos (6U) 5522 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5523 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5524 #define TIM_SR_CC1OF_Pos (9U) 5525 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5526 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5527 #define TIM_SR_CC2OF_Pos (10U) 5528 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5529 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5530 #define TIM_SR_CC3OF_Pos (11U) 5531 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5532 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5533 #define TIM_SR_CC4OF_Pos (12U) 5534 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5535 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5536 5537 /******************* Bit definition for TIM_EGR register ********************/ 5538 #define TIM_EGR_UG_Pos (0U) 5539 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5540 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5541 #define TIM_EGR_CC1G_Pos (1U) 5542 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5543 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5544 #define TIM_EGR_CC2G_Pos (2U) 5545 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5546 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5547 #define TIM_EGR_CC3G_Pos (3U) 5548 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5549 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5550 #define TIM_EGR_CC4G_Pos (4U) 5551 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5552 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5553 #define TIM_EGR_TG_Pos (6U) 5554 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5555 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5556 5557 /****************** Bit definition for TIM_CCMR1 register *******************/ 5558 #define TIM_CCMR1_CC1S_Pos (0U) 5559 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5560 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5561 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5562 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5563 5564 #define TIM_CCMR1_OC1FE_Pos (2U) 5565 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5566 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5567 #define TIM_CCMR1_OC1PE_Pos (3U) 5568 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5569 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5570 5571 #define TIM_CCMR1_OC1M_Pos (4U) 5572 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 5573 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5574 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5575 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5576 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5577 5578 #define TIM_CCMR1_OC1CE_Pos (7U) 5579 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5580 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 5581 5582 #define TIM_CCMR1_CC2S_Pos (8U) 5583 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5584 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5585 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5586 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5587 5588 #define TIM_CCMR1_OC2FE_Pos (10U) 5589 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5590 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5591 #define TIM_CCMR1_OC2PE_Pos (11U) 5592 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5593 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5594 5595 #define TIM_CCMR1_OC2M_Pos (12U) 5596 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 5597 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5598 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5599 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5600 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5601 5602 #define TIM_CCMR1_OC2CE_Pos (15U) 5603 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5604 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5605 5606 /*----------------------------------------------------------------------------*/ 5607 5608 #define TIM_CCMR1_IC1PSC_Pos (2U) 5609 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5610 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5611 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5612 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5613 5614 #define TIM_CCMR1_IC1F_Pos (4U) 5615 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5616 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5617 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5618 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5619 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5620 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5621 5622 #define TIM_CCMR1_IC2PSC_Pos (10U) 5623 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5624 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5625 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5626 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5627 5628 #define TIM_CCMR1_IC2F_Pos (12U) 5629 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5630 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5631 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5632 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5633 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5634 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5635 5636 /****************** Bit definition for TIM_CCMR2 register *******************/ 5637 #define TIM_CCMR2_CC3S_Pos (0U) 5638 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5639 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5640 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5641 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5642 5643 #define TIM_CCMR2_OC3FE_Pos (2U) 5644 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5645 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5646 #define TIM_CCMR2_OC3PE_Pos (3U) 5647 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5648 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5649 5650 #define TIM_CCMR2_OC3M_Pos (4U) 5651 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 5652 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5653 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5654 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5655 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5656 5657 #define TIM_CCMR2_OC3CE_Pos (7U) 5658 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5659 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5660 5661 #define TIM_CCMR2_CC4S_Pos (8U) 5662 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5663 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5664 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5665 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5666 5667 #define TIM_CCMR2_OC4FE_Pos (10U) 5668 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5669 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5670 #define TIM_CCMR2_OC4PE_Pos (11U) 5671 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5672 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5673 5674 #define TIM_CCMR2_OC4M_Pos (12U) 5675 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 5676 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5677 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5678 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5679 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5680 5681 #define TIM_CCMR2_OC4CE_Pos (15U) 5682 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5683 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5684 5685 /*----------------------------------------------------------------------------*/ 5686 5687 #define TIM_CCMR2_IC3PSC_Pos (2U) 5688 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 5689 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5690 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 5691 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 5692 5693 #define TIM_CCMR2_IC3F_Pos (4U) 5694 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 5695 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5696 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 5697 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 5698 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 5699 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 5700 5701 #define TIM_CCMR2_IC4PSC_Pos (10U) 5702 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 5703 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5704 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 5705 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 5706 5707 #define TIM_CCMR2_IC4F_Pos (12U) 5708 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 5709 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5710 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 5711 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 5712 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 5713 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 5714 5715 /******************* Bit definition for TIM_CCER register *******************/ 5716 #define TIM_CCER_CC1E_Pos (0U) 5717 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 5718 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 5719 #define TIM_CCER_CC1P_Pos (1U) 5720 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 5721 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 5722 #define TIM_CCER_CC1NP_Pos (3U) 5723 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 5724 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 5725 #define TIM_CCER_CC2E_Pos (4U) 5726 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 5727 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 5728 #define TIM_CCER_CC2P_Pos (5U) 5729 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 5730 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 5731 #define TIM_CCER_CC2NP_Pos (7U) 5732 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 5733 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 5734 #define TIM_CCER_CC3E_Pos (8U) 5735 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 5736 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 5737 #define TIM_CCER_CC3P_Pos (9U) 5738 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 5739 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 5740 #define TIM_CCER_CC3NP_Pos (11U) 5741 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 5742 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 5743 #define TIM_CCER_CC4E_Pos (12U) 5744 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 5745 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 5746 #define TIM_CCER_CC4P_Pos (13U) 5747 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 5748 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 5749 #define TIM_CCER_CC4NP_Pos (15U) 5750 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 5751 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 5752 5753 /******************* Bit definition for TIM_CNT register ********************/ 5754 #define TIM_CNT_CNT_Pos (0U) 5755 #define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 5756 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 5757 5758 /******************* Bit definition for TIM_PSC register ********************/ 5759 #define TIM_PSC_PSC_Pos (0U) 5760 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 5761 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 5762 5763 /******************* Bit definition for TIM_ARR register ********************/ 5764 #define TIM_ARR_ARR_Pos (0U) 5765 #define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 5766 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 5767 5768 /******************* Bit definition for TIM_CCR1 register *******************/ 5769 #define TIM_CCR1_CCR1_Pos (0U) 5770 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 5771 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5772 5773 /******************* Bit definition for TIM_CCR2 register *******************/ 5774 #define TIM_CCR2_CCR2_Pos (0U) 5775 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 5776 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5777 5778 /******************* Bit definition for TIM_CCR3 register *******************/ 5779 #define TIM_CCR3_CCR3_Pos (0U) 5780 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 5781 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5782 5783 /******************* Bit definition for TIM_CCR4 register *******************/ 5784 #define TIM_CCR4_CCR4_Pos (0U) 5785 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 5786 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5787 5788 /******************* Bit definition for TIM_DCR register ********************/ 5789 #define TIM_DCR_DBA_Pos (0U) 5790 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5791 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5792 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5793 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5794 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5795 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5796 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5797 5798 #define TIM_DCR_DBL_Pos (8U) 5799 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5800 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5801 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5802 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5803 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5804 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5805 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5806 5807 /******************* Bit definition for TIM_DMAR register *******************/ 5808 #define TIM_DMAR_DMAB_Pos (0U) 5809 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5810 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5811 5812 /******************* Bit definition for TIM_OR register *********************/ 5813 #define TIM2_OR_ETR_RMP_Pos (0U) 5814 #define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */ 5815 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */ 5816 #define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5817 #define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5818 #define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 5819 #define TIM2_OR_TI4_RMP_Pos (3U) 5820 #define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */ 5821 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */ 5822 #define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */ 5823 #define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */ 5824 5825 #define TIM21_OR_ETR_RMP_Pos (0U) 5826 #define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5827 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */ 5828 #define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5829 #define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5830 #define TIM21_OR_TI1_RMP_Pos (2U) 5831 #define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */ 5832 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */ 5833 #define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5834 #define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */ 5835 #define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */ 5836 #define TIM21_OR_TI2_RMP_Pos (5U) 5837 #define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */ 5838 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */ 5839 5840 #define TIM22_OR_ETR_RMP_Pos (0U) 5841 #define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5842 #define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */ 5843 #define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5844 #define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5845 #define TIM22_OR_TI1_RMP_Pos (2U) 5846 #define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */ 5847 #define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */ 5848 #define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5849 #define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */ 5850 5851 #define TIM3_OR_ETR_RMP_Pos (0U) 5852 #define TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5853 #define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */ 5854 #define TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5855 #define TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5856 #define TIM3_OR_TI1_RMP_Pos (2U) 5857 #define TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5858 #define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */ 5859 #define TIM3_OR_TI2_RMP_Pos (3U) 5860 #define TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */ 5861 #define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */ 5862 #define TIM3_OR_TI4_RMP_Pos (4U) 5863 #define TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */ 5864 #define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */ 5865 5866 5867 /******************************************************************************/ 5868 /* */ 5869 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5870 /* */ 5871 /******************************************************************************/ 5872 5873 /* 5874 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 5875 */ 5876 /* Note: No specific macro feature on this device */ 5877 5878 /****************** Bit definition for USART_CR1 register *******************/ 5879 #define USART_CR1_UE_Pos (0U) 5880 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 5881 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5882 #define USART_CR1_UESM_Pos (1U) 5883 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 5884 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 5885 #define USART_CR1_RE_Pos (2U) 5886 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5887 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5888 #define USART_CR1_TE_Pos (3U) 5889 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5890 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5891 #define USART_CR1_IDLEIE_Pos (4U) 5892 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5893 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5894 #define USART_CR1_RXNEIE_Pos (5U) 5895 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5896 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5897 #define USART_CR1_TCIE_Pos (6U) 5898 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5899 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5900 #define USART_CR1_TXEIE_Pos (7U) 5901 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5902 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 5903 #define USART_CR1_PEIE_Pos (8U) 5904 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5905 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5906 #define USART_CR1_PS_Pos (9U) 5907 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5908 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5909 #define USART_CR1_PCE_Pos (10U) 5910 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5911 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5912 #define USART_CR1_WAKE_Pos (11U) 5913 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5914 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 5915 #define USART_CR1_M_Pos (12U) 5916 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 5917 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 5918 #define USART_CR1_M0_Pos (12U) 5919 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 5920 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 5921 #define USART_CR1_MME_Pos (13U) 5922 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 5923 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 5924 #define USART_CR1_CMIE_Pos (14U) 5925 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 5926 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 5927 #define USART_CR1_OVER8_Pos (15U) 5928 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5929 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 5930 #define USART_CR1_DEDT_Pos (16U) 5931 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 5932 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 5933 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 5934 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 5935 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 5936 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 5937 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 5938 #define USART_CR1_DEAT_Pos (21U) 5939 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 5940 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 5941 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 5942 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 5943 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 5944 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 5945 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 5946 #define USART_CR1_RTOIE_Pos (26U) 5947 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 5948 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 5949 #define USART_CR1_EOBIE_Pos (27U) 5950 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 5951 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 5952 #define USART_CR1_M1_Pos (28U) 5953 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 5954 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 5955 /****************** Bit definition for USART_CR2 register *******************/ 5956 #define USART_CR2_ADDM7_Pos (4U) 5957 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 5958 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 5959 #define USART_CR2_LBDL_Pos (5U) 5960 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 5961 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 5962 #define USART_CR2_LBDIE_Pos (6U) 5963 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 5964 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 5965 #define USART_CR2_LBCL_Pos (8U) 5966 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5967 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5968 #define USART_CR2_CPHA_Pos (9U) 5969 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5970 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5971 #define USART_CR2_CPOL_Pos (10U) 5972 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5973 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5974 #define USART_CR2_CLKEN_Pos (11U) 5975 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5976 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5977 #define USART_CR2_STOP_Pos (12U) 5978 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5979 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5980 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5981 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5982 #define USART_CR2_LINEN_Pos (14U) 5983 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 5984 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 5985 #define USART_CR2_SWAP_Pos (15U) 5986 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 5987 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 5988 #define USART_CR2_RXINV_Pos (16U) 5989 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 5990 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 5991 #define USART_CR2_TXINV_Pos (17U) 5992 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 5993 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 5994 #define USART_CR2_DATAINV_Pos (18U) 5995 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 5996 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 5997 #define USART_CR2_MSBFIRST_Pos (19U) 5998 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 5999 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 6000 #define USART_CR2_ABREN_Pos (20U) 6001 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 6002 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 6003 #define USART_CR2_ABRMODE_Pos (21U) 6004 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 6005 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 6006 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 6007 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 6008 #define USART_CR2_RTOEN_Pos (23U) 6009 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 6010 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 6011 #define USART_CR2_ADD_Pos (24U) 6012 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 6013 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6014 6015 /****************** Bit definition for USART_CR3 register *******************/ 6016 #define USART_CR3_EIE_Pos (0U) 6017 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6018 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6019 #define USART_CR3_IREN_Pos (1U) 6020 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6021 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6022 #define USART_CR3_IRLP_Pos (2U) 6023 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6024 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6025 #define USART_CR3_HDSEL_Pos (3U) 6026 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6027 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6028 #define USART_CR3_NACK_Pos (4U) 6029 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6030 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 6031 #define USART_CR3_SCEN_Pos (5U) 6032 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6033 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 6034 #define USART_CR3_DMAR_Pos (6U) 6035 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6036 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6037 #define USART_CR3_DMAT_Pos (7U) 6038 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6039 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6040 #define USART_CR3_RTSE_Pos (8U) 6041 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6042 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6043 #define USART_CR3_CTSE_Pos (9U) 6044 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6045 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6046 #define USART_CR3_CTSIE_Pos (10U) 6047 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6048 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6049 #define USART_CR3_ONEBIT_Pos (11U) 6050 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6051 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6052 #define USART_CR3_OVRDIS_Pos (12U) 6053 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 6054 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 6055 #define USART_CR3_DDRE_Pos (13U) 6056 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 6057 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 6058 #define USART_CR3_DEM_Pos (14U) 6059 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 6060 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 6061 #define USART_CR3_DEP_Pos (15U) 6062 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 6063 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 6064 #define USART_CR3_SCARCNT_Pos (17U) 6065 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 6066 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 6067 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 6068 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 6069 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 6070 #define USART_CR3_WUS_Pos (20U) 6071 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 6072 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 6073 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 6074 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 6075 #define USART_CR3_WUFIE_Pos (22U) 6076 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 6077 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 6078 #define USART_CR3_UCESM_Pos (23U) 6079 #define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */ 6080 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */ 6081 6082 /****************** Bit definition for USART_BRR register *******************/ 6083 #define USART_BRR_DIV_FRACTION_Pos (0U) 6084 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 6085 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 6086 #define USART_BRR_DIV_MANTISSA_Pos (4U) 6087 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 6088 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 6089 6090 /****************** Bit definition for USART_GTPR register ******************/ 6091 #define USART_GTPR_PSC_Pos (0U) 6092 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6093 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6094 #define USART_GTPR_GT_Pos (8U) 6095 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6096 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 6097 6098 6099 /******************* Bit definition for USART_RTOR register *****************/ 6100 #define USART_RTOR_RTO_Pos (0U) 6101 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 6102 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 6103 #define USART_RTOR_BLEN_Pos (24U) 6104 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 6105 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 6106 6107 /******************* Bit definition for USART_RQR register ******************/ 6108 #define USART_RQR_ABRRQ_Pos (0U) 6109 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 6110 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 6111 #define USART_RQR_SBKRQ_Pos (1U) 6112 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 6113 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 6114 #define USART_RQR_MMRQ_Pos (2U) 6115 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 6116 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 6117 #define USART_RQR_RXFRQ_Pos (3U) 6118 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 6119 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 6120 #define USART_RQR_TXFRQ_Pos (4U) 6121 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 6122 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 6123 6124 /******************* Bit definition for USART_ISR register ******************/ 6125 #define USART_ISR_PE_Pos (0U) 6126 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 6127 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 6128 #define USART_ISR_FE_Pos (1U) 6129 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 6130 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 6131 #define USART_ISR_NE_Pos (2U) 6132 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 6133 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 6134 #define USART_ISR_ORE_Pos (3U) 6135 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 6136 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 6137 #define USART_ISR_IDLE_Pos (4U) 6138 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 6139 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 6140 #define USART_ISR_RXNE_Pos (5U) 6141 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 6142 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 6143 #define USART_ISR_TC_Pos (6U) 6144 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 6145 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 6146 #define USART_ISR_TXE_Pos (7U) 6147 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 6148 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 6149 #define USART_ISR_LBDF_Pos (8U) 6150 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 6151 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 6152 #define USART_ISR_CTSIF_Pos (9U) 6153 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 6154 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 6155 #define USART_ISR_CTS_Pos (10U) 6156 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 6157 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 6158 #define USART_ISR_RTOF_Pos (11U) 6159 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 6160 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 6161 #define USART_ISR_EOBF_Pos (12U) 6162 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 6163 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 6164 #define USART_ISR_ABRE_Pos (14U) 6165 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 6166 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 6167 #define USART_ISR_ABRF_Pos (15U) 6168 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 6169 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 6170 #define USART_ISR_BUSY_Pos (16U) 6171 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 6172 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 6173 #define USART_ISR_CMF_Pos (17U) 6174 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 6175 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 6176 #define USART_ISR_SBKF_Pos (18U) 6177 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 6178 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 6179 #define USART_ISR_RWU_Pos (19U) 6180 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 6181 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 6182 #define USART_ISR_WUF_Pos (20U) 6183 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 6184 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 6185 #define USART_ISR_TEACK_Pos (21U) 6186 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 6187 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 6188 #define USART_ISR_REACK_Pos (22U) 6189 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 6190 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 6191 6192 /******************* Bit definition for USART_ICR register ******************/ 6193 #define USART_ICR_PECF_Pos (0U) 6194 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 6195 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 6196 #define USART_ICR_FECF_Pos (1U) 6197 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 6198 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 6199 #define USART_ICR_NCF_Pos (2U) 6200 #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 6201 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 6202 #define USART_ICR_ORECF_Pos (3U) 6203 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 6204 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 6205 #define USART_ICR_IDLECF_Pos (4U) 6206 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 6207 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 6208 #define USART_ICR_TCCF_Pos (6U) 6209 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 6210 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 6211 #define USART_ICR_LBDCF_Pos (8U) 6212 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 6213 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 6214 #define USART_ICR_CTSCF_Pos (9U) 6215 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 6216 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 6217 #define USART_ICR_RTOCF_Pos (11U) 6218 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 6219 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 6220 #define USART_ICR_EOBCF_Pos (12U) 6221 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 6222 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 6223 #define USART_ICR_CMCF_Pos (17U) 6224 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 6225 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 6226 #define USART_ICR_WUCF_Pos (20U) 6227 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 6228 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 6229 6230 /* Compatibility defines with other series */ 6231 #define USART_ICR_NECF USART_ICR_NCF 6232 6233 /******************* Bit definition for USART_RDR register ******************/ 6234 #define USART_RDR_RDR_Pos (0U) 6235 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 6236 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 6237 6238 /******************* Bit definition for USART_TDR register ******************/ 6239 #define USART_TDR_TDR_Pos (0U) 6240 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 6241 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 6242 6243 /******************************************************************************/ 6244 /* */ 6245 /* Window WATCHDOG (WWDG) */ 6246 /* */ 6247 /******************************************************************************/ 6248 6249 /******************* Bit definition for WWDG_CR register ********************/ 6250 #define WWDG_CR_T_Pos (0U) 6251 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 6252 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 6253 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 6254 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 6255 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 6256 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 6257 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 6258 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 6259 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 6260 6261 /* Legacy defines */ 6262 #define WWDG_CR_T0 WWDG_CR_T_0 6263 #define WWDG_CR_T1 WWDG_CR_T_1 6264 #define WWDG_CR_T2 WWDG_CR_T_2 6265 #define WWDG_CR_T3 WWDG_CR_T_3 6266 #define WWDG_CR_T4 WWDG_CR_T_4 6267 #define WWDG_CR_T5 WWDG_CR_T_5 6268 #define WWDG_CR_T6 WWDG_CR_T_6 6269 6270 #define WWDG_CR_WDGA_Pos (7U) 6271 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 6272 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 6273 6274 /******************* Bit definition for WWDG_CFR register *******************/ 6275 #define WWDG_CFR_W_Pos (0U) 6276 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 6277 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 6278 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 6279 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 6280 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 6281 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 6282 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 6283 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 6284 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 6285 6286 /* Legacy defines */ 6287 #define WWDG_CFR_W0 WWDG_CFR_W_0 6288 #define WWDG_CFR_W1 WWDG_CFR_W_1 6289 #define WWDG_CFR_W2 WWDG_CFR_W_2 6290 #define WWDG_CFR_W3 WWDG_CFR_W_3 6291 #define WWDG_CFR_W4 WWDG_CFR_W_4 6292 #define WWDG_CFR_W5 WWDG_CFR_W_5 6293 #define WWDG_CFR_W6 WWDG_CFR_W_6 6294 6295 #define WWDG_CFR_WDGTB_Pos (7U) 6296 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 6297 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 6298 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 6299 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 6300 6301 /* Legacy defines */ 6302 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 6303 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 6304 6305 #define WWDG_CFR_EWI_Pos (9U) 6306 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 6307 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 6308 6309 /******************* Bit definition for WWDG_SR register ********************/ 6310 #define WWDG_SR_EWIF_Pos (0U) 6311 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 6312 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 6313 6314 /** 6315 * @} 6316 */ 6317 6318 /** 6319 * @} 6320 */ 6321 6322 /** @addtogroup Exported_macros 6323 * @{ 6324 */ 6325 6326 /******************************* ADC Instances ********************************/ 6327 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 6328 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 6329 6330 /******************************* AES Instances ********************************/ 6331 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) 6332 6333 /******************************* COMP Instances *******************************/ 6334 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 6335 ((INSTANCE) == COMP2)) 6336 6337 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 6338 6339 /******************************* CRC Instances ********************************/ 6340 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 6341 6342 /******************************* DMA Instances *********************************/ 6343 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 6344 ((INSTANCE) == DMA1_Channel2) || \ 6345 ((INSTANCE) == DMA1_Channel3) || \ 6346 ((INSTANCE) == DMA1_Channel4) || \ 6347 ((INSTANCE) == DMA1_Channel5) || \ 6348 ((INSTANCE) == DMA1_Channel6) || \ 6349 ((INSTANCE) == DMA1_Channel7)) 6350 6351 /******************************* GPIO Instances *******************************/ 6352 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6353 ((INSTANCE) == GPIOB) || \ 6354 ((INSTANCE) == GPIOC) || \ 6355 ((INSTANCE) == GPIOD) || \ 6356 ((INSTANCE) == GPIOE) || \ 6357 ((INSTANCE) == GPIOH)) 6358 6359 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6360 ((INSTANCE) == GPIOB) || \ 6361 ((INSTANCE) == GPIOC) || \ 6362 ((INSTANCE) == GPIOD) || \ 6363 ((INSTANCE) == GPIOE)) 6364 6365 /******************************** I2C Instances *******************************/ 6366 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6367 ((INSTANCE) == I2C2) || \ 6368 ((INSTANCE) == I2C3)) 6369 6370 /****************** I2C Instances : wakeup capability from stop modes *********/ 6371 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6372 ((INSTANCE) == I2C3)) 6373 6374 6375 /******************************** I2S Instances *******************************/ 6376 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2) 6377 6378 6379 /****************************** RTC Instances *********************************/ 6380 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 6381 6382 /******************************** SMBUS Instances *****************************/ 6383 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6384 ((INSTANCE) == I2C3)) 6385 6386 /******************************** SPI Instances *******************************/ 6387 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 6388 ((INSTANCE) == SPI2)) 6389 6390 /****************** LPTIM Instances : All supported instances *****************/ 6391 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 6392 6393 /************* LPTIM instances supporting the encoder mode feature ************/ 6394 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 6395 6396 /****************** TIM Instances : All supported instances *******************/ 6397 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6398 ((INSTANCE) == TIM3) || \ 6399 ((INSTANCE) == TIM6) || \ 6400 ((INSTANCE) == TIM7) || \ 6401 ((INSTANCE) == TIM21) || \ 6402 ((INSTANCE) == TIM22)) 6403 6404 /************* TIM Instances : at least 1 capture/compare channel *************/ 6405 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6406 ((INSTANCE) == TIM3) || \ 6407 ((INSTANCE) == TIM21) || \ 6408 ((INSTANCE) == TIM22)) 6409 6410 /************ TIM Instances : at least 2 capture/compare channels *************/ 6411 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6412 ((INSTANCE) == TIM3) || \ 6413 ((INSTANCE) == TIM21) || \ 6414 ((INSTANCE) == TIM22)) 6415 6416 /************ TIM Instances : at least 3 capture/compare channels *************/ 6417 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6418 ((INSTANCE) == TIM3)) 6419 6420 /************ TIM Instances : at least 4 capture/compare channels *************/ 6421 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6422 ((INSTANCE) == TIM3)) 6423 6424 /****************** TIM Instances : DMA requests generation (UDE) *************/ 6425 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6426 ((INSTANCE) == TIM3) || \ 6427 ((INSTANCE) == TIM6) || \ 6428 ((INSTANCE) == TIM7)) 6429 6430 /************ TIM Instances : DMA requests generation (CCxDE) *****************/ 6431 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6432 ((INSTANCE) == TIM3)) 6433 6434 /******************** TIM Instances : DMA burst feature ***********************/ 6435 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6436 ((INSTANCE) == TIM3)) 6437 6438 /******************* TIM Instances : output(s) available **********************/ 6439 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 6440 (((((INSTANCE) == TIM2) || \ 6441 ((INSTANCE) == TIM3)) \ 6442 && \ 6443 (((CHANNEL) == TIM_CHANNEL_1) || \ 6444 ((CHANNEL) == TIM_CHANNEL_2) || \ 6445 ((CHANNEL) == TIM_CHANNEL_3) || \ 6446 ((CHANNEL) == TIM_CHANNEL_4))) \ 6447 || \ 6448 (((INSTANCE) == TIM21) && \ 6449 (((CHANNEL) == TIM_CHANNEL_1) || \ 6450 ((CHANNEL) == TIM_CHANNEL_2))) \ 6451 || \ 6452 (((INSTANCE) == TIM22) && \ 6453 (((CHANNEL) == TIM_CHANNEL_1) || \ 6454 ((CHANNEL) == TIM_CHANNEL_2)))) 6455 6456 /****************** TIM Instances : supporting clock division *****************/ 6457 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6458 ((INSTANCE) == TIM3) || \ 6459 ((INSTANCE) == TIM21) || \ 6460 ((INSTANCE) == TIM22)) 6461 6462 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 6463 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6464 ((INSTANCE) == TIM3) || \ 6465 ((INSTANCE) == TIM21)) 6466 6467 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 6468 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6469 ((INSTANCE) == TIM3) || \ 6470 ((INSTANCE) == TIM21) || \ 6471 ((INSTANCE) == TIM22)) 6472 6473 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 6474 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6475 ((INSTANCE) == TIM3) || \ 6476 ((INSTANCE) == TIM21)) 6477 6478 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 6479 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6480 ((INSTANCE) == TIM3) || \ 6481 ((INSTANCE) == TIM21) || \ 6482 ((INSTANCE) == TIM22)) 6483 6484 /****************** TIM Instances : supporting counting mode selection ********/ 6485 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6486 ((INSTANCE) == TIM3) || \ 6487 ((INSTANCE) == TIM21) || \ 6488 ((INSTANCE) == TIM22)) 6489 6490 /****************** TIM Instances : supporting encoder interface **************/ 6491 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6492 ((INSTANCE) == TIM3) || \ 6493 ((INSTANCE) == TIM21) || \ 6494 ((INSTANCE) == TIM22)) 6495 6496 /***************** TIM Instances : external trigger input available ************/ 6497 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6498 ((INSTANCE) == TIM3) || \ 6499 ((INSTANCE) == TIM21) || \ 6500 ((INSTANCE) == TIM22)) 6501 6502 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ 6503 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6504 ((INSTANCE) == TIM3) || \ 6505 ((INSTANCE) == TIM6) || \ 6506 ((INSTANCE) == TIM7) || \ 6507 ((INSTANCE) == TIM21) || \ 6508 ((INSTANCE) == TIM22)) 6509 6510 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 6511 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6512 ((INSTANCE) == TIM3) || \ 6513 ((INSTANCE) == TIM21) || \ 6514 ((INSTANCE) == TIM22)) 6515 6516 /****************** TIM Instances : remapping capability **********************/ 6517 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6518 ((INSTANCE) == TIM3) || \ 6519 ((INSTANCE) == TIM21) || \ 6520 ((INSTANCE) == TIM22)) 6521 6522 /******************* TIM Instances : output(s) OCXEC register *****************/ 6523 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6524 ((INSTANCE) == TIM3)) 6525 6526 /******************* TIM Instances : Timer input XOR function *****************/ 6527 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6528 ((INSTANCE) == TIM3)) 6529 6530 /******************** UART Instances : Asynchronous mode **********************/ 6531 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6532 ((INSTANCE) == USART2) || \ 6533 ((INSTANCE) == USART4) || \ 6534 ((INSTANCE) == USART5)) 6535 6536 /******************** USART Instances : Synchronous mode **********************/ 6537 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6538 ((INSTANCE) == USART2) || \ 6539 ((INSTANCE) == USART4) || \ 6540 ((INSTANCE) == USART5)) 6541 6542 /****************** USART Instances : Auto Baud Rate detection ****************/ 6543 6544 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6545 ((INSTANCE) == USART2)) 6546 6547 /****************** UART Instances : Driver Enable *****************/ 6548 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6549 ((INSTANCE) == USART2) || \ 6550 ((INSTANCE) == USART4) || \ 6551 ((INSTANCE) == USART5) || \ 6552 ((INSTANCE) == LPUART1)) 6553 6554 /******************** UART Instances : Half-Duplex mode **********************/ 6555 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6556 ((INSTANCE) == USART2) || \ 6557 ((INSTANCE) == USART4) || \ 6558 ((INSTANCE) == USART5) || \ 6559 ((INSTANCE) == LPUART1)) 6560 6561 /******************** UART Instances : LIN mode **********************/ 6562 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6563 ((INSTANCE) == USART2)) 6564 6565 /******************** UART Instances : Wake-up from Stop mode **********************/ 6566 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6567 ((INSTANCE) == USART2) || \ 6568 ((INSTANCE) == LPUART1)) 6569 6570 /****************** UART Instances : Hardware Flow control ********************/ 6571 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6572 ((INSTANCE) == USART2) || \ 6573 ((INSTANCE) == USART4) || \ 6574 ((INSTANCE) == USART5) || \ 6575 ((INSTANCE) == LPUART1)) 6576 6577 /********************* UART Instances : Smard card mode ***********************/ 6578 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6579 ((INSTANCE) == USART2)) 6580 6581 /*********************** UART Instances : IRDA mode ***************************/ 6582 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6583 ((INSTANCE) == USART2)) 6584 6585 /******************** LPUART Instance *****************************************/ 6586 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 6587 6588 /****************************** IWDG Instances ********************************/ 6589 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6590 6591 /****************************** WWDG Instances ********************************/ 6592 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6593 6594 /** 6595 * @} 6596 */ 6597 6598 /******************************************************************************/ 6599 /* For a painless codes migration between the STM32L0xx device product */ 6600 /* lines, the aliases defined below are put in place to overcome the */ 6601 /* differences in the interrupt handlers and IRQn definitions. */ 6602 /* No need to update developed interrupt code when moving across */ 6603 /* product lines within the same STM32L0 Family */ 6604 /******************************************************************************/ 6605 6606 /* Aliases for __IRQn */ 6607 6608 #define RNG_LPUART1_IRQn AES_LPUART1_IRQn 6609 #define LPUART1_IRQn AES_LPUART1_IRQn 6610 #define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn 6611 #define TIM6_DAC_IRQn TIM6_IRQn 6612 #define RCC_CRS_IRQn RCC_IRQn 6613 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn 6614 #define ADC1_IRQn ADC1_COMP_IRQn 6615 #define SVC_IRQn SVCall_IRQn 6616 6617 /* Aliases for __IRQHandler */ 6618 #define LPUART1_IRQHandler AES_LPUART1_IRQHandler 6619 #define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6620 #define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6621 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 6622 #define RCC_CRS_IRQHandler RCC_IRQHandler 6623 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler 6624 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 6625 6626 /** 6627 * @} 6628 */ 6629 6630 /** 6631 * @} 6632 */ 6633 6634 #ifdef __cplusplus 6635 } 6636 #endif /* __cplusplus */ 6637 6638 #endif /* __STM32L081xx_H */ 6639 6640 6641 6642
