1 /** 2 ****************************************************************************** 3 * @file stm32f101x6.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral�s registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 18 * All rights reserved.</center></h2> 19 * 20 * This software component is licensed by ST under BSD 3-Clause license, 21 * the "License"; You may not use this file except in compliance with the 22 * License. You may obtain a copy of the License at: 23 * opensource.org/licenses/BSD-3-Clause 24 * 25 ****************************************************************************** 26 */ 27 28 29 /** @addtogroup CMSIS 30 * @{ 31 */ 32 33 /** @addtogroup stm32f101x6 34 * @{ 35 */ 36 37 #ifndef __STM32F101x6_H 38 #define __STM32F101x6_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /** @addtogroup Configuration_section_for_CMSIS 45 * @{ 46 */ 47 /** 48 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 49 */ 50 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ 51 #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ 52 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ 53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 54 55 /** 56 * @} 57 */ 58 59 /** @addtogroup Peripheral_interrupt_number_definition 60 * @{ 61 */ 62 63 /** 64 * @brief STM32F10x Interrupt Number Definition, according to the selected device 65 * in @ref Library_configuration_section 66 */ 67 68 /*!< Interrupt Number Definition */ 69 typedef enum 70 { 71 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 72 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 73 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 74 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 75 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 76 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 77 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 78 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 79 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 80 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 81 82 /****** STM32 specific Interrupt Numbers *********************************************************/ 83 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 84 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 85 TAMPER_IRQn = 2, /*!< Tamper Interrupt */ 86 RTC_IRQn = 3, /*!< RTC global Interrupt */ 87 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 88 RCC_IRQn = 5, /*!< RCC global Interrupt */ 89 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 90 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 91 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 92 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 93 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 94 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 95 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 96 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 97 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 98 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 99 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 100 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 101 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 103 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 104 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 105 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 106 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 107 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 108 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 109 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 110 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 111 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 112 } IRQn_Type; 113 114 /** 115 * @} 116 */ 117 118 #include "core_cm3.h" 119 #include "system_stm32f1xx.h" 120 #include <stdint.h> 121 122 /** @addtogroup Peripheral_registers_structures 123 * @{ 124 */ 125 126 /** 127 * @brief Analog to Digital Converter 128 */ 129 130 typedef struct 131 { 132 __IO uint32_t SR; 133 __IO uint32_t CR1; 134 __IO uint32_t CR2; 135 __IO uint32_t SMPR1; 136 __IO uint32_t SMPR2; 137 __IO uint32_t JOFR1; 138 __IO uint32_t JOFR2; 139 __IO uint32_t JOFR3; 140 __IO uint32_t JOFR4; 141 __IO uint32_t HTR; 142 __IO uint32_t LTR; 143 __IO uint32_t SQR1; 144 __IO uint32_t SQR2; 145 __IO uint32_t SQR3; 146 __IO uint32_t JSQR; 147 __IO uint32_t JDR1; 148 __IO uint32_t JDR2; 149 __IO uint32_t JDR3; 150 __IO uint32_t JDR4; 151 __IO uint32_t DR; 152 } ADC_TypeDef; 153 154 typedef struct 155 { 156 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ 157 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ 158 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ 159 uint32_t RESERVED[16]; 160 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ 161 } ADC_Common_TypeDef; 162 163 /** 164 * @brief Backup Registers 165 */ 166 167 typedef struct 168 { 169 uint32_t RESERVED0; 170 __IO uint32_t DR1; 171 __IO uint32_t DR2; 172 __IO uint32_t DR3; 173 __IO uint32_t DR4; 174 __IO uint32_t DR5; 175 __IO uint32_t DR6; 176 __IO uint32_t DR7; 177 __IO uint32_t DR8; 178 __IO uint32_t DR9; 179 __IO uint32_t DR10; 180 __IO uint32_t RTCCR; 181 __IO uint32_t CR; 182 __IO uint32_t CSR; 183 } BKP_TypeDef; 184 185 186 /** 187 * @brief CRC calculation unit 188 */ 189 190 typedef struct 191 { 192 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 193 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 194 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 195 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 196 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 197 } CRC_TypeDef; 198 199 200 /** 201 * @brief Debug MCU 202 */ 203 204 typedef struct 205 { 206 __IO uint32_t IDCODE; 207 __IO uint32_t CR; 208 }DBGMCU_TypeDef; 209 210 /** 211 * @brief DMA Controller 212 */ 213 214 typedef struct 215 { 216 __IO uint32_t CCR; 217 __IO uint32_t CNDTR; 218 __IO uint32_t CPAR; 219 __IO uint32_t CMAR; 220 } DMA_Channel_TypeDef; 221 222 typedef struct 223 { 224 __IO uint32_t ISR; 225 __IO uint32_t IFCR; 226 } DMA_TypeDef; 227 228 229 230 /** 231 * @brief External Interrupt/Event Controller 232 */ 233 234 typedef struct 235 { 236 __IO uint32_t IMR; 237 __IO uint32_t EMR; 238 __IO uint32_t RTSR; 239 __IO uint32_t FTSR; 240 __IO uint32_t SWIER; 241 __IO uint32_t PR; 242 } EXTI_TypeDef; 243 244 /** 245 * @brief FLASH Registers 246 */ 247 248 typedef struct 249 { 250 __IO uint32_t ACR; 251 __IO uint32_t KEYR; 252 __IO uint32_t OPTKEYR; 253 __IO uint32_t SR; 254 __IO uint32_t CR; 255 __IO uint32_t AR; 256 __IO uint32_t RESERVED; 257 __IO uint32_t OBR; 258 __IO uint32_t WRPR; 259 } FLASH_TypeDef; 260 261 /** 262 * @brief Option Bytes Registers 263 */ 264 265 typedef struct 266 { 267 __IO uint16_t RDP; 268 __IO uint16_t USER; 269 __IO uint16_t Data0; 270 __IO uint16_t Data1; 271 __IO uint16_t WRP0; 272 __IO uint16_t WRP1; 273 __IO uint16_t WRP2; 274 __IO uint16_t WRP3; 275 } OB_TypeDef; 276 277 /** 278 * @brief General Purpose I/O 279 */ 280 281 typedef struct 282 { 283 __IO uint32_t CRL; 284 __IO uint32_t CRH; 285 __IO uint32_t IDR; 286 __IO uint32_t ODR; 287 __IO uint32_t BSRR; 288 __IO uint32_t BRR; 289 __IO uint32_t LCKR; 290 } GPIO_TypeDef; 291 292 /** 293 * @brief Alternate Function I/O 294 */ 295 296 typedef struct 297 { 298 __IO uint32_t EVCR; 299 __IO uint32_t MAPR; 300 __IO uint32_t EXTICR[4]; 301 uint32_t RESERVED0; 302 __IO uint32_t MAPR2; 303 } AFIO_TypeDef; 304 /** 305 * @brief Inter Integrated Circuit Interface 306 */ 307 308 typedef struct 309 { 310 __IO uint32_t CR1; 311 __IO uint32_t CR2; 312 __IO uint32_t OAR1; 313 __IO uint32_t OAR2; 314 __IO uint32_t DR; 315 __IO uint32_t SR1; 316 __IO uint32_t SR2; 317 __IO uint32_t CCR; 318 __IO uint32_t TRISE; 319 } I2C_TypeDef; 320 321 /** 322 * @brief Independent WATCHDOG 323 */ 324 325 typedef struct 326 { 327 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 328 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 329 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 330 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 331 } IWDG_TypeDef; 332 333 /** 334 * @brief Power Control 335 */ 336 337 typedef struct 338 { 339 __IO uint32_t CR; 340 __IO uint32_t CSR; 341 } PWR_TypeDef; 342 343 /** 344 * @brief Reset and Clock Control 345 */ 346 347 typedef struct 348 { 349 __IO uint32_t CR; 350 __IO uint32_t CFGR; 351 __IO uint32_t CIR; 352 __IO uint32_t APB2RSTR; 353 __IO uint32_t APB1RSTR; 354 __IO uint32_t AHBENR; 355 __IO uint32_t APB2ENR; 356 __IO uint32_t APB1ENR; 357 __IO uint32_t BDCR; 358 __IO uint32_t CSR; 359 360 361 } RCC_TypeDef; 362 363 /** 364 * @brief Real-Time Clock 365 */ 366 367 typedef struct 368 { 369 __IO uint32_t CRH; 370 __IO uint32_t CRL; 371 __IO uint32_t PRLH; 372 __IO uint32_t PRLL; 373 __IO uint32_t DIVH; 374 __IO uint32_t DIVL; 375 __IO uint32_t CNTH; 376 __IO uint32_t CNTL; 377 __IO uint32_t ALRH; 378 __IO uint32_t ALRL; 379 } RTC_TypeDef; 380 381 /** 382 * @brief Serial Peripheral Interface 383 */ 384 385 typedef struct 386 { 387 __IO uint32_t CR1; 388 __IO uint32_t CR2; 389 __IO uint32_t SR; 390 __IO uint32_t DR; 391 __IO uint32_t CRCPR; 392 __IO uint32_t RXCRCR; 393 __IO uint32_t TXCRCR; 394 __IO uint32_t I2SCFGR; 395 } SPI_TypeDef; 396 397 /** 398 * @brief TIM Timers 399 */ 400 typedef struct 401 { 402 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 403 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 404 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 405 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 406 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 407 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 408 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 409 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 410 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 411 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 412 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 413 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 414 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 415 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 416 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 417 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 418 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 419 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 420 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 421 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 422 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 423 }TIM_TypeDef; 424 425 426 /** 427 * @brief Universal Synchronous Asynchronous Receiver Transmitter 428 */ 429 430 typedef struct 431 { 432 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 433 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 434 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 435 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 436 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 437 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 438 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 439 } USART_TypeDef; 440 441 442 443 /** 444 * @brief Window WATCHDOG 445 */ 446 447 typedef struct 448 { 449 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 450 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 451 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 452 } WWDG_TypeDef; 453 454 /** 455 * @} 456 */ 457 458 /** @addtogroup Peripheral_memory_map 459 * @{ 460 */ 461 462 463 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 464 #define FLASH_BANK1_END 0x08007FFFUL /*!< FLASH END address of bank1 */ 465 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 466 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 467 468 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ 469 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 470 471 472 /*!< Peripheral memory map */ 473 #define APB1PERIPH_BASE PERIPH_BASE 474 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 475 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 476 477 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 478 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 479 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 480 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 481 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 482 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 483 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 484 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) 485 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 486 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) 487 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 488 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) 489 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) 490 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) 491 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) 492 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 493 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 494 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 495 496 497 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 498 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) 499 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) 500 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) 501 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) 502 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) 503 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) 504 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) 505 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 506 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 507 508 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ 509 #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ 510 #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ 511 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ 512 513 514 515 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ 516 517 518 519 /** 520 * @} 521 */ 522 523 /** @addtogroup Peripheral_declaration 524 * @{ 525 */ 526 527 #define TIM2 ((TIM_TypeDef *)TIM2_BASE) 528 #define TIM3 ((TIM_TypeDef *)TIM3_BASE) 529 #define RTC ((RTC_TypeDef *)RTC_BASE) 530 #define WWDG ((WWDG_TypeDef *)WWDG_BASE) 531 #define IWDG ((IWDG_TypeDef *)IWDG_BASE) 532 #define USART2 ((USART_TypeDef *)USART2_BASE) 533 #define I2C1 ((I2C_TypeDef *)I2C1_BASE) 534 #define BKP ((BKP_TypeDef *)BKP_BASE) 535 #define PWR ((PWR_TypeDef *)PWR_BASE) 536 #define AFIO ((AFIO_TypeDef *)AFIO_BASE) 537 #define EXTI ((EXTI_TypeDef *)EXTI_BASE) 538 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) 539 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) 540 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) 541 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) 542 #define ADC1 ((ADC_TypeDef *)ADC1_BASE) 543 #define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) 544 #define SPI1 ((SPI_TypeDef *)SPI1_BASE) 545 #define USART1 ((USART_TypeDef *)USART1_BASE) 546 #define DMA1 ((DMA_TypeDef *)DMA1_BASE) 547 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) 548 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) 549 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) 550 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) 551 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) 552 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) 553 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) 554 #define RCC ((RCC_TypeDef *)RCC_BASE) 555 #define CRC ((CRC_TypeDef *)CRC_BASE) 556 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) 557 #define OB ((OB_TypeDef *)OB_BASE) 558 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) 559 560 561 /** 562 * @} 563 */ 564 565 /** @addtogroup Exported_constants 566 * @{ 567 */ 568 569 /** @addtogroup Hardware_Constant_Definition 570 * @{ 571 */ 572 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 573 /** 574 * @} 575 */ 576 577 /** @addtogroup Peripheral_Registers_Bits_Definition 578 * @{ 579 */ 580 581 /******************************************************************************/ 582 /* Peripheral Registers_Bits_Definition */ 583 /******************************************************************************/ 584 585 /******************************************************************************/ 586 /* */ 587 /* CRC calculation unit (CRC) */ 588 /* */ 589 /******************************************************************************/ 590 591 /******************* Bit definition for CRC_DR register *********************/ 592 #define CRC_DR_DR_Pos (0U) 593 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 594 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 595 596 /******************* Bit definition for CRC_IDR register ********************/ 597 #define CRC_IDR_IDR_Pos (0U) 598 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 599 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 600 601 /******************** Bit definition for CRC_CR register ********************/ 602 #define CRC_CR_RESET_Pos (0U) 603 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 604 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 605 606 /******************************************************************************/ 607 /* */ 608 /* Power Control */ 609 /* */ 610 /******************************************************************************/ 611 612 /******************** Bit definition for PWR_CR register ********************/ 613 #define PWR_CR_LPDS_Pos (0U) 614 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 615 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ 616 #define PWR_CR_PDDS_Pos (1U) 617 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 618 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 619 #define PWR_CR_CWUF_Pos (2U) 620 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 621 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 622 #define PWR_CR_CSBF_Pos (3U) 623 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 624 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 625 #define PWR_CR_PVDE_Pos (4U) 626 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 627 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 628 629 #define PWR_CR_PLS_Pos (5U) 630 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 631 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 632 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 633 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 634 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 635 636 /*!< PVD level configuration */ 637 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ 638 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ 639 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ 640 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ 641 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ 642 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ 643 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ 644 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ 645 646 /* Legacy defines */ 647 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 648 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 649 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 650 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 651 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 652 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 653 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 654 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 655 656 #define PWR_CR_DBP_Pos (8U) 657 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 658 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 659 660 661 /******************* Bit definition for PWR_CSR register ********************/ 662 #define PWR_CSR_WUF_Pos (0U) 663 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 664 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 665 #define PWR_CSR_SBF_Pos (1U) 666 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 667 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 668 #define PWR_CSR_PVDO_Pos (2U) 669 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 670 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 671 #define PWR_CSR_EWUP_Pos (8U) 672 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ 673 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ 674 675 /******************************************************************************/ 676 /* */ 677 /* Backup registers */ 678 /* */ 679 /******************************************************************************/ 680 681 /******************* Bit definition for BKP_DR1 register ********************/ 682 #define BKP_DR1_D_Pos (0U) 683 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ 684 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ 685 686 /******************* Bit definition for BKP_DR2 register ********************/ 687 #define BKP_DR2_D_Pos (0U) 688 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ 689 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ 690 691 /******************* Bit definition for BKP_DR3 register ********************/ 692 #define BKP_DR3_D_Pos (0U) 693 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ 694 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ 695 696 /******************* Bit definition for BKP_DR4 register ********************/ 697 #define BKP_DR4_D_Pos (0U) 698 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ 699 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ 700 701 /******************* Bit definition for BKP_DR5 register ********************/ 702 #define BKP_DR5_D_Pos (0U) 703 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ 704 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ 705 706 /******************* Bit definition for BKP_DR6 register ********************/ 707 #define BKP_DR6_D_Pos (0U) 708 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ 709 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ 710 711 /******************* Bit definition for BKP_DR7 register ********************/ 712 #define BKP_DR7_D_Pos (0U) 713 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ 714 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ 715 716 /******************* Bit definition for BKP_DR8 register ********************/ 717 #define BKP_DR8_D_Pos (0U) 718 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ 719 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ 720 721 /******************* Bit definition for BKP_DR9 register ********************/ 722 #define BKP_DR9_D_Pos (0U) 723 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ 724 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ 725 726 /******************* Bit definition for BKP_DR10 register *******************/ 727 #define BKP_DR10_D_Pos (0U) 728 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ 729 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ 730 731 #define RTC_BKP_NUMBER 10 732 733 /****************** Bit definition for BKP_RTCCR register *******************/ 734 #define BKP_RTCCR_CAL_Pos (0U) 735 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ 736 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ 737 #define BKP_RTCCR_CCO_Pos (7U) 738 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ 739 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ 740 #define BKP_RTCCR_ASOE_Pos (8U) 741 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ 742 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ 743 #define BKP_RTCCR_ASOS_Pos (9U) 744 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ 745 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ 746 747 /******************** Bit definition for BKP_CR register ********************/ 748 #define BKP_CR_TPE_Pos (0U) 749 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ 750 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ 751 #define BKP_CR_TPAL_Pos (1U) 752 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ 753 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ 754 755 /******************* Bit definition for BKP_CSR register ********************/ 756 #define BKP_CSR_CTE_Pos (0U) 757 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ 758 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ 759 #define BKP_CSR_CTI_Pos (1U) 760 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ 761 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ 762 #define BKP_CSR_TPIE_Pos (2U) 763 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ 764 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ 765 #define BKP_CSR_TEF_Pos (8U) 766 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ 767 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ 768 #define BKP_CSR_TIF_Pos (9U) 769 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ 770 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ 771 772 /******************************************************************************/ 773 /* */ 774 /* Reset and Clock Control */ 775 /* */ 776 /******************************************************************************/ 777 778 /******************** Bit definition for RCC_CR register ********************/ 779 #define RCC_CR_HSION_Pos (0U) 780 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 781 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 782 #define RCC_CR_HSIRDY_Pos (1U) 783 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 784 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 785 #define RCC_CR_HSITRIM_Pos (3U) 786 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 787 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 788 #define RCC_CR_HSICAL_Pos (8U) 789 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 790 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 791 #define RCC_CR_HSEON_Pos (16U) 792 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 793 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 794 #define RCC_CR_HSERDY_Pos (17U) 795 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 796 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 797 #define RCC_CR_HSEBYP_Pos (18U) 798 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 799 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 800 #define RCC_CR_CSSON_Pos (19U) 801 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 802 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 803 #define RCC_CR_PLLON_Pos (24U) 804 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 805 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 806 #define RCC_CR_PLLRDY_Pos (25U) 807 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 808 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 809 810 811 /******************* Bit definition for RCC_CFGR register *******************/ 812 /*!< SW configuration */ 813 #define RCC_CFGR_SW_Pos (0U) 814 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 815 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 816 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 817 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 818 819 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ 820 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ 821 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ 822 823 /*!< SWS configuration */ 824 #define RCC_CFGR_SWS_Pos (2U) 825 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 826 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 827 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 828 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 829 830 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ 831 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ 832 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ 833 834 /*!< HPRE configuration */ 835 #define RCC_CFGR_HPRE_Pos (4U) 836 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 837 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 838 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 839 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 840 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 841 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 842 843 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ 844 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ 845 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ 846 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ 847 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ 848 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ 849 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ 850 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ 851 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ 852 853 /*!< PPRE1 configuration */ 854 #define RCC_CFGR_PPRE1_Pos (8U) 855 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 856 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 857 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 858 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 859 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 860 861 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ 862 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ 863 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ 864 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ 865 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ 866 867 /*!< PPRE2 configuration */ 868 #define RCC_CFGR_PPRE2_Pos (11U) 869 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 870 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 871 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 872 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 873 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 874 875 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ 876 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ 877 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ 878 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ 879 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ 880 881 /*!< ADCPPRE configuration */ 882 #define RCC_CFGR_ADCPRE_Pos (14U) 883 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ 884 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ 885 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 886 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ 887 888 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ 889 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ 890 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ 891 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ 892 893 #define RCC_CFGR_PLLSRC_Pos (16U) 894 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 895 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 896 897 #define RCC_CFGR_PLLXTPRE_Pos (17U) 898 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 899 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 900 901 /*!< PLLMUL configuration */ 902 #define RCC_CFGR_PLLMULL_Pos (18U) 903 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ 904 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 905 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ 906 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ 907 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ 908 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ 909 910 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ 911 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ 912 913 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ 914 #define RCC_CFGR_PLLMULL3_Pos (18U) 915 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ 916 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ 917 #define RCC_CFGR_PLLMULL4_Pos (19U) 918 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ 919 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ 920 #define RCC_CFGR_PLLMULL5_Pos (18U) 921 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ 922 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ 923 #define RCC_CFGR_PLLMULL6_Pos (20U) 924 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ 925 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ 926 #define RCC_CFGR_PLLMULL7_Pos (18U) 927 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ 928 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ 929 #define RCC_CFGR_PLLMULL8_Pos (19U) 930 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ 931 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ 932 #define RCC_CFGR_PLLMULL9_Pos (18U) 933 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ 934 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ 935 #define RCC_CFGR_PLLMULL10_Pos (21U) 936 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ 937 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ 938 #define RCC_CFGR_PLLMULL11_Pos (18U) 939 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ 940 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ 941 #define RCC_CFGR_PLLMULL12_Pos (19U) 942 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ 943 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ 944 #define RCC_CFGR_PLLMULL13_Pos (18U) 945 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ 946 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ 947 #define RCC_CFGR_PLLMULL14_Pos (20U) 948 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ 949 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ 950 #define RCC_CFGR_PLLMULL15_Pos (18U) 951 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ 952 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ 953 #define RCC_CFGR_PLLMULL16_Pos (19U) 954 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ 955 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ 956 957 /*!< MCO configuration */ 958 #define RCC_CFGR_MCO_Pos (24U) 959 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 960 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 961 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 962 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 963 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 964 965 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ 966 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ 967 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ 968 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ 969 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ 970 971 /* Reference defines */ 972 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 973 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 974 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 975 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 976 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 977 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 978 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 979 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 980 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 981 982 /*!<****************** Bit definition for RCC_CIR register ********************/ 983 #define RCC_CIR_LSIRDYF_Pos (0U) 984 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 985 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 986 #define RCC_CIR_LSERDYF_Pos (1U) 987 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 988 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 989 #define RCC_CIR_HSIRDYF_Pos (2U) 990 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 991 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 992 #define RCC_CIR_HSERDYF_Pos (3U) 993 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 994 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 995 #define RCC_CIR_PLLRDYF_Pos (4U) 996 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 997 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 998 #define RCC_CIR_CSSF_Pos (7U) 999 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 1000 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 1001 #define RCC_CIR_LSIRDYIE_Pos (8U) 1002 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 1003 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 1004 #define RCC_CIR_LSERDYIE_Pos (9U) 1005 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 1006 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 1007 #define RCC_CIR_HSIRDYIE_Pos (10U) 1008 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 1009 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 1010 #define RCC_CIR_HSERDYIE_Pos (11U) 1011 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 1012 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 1013 #define RCC_CIR_PLLRDYIE_Pos (12U) 1014 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 1015 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 1016 #define RCC_CIR_LSIRDYC_Pos (16U) 1017 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 1018 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 1019 #define RCC_CIR_LSERDYC_Pos (17U) 1020 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 1021 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 1022 #define RCC_CIR_HSIRDYC_Pos (18U) 1023 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 1024 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 1025 #define RCC_CIR_HSERDYC_Pos (19U) 1026 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 1027 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 1028 #define RCC_CIR_PLLRDYC_Pos (20U) 1029 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 1030 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 1031 #define RCC_CIR_CSSC_Pos (23U) 1032 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 1033 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 1034 1035 1036 /***************** Bit definition for RCC_APB2RSTR register *****************/ 1037 #define RCC_APB2RSTR_AFIORST_Pos (0U) 1038 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ 1039 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ 1040 #define RCC_APB2RSTR_IOPARST_Pos (2U) 1041 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ 1042 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ 1043 #define RCC_APB2RSTR_IOPBRST_Pos (3U) 1044 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ 1045 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ 1046 #define RCC_APB2RSTR_IOPCRST_Pos (4U) 1047 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ 1048 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ 1049 #define RCC_APB2RSTR_IOPDRST_Pos (5U) 1050 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ 1051 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ 1052 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 1053 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 1054 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ 1055 1056 1057 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 1058 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 1059 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ 1060 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 1061 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 1062 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ 1063 #define RCC_APB2RSTR_USART1RST_Pos (14U) 1064 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 1065 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 1066 1067 1068 1069 1070 1071 1072 /***************** Bit definition for RCC_APB1RSTR register *****************/ 1073 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 1074 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 1075 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 1076 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 1077 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 1078 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 1079 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 1080 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 1081 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 1082 #define RCC_APB1RSTR_USART2RST_Pos (17U) 1083 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 1084 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 1085 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 1086 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 1087 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 1088 1089 1090 #define RCC_APB1RSTR_BKPRST_Pos (27U) 1091 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ 1092 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ 1093 #define RCC_APB1RSTR_PWRRST_Pos (28U) 1094 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 1095 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 1096 1097 1098 1099 1100 1101 1102 1103 1104 /****************** Bit definition for RCC_AHBENR register ******************/ 1105 #define RCC_AHBENR_DMA1EN_Pos (0U) 1106 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 1107 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 1108 #define RCC_AHBENR_SRAMEN_Pos (2U) 1109 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 1110 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 1111 #define RCC_AHBENR_FLITFEN_Pos (4U) 1112 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 1113 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 1114 #define RCC_AHBENR_CRCEN_Pos (6U) 1115 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 1116 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 1117 1118 1119 1120 1121 /****************** Bit definition for RCC_APB2ENR register *****************/ 1122 #define RCC_APB2ENR_AFIOEN_Pos (0U) 1123 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ 1124 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ 1125 #define RCC_APB2ENR_IOPAEN_Pos (2U) 1126 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ 1127 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ 1128 #define RCC_APB2ENR_IOPBEN_Pos (3U) 1129 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ 1130 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ 1131 #define RCC_APB2ENR_IOPCEN_Pos (4U) 1132 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ 1133 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ 1134 #define RCC_APB2ENR_IOPDEN_Pos (5U) 1135 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ 1136 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ 1137 #define RCC_APB2ENR_ADC1EN_Pos (9U) 1138 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 1139 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ 1140 1141 1142 #define RCC_APB2ENR_TIM1EN_Pos (11U) 1143 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 1144 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ 1145 #define RCC_APB2ENR_SPI1EN_Pos (12U) 1146 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 1147 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ 1148 #define RCC_APB2ENR_USART1EN_Pos (14U) 1149 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 1150 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 1151 1152 1153 1154 1155 1156 1157 /***************** Bit definition for RCC_APB1ENR register ******************/ 1158 #define RCC_APB1ENR_TIM2EN_Pos (0U) 1159 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 1160 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 1161 #define RCC_APB1ENR_TIM3EN_Pos (1U) 1162 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 1163 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 1164 #define RCC_APB1ENR_WWDGEN_Pos (11U) 1165 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 1166 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 1167 #define RCC_APB1ENR_USART2EN_Pos (17U) 1168 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 1169 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 1170 #define RCC_APB1ENR_I2C1EN_Pos (21U) 1171 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 1172 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 1173 1174 1175 #define RCC_APB1ENR_BKPEN_Pos (27U) 1176 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ 1177 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ 1178 #define RCC_APB1ENR_PWREN_Pos (28U) 1179 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 1180 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 1181 1182 1183 1184 1185 1186 1187 1188 1189 /******************* Bit definition for RCC_BDCR register *******************/ 1190 #define RCC_BDCR_LSEON_Pos (0U) 1191 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 1192 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 1193 #define RCC_BDCR_LSERDY_Pos (1U) 1194 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 1195 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 1196 #define RCC_BDCR_LSEBYP_Pos (2U) 1197 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 1198 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 1199 1200 #define RCC_BDCR_RTCSEL_Pos (8U) 1201 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 1202 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 1203 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 1204 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 1205 1206 /*!< RTC congiguration */ 1207 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ 1208 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ 1209 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ 1210 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ 1211 1212 #define RCC_BDCR_RTCEN_Pos (15U) 1213 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 1214 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 1215 #define RCC_BDCR_BDRST_Pos (16U) 1216 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 1217 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 1218 1219 /******************* Bit definition for RCC_CSR register ********************/ 1220 #define RCC_CSR_LSION_Pos (0U) 1221 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 1222 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 1223 #define RCC_CSR_LSIRDY_Pos (1U) 1224 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 1225 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 1226 #define RCC_CSR_RMVF_Pos (24U) 1227 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 1228 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 1229 #define RCC_CSR_PINRSTF_Pos (26U) 1230 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 1231 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 1232 #define RCC_CSR_PORRSTF_Pos (27U) 1233 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 1234 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 1235 #define RCC_CSR_SFTRSTF_Pos (28U) 1236 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 1237 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 1238 #define RCC_CSR_IWDGRSTF_Pos (29U) 1239 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 1240 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 1241 #define RCC_CSR_WWDGRSTF_Pos (30U) 1242 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 1243 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 1244 #define RCC_CSR_LPWRRSTF_Pos (31U) 1245 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 1246 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 1247 1248 1249 1250 /******************************************************************************/ 1251 /* */ 1252 /* General Purpose and Alternate Function I/O */ 1253 /* */ 1254 /******************************************************************************/ 1255 1256 /******************* Bit definition for GPIO_CRL register *******************/ 1257 #define GPIO_CRL_MODE_Pos (0U) 1258 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ 1259 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ 1260 1261 #define GPIO_CRL_MODE0_Pos (0U) 1262 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ 1263 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ 1264 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ 1265 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ 1266 1267 #define GPIO_CRL_MODE1_Pos (4U) 1268 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ 1269 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ 1270 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ 1271 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ 1272 1273 #define GPIO_CRL_MODE2_Pos (8U) 1274 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ 1275 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ 1276 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ 1277 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ 1278 1279 #define GPIO_CRL_MODE3_Pos (12U) 1280 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ 1281 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ 1282 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ 1283 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ 1284 1285 #define GPIO_CRL_MODE4_Pos (16U) 1286 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ 1287 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ 1288 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ 1289 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ 1290 1291 #define GPIO_CRL_MODE5_Pos (20U) 1292 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ 1293 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ 1294 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ 1295 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ 1296 1297 #define GPIO_CRL_MODE6_Pos (24U) 1298 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ 1299 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ 1300 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ 1301 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ 1302 1303 #define GPIO_CRL_MODE7_Pos (28U) 1304 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ 1305 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ 1306 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ 1307 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ 1308 1309 #define GPIO_CRL_CNF_Pos (2U) 1310 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ 1311 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ 1312 1313 #define GPIO_CRL_CNF0_Pos (2U) 1314 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ 1315 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ 1316 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ 1317 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ 1318 1319 #define GPIO_CRL_CNF1_Pos (6U) 1320 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ 1321 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ 1322 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ 1323 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ 1324 1325 #define GPIO_CRL_CNF2_Pos (10U) 1326 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ 1327 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ 1328 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ 1329 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ 1330 1331 #define GPIO_CRL_CNF3_Pos (14U) 1332 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ 1333 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ 1334 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ 1335 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ 1336 1337 #define GPIO_CRL_CNF4_Pos (18U) 1338 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ 1339 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ 1340 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ 1341 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ 1342 1343 #define GPIO_CRL_CNF5_Pos (22U) 1344 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ 1345 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ 1346 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ 1347 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ 1348 1349 #define GPIO_CRL_CNF6_Pos (26U) 1350 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ 1351 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ 1352 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ 1353 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ 1354 1355 #define GPIO_CRL_CNF7_Pos (30U) 1356 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ 1357 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ 1358 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ 1359 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ 1360 1361 /******************* Bit definition for GPIO_CRH register *******************/ 1362 #define GPIO_CRH_MODE_Pos (0U) 1363 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ 1364 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ 1365 1366 #define GPIO_CRH_MODE8_Pos (0U) 1367 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ 1368 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ 1369 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ 1370 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ 1371 1372 #define GPIO_CRH_MODE9_Pos (4U) 1373 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ 1374 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ 1375 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ 1376 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ 1377 1378 #define GPIO_CRH_MODE10_Pos (8U) 1379 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ 1380 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ 1381 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ 1382 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ 1383 1384 #define GPIO_CRH_MODE11_Pos (12U) 1385 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ 1386 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ 1387 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ 1388 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ 1389 1390 #define GPIO_CRH_MODE12_Pos (16U) 1391 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ 1392 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ 1393 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ 1394 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ 1395 1396 #define GPIO_CRH_MODE13_Pos (20U) 1397 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ 1398 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ 1399 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ 1400 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ 1401 1402 #define GPIO_CRH_MODE14_Pos (24U) 1403 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ 1404 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ 1405 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ 1406 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ 1407 1408 #define GPIO_CRH_MODE15_Pos (28U) 1409 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ 1410 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ 1411 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ 1412 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ 1413 1414 #define GPIO_CRH_CNF_Pos (2U) 1415 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ 1416 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ 1417 1418 #define GPIO_CRH_CNF8_Pos (2U) 1419 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ 1420 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ 1421 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ 1422 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ 1423 1424 #define GPIO_CRH_CNF9_Pos (6U) 1425 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ 1426 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ 1427 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ 1428 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ 1429 1430 #define GPIO_CRH_CNF10_Pos (10U) 1431 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ 1432 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ 1433 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ 1434 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ 1435 1436 #define GPIO_CRH_CNF11_Pos (14U) 1437 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ 1438 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ 1439 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ 1440 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ 1441 1442 #define GPIO_CRH_CNF12_Pos (18U) 1443 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ 1444 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ 1445 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ 1446 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ 1447 1448 #define GPIO_CRH_CNF13_Pos (22U) 1449 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ 1450 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ 1451 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ 1452 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ 1453 1454 #define GPIO_CRH_CNF14_Pos (26U) 1455 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ 1456 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ 1457 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ 1458 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ 1459 1460 #define GPIO_CRH_CNF15_Pos (30U) 1461 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ 1462 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ 1463 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ 1464 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ 1465 1466 /*!<****************** Bit definition for GPIO_IDR register *******************/ 1467 #define GPIO_IDR_IDR0_Pos (0U) 1468 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ 1469 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ 1470 #define GPIO_IDR_IDR1_Pos (1U) 1471 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ 1472 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ 1473 #define GPIO_IDR_IDR2_Pos (2U) 1474 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ 1475 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ 1476 #define GPIO_IDR_IDR3_Pos (3U) 1477 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ 1478 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ 1479 #define GPIO_IDR_IDR4_Pos (4U) 1480 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ 1481 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ 1482 #define GPIO_IDR_IDR5_Pos (5U) 1483 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ 1484 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ 1485 #define GPIO_IDR_IDR6_Pos (6U) 1486 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ 1487 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ 1488 #define GPIO_IDR_IDR7_Pos (7U) 1489 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ 1490 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ 1491 #define GPIO_IDR_IDR8_Pos (8U) 1492 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ 1493 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ 1494 #define GPIO_IDR_IDR9_Pos (9U) 1495 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ 1496 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ 1497 #define GPIO_IDR_IDR10_Pos (10U) 1498 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ 1499 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ 1500 #define GPIO_IDR_IDR11_Pos (11U) 1501 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ 1502 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ 1503 #define GPIO_IDR_IDR12_Pos (12U) 1504 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ 1505 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ 1506 #define GPIO_IDR_IDR13_Pos (13U) 1507 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ 1508 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ 1509 #define GPIO_IDR_IDR14_Pos (14U) 1510 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ 1511 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ 1512 #define GPIO_IDR_IDR15_Pos (15U) 1513 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ 1514 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ 1515 1516 /******************* Bit definition for GPIO_ODR register *******************/ 1517 #define GPIO_ODR_ODR0_Pos (0U) 1518 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ 1519 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ 1520 #define GPIO_ODR_ODR1_Pos (1U) 1521 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ 1522 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ 1523 #define GPIO_ODR_ODR2_Pos (2U) 1524 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ 1525 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ 1526 #define GPIO_ODR_ODR3_Pos (3U) 1527 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ 1528 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ 1529 #define GPIO_ODR_ODR4_Pos (4U) 1530 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ 1531 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ 1532 #define GPIO_ODR_ODR5_Pos (5U) 1533 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ 1534 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ 1535 #define GPIO_ODR_ODR6_Pos (6U) 1536 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ 1537 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ 1538 #define GPIO_ODR_ODR7_Pos (7U) 1539 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ 1540 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ 1541 #define GPIO_ODR_ODR8_Pos (8U) 1542 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ 1543 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ 1544 #define GPIO_ODR_ODR9_Pos (9U) 1545 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ 1546 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ 1547 #define GPIO_ODR_ODR10_Pos (10U) 1548 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ 1549 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ 1550 #define GPIO_ODR_ODR11_Pos (11U) 1551 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ 1552 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ 1553 #define GPIO_ODR_ODR12_Pos (12U) 1554 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ 1555 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ 1556 #define GPIO_ODR_ODR13_Pos (13U) 1557 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ 1558 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ 1559 #define GPIO_ODR_ODR14_Pos (14U) 1560 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ 1561 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ 1562 #define GPIO_ODR_ODR15_Pos (15U) 1563 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ 1564 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ 1565 1566 /****************** Bit definition for GPIO_BSRR register *******************/ 1567 #define GPIO_BSRR_BS0_Pos (0U) 1568 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 1569 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ 1570 #define GPIO_BSRR_BS1_Pos (1U) 1571 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 1572 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ 1573 #define GPIO_BSRR_BS2_Pos (2U) 1574 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 1575 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ 1576 #define GPIO_BSRR_BS3_Pos (3U) 1577 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 1578 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ 1579 #define GPIO_BSRR_BS4_Pos (4U) 1580 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 1581 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ 1582 #define GPIO_BSRR_BS5_Pos (5U) 1583 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 1584 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ 1585 #define GPIO_BSRR_BS6_Pos (6U) 1586 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 1587 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ 1588 #define GPIO_BSRR_BS7_Pos (7U) 1589 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 1590 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ 1591 #define GPIO_BSRR_BS8_Pos (8U) 1592 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 1593 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ 1594 #define GPIO_BSRR_BS9_Pos (9U) 1595 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 1596 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ 1597 #define GPIO_BSRR_BS10_Pos (10U) 1598 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 1599 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ 1600 #define GPIO_BSRR_BS11_Pos (11U) 1601 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 1602 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ 1603 #define GPIO_BSRR_BS12_Pos (12U) 1604 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 1605 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ 1606 #define GPIO_BSRR_BS13_Pos (13U) 1607 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 1608 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ 1609 #define GPIO_BSRR_BS14_Pos (14U) 1610 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 1611 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ 1612 #define GPIO_BSRR_BS15_Pos (15U) 1613 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 1614 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ 1615 1616 #define GPIO_BSRR_BR0_Pos (16U) 1617 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 1618 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ 1619 #define GPIO_BSRR_BR1_Pos (17U) 1620 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 1621 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ 1622 #define GPIO_BSRR_BR2_Pos (18U) 1623 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 1624 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ 1625 #define GPIO_BSRR_BR3_Pos (19U) 1626 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 1627 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ 1628 #define GPIO_BSRR_BR4_Pos (20U) 1629 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 1630 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ 1631 #define GPIO_BSRR_BR5_Pos (21U) 1632 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 1633 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ 1634 #define GPIO_BSRR_BR6_Pos (22U) 1635 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 1636 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ 1637 #define GPIO_BSRR_BR7_Pos (23U) 1638 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 1639 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ 1640 #define GPIO_BSRR_BR8_Pos (24U) 1641 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 1642 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ 1643 #define GPIO_BSRR_BR9_Pos (25U) 1644 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 1645 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ 1646 #define GPIO_BSRR_BR10_Pos (26U) 1647 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 1648 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ 1649 #define GPIO_BSRR_BR11_Pos (27U) 1650 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 1651 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ 1652 #define GPIO_BSRR_BR12_Pos (28U) 1653 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 1654 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ 1655 #define GPIO_BSRR_BR13_Pos (29U) 1656 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 1657 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ 1658 #define GPIO_BSRR_BR14_Pos (30U) 1659 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 1660 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ 1661 #define GPIO_BSRR_BR15_Pos (31U) 1662 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 1663 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ 1664 1665 /******************* Bit definition for GPIO_BRR register *******************/ 1666 #define GPIO_BRR_BR0_Pos (0U) 1667 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 1668 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ 1669 #define GPIO_BRR_BR1_Pos (1U) 1670 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 1671 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ 1672 #define GPIO_BRR_BR2_Pos (2U) 1673 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 1674 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ 1675 #define GPIO_BRR_BR3_Pos (3U) 1676 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 1677 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ 1678 #define GPIO_BRR_BR4_Pos (4U) 1679 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 1680 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ 1681 #define GPIO_BRR_BR5_Pos (5U) 1682 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 1683 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ 1684 #define GPIO_BRR_BR6_Pos (6U) 1685 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 1686 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ 1687 #define GPIO_BRR_BR7_Pos (7U) 1688 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 1689 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ 1690 #define GPIO_BRR_BR8_Pos (8U) 1691 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 1692 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ 1693 #define GPIO_BRR_BR9_Pos (9U) 1694 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 1695 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ 1696 #define GPIO_BRR_BR10_Pos (10U) 1697 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 1698 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ 1699 #define GPIO_BRR_BR11_Pos (11U) 1700 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 1701 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ 1702 #define GPIO_BRR_BR12_Pos (12U) 1703 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 1704 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ 1705 #define GPIO_BRR_BR13_Pos (13U) 1706 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 1707 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ 1708 #define GPIO_BRR_BR14_Pos (14U) 1709 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 1710 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ 1711 #define GPIO_BRR_BR15_Pos (15U) 1712 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 1713 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ 1714 1715 /****************** Bit definition for GPIO_LCKR register *******************/ 1716 #define GPIO_LCKR_LCK0_Pos (0U) 1717 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 1718 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ 1719 #define GPIO_LCKR_LCK1_Pos (1U) 1720 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 1721 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ 1722 #define GPIO_LCKR_LCK2_Pos (2U) 1723 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 1724 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ 1725 #define GPIO_LCKR_LCK3_Pos (3U) 1726 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 1727 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ 1728 #define GPIO_LCKR_LCK4_Pos (4U) 1729 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 1730 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ 1731 #define GPIO_LCKR_LCK5_Pos (5U) 1732 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 1733 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ 1734 #define GPIO_LCKR_LCK6_Pos (6U) 1735 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 1736 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ 1737 #define GPIO_LCKR_LCK7_Pos (7U) 1738 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 1739 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ 1740 #define GPIO_LCKR_LCK8_Pos (8U) 1741 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 1742 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ 1743 #define GPIO_LCKR_LCK9_Pos (9U) 1744 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 1745 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ 1746 #define GPIO_LCKR_LCK10_Pos (10U) 1747 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 1748 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ 1749 #define GPIO_LCKR_LCK11_Pos (11U) 1750 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 1751 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ 1752 #define GPIO_LCKR_LCK12_Pos (12U) 1753 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 1754 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ 1755 #define GPIO_LCKR_LCK13_Pos (13U) 1756 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 1757 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ 1758 #define GPIO_LCKR_LCK14_Pos (14U) 1759 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 1760 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ 1761 #define GPIO_LCKR_LCK15_Pos (15U) 1762 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 1763 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ 1764 #define GPIO_LCKR_LCKK_Pos (16U) 1765 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 1766 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ 1767 1768 /*----------------------------------------------------------------------------*/ 1769 1770 /****************** Bit definition for AFIO_EVCR register *******************/ 1771 #define AFIO_EVCR_PIN_Pos (0U) 1772 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ 1773 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ 1774 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ 1775 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ 1776 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ 1777 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ 1778 1779 /*!< PIN configuration */ 1780 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ 1781 #define AFIO_EVCR_PIN_PX1_Pos (0U) 1782 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ 1783 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ 1784 #define AFIO_EVCR_PIN_PX2_Pos (1U) 1785 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ 1786 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ 1787 #define AFIO_EVCR_PIN_PX3_Pos (0U) 1788 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ 1789 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ 1790 #define AFIO_EVCR_PIN_PX4_Pos (2U) 1791 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ 1792 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ 1793 #define AFIO_EVCR_PIN_PX5_Pos (0U) 1794 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ 1795 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ 1796 #define AFIO_EVCR_PIN_PX6_Pos (1U) 1797 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ 1798 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ 1799 #define AFIO_EVCR_PIN_PX7_Pos (0U) 1800 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ 1801 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ 1802 #define AFIO_EVCR_PIN_PX8_Pos (3U) 1803 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ 1804 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ 1805 #define AFIO_EVCR_PIN_PX9_Pos (0U) 1806 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ 1807 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ 1808 #define AFIO_EVCR_PIN_PX10_Pos (1U) 1809 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ 1810 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ 1811 #define AFIO_EVCR_PIN_PX11_Pos (0U) 1812 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ 1813 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ 1814 #define AFIO_EVCR_PIN_PX12_Pos (2U) 1815 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ 1816 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ 1817 #define AFIO_EVCR_PIN_PX13_Pos (0U) 1818 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ 1819 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ 1820 #define AFIO_EVCR_PIN_PX14_Pos (1U) 1821 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ 1822 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ 1823 #define AFIO_EVCR_PIN_PX15_Pos (0U) 1824 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ 1825 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ 1826 1827 #define AFIO_EVCR_PORT_Pos (4U) 1828 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ 1829 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ 1830 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ 1831 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ 1832 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ 1833 1834 /*!< PORT configuration */ 1835 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ 1836 #define AFIO_EVCR_PORT_PB_Pos (4U) 1837 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ 1838 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ 1839 #define AFIO_EVCR_PORT_PC_Pos (5U) 1840 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ 1841 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ 1842 #define AFIO_EVCR_PORT_PD_Pos (4U) 1843 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ 1844 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ 1845 #define AFIO_EVCR_PORT_PE_Pos (6U) 1846 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ 1847 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ 1848 1849 #define AFIO_EVCR_EVOE_Pos (7U) 1850 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ 1851 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ 1852 1853 /****************** Bit definition for AFIO_MAPR register *******************/ 1854 #define AFIO_MAPR_SPI1_REMAP_Pos (0U) 1855 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ 1856 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ 1857 #define AFIO_MAPR_I2C1_REMAP_Pos (1U) 1858 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ 1859 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ 1860 #define AFIO_MAPR_USART1_REMAP_Pos (2U) 1861 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ 1862 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ 1863 #define AFIO_MAPR_USART2_REMAP_Pos (3U) 1864 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ 1865 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ 1866 1867 1868 #define AFIO_MAPR_TIM1_REMAP_Pos (6U) 1869 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ 1870 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ 1871 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ 1872 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ 1873 1874 /*!< TIM1_REMAP configuration */ 1875 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ 1876 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) 1877 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ 1878 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ 1879 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) 1880 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ 1881 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ 1882 1883 #define AFIO_MAPR_TIM2_REMAP_Pos (8U) 1884 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ 1885 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ 1886 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ 1887 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ 1888 1889 /*!< TIM2_REMAP configuration */ 1890 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ 1891 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) 1892 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ 1893 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ 1894 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) 1895 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ 1896 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ 1897 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) 1898 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ 1899 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ 1900 1901 #define AFIO_MAPR_TIM3_REMAP_Pos (10U) 1902 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ 1903 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ 1904 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ 1905 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ 1906 1907 /*!< TIM3_REMAP configuration */ 1908 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ 1909 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) 1910 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ 1911 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ 1912 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) 1913 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ 1914 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ 1915 1916 1917 1918 #define AFIO_MAPR_PD01_REMAP_Pos (15U) 1919 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ 1920 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ 1921 1922 /*!< SWJ_CFG configuration */ 1923 #define AFIO_MAPR_SWJ_CFG_Pos (24U) 1924 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ 1925 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ 1926 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ 1927 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ 1928 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ 1929 1930 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ 1931 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) 1932 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ 1933 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ 1934 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) 1935 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ 1936 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ 1937 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) 1938 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ 1939 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ 1940 1941 1942 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 1943 #define AFIO_EXTICR1_EXTI0_Pos (0U) 1944 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 1945 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 1946 #define AFIO_EXTICR1_EXTI1_Pos (4U) 1947 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 1948 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 1949 #define AFIO_EXTICR1_EXTI2_Pos (8U) 1950 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 1951 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 1952 #define AFIO_EXTICR1_EXTI3_Pos (12U) 1953 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 1954 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 1955 1956 /*!< EXTI0 configuration */ 1957 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ 1958 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) 1959 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ 1960 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ 1961 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) 1962 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ 1963 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ 1964 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) 1965 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ 1966 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ 1967 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) 1968 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ 1969 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ 1970 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) 1971 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ 1972 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ 1973 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) 1974 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ 1975 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ 1976 1977 /*!< EXTI1 configuration */ 1978 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ 1979 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) 1980 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ 1981 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ 1982 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) 1983 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ 1984 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ 1985 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) 1986 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ 1987 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ 1988 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) 1989 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ 1990 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ 1991 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) 1992 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ 1993 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ 1994 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) 1995 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ 1996 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ 1997 1998 /*!< EXTI2 configuration */ 1999 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ 2000 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) 2001 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ 2002 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ 2003 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) 2004 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ 2005 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ 2006 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) 2007 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ 2008 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ 2009 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) 2010 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ 2011 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ 2012 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) 2013 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ 2014 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ 2015 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) 2016 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ 2017 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ 2018 2019 /*!< EXTI3 configuration */ 2020 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ 2021 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) 2022 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ 2023 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ 2024 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) 2025 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ 2026 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ 2027 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) 2028 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ 2029 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ 2030 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) 2031 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ 2032 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ 2033 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) 2034 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ 2035 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ 2036 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) 2037 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ 2038 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ 2039 2040 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 2041 #define AFIO_EXTICR2_EXTI4_Pos (0U) 2042 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 2043 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 2044 #define AFIO_EXTICR2_EXTI5_Pos (4U) 2045 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 2046 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 2047 #define AFIO_EXTICR2_EXTI6_Pos (8U) 2048 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 2049 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 2050 #define AFIO_EXTICR2_EXTI7_Pos (12U) 2051 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 2052 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 2053 2054 /*!< EXTI4 configuration */ 2055 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ 2056 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) 2057 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ 2058 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ 2059 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) 2060 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ 2061 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ 2062 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) 2063 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ 2064 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ 2065 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) 2066 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ 2067 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ 2068 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) 2069 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ 2070 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ 2071 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) 2072 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ 2073 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ 2074 2075 /* EXTI5 configuration */ 2076 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ 2077 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) 2078 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ 2079 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ 2080 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) 2081 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ 2082 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ 2083 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) 2084 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ 2085 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ 2086 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) 2087 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ 2088 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ 2089 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) 2090 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ 2091 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ 2092 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) 2093 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ 2094 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ 2095 2096 /*!< EXTI6 configuration */ 2097 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ 2098 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) 2099 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ 2100 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ 2101 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) 2102 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ 2103 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ 2104 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) 2105 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ 2106 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ 2107 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) 2108 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ 2109 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ 2110 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) 2111 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ 2112 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ 2113 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) 2114 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ 2115 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ 2116 2117 /*!< EXTI7 configuration */ 2118 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ 2119 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) 2120 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ 2121 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ 2122 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) 2123 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ 2124 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ 2125 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) 2126 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ 2127 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ 2128 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) 2129 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ 2130 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ 2131 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) 2132 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ 2133 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ 2134 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) 2135 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ 2136 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ 2137 2138 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 2139 #define AFIO_EXTICR3_EXTI8_Pos (0U) 2140 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 2141 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 2142 #define AFIO_EXTICR3_EXTI9_Pos (4U) 2143 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 2144 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 2145 #define AFIO_EXTICR3_EXTI10_Pos (8U) 2146 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 2147 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 2148 #define AFIO_EXTICR3_EXTI11_Pos (12U) 2149 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 2150 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 2151 2152 /*!< EXTI8 configuration */ 2153 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ 2154 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) 2155 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ 2156 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ 2157 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) 2158 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ 2159 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ 2160 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) 2161 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ 2162 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ 2163 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) 2164 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ 2165 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ 2166 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) 2167 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ 2168 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ 2169 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) 2170 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ 2171 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ 2172 2173 /*!< EXTI9 configuration */ 2174 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ 2175 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) 2176 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ 2177 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ 2178 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) 2179 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ 2180 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ 2181 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) 2182 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ 2183 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ 2184 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) 2185 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ 2186 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ 2187 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) 2188 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ 2189 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ 2190 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) 2191 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ 2192 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ 2193 2194 /*!< EXTI10 configuration */ 2195 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ 2196 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) 2197 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ 2198 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ 2199 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) 2200 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ 2201 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ 2202 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) 2203 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ 2204 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ 2205 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) 2206 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ 2207 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ 2208 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) 2209 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ 2210 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ 2211 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) 2212 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ 2213 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ 2214 2215 /*!< EXTI11 configuration */ 2216 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ 2217 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) 2218 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ 2219 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ 2220 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) 2221 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ 2222 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ 2223 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) 2224 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ 2225 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ 2226 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) 2227 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ 2228 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ 2229 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) 2230 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ 2231 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ 2232 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) 2233 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ 2234 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ 2235 2236 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 2237 #define AFIO_EXTICR4_EXTI12_Pos (0U) 2238 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 2239 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 2240 #define AFIO_EXTICR4_EXTI13_Pos (4U) 2241 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 2242 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 2243 #define AFIO_EXTICR4_EXTI14_Pos (8U) 2244 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 2245 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 2246 #define AFIO_EXTICR4_EXTI15_Pos (12U) 2247 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 2248 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 2249 2250 /* EXTI12 configuration */ 2251 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ 2252 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) 2253 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ 2254 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ 2255 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) 2256 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ 2257 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ 2258 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) 2259 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ 2260 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ 2261 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) 2262 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ 2263 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ 2264 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) 2265 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ 2266 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ 2267 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) 2268 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ 2269 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ 2270 2271 /* EXTI13 configuration */ 2272 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ 2273 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) 2274 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ 2275 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ 2276 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) 2277 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ 2278 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ 2279 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) 2280 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ 2281 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ 2282 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) 2283 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ 2284 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ 2285 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) 2286 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ 2287 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ 2288 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) 2289 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ 2290 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ 2291 2292 /*!< EXTI14 configuration */ 2293 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ 2294 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) 2295 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ 2296 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ 2297 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) 2298 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ 2299 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ 2300 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) 2301 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ 2302 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ 2303 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) 2304 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ 2305 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ 2306 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) 2307 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ 2308 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ 2309 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) 2310 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ 2311 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ 2312 2313 /*!< EXTI15 configuration */ 2314 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ 2315 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) 2316 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ 2317 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ 2318 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) 2319 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ 2320 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ 2321 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) 2322 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ 2323 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ 2324 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) 2325 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ 2326 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ 2327 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) 2328 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ 2329 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ 2330 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) 2331 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ 2332 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ 2333 2334 /****************** Bit definition for AFIO_MAPR2 register ******************/ 2335 2336 2337 2338 /******************************************************************************/ 2339 /* */ 2340 /* External Interrupt/Event Controller */ 2341 /* */ 2342 /******************************************************************************/ 2343 2344 /******************* Bit definition for EXTI_IMR register *******************/ 2345 #define EXTI_IMR_MR0_Pos (0U) 2346 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2347 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2348 #define EXTI_IMR_MR1_Pos (1U) 2349 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2350 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2351 #define EXTI_IMR_MR2_Pos (2U) 2352 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2353 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2354 #define EXTI_IMR_MR3_Pos (3U) 2355 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2356 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2357 #define EXTI_IMR_MR4_Pos (4U) 2358 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2359 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2360 #define EXTI_IMR_MR5_Pos (5U) 2361 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2362 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2363 #define EXTI_IMR_MR6_Pos (6U) 2364 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2365 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2366 #define EXTI_IMR_MR7_Pos (7U) 2367 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2368 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2369 #define EXTI_IMR_MR8_Pos (8U) 2370 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2371 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2372 #define EXTI_IMR_MR9_Pos (9U) 2373 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2374 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2375 #define EXTI_IMR_MR10_Pos (10U) 2376 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2377 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2378 #define EXTI_IMR_MR11_Pos (11U) 2379 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2380 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2381 #define EXTI_IMR_MR12_Pos (12U) 2382 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2383 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2384 #define EXTI_IMR_MR13_Pos (13U) 2385 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2386 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2387 #define EXTI_IMR_MR14_Pos (14U) 2388 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2389 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2390 #define EXTI_IMR_MR15_Pos (15U) 2391 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2392 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2393 #define EXTI_IMR_MR16_Pos (16U) 2394 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2395 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2396 #define EXTI_IMR_MR17_Pos (17U) 2397 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2398 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2399 #define EXTI_IMR_MR18_Pos (18U) 2400 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 2401 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 2402 2403 /* References Defines */ 2404 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2405 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2406 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2407 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2408 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2409 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2410 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2411 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2412 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2413 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2414 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2415 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2416 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2417 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2418 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2419 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2420 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2421 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2422 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2423 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ 2424 2425 /******************* Bit definition for EXTI_EMR register *******************/ 2426 #define EXTI_EMR_MR0_Pos (0U) 2427 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2428 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2429 #define EXTI_EMR_MR1_Pos (1U) 2430 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2431 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2432 #define EXTI_EMR_MR2_Pos (2U) 2433 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2434 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2435 #define EXTI_EMR_MR3_Pos (3U) 2436 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2437 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2438 #define EXTI_EMR_MR4_Pos (4U) 2439 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2440 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2441 #define EXTI_EMR_MR5_Pos (5U) 2442 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2443 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2444 #define EXTI_EMR_MR6_Pos (6U) 2445 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2446 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2447 #define EXTI_EMR_MR7_Pos (7U) 2448 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2449 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2450 #define EXTI_EMR_MR8_Pos (8U) 2451 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2452 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2453 #define EXTI_EMR_MR9_Pos (9U) 2454 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2455 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2456 #define EXTI_EMR_MR10_Pos (10U) 2457 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2458 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2459 #define EXTI_EMR_MR11_Pos (11U) 2460 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2461 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2462 #define EXTI_EMR_MR12_Pos (12U) 2463 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2464 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2465 #define EXTI_EMR_MR13_Pos (13U) 2466 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2467 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2468 #define EXTI_EMR_MR14_Pos (14U) 2469 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2470 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2471 #define EXTI_EMR_MR15_Pos (15U) 2472 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2473 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2474 #define EXTI_EMR_MR16_Pos (16U) 2475 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2476 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2477 #define EXTI_EMR_MR17_Pos (17U) 2478 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2479 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2480 #define EXTI_EMR_MR18_Pos (18U) 2481 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 2482 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 2483 2484 /* References Defines */ 2485 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2486 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2487 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2488 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2489 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2490 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2491 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2492 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2493 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2494 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2495 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2496 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2497 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2498 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2499 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2500 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2501 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2502 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2503 #define EXTI_EMR_EM18 EXTI_EMR_MR18 2504 2505 /****************** Bit definition for EXTI_RTSR register *******************/ 2506 #define EXTI_RTSR_TR0_Pos (0U) 2507 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2508 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2509 #define EXTI_RTSR_TR1_Pos (1U) 2510 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2511 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2512 #define EXTI_RTSR_TR2_Pos (2U) 2513 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2514 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2515 #define EXTI_RTSR_TR3_Pos (3U) 2516 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2517 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2518 #define EXTI_RTSR_TR4_Pos (4U) 2519 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2520 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2521 #define EXTI_RTSR_TR5_Pos (5U) 2522 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2523 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2524 #define EXTI_RTSR_TR6_Pos (6U) 2525 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2526 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2527 #define EXTI_RTSR_TR7_Pos (7U) 2528 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2529 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2530 #define EXTI_RTSR_TR8_Pos (8U) 2531 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2532 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2533 #define EXTI_RTSR_TR9_Pos (9U) 2534 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2535 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2536 #define EXTI_RTSR_TR10_Pos (10U) 2537 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2538 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2539 #define EXTI_RTSR_TR11_Pos (11U) 2540 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2541 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2542 #define EXTI_RTSR_TR12_Pos (12U) 2543 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2544 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2545 #define EXTI_RTSR_TR13_Pos (13U) 2546 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2547 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2548 #define EXTI_RTSR_TR14_Pos (14U) 2549 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2550 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2551 #define EXTI_RTSR_TR15_Pos (15U) 2552 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2553 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2554 #define EXTI_RTSR_TR16_Pos (16U) 2555 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2556 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2557 #define EXTI_RTSR_TR17_Pos (17U) 2558 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2559 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2560 #define EXTI_RTSR_TR18_Pos (18U) 2561 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 2562 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2563 2564 /* References Defines */ 2565 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2566 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2567 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2568 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2569 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2570 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2571 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2572 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2573 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2574 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2575 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2576 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2577 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2578 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2579 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2580 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2581 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2582 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2583 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 2584 2585 /****************** Bit definition for EXTI_FTSR register *******************/ 2586 #define EXTI_FTSR_TR0_Pos (0U) 2587 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2588 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2589 #define EXTI_FTSR_TR1_Pos (1U) 2590 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2591 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2592 #define EXTI_FTSR_TR2_Pos (2U) 2593 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2594 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2595 #define EXTI_FTSR_TR3_Pos (3U) 2596 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2597 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2598 #define EXTI_FTSR_TR4_Pos (4U) 2599 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2600 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2601 #define EXTI_FTSR_TR5_Pos (5U) 2602 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2603 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2604 #define EXTI_FTSR_TR6_Pos (6U) 2605 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2606 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2607 #define EXTI_FTSR_TR7_Pos (7U) 2608 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2609 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2610 #define EXTI_FTSR_TR8_Pos (8U) 2611 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2612 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2613 #define EXTI_FTSR_TR9_Pos (9U) 2614 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2615 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2616 #define EXTI_FTSR_TR10_Pos (10U) 2617 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2618 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2619 #define EXTI_FTSR_TR11_Pos (11U) 2620 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2621 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2622 #define EXTI_FTSR_TR12_Pos (12U) 2623 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2624 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2625 #define EXTI_FTSR_TR13_Pos (13U) 2626 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2627 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2628 #define EXTI_FTSR_TR14_Pos (14U) 2629 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2630 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2631 #define EXTI_FTSR_TR15_Pos (15U) 2632 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2633 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2634 #define EXTI_FTSR_TR16_Pos (16U) 2635 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2636 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2637 #define EXTI_FTSR_TR17_Pos (17U) 2638 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2639 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2640 #define EXTI_FTSR_TR18_Pos (18U) 2641 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 2642 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2643 2644 /* References Defines */ 2645 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2646 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2647 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2648 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2649 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2650 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2651 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2652 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2653 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2654 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2655 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2656 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2657 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2658 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2659 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2660 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2661 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2662 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2663 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 2664 2665 /****************** Bit definition for EXTI_SWIER register ******************/ 2666 #define EXTI_SWIER_SWIER0_Pos (0U) 2667 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2668 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2669 #define EXTI_SWIER_SWIER1_Pos (1U) 2670 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2671 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2672 #define EXTI_SWIER_SWIER2_Pos (2U) 2673 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2674 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2675 #define EXTI_SWIER_SWIER3_Pos (3U) 2676 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2677 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2678 #define EXTI_SWIER_SWIER4_Pos (4U) 2679 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2680 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2681 #define EXTI_SWIER_SWIER5_Pos (5U) 2682 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2683 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2684 #define EXTI_SWIER_SWIER6_Pos (6U) 2685 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2686 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2687 #define EXTI_SWIER_SWIER7_Pos (7U) 2688 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2689 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2690 #define EXTI_SWIER_SWIER8_Pos (8U) 2691 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2692 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2693 #define EXTI_SWIER_SWIER9_Pos (9U) 2694 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2695 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2696 #define EXTI_SWIER_SWIER10_Pos (10U) 2697 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2698 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2699 #define EXTI_SWIER_SWIER11_Pos (11U) 2700 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2701 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2702 #define EXTI_SWIER_SWIER12_Pos (12U) 2703 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2704 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2705 #define EXTI_SWIER_SWIER13_Pos (13U) 2706 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2707 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2708 #define EXTI_SWIER_SWIER14_Pos (14U) 2709 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2710 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2711 #define EXTI_SWIER_SWIER15_Pos (15U) 2712 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2713 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2714 #define EXTI_SWIER_SWIER16_Pos (16U) 2715 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 2716 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 2717 #define EXTI_SWIER_SWIER17_Pos (17U) 2718 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 2719 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 2720 #define EXTI_SWIER_SWIER18_Pos (18U) 2721 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 2722 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 2723 2724 /* References Defines */ 2725 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 2726 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 2727 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 2728 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 2729 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 2730 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 2731 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 2732 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 2733 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 2734 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 2735 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 2736 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 2737 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 2738 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 2739 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 2740 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 2741 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 2742 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 2743 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 2744 2745 /******************* Bit definition for EXTI_PR register ********************/ 2746 #define EXTI_PR_PR0_Pos (0U) 2747 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 2748 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 2749 #define EXTI_PR_PR1_Pos (1U) 2750 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 2751 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 2752 #define EXTI_PR_PR2_Pos (2U) 2753 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 2754 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 2755 #define EXTI_PR_PR3_Pos (3U) 2756 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 2757 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 2758 #define EXTI_PR_PR4_Pos (4U) 2759 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 2760 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 2761 #define EXTI_PR_PR5_Pos (5U) 2762 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 2763 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 2764 #define EXTI_PR_PR6_Pos (6U) 2765 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 2766 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 2767 #define EXTI_PR_PR7_Pos (7U) 2768 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 2769 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 2770 #define EXTI_PR_PR8_Pos (8U) 2771 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 2772 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 2773 #define EXTI_PR_PR9_Pos (9U) 2774 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 2775 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 2776 #define EXTI_PR_PR10_Pos (10U) 2777 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 2778 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 2779 #define EXTI_PR_PR11_Pos (11U) 2780 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 2781 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 2782 #define EXTI_PR_PR12_Pos (12U) 2783 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 2784 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 2785 #define EXTI_PR_PR13_Pos (13U) 2786 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 2787 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 2788 #define EXTI_PR_PR14_Pos (14U) 2789 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 2790 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 2791 #define EXTI_PR_PR15_Pos (15U) 2792 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 2793 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 2794 #define EXTI_PR_PR16_Pos (16U) 2795 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 2796 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 2797 #define EXTI_PR_PR17_Pos (17U) 2798 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 2799 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 2800 #define EXTI_PR_PR18_Pos (18U) 2801 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 2802 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 2803 2804 /* References Defines */ 2805 #define EXTI_PR_PIF0 EXTI_PR_PR0 2806 #define EXTI_PR_PIF1 EXTI_PR_PR1 2807 #define EXTI_PR_PIF2 EXTI_PR_PR2 2808 #define EXTI_PR_PIF3 EXTI_PR_PR3 2809 #define EXTI_PR_PIF4 EXTI_PR_PR4 2810 #define EXTI_PR_PIF5 EXTI_PR_PR5 2811 #define EXTI_PR_PIF6 EXTI_PR_PR6 2812 #define EXTI_PR_PIF7 EXTI_PR_PR7 2813 #define EXTI_PR_PIF8 EXTI_PR_PR8 2814 #define EXTI_PR_PIF9 EXTI_PR_PR9 2815 #define EXTI_PR_PIF10 EXTI_PR_PR10 2816 #define EXTI_PR_PIF11 EXTI_PR_PR11 2817 #define EXTI_PR_PIF12 EXTI_PR_PR12 2818 #define EXTI_PR_PIF13 EXTI_PR_PR13 2819 #define EXTI_PR_PIF14 EXTI_PR_PR14 2820 #define EXTI_PR_PIF15 EXTI_PR_PR15 2821 #define EXTI_PR_PIF16 EXTI_PR_PR16 2822 #define EXTI_PR_PIF17 EXTI_PR_PR17 2823 #define EXTI_PR_PIF18 EXTI_PR_PR18 2824 2825 /******************************************************************************/ 2826 /* */ 2827 /* DMA Controller */ 2828 /* */ 2829 /******************************************************************************/ 2830 2831 /******************* Bit definition for DMA_ISR register ********************/ 2832 #define DMA_ISR_GIF1_Pos (0U) 2833 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2834 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2835 #define DMA_ISR_TCIF1_Pos (1U) 2836 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2837 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2838 #define DMA_ISR_HTIF1_Pos (2U) 2839 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2840 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2841 #define DMA_ISR_TEIF1_Pos (3U) 2842 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2843 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2844 #define DMA_ISR_GIF2_Pos (4U) 2845 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2846 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2847 #define DMA_ISR_TCIF2_Pos (5U) 2848 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2849 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2850 #define DMA_ISR_HTIF2_Pos (6U) 2851 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2852 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2853 #define DMA_ISR_TEIF2_Pos (7U) 2854 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2855 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2856 #define DMA_ISR_GIF3_Pos (8U) 2857 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2858 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2859 #define DMA_ISR_TCIF3_Pos (9U) 2860 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2861 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2862 #define DMA_ISR_HTIF3_Pos (10U) 2863 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2864 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2865 #define DMA_ISR_TEIF3_Pos (11U) 2866 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2867 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2868 #define DMA_ISR_GIF4_Pos (12U) 2869 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2870 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2871 #define DMA_ISR_TCIF4_Pos (13U) 2872 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2873 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2874 #define DMA_ISR_HTIF4_Pos (14U) 2875 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2876 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2877 #define DMA_ISR_TEIF4_Pos (15U) 2878 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2879 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2880 #define DMA_ISR_GIF5_Pos (16U) 2881 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2882 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2883 #define DMA_ISR_TCIF5_Pos (17U) 2884 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2885 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2886 #define DMA_ISR_HTIF5_Pos (18U) 2887 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2888 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2889 #define DMA_ISR_TEIF5_Pos (19U) 2890 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2891 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2892 #define DMA_ISR_GIF6_Pos (20U) 2893 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2894 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2895 #define DMA_ISR_TCIF6_Pos (21U) 2896 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2897 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2898 #define DMA_ISR_HTIF6_Pos (22U) 2899 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2900 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2901 #define DMA_ISR_TEIF6_Pos (23U) 2902 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2903 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2904 #define DMA_ISR_GIF7_Pos (24U) 2905 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2906 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2907 #define DMA_ISR_TCIF7_Pos (25U) 2908 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2909 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2910 #define DMA_ISR_HTIF7_Pos (26U) 2911 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2912 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2913 #define DMA_ISR_TEIF7_Pos (27U) 2914 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2915 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2916 2917 /******************* Bit definition for DMA_IFCR register *******************/ 2918 #define DMA_IFCR_CGIF1_Pos (0U) 2919 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2920 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2921 #define DMA_IFCR_CTCIF1_Pos (1U) 2922 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2923 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2924 #define DMA_IFCR_CHTIF1_Pos (2U) 2925 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2926 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2927 #define DMA_IFCR_CTEIF1_Pos (3U) 2928 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2929 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2930 #define DMA_IFCR_CGIF2_Pos (4U) 2931 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2932 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2933 #define DMA_IFCR_CTCIF2_Pos (5U) 2934 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2935 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2936 #define DMA_IFCR_CHTIF2_Pos (6U) 2937 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2938 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2939 #define DMA_IFCR_CTEIF2_Pos (7U) 2940 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2941 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2942 #define DMA_IFCR_CGIF3_Pos (8U) 2943 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2944 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2945 #define DMA_IFCR_CTCIF3_Pos (9U) 2946 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2947 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2948 #define DMA_IFCR_CHTIF3_Pos (10U) 2949 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2950 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2951 #define DMA_IFCR_CTEIF3_Pos (11U) 2952 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2953 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2954 #define DMA_IFCR_CGIF4_Pos (12U) 2955 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2956 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2957 #define DMA_IFCR_CTCIF4_Pos (13U) 2958 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2959 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2960 #define DMA_IFCR_CHTIF4_Pos (14U) 2961 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2962 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2963 #define DMA_IFCR_CTEIF4_Pos (15U) 2964 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2965 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2966 #define DMA_IFCR_CGIF5_Pos (16U) 2967 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2968 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2969 #define DMA_IFCR_CTCIF5_Pos (17U) 2970 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2971 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2972 #define DMA_IFCR_CHTIF5_Pos (18U) 2973 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2974 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2975 #define DMA_IFCR_CTEIF5_Pos (19U) 2976 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2977 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2978 #define DMA_IFCR_CGIF6_Pos (20U) 2979 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2980 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2981 #define DMA_IFCR_CTCIF6_Pos (21U) 2982 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2983 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2984 #define DMA_IFCR_CHTIF6_Pos (22U) 2985 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2986 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2987 #define DMA_IFCR_CTEIF6_Pos (23U) 2988 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2989 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2990 #define DMA_IFCR_CGIF7_Pos (24U) 2991 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2992 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2993 #define DMA_IFCR_CTCIF7_Pos (25U) 2994 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2995 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2996 #define DMA_IFCR_CHTIF7_Pos (26U) 2997 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2998 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2999 #define DMA_IFCR_CTEIF7_Pos (27U) 3000 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 3001 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 3002 3003 /******************* Bit definition for DMA_CCR register *******************/ 3004 #define DMA_CCR_EN_Pos (0U) 3005 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 3006 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 3007 #define DMA_CCR_TCIE_Pos (1U) 3008 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 3009 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 3010 #define DMA_CCR_HTIE_Pos (2U) 3011 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 3012 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 3013 #define DMA_CCR_TEIE_Pos (3U) 3014 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 3015 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 3016 #define DMA_CCR_DIR_Pos (4U) 3017 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 3018 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 3019 #define DMA_CCR_CIRC_Pos (5U) 3020 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 3021 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 3022 #define DMA_CCR_PINC_Pos (6U) 3023 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 3024 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 3025 #define DMA_CCR_MINC_Pos (7U) 3026 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 3027 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 3028 3029 #define DMA_CCR_PSIZE_Pos (8U) 3030 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 3031 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 3032 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 3033 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 3034 3035 #define DMA_CCR_MSIZE_Pos (10U) 3036 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 3037 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 3038 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 3039 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 3040 3041 #define DMA_CCR_PL_Pos (12U) 3042 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 3043 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 3044 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 3045 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 3046 3047 #define DMA_CCR_MEM2MEM_Pos (14U) 3048 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 3049 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 3050 3051 /****************** Bit definition for DMA_CNDTR register ******************/ 3052 #define DMA_CNDTR_NDT_Pos (0U) 3053 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 3054 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 3055 3056 /****************** Bit definition for DMA_CPAR register *******************/ 3057 #define DMA_CPAR_PA_Pos (0U) 3058 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 3059 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 3060 3061 /****************** Bit definition for DMA_CMAR register *******************/ 3062 #define DMA_CMAR_MA_Pos (0U) 3063 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 3064 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 3065 3066 /******************************************************************************/ 3067 /* */ 3068 /* Analog to Digital Converter (ADC) */ 3069 /* */ 3070 /******************************************************************************/ 3071 3072 /* 3073 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) 3074 */ 3075 /* Note: No specific macro feature on this device */ 3076 3077 /******************** Bit definition for ADC_SR register ********************/ 3078 #define ADC_SR_AWD_Pos (0U) 3079 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 3080 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 3081 #define ADC_SR_EOS_Pos (1U) 3082 #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ 3083 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 3084 #define ADC_SR_JEOS_Pos (2U) 3085 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 3086 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 3087 #define ADC_SR_JSTRT_Pos (3U) 3088 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 3089 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 3090 #define ADC_SR_STRT_Pos (4U) 3091 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 3092 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 3093 3094 /* Legacy defines */ 3095 #define ADC_SR_EOC (ADC_SR_EOS) 3096 #define ADC_SR_JEOC (ADC_SR_JEOS) 3097 3098 /******************* Bit definition for ADC_CR1 register ********************/ 3099 #define ADC_CR1_AWDCH_Pos (0U) 3100 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 3101 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 3102 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 3103 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 3104 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 3105 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 3106 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 3107 3108 #define ADC_CR1_EOSIE_Pos (5U) 3109 #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ 3110 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 3111 #define ADC_CR1_AWDIE_Pos (6U) 3112 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 3113 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 3114 #define ADC_CR1_JEOSIE_Pos (7U) 3115 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 3116 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 3117 #define ADC_CR1_SCAN_Pos (8U) 3118 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 3119 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 3120 #define ADC_CR1_AWDSGL_Pos (9U) 3121 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 3122 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 3123 #define ADC_CR1_JAUTO_Pos (10U) 3124 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 3125 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 3126 #define ADC_CR1_DISCEN_Pos (11U) 3127 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 3128 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 3129 #define ADC_CR1_JDISCEN_Pos (12U) 3130 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 3131 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 3132 3133 #define ADC_CR1_DISCNUM_Pos (13U) 3134 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 3135 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 3136 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 3137 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 3138 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 3139 3140 #define ADC_CR1_JAWDEN_Pos (22U) 3141 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 3142 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 3143 #define ADC_CR1_AWDEN_Pos (23U) 3144 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 3145 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 3146 3147 /* Legacy defines */ 3148 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) 3149 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 3150 3151 /******************* Bit definition for ADC_CR2 register ********************/ 3152 #define ADC_CR2_ADON_Pos (0U) 3153 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 3154 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 3155 #define ADC_CR2_CONT_Pos (1U) 3156 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 3157 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 3158 #define ADC_CR2_CAL_Pos (2U) 3159 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ 3160 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ 3161 #define ADC_CR2_RSTCAL_Pos (3U) 3162 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ 3163 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ 3164 #define ADC_CR2_DMA_Pos (8U) 3165 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 3166 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 3167 #define ADC_CR2_ALIGN_Pos (11U) 3168 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 3169 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 3170 3171 #define ADC_CR2_JEXTSEL_Pos (12U) 3172 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ 3173 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 3174 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ 3175 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ 3176 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ 3177 3178 #define ADC_CR2_JEXTTRIG_Pos (15U) 3179 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ 3180 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ 3181 3182 #define ADC_CR2_EXTSEL_Pos (17U) 3183 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ 3184 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 3185 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ 3186 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ 3187 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ 3188 3189 #define ADC_CR2_EXTTRIG_Pos (20U) 3190 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ 3191 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ 3192 #define ADC_CR2_JSWSTART_Pos (21U) 3193 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ 3194 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 3195 #define ADC_CR2_SWSTART_Pos (22U) 3196 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ 3197 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 3198 #define ADC_CR2_TSVREFE_Pos (23U) 3199 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ 3200 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 3201 3202 /****************** Bit definition for ADC_SMPR1 register *******************/ 3203 #define ADC_SMPR1_SMP10_Pos (0U) 3204 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ 3205 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 3206 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ 3207 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ 3208 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ 3209 3210 #define ADC_SMPR1_SMP11_Pos (3U) 3211 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ 3212 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 3213 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ 3214 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ 3215 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ 3216 3217 #define ADC_SMPR1_SMP12_Pos (6U) 3218 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ 3219 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 3220 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ 3221 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ 3222 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ 3223 3224 #define ADC_SMPR1_SMP13_Pos (9U) 3225 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ 3226 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 3227 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ 3228 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ 3229 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ 3230 3231 #define ADC_SMPR1_SMP14_Pos (12U) 3232 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ 3233 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 3234 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ 3235 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ 3236 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ 3237 3238 #define ADC_SMPR1_SMP15_Pos (15U) 3239 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ 3240 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 3241 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ 3242 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ 3243 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ 3244 3245 #define ADC_SMPR1_SMP16_Pos (18U) 3246 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ 3247 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 3248 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ 3249 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ 3250 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ 3251 3252 #define ADC_SMPR1_SMP17_Pos (21U) 3253 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ 3254 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 3255 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ 3256 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ 3257 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ 3258 3259 /****************** Bit definition for ADC_SMPR2 register *******************/ 3260 #define ADC_SMPR2_SMP0_Pos (0U) 3261 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ 3262 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 3263 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ 3264 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ 3265 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ 3266 3267 #define ADC_SMPR2_SMP1_Pos (3U) 3268 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ 3269 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 3270 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ 3271 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ 3272 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ 3273 3274 #define ADC_SMPR2_SMP2_Pos (6U) 3275 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ 3276 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 3277 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ 3278 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ 3279 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ 3280 3281 #define ADC_SMPR2_SMP3_Pos (9U) 3282 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ 3283 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 3284 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ 3285 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ 3286 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ 3287 3288 #define ADC_SMPR2_SMP4_Pos (12U) 3289 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ 3290 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 3291 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ 3292 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ 3293 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ 3294 3295 #define ADC_SMPR2_SMP5_Pos (15U) 3296 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ 3297 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 3298 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ 3299 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ 3300 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ 3301 3302 #define ADC_SMPR2_SMP6_Pos (18U) 3303 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ 3304 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 3305 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ 3306 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ 3307 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ 3308 3309 #define ADC_SMPR2_SMP7_Pos (21U) 3310 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ 3311 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 3312 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ 3313 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ 3314 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ 3315 3316 #define ADC_SMPR2_SMP8_Pos (24U) 3317 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ 3318 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 3319 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ 3320 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ 3321 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ 3322 3323 #define ADC_SMPR2_SMP9_Pos (27U) 3324 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ 3325 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 3326 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ 3327 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ 3328 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ 3329 3330 /****************** Bit definition for ADC_JOFR1 register *******************/ 3331 #define ADC_JOFR1_JOFFSET1_Pos (0U) 3332 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 3333 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 3334 3335 /****************** Bit definition for ADC_JOFR2 register *******************/ 3336 #define ADC_JOFR2_JOFFSET2_Pos (0U) 3337 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 3338 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 3339 3340 /****************** Bit definition for ADC_JOFR3 register *******************/ 3341 #define ADC_JOFR3_JOFFSET3_Pos (0U) 3342 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 3343 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 3344 3345 /****************** Bit definition for ADC_JOFR4 register *******************/ 3346 #define ADC_JOFR4_JOFFSET4_Pos (0U) 3347 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 3348 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 3349 3350 /******************* Bit definition for ADC_HTR register ********************/ 3351 #define ADC_HTR_HT_Pos (0U) 3352 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 3353 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 3354 3355 /******************* Bit definition for ADC_LTR register ********************/ 3356 #define ADC_LTR_LT_Pos (0U) 3357 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 3358 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 3359 3360 /******************* Bit definition for ADC_SQR1 register *******************/ 3361 #define ADC_SQR1_SQ13_Pos (0U) 3362 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ 3363 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 3364 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ 3365 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ 3366 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ 3367 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ 3368 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ 3369 3370 #define ADC_SQR1_SQ14_Pos (5U) 3371 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ 3372 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 3373 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ 3374 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ 3375 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ 3376 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ 3377 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ 3378 3379 #define ADC_SQR1_SQ15_Pos (10U) 3380 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ 3381 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 3382 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ 3383 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ 3384 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ 3385 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ 3386 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ 3387 3388 #define ADC_SQR1_SQ16_Pos (15U) 3389 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ 3390 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 3391 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ 3392 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ 3393 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ 3394 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ 3395 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ 3396 3397 #define ADC_SQR1_L_Pos (20U) 3398 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ 3399 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 3400 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 3401 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 3402 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 3403 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 3404 3405 /******************* Bit definition for ADC_SQR2 register *******************/ 3406 #define ADC_SQR2_SQ7_Pos (0U) 3407 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ 3408 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 3409 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ 3410 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ 3411 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ 3412 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ 3413 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ 3414 3415 #define ADC_SQR2_SQ8_Pos (5U) 3416 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ 3417 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 3418 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ 3419 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ 3420 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ 3421 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ 3422 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ 3423 3424 #define ADC_SQR2_SQ9_Pos (10U) 3425 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ 3426 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 3427 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ 3428 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ 3429 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ 3430 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ 3431 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ 3432 3433 #define ADC_SQR2_SQ10_Pos (15U) 3434 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ 3435 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 3436 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ 3437 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ 3438 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ 3439 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ 3440 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ 3441 3442 #define ADC_SQR2_SQ11_Pos (20U) 3443 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ 3444 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ 3445 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ 3446 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ 3447 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ 3448 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ 3449 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ 3450 3451 #define ADC_SQR2_SQ12_Pos (25U) 3452 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ 3453 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 3454 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ 3455 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ 3456 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ 3457 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ 3458 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ 3459 3460 /******************* Bit definition for ADC_SQR3 register *******************/ 3461 #define ADC_SQR3_SQ1_Pos (0U) 3462 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ 3463 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 3464 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ 3465 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ 3466 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ 3467 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ 3468 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ 3469 3470 #define ADC_SQR3_SQ2_Pos (5U) 3471 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ 3472 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 3473 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ 3474 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ 3475 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ 3476 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ 3477 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ 3478 3479 #define ADC_SQR3_SQ3_Pos (10U) 3480 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ 3481 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 3482 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ 3483 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ 3484 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ 3485 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ 3486 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ 3487 3488 #define ADC_SQR3_SQ4_Pos (15U) 3489 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ 3490 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 3491 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ 3492 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ 3493 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ 3494 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ 3495 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ 3496 3497 #define ADC_SQR3_SQ5_Pos (20U) 3498 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ 3499 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 3500 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ 3501 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ 3502 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ 3503 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ 3504 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ 3505 3506 #define ADC_SQR3_SQ6_Pos (25U) 3507 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ 3508 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 3509 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ 3510 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ 3511 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ 3512 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ 3513 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ 3514 3515 /******************* Bit definition for ADC_JSQR register *******************/ 3516 #define ADC_JSQR_JSQ1_Pos (0U) 3517 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 3518 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 3519 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 3520 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 3521 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 3522 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 3523 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 3524 3525 #define ADC_JSQR_JSQ2_Pos (5U) 3526 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 3527 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 3528 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 3529 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 3530 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 3531 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 3532 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 3533 3534 #define ADC_JSQR_JSQ3_Pos (10U) 3535 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 3536 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 3537 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 3538 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 3539 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 3540 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 3541 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 3542 3543 #define ADC_JSQR_JSQ4_Pos (15U) 3544 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 3545 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 3546 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 3547 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 3548 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 3549 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 3550 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 3551 3552 #define ADC_JSQR_JL_Pos (20U) 3553 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 3554 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 3555 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 3556 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 3557 3558 /******************* Bit definition for ADC_JDR1 register *******************/ 3559 #define ADC_JDR1_JDATA_Pos (0U) 3560 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 3561 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 3562 3563 /******************* Bit definition for ADC_JDR2 register *******************/ 3564 #define ADC_JDR2_JDATA_Pos (0U) 3565 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 3566 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 3567 3568 /******************* Bit definition for ADC_JDR3 register *******************/ 3569 #define ADC_JDR3_JDATA_Pos (0U) 3570 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 3571 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 3572 3573 /******************* Bit definition for ADC_JDR4 register *******************/ 3574 #define ADC_JDR4_JDATA_Pos (0U) 3575 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 3576 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 3577 3578 /******************** Bit definition for ADC_DR register ********************/ 3579 #define ADC_DR_DATA_Pos (0U) 3580 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 3581 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 3582 3583 3584 /*****************************************************************************/ 3585 /* */ 3586 /* Timers (TIM) */ 3587 /* */ 3588 /*****************************************************************************/ 3589 /******************* Bit definition for TIM_CR1 register *******************/ 3590 #define TIM_CR1_CEN_Pos (0U) 3591 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 3592 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 3593 #define TIM_CR1_UDIS_Pos (1U) 3594 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 3595 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 3596 #define TIM_CR1_URS_Pos (2U) 3597 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 3598 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 3599 #define TIM_CR1_OPM_Pos (3U) 3600 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 3601 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 3602 #define TIM_CR1_DIR_Pos (4U) 3603 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 3604 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 3605 3606 #define TIM_CR1_CMS_Pos (5U) 3607 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 3608 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 3609 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 3610 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 3611 3612 #define TIM_CR1_ARPE_Pos (7U) 3613 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 3614 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 3615 3616 #define TIM_CR1_CKD_Pos (8U) 3617 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 3618 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 3619 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 3620 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 3621 3622 /******************* Bit definition for TIM_CR2 register *******************/ 3623 #define TIM_CR2_CCPC_Pos (0U) 3624 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 3625 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 3626 #define TIM_CR2_CCUS_Pos (2U) 3627 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 3628 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 3629 #define TIM_CR2_CCDS_Pos (3U) 3630 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 3631 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 3632 3633 #define TIM_CR2_MMS_Pos (4U) 3634 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 3635 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 3636 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 3637 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 3638 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 3639 3640 #define TIM_CR2_TI1S_Pos (7U) 3641 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 3642 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 3643 #define TIM_CR2_OIS1_Pos (8U) 3644 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 3645 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 3646 #define TIM_CR2_OIS1N_Pos (9U) 3647 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 3648 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 3649 #define TIM_CR2_OIS2_Pos (10U) 3650 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 3651 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 3652 #define TIM_CR2_OIS2N_Pos (11U) 3653 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 3654 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 3655 #define TIM_CR2_OIS3_Pos (12U) 3656 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 3657 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 3658 #define TIM_CR2_OIS3N_Pos (13U) 3659 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 3660 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 3661 #define TIM_CR2_OIS4_Pos (14U) 3662 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 3663 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 3664 3665 /******************* Bit definition for TIM_SMCR register ******************/ 3666 #define TIM_SMCR_SMS_Pos (0U) 3667 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 3668 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 3669 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 3670 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 3671 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 3672 3673 #define TIM_SMCR_TS_Pos (4U) 3674 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 3675 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 3676 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 3677 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 3678 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 3679 3680 #define TIM_SMCR_MSM_Pos (7U) 3681 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 3682 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 3683 3684 #define TIM_SMCR_ETF_Pos (8U) 3685 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 3686 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 3687 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 3688 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 3689 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 3690 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 3691 3692 #define TIM_SMCR_ETPS_Pos (12U) 3693 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 3694 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 3695 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 3696 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 3697 3698 #define TIM_SMCR_ECE_Pos (14U) 3699 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 3700 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 3701 #define TIM_SMCR_ETP_Pos (15U) 3702 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 3703 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 3704 3705 /******************* Bit definition for TIM_DIER register ******************/ 3706 #define TIM_DIER_UIE_Pos (0U) 3707 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 3708 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 3709 #define TIM_DIER_CC1IE_Pos (1U) 3710 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 3711 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 3712 #define TIM_DIER_CC2IE_Pos (2U) 3713 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 3714 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 3715 #define TIM_DIER_CC3IE_Pos (3U) 3716 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 3717 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 3718 #define TIM_DIER_CC4IE_Pos (4U) 3719 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 3720 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 3721 #define TIM_DIER_COMIE_Pos (5U) 3722 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 3723 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 3724 #define TIM_DIER_TIE_Pos (6U) 3725 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 3726 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 3727 #define TIM_DIER_BIE_Pos (7U) 3728 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 3729 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 3730 #define TIM_DIER_UDE_Pos (8U) 3731 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 3732 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 3733 #define TIM_DIER_CC1DE_Pos (9U) 3734 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 3735 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 3736 #define TIM_DIER_CC2DE_Pos (10U) 3737 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 3738 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 3739 #define TIM_DIER_CC3DE_Pos (11U) 3740 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 3741 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 3742 #define TIM_DIER_CC4DE_Pos (12U) 3743 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 3744 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 3745 #define TIM_DIER_COMDE_Pos (13U) 3746 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 3747 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 3748 #define TIM_DIER_TDE_Pos (14U) 3749 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 3750 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 3751 3752 /******************** Bit definition for TIM_SR register *******************/ 3753 #define TIM_SR_UIF_Pos (0U) 3754 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 3755 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 3756 #define TIM_SR_CC1IF_Pos (1U) 3757 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 3758 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 3759 #define TIM_SR_CC2IF_Pos (2U) 3760 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 3761 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 3762 #define TIM_SR_CC3IF_Pos (3U) 3763 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 3764 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 3765 #define TIM_SR_CC4IF_Pos (4U) 3766 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 3767 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 3768 #define TIM_SR_COMIF_Pos (5U) 3769 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 3770 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 3771 #define TIM_SR_TIF_Pos (6U) 3772 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 3773 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 3774 #define TIM_SR_BIF_Pos (7U) 3775 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 3776 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 3777 #define TIM_SR_CC1OF_Pos (9U) 3778 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 3779 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 3780 #define TIM_SR_CC2OF_Pos (10U) 3781 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 3782 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 3783 #define TIM_SR_CC3OF_Pos (11U) 3784 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 3785 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 3786 #define TIM_SR_CC4OF_Pos (12U) 3787 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 3788 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 3789 3790 /******************* Bit definition for TIM_EGR register *******************/ 3791 #define TIM_EGR_UG_Pos (0U) 3792 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 3793 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 3794 #define TIM_EGR_CC1G_Pos (1U) 3795 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 3796 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 3797 #define TIM_EGR_CC2G_Pos (2U) 3798 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 3799 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 3800 #define TIM_EGR_CC3G_Pos (3U) 3801 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 3802 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 3803 #define TIM_EGR_CC4G_Pos (4U) 3804 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 3805 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 3806 #define TIM_EGR_COMG_Pos (5U) 3807 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 3808 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 3809 #define TIM_EGR_TG_Pos (6U) 3810 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 3811 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 3812 #define TIM_EGR_BG_Pos (7U) 3813 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 3814 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 3815 3816 /****************** Bit definition for TIM_CCMR1 register ******************/ 3817 #define TIM_CCMR1_CC1S_Pos (0U) 3818 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 3819 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 3820 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 3821 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 3822 3823 #define TIM_CCMR1_OC1FE_Pos (2U) 3824 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 3825 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 3826 #define TIM_CCMR1_OC1PE_Pos (3U) 3827 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 3828 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 3829 3830 #define TIM_CCMR1_OC1M_Pos (4U) 3831 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 3832 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 3833 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 3834 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 3835 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 3836 3837 #define TIM_CCMR1_OC1CE_Pos (7U) 3838 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 3839 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 3840 3841 #define TIM_CCMR1_CC2S_Pos (8U) 3842 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 3843 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 3844 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 3845 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 3846 3847 #define TIM_CCMR1_OC2FE_Pos (10U) 3848 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 3849 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 3850 #define TIM_CCMR1_OC2PE_Pos (11U) 3851 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 3852 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 3853 3854 #define TIM_CCMR1_OC2M_Pos (12U) 3855 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 3856 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 3857 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 3858 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 3859 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 3860 3861 #define TIM_CCMR1_OC2CE_Pos (15U) 3862 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 3863 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 3864 3865 /*---------------------------------------------------------------------------*/ 3866 3867 #define TIM_CCMR1_IC1PSC_Pos (2U) 3868 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 3869 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 3870 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 3871 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 3872 3873 #define TIM_CCMR1_IC1F_Pos (4U) 3874 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 3875 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 3876 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 3877 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 3878 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 3879 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 3880 3881 #define TIM_CCMR1_IC2PSC_Pos (10U) 3882 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 3883 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 3884 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 3885 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 3886 3887 #define TIM_CCMR1_IC2F_Pos (12U) 3888 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 3889 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 3890 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 3891 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 3892 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 3893 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 3894 3895 /****************** Bit definition for TIM_CCMR2 register ******************/ 3896 #define TIM_CCMR2_CC3S_Pos (0U) 3897 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 3898 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 3899 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 3900 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 3901 3902 #define TIM_CCMR2_OC3FE_Pos (2U) 3903 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 3904 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 3905 #define TIM_CCMR2_OC3PE_Pos (3U) 3906 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 3907 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 3908 3909 #define TIM_CCMR2_OC3M_Pos (4U) 3910 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 3911 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 3912 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 3913 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 3914 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 3915 3916 #define TIM_CCMR2_OC3CE_Pos (7U) 3917 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 3918 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 3919 3920 #define TIM_CCMR2_CC4S_Pos (8U) 3921 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 3922 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 3923 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 3924 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 3925 3926 #define TIM_CCMR2_OC4FE_Pos (10U) 3927 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 3928 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 3929 #define TIM_CCMR2_OC4PE_Pos (11U) 3930 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 3931 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 3932 3933 #define TIM_CCMR2_OC4M_Pos (12U) 3934 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 3935 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 3936 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 3937 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 3938 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 3939 3940 #define TIM_CCMR2_OC4CE_Pos (15U) 3941 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 3942 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 3943 3944 /*---------------------------------------------------------------------------*/ 3945 3946 #define TIM_CCMR2_IC3PSC_Pos (2U) 3947 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 3948 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 3949 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 3950 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 3951 3952 #define TIM_CCMR2_IC3F_Pos (4U) 3953 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 3954 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 3955 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 3956 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 3957 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 3958 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 3959 3960 #define TIM_CCMR2_IC4PSC_Pos (10U) 3961 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 3962 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 3963 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 3964 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 3965 3966 #define TIM_CCMR2_IC4F_Pos (12U) 3967 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 3968 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 3969 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 3970 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 3971 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 3972 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 3973 3974 /******************* Bit definition for TIM_CCER register ******************/ 3975 #define TIM_CCER_CC1E_Pos (0U) 3976 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 3977 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 3978 #define TIM_CCER_CC1P_Pos (1U) 3979 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 3980 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 3981 #define TIM_CCER_CC1NE_Pos (2U) 3982 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 3983 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 3984 #define TIM_CCER_CC1NP_Pos (3U) 3985 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 3986 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 3987 #define TIM_CCER_CC2E_Pos (4U) 3988 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 3989 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 3990 #define TIM_CCER_CC2P_Pos (5U) 3991 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 3992 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 3993 #define TIM_CCER_CC2NE_Pos (6U) 3994 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 3995 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 3996 #define TIM_CCER_CC2NP_Pos (7U) 3997 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 3998 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 3999 #define TIM_CCER_CC3E_Pos (8U) 4000 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 4001 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 4002 #define TIM_CCER_CC3P_Pos (9U) 4003 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 4004 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 4005 #define TIM_CCER_CC3NE_Pos (10U) 4006 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 4007 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 4008 #define TIM_CCER_CC3NP_Pos (11U) 4009 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 4010 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 4011 #define TIM_CCER_CC4E_Pos (12U) 4012 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 4013 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 4014 #define TIM_CCER_CC4P_Pos (13U) 4015 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 4016 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 4017 4018 /******************* Bit definition for TIM_CNT register *******************/ 4019 #define TIM_CNT_CNT_Pos (0U) 4020 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 4021 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 4022 4023 /******************* Bit definition for TIM_PSC register *******************/ 4024 #define TIM_PSC_PSC_Pos (0U) 4025 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 4026 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 4027 4028 /******************* Bit definition for TIM_ARR register *******************/ 4029 #define TIM_ARR_ARR_Pos (0U) 4030 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 4031 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 4032 4033 /******************* Bit definition for TIM_RCR register *******************/ 4034 #define TIM_RCR_REP_Pos (0U) 4035 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 4036 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 4037 4038 /******************* Bit definition for TIM_CCR1 register ******************/ 4039 #define TIM_CCR1_CCR1_Pos (0U) 4040 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 4041 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 4042 4043 /******************* Bit definition for TIM_CCR2 register ******************/ 4044 #define TIM_CCR2_CCR2_Pos (0U) 4045 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 4046 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 4047 4048 /******************* Bit definition for TIM_CCR3 register ******************/ 4049 #define TIM_CCR3_CCR3_Pos (0U) 4050 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 4051 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 4052 4053 /******************* Bit definition for TIM_CCR4 register ******************/ 4054 #define TIM_CCR4_CCR4_Pos (0U) 4055 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 4056 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 4057 4058 /******************* Bit definition for TIM_BDTR register ******************/ 4059 #define TIM_BDTR_DTG_Pos (0U) 4060 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 4061 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 4062 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 4063 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 4064 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 4065 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 4066 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 4067 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 4068 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 4069 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 4070 4071 #define TIM_BDTR_LOCK_Pos (8U) 4072 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 4073 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 4074 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 4075 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 4076 4077 #define TIM_BDTR_OSSI_Pos (10U) 4078 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 4079 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 4080 #define TIM_BDTR_OSSR_Pos (11U) 4081 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 4082 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 4083 #define TIM_BDTR_BKE_Pos (12U) 4084 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 4085 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 4086 #define TIM_BDTR_BKP_Pos (13U) 4087 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 4088 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 4089 #define TIM_BDTR_AOE_Pos (14U) 4090 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 4091 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 4092 #define TIM_BDTR_MOE_Pos (15U) 4093 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 4094 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 4095 4096 /******************* Bit definition for TIM_DCR register *******************/ 4097 #define TIM_DCR_DBA_Pos (0U) 4098 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 4099 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 4100 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 4101 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 4102 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 4103 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 4104 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 4105 4106 #define TIM_DCR_DBL_Pos (8U) 4107 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 4108 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 4109 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 4110 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 4111 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 4112 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 4113 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 4114 4115 /******************* Bit definition for TIM_DMAR register ******************/ 4116 #define TIM_DMAR_DMAB_Pos (0U) 4117 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 4118 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 4119 4120 /******************************************************************************/ 4121 /* */ 4122 /* Real-Time Clock */ 4123 /* */ 4124 /******************************************************************************/ 4125 4126 /******************* Bit definition for RTC_CRH register ********************/ 4127 #define RTC_CRH_SECIE_Pos (0U) 4128 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ 4129 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ 4130 #define RTC_CRH_ALRIE_Pos (1U) 4131 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ 4132 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ 4133 #define RTC_CRH_OWIE_Pos (2U) 4134 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ 4135 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ 4136 4137 /******************* Bit definition for RTC_CRL register ********************/ 4138 #define RTC_CRL_SECF_Pos (0U) 4139 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ 4140 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ 4141 #define RTC_CRL_ALRF_Pos (1U) 4142 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ 4143 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ 4144 #define RTC_CRL_OWF_Pos (2U) 4145 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ 4146 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ 4147 #define RTC_CRL_RSF_Pos (3U) 4148 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ 4149 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ 4150 #define RTC_CRL_CNF_Pos (4U) 4151 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ 4152 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ 4153 #define RTC_CRL_RTOFF_Pos (5U) 4154 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ 4155 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ 4156 4157 /******************* Bit definition for RTC_PRLH register *******************/ 4158 #define RTC_PRLH_PRL_Pos (0U) 4159 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ 4160 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ 4161 4162 /******************* Bit definition for RTC_PRLL register *******************/ 4163 #define RTC_PRLL_PRL_Pos (0U) 4164 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ 4165 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ 4166 4167 /******************* Bit definition for RTC_DIVH register *******************/ 4168 #define RTC_DIVH_RTC_DIV_Pos (0U) 4169 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ 4170 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ 4171 4172 /******************* Bit definition for RTC_DIVL register *******************/ 4173 #define RTC_DIVL_RTC_DIV_Pos (0U) 4174 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ 4175 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ 4176 4177 /******************* Bit definition for RTC_CNTH register *******************/ 4178 #define RTC_CNTH_RTC_CNT_Pos (0U) 4179 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4180 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ 4181 4182 /******************* Bit definition for RTC_CNTL register *******************/ 4183 #define RTC_CNTL_RTC_CNT_Pos (0U) 4184 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4185 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ 4186 4187 /******************* Bit definition for RTC_ALRH register *******************/ 4188 #define RTC_ALRH_RTC_ALR_Pos (0U) 4189 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ 4190 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ 4191 4192 /******************* Bit definition for RTC_ALRL register *******************/ 4193 #define RTC_ALRL_RTC_ALR_Pos (0U) 4194 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ 4195 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ 4196 4197 /******************************************************************************/ 4198 /* */ 4199 /* Independent WATCHDOG (IWDG) */ 4200 /* */ 4201 /******************************************************************************/ 4202 4203 /******************* Bit definition for IWDG_KR register ********************/ 4204 #define IWDG_KR_KEY_Pos (0U) 4205 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 4206 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 4207 4208 /******************* Bit definition for IWDG_PR register ********************/ 4209 #define IWDG_PR_PR_Pos (0U) 4210 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 4211 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 4212 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 4213 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 4214 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 4215 4216 /******************* Bit definition for IWDG_RLR register *******************/ 4217 #define IWDG_RLR_RL_Pos (0U) 4218 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 4219 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 4220 4221 /******************* Bit definition for IWDG_SR register ********************/ 4222 #define IWDG_SR_PVU_Pos (0U) 4223 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 4224 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 4225 #define IWDG_SR_RVU_Pos (1U) 4226 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 4227 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 4228 4229 /******************************************************************************/ 4230 /* */ 4231 /* Window WATCHDOG (WWDG) */ 4232 /* */ 4233 /******************************************************************************/ 4234 4235 /******************* Bit definition for WWDG_CR register ********************/ 4236 #define WWDG_CR_T_Pos (0U) 4237 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 4238 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 4239 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 4240 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 4241 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 4242 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 4243 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 4244 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 4245 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 4246 4247 /* Legacy defines */ 4248 #define WWDG_CR_T0 WWDG_CR_T_0 4249 #define WWDG_CR_T1 WWDG_CR_T_1 4250 #define WWDG_CR_T2 WWDG_CR_T_2 4251 #define WWDG_CR_T3 WWDG_CR_T_3 4252 #define WWDG_CR_T4 WWDG_CR_T_4 4253 #define WWDG_CR_T5 WWDG_CR_T_5 4254 #define WWDG_CR_T6 WWDG_CR_T_6 4255 4256 #define WWDG_CR_WDGA_Pos (7U) 4257 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 4258 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 4259 4260 /******************* Bit definition for WWDG_CFR register *******************/ 4261 #define WWDG_CFR_W_Pos (0U) 4262 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 4263 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 4264 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 4265 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 4266 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 4267 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 4268 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 4269 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 4270 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 4271 4272 /* Legacy defines */ 4273 #define WWDG_CFR_W0 WWDG_CFR_W_0 4274 #define WWDG_CFR_W1 WWDG_CFR_W_1 4275 #define WWDG_CFR_W2 WWDG_CFR_W_2 4276 #define WWDG_CFR_W3 WWDG_CFR_W_3 4277 #define WWDG_CFR_W4 WWDG_CFR_W_4 4278 #define WWDG_CFR_W5 WWDG_CFR_W_5 4279 #define WWDG_CFR_W6 WWDG_CFR_W_6 4280 4281 #define WWDG_CFR_WDGTB_Pos (7U) 4282 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 4283 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 4284 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 4285 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 4286 4287 /* Legacy defines */ 4288 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 4289 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 4290 4291 #define WWDG_CFR_EWI_Pos (9U) 4292 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 4293 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 4294 4295 /******************* Bit definition for WWDG_SR register ********************/ 4296 #define WWDG_SR_EWIF_Pos (0U) 4297 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 4298 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 4299 4300 4301 4302 /******************************************************************************/ 4303 /* */ 4304 /* Serial Peripheral Interface */ 4305 /* */ 4306 /******************************************************************************/ 4307 4308 /******************* Bit definition for SPI_CR1 register ********************/ 4309 #define SPI_CR1_CPHA_Pos (0U) 4310 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4311 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4312 #define SPI_CR1_CPOL_Pos (1U) 4313 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4314 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4315 #define SPI_CR1_MSTR_Pos (2U) 4316 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4317 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4318 4319 #define SPI_CR1_BR_Pos (3U) 4320 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4321 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4322 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4323 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4324 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4325 4326 #define SPI_CR1_SPE_Pos (6U) 4327 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4328 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4329 #define SPI_CR1_LSBFIRST_Pos (7U) 4330 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4331 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4332 #define SPI_CR1_SSI_Pos (8U) 4333 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4334 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4335 #define SPI_CR1_SSM_Pos (9U) 4336 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4337 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4338 #define SPI_CR1_RXONLY_Pos (10U) 4339 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4340 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4341 #define SPI_CR1_DFF_Pos (11U) 4342 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 4343 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 4344 #define SPI_CR1_CRCNEXT_Pos (12U) 4345 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4346 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4347 #define SPI_CR1_CRCEN_Pos (13U) 4348 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4349 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4350 #define SPI_CR1_BIDIOE_Pos (14U) 4351 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4352 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4353 #define SPI_CR1_BIDIMODE_Pos (15U) 4354 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4355 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4356 4357 /******************* Bit definition for SPI_CR2 register ********************/ 4358 #define SPI_CR2_RXDMAEN_Pos (0U) 4359 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4360 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4361 #define SPI_CR2_TXDMAEN_Pos (1U) 4362 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4363 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4364 #define SPI_CR2_SSOE_Pos (2U) 4365 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4366 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4367 #define SPI_CR2_ERRIE_Pos (5U) 4368 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4369 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4370 #define SPI_CR2_RXNEIE_Pos (6U) 4371 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4372 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4373 #define SPI_CR2_TXEIE_Pos (7U) 4374 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4375 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4376 4377 /******************** Bit definition for SPI_SR register ********************/ 4378 #define SPI_SR_RXNE_Pos (0U) 4379 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4380 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4381 #define SPI_SR_TXE_Pos (1U) 4382 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4383 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4384 #define SPI_SR_CHSIDE_Pos (2U) 4385 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4386 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4387 #define SPI_SR_UDR_Pos (3U) 4388 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4389 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 4390 #define SPI_SR_CRCERR_Pos (4U) 4391 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4392 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4393 #define SPI_SR_MODF_Pos (5U) 4394 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4395 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4396 #define SPI_SR_OVR_Pos (6U) 4397 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4398 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 4399 #define SPI_SR_BSY_Pos (7U) 4400 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 4401 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 4402 4403 /******************** Bit definition for SPI_DR register ********************/ 4404 #define SPI_DR_DR_Pos (0U) 4405 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 4406 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 4407 4408 /******************* Bit definition for SPI_CRCPR register ******************/ 4409 #define SPI_CRCPR_CRCPOLY_Pos (0U) 4410 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 4411 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 4412 4413 /****************** Bit definition for SPI_RXCRCR register ******************/ 4414 #define SPI_RXCRCR_RXCRC_Pos (0U) 4415 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 4416 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 4417 4418 /****************** Bit definition for SPI_TXCRCR register ******************/ 4419 #define SPI_TXCRCR_TXCRC_Pos (0U) 4420 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 4421 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 4422 4423 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 4424 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 4425 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ 4426 4427 /******************************************************************************/ 4428 /* */ 4429 /* Inter-integrated Circuit Interface */ 4430 /* */ 4431 /******************************************************************************/ 4432 4433 /******************* Bit definition for I2C_CR1 register ********************/ 4434 #define I2C_CR1_PE_Pos (0U) 4435 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 4436 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 4437 #define I2C_CR1_SMBUS_Pos (1U) 4438 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 4439 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 4440 #define I2C_CR1_SMBTYPE_Pos (3U) 4441 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 4442 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 4443 #define I2C_CR1_ENARP_Pos (4U) 4444 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 4445 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 4446 #define I2C_CR1_ENPEC_Pos (5U) 4447 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 4448 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 4449 #define I2C_CR1_ENGC_Pos (6U) 4450 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 4451 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 4452 #define I2C_CR1_NOSTRETCH_Pos (7U) 4453 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 4454 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 4455 #define I2C_CR1_START_Pos (8U) 4456 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 4457 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 4458 #define I2C_CR1_STOP_Pos (9U) 4459 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 4460 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 4461 #define I2C_CR1_ACK_Pos (10U) 4462 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 4463 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 4464 #define I2C_CR1_POS_Pos (11U) 4465 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 4466 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 4467 #define I2C_CR1_PEC_Pos (12U) 4468 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 4469 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 4470 #define I2C_CR1_ALERT_Pos (13U) 4471 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 4472 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 4473 #define I2C_CR1_SWRST_Pos (15U) 4474 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 4475 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 4476 4477 /******************* Bit definition for I2C_CR2 register ********************/ 4478 #define I2C_CR2_FREQ_Pos (0U) 4479 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 4480 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 4481 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 4482 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 4483 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 4484 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 4485 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 4486 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 4487 4488 #define I2C_CR2_ITERREN_Pos (8U) 4489 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 4490 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 4491 #define I2C_CR2_ITEVTEN_Pos (9U) 4492 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 4493 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 4494 #define I2C_CR2_ITBUFEN_Pos (10U) 4495 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 4496 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 4497 #define I2C_CR2_DMAEN_Pos (11U) 4498 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 4499 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 4500 #define I2C_CR2_LAST_Pos (12U) 4501 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 4502 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 4503 4504 /******************* Bit definition for I2C_OAR1 register *******************/ 4505 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ 4506 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ 4507 4508 #define I2C_OAR1_ADD0_Pos (0U) 4509 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 4510 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 4511 #define I2C_OAR1_ADD1_Pos (1U) 4512 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 4513 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 4514 #define I2C_OAR1_ADD2_Pos (2U) 4515 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 4516 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 4517 #define I2C_OAR1_ADD3_Pos (3U) 4518 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 4519 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 4520 #define I2C_OAR1_ADD4_Pos (4U) 4521 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 4522 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 4523 #define I2C_OAR1_ADD5_Pos (5U) 4524 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 4525 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 4526 #define I2C_OAR1_ADD6_Pos (6U) 4527 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 4528 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 4529 #define I2C_OAR1_ADD7_Pos (7U) 4530 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 4531 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 4532 #define I2C_OAR1_ADD8_Pos (8U) 4533 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 4534 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 4535 #define I2C_OAR1_ADD9_Pos (9U) 4536 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 4537 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 4538 4539 #define I2C_OAR1_ADDMODE_Pos (15U) 4540 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 4541 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 4542 4543 /******************* Bit definition for I2C_OAR2 register *******************/ 4544 #define I2C_OAR2_ENDUAL_Pos (0U) 4545 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 4546 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 4547 #define I2C_OAR2_ADD2_Pos (1U) 4548 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 4549 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 4550 4551 /******************** Bit definition for I2C_DR register ********************/ 4552 #define I2C_DR_DR_Pos (0U) 4553 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 4554 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 4555 4556 /******************* Bit definition for I2C_SR1 register ********************/ 4557 #define I2C_SR1_SB_Pos (0U) 4558 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 4559 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 4560 #define I2C_SR1_ADDR_Pos (1U) 4561 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 4562 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 4563 #define I2C_SR1_BTF_Pos (2U) 4564 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 4565 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 4566 #define I2C_SR1_ADD10_Pos (3U) 4567 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 4568 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 4569 #define I2C_SR1_STOPF_Pos (4U) 4570 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 4571 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 4572 #define I2C_SR1_RXNE_Pos (6U) 4573 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 4574 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 4575 #define I2C_SR1_TXE_Pos (7U) 4576 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 4577 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 4578 #define I2C_SR1_BERR_Pos (8U) 4579 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 4580 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 4581 #define I2C_SR1_ARLO_Pos (9U) 4582 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 4583 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 4584 #define I2C_SR1_AF_Pos (10U) 4585 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 4586 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 4587 #define I2C_SR1_OVR_Pos (11U) 4588 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 4589 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 4590 #define I2C_SR1_PECERR_Pos (12U) 4591 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 4592 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 4593 #define I2C_SR1_TIMEOUT_Pos (14U) 4594 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 4595 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 4596 #define I2C_SR1_SMBALERT_Pos (15U) 4597 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 4598 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 4599 4600 /******************* Bit definition for I2C_SR2 register ********************/ 4601 #define I2C_SR2_MSL_Pos (0U) 4602 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 4603 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 4604 #define I2C_SR2_BUSY_Pos (1U) 4605 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 4606 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 4607 #define I2C_SR2_TRA_Pos (2U) 4608 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 4609 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 4610 #define I2C_SR2_GENCALL_Pos (4U) 4611 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 4612 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 4613 #define I2C_SR2_SMBDEFAULT_Pos (5U) 4614 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 4615 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 4616 #define I2C_SR2_SMBHOST_Pos (6U) 4617 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 4618 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 4619 #define I2C_SR2_DUALF_Pos (7U) 4620 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 4621 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 4622 #define I2C_SR2_PEC_Pos (8U) 4623 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 4624 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 4625 4626 /******************* Bit definition for I2C_CCR register ********************/ 4627 #define I2C_CCR_CCR_Pos (0U) 4628 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 4629 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 4630 #define I2C_CCR_DUTY_Pos (14U) 4631 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 4632 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 4633 #define I2C_CCR_FS_Pos (15U) 4634 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 4635 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 4636 4637 /****************** Bit definition for I2C_TRISE register *******************/ 4638 #define I2C_TRISE_TRISE_Pos (0U) 4639 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 4640 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 4641 4642 /******************************************************************************/ 4643 /* */ 4644 /* Universal Synchronous Asynchronous Receiver Transmitter */ 4645 /* */ 4646 /******************************************************************************/ 4647 4648 /******************* Bit definition for USART_SR register *******************/ 4649 #define USART_SR_PE_Pos (0U) 4650 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 4651 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 4652 #define USART_SR_FE_Pos (1U) 4653 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 4654 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 4655 #define USART_SR_NE_Pos (2U) 4656 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 4657 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 4658 #define USART_SR_ORE_Pos (3U) 4659 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 4660 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 4661 #define USART_SR_IDLE_Pos (4U) 4662 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 4663 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 4664 #define USART_SR_RXNE_Pos (5U) 4665 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 4666 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 4667 #define USART_SR_TC_Pos (6U) 4668 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 4669 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 4670 #define USART_SR_TXE_Pos (7U) 4671 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 4672 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 4673 #define USART_SR_LBD_Pos (8U) 4674 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 4675 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 4676 #define USART_SR_CTS_Pos (9U) 4677 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 4678 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 4679 4680 /******************* Bit definition for USART_DR register *******************/ 4681 #define USART_DR_DR_Pos (0U) 4682 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 4683 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 4684 4685 /****************** Bit definition for USART_BRR register *******************/ 4686 #define USART_BRR_DIV_Fraction_Pos (0U) 4687 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 4688 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ 4689 #define USART_BRR_DIV_Mantissa_Pos (4U) 4690 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 4691 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ 4692 4693 /****************** Bit definition for USART_CR1 register *******************/ 4694 #define USART_CR1_SBK_Pos (0U) 4695 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 4696 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 4697 #define USART_CR1_RWU_Pos (1U) 4698 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 4699 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 4700 #define USART_CR1_RE_Pos (2U) 4701 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 4702 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 4703 #define USART_CR1_TE_Pos (3U) 4704 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 4705 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 4706 #define USART_CR1_IDLEIE_Pos (4U) 4707 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 4708 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 4709 #define USART_CR1_RXNEIE_Pos (5U) 4710 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 4711 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 4712 #define USART_CR1_TCIE_Pos (6U) 4713 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 4714 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 4715 #define USART_CR1_TXEIE_Pos (7U) 4716 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 4717 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 4718 #define USART_CR1_PEIE_Pos (8U) 4719 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 4720 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 4721 #define USART_CR1_PS_Pos (9U) 4722 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 4723 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 4724 #define USART_CR1_PCE_Pos (10U) 4725 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 4726 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 4727 #define USART_CR1_WAKE_Pos (11U) 4728 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 4729 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 4730 #define USART_CR1_M_Pos (12U) 4731 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 4732 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 4733 #define USART_CR1_UE_Pos (13U) 4734 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 4735 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 4736 4737 /****************** Bit definition for USART_CR2 register *******************/ 4738 #define USART_CR2_ADD_Pos (0U) 4739 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 4740 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 4741 #define USART_CR2_LBDL_Pos (5U) 4742 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 4743 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 4744 #define USART_CR2_LBDIE_Pos (6U) 4745 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 4746 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 4747 #define USART_CR2_LBCL_Pos (8U) 4748 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 4749 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 4750 #define USART_CR2_CPHA_Pos (9U) 4751 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 4752 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 4753 #define USART_CR2_CPOL_Pos (10U) 4754 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 4755 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 4756 #define USART_CR2_CLKEN_Pos (11U) 4757 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 4758 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 4759 4760 #define USART_CR2_STOP_Pos (12U) 4761 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 4762 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 4763 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 4764 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 4765 4766 #define USART_CR2_LINEN_Pos (14U) 4767 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 4768 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 4769 4770 /****************** Bit definition for USART_CR3 register *******************/ 4771 #define USART_CR3_EIE_Pos (0U) 4772 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 4773 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 4774 #define USART_CR3_IREN_Pos (1U) 4775 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 4776 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 4777 #define USART_CR3_IRLP_Pos (2U) 4778 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 4779 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 4780 #define USART_CR3_HDSEL_Pos (3U) 4781 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 4782 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 4783 #define USART_CR3_NACK_Pos (4U) 4784 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 4785 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 4786 #define USART_CR3_SCEN_Pos (5U) 4787 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 4788 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 4789 #define USART_CR3_DMAR_Pos (6U) 4790 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 4791 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 4792 #define USART_CR3_DMAT_Pos (7U) 4793 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 4794 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 4795 #define USART_CR3_RTSE_Pos (8U) 4796 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 4797 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 4798 #define USART_CR3_CTSE_Pos (9U) 4799 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 4800 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 4801 #define USART_CR3_CTSIE_Pos (10U) 4802 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 4803 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 4804 4805 /****************** Bit definition for USART_GTPR register ******************/ 4806 #define USART_GTPR_PSC_Pos (0U) 4807 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 4808 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 4809 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 4810 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 4811 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 4812 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 4813 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 4814 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 4815 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 4816 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 4817 4818 #define USART_GTPR_GT_Pos (8U) 4819 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 4820 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 4821 4822 /******************************************************************************/ 4823 /* */ 4824 /* Debug MCU */ 4825 /* */ 4826 /******************************************************************************/ 4827 4828 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 4829 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 4830 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 4831 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 4832 4833 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 4834 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 4835 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 4836 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 4837 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 4838 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 4839 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 4840 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 4841 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 4842 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 4843 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 4844 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 4845 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 4846 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 4847 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 4848 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 4849 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 4850 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 4851 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 4852 4853 /****************** Bit definition for DBGMCU_CR register *******************/ 4854 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 4855 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 4856 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 4857 #define DBGMCU_CR_DBG_STOP_Pos (1U) 4858 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 4859 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 4860 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 4861 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 4862 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 4863 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 4864 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 4865 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 4866 4867 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 4868 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 4869 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 4870 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 4871 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 4872 4873 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) 4874 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ 4875 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 4876 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) 4877 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ 4878 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 4879 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) 4880 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ 4881 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 4882 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) 4883 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ 4884 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 4885 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) 4886 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ 4887 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 4888 4889 /******************************************************************************/ 4890 /* */ 4891 /* FLASH and Option Bytes Registers */ 4892 /* */ 4893 /******************************************************************************/ 4894 /******************* Bit definition for FLASH_ACR register ******************/ 4895 #define FLASH_ACR_LATENCY_Pos (0U) 4896 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 4897 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ 4898 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 4899 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 4900 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 4901 4902 #define FLASH_ACR_HLFCYA_Pos (3U) 4903 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 4904 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 4905 #define FLASH_ACR_PRFTBE_Pos (4U) 4906 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 4907 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 4908 #define FLASH_ACR_PRFTBS_Pos (5U) 4909 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 4910 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 4911 4912 /****************** Bit definition for FLASH_KEYR register ******************/ 4913 #define FLASH_KEYR_FKEYR_Pos (0U) 4914 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 4915 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 4916 4917 #define RDP_KEY_Pos (0U) 4918 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ 4919 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 4920 #define FLASH_KEY1_Pos (0U) 4921 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 4922 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 4923 #define FLASH_KEY2_Pos (0U) 4924 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 4925 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 4926 4927 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 4928 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 4929 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 4930 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 4931 4932 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 4933 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 4934 4935 /****************** Bit definition for FLASH_SR register ********************/ 4936 #define FLASH_SR_BSY_Pos (0U) 4937 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 4938 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 4939 #define FLASH_SR_PGERR_Pos (2U) 4940 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 4941 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 4942 #define FLASH_SR_WRPRTERR_Pos (4U) 4943 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 4944 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 4945 #define FLASH_SR_EOP_Pos (5U) 4946 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 4947 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 4948 4949 /******************* Bit definition for FLASH_CR register *******************/ 4950 #define FLASH_CR_PG_Pos (0U) 4951 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 4952 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 4953 #define FLASH_CR_PER_Pos (1U) 4954 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 4955 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 4956 #define FLASH_CR_MER_Pos (2U) 4957 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 4958 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 4959 #define FLASH_CR_OPTPG_Pos (4U) 4960 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 4961 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 4962 #define FLASH_CR_OPTER_Pos (5U) 4963 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 4964 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 4965 #define FLASH_CR_STRT_Pos (6U) 4966 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 4967 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 4968 #define FLASH_CR_LOCK_Pos (7U) 4969 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 4970 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 4971 #define FLASH_CR_OPTWRE_Pos (9U) 4972 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 4973 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 4974 #define FLASH_CR_ERRIE_Pos (10U) 4975 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 4976 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 4977 #define FLASH_CR_EOPIE_Pos (12U) 4978 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 4979 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 4980 4981 /******************* Bit definition for FLASH_AR register *******************/ 4982 #define FLASH_AR_FAR_Pos (0U) 4983 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 4984 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 4985 4986 /****************** Bit definition for FLASH_OBR register *******************/ 4987 #define FLASH_OBR_OPTERR_Pos (0U) 4988 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 4989 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 4990 #define FLASH_OBR_RDPRT_Pos (1U) 4991 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 4992 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 4993 4994 #define FLASH_OBR_IWDG_SW_Pos (2U) 4995 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ 4996 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 4997 #define FLASH_OBR_nRST_STOP_Pos (3U) 4998 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ 4999 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 5000 #define FLASH_OBR_nRST_STDBY_Pos (4U) 5001 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ 5002 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 5003 #define FLASH_OBR_USER_Pos (2U) 5004 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ 5005 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 5006 #define FLASH_OBR_DATA0_Pos (10U) 5007 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ 5008 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 5009 #define FLASH_OBR_DATA1_Pos (18U) 5010 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ 5011 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 5012 5013 /****************** Bit definition for FLASH_WRPR register ******************/ 5014 #define FLASH_WRPR_WRP_Pos (0U) 5015 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 5016 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 5017 5018 /*----------------------------------------------------------------------------*/ 5019 5020 /****************** Bit definition for FLASH_RDP register *******************/ 5021 #define FLASH_RDP_RDP_Pos (0U) 5022 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ 5023 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ 5024 #define FLASH_RDP_nRDP_Pos (8U) 5025 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 5026 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 5027 5028 /****************** Bit definition for FLASH_USER register ******************/ 5029 #define FLASH_USER_USER_Pos (16U) 5030 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ 5031 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ 5032 #define FLASH_USER_nUSER_Pos (24U) 5033 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ 5034 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ 5035 5036 /****************** Bit definition for FLASH_Data0 register *****************/ 5037 #define FLASH_DATA0_DATA0_Pos (0U) 5038 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ 5039 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ 5040 #define FLASH_DATA0_nDATA0_Pos (8U) 5041 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ 5042 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ 5043 5044 /****************** Bit definition for FLASH_Data1 register *****************/ 5045 #define FLASH_DATA1_DATA1_Pos (16U) 5046 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ 5047 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ 5048 #define FLASH_DATA1_nDATA1_Pos (24U) 5049 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ 5050 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ 5051 5052 /****************** Bit definition for FLASH_WRP0 register ******************/ 5053 #define FLASH_WRP0_WRP0_Pos (0U) 5054 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ 5055 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 5056 #define FLASH_WRP0_nWRP0_Pos (8U) 5057 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 5058 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 5059 5060 5061 5062 /** 5063 * @} 5064 */ 5065 5066 /** 5067 * @} 5068 */ 5069 5070 /** @addtogroup Exported_macro 5071 * @{ 5072 */ 5073 5074 /****************************** ADC Instances *********************************/ 5075 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) 5076 5077 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 5078 5079 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 5080 5081 /****************************** CRC Instances *********************************/ 5082 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 5083 5084 /****************************** DAC Instances *********************************/ 5085 5086 /****************************** DMA Instances *********************************/ 5087 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 5088 ((INSTANCE) == DMA1_Channel2) || \ 5089 ((INSTANCE) == DMA1_Channel3) || \ 5090 ((INSTANCE) == DMA1_Channel4) || \ 5091 ((INSTANCE) == DMA1_Channel5) || \ 5092 ((INSTANCE) == DMA1_Channel6) || \ 5093 ((INSTANCE) == DMA1_Channel7)) 5094 5095 /******************************* GPIO Instances *******************************/ 5096 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5097 ((INSTANCE) == GPIOB) || \ 5098 ((INSTANCE) == GPIOC) || \ 5099 ((INSTANCE) == GPIOD)) 5100 5101 /**************************** GPIO Alternate Function Instances ***************/ 5102 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 5103 5104 /**************************** GPIO Lock Instances *****************************/ 5105 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 5106 5107 /******************************** I2C Instances *******************************/ 5108 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1) 5109 5110 /******************************* SMBUS Instances ******************************/ 5111 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE 5112 5113 /****************************** IWDG Instances ********************************/ 5114 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 5115 5116 /******************************** SPI Instances *******************************/ 5117 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1) 5118 5119 /****************************** START TIM Instances ***************************/ 5120 /****************************** TIM Instances *********************************/ 5121 #define IS_TIM_INSTANCE(INSTANCE)\ 5122 (((INSTANCE) == TIM2) || \ 5123 ((INSTANCE) == TIM3)) 5124 5125 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U 5126 5127 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 5128 (((INSTANCE) == TIM2) || \ 5129 ((INSTANCE) == TIM3)) 5130 5131 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 5132 (((INSTANCE) == TIM2) || \ 5133 ((INSTANCE) == TIM3)) 5134 5135 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 5136 (((INSTANCE) == TIM2) || \ 5137 ((INSTANCE) == TIM3)) 5138 5139 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 5140 (((INSTANCE) == TIM2) || \ 5141 ((INSTANCE) == TIM3)) 5142 5143 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 5144 (((INSTANCE) == TIM2) || \ 5145 ((INSTANCE) == TIM3)) 5146 5147 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 5148 (((INSTANCE) == TIM2) || \ 5149 ((INSTANCE) == TIM3)) 5150 5151 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 5152 (((INSTANCE) == TIM2) || \ 5153 ((INSTANCE) == TIM3)) 5154 5155 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 5156 (((INSTANCE) == TIM2) || \ 5157 ((INSTANCE) == TIM3)) 5158 5159 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 5160 (((INSTANCE) == TIM2) || \ 5161 ((INSTANCE) == TIM3)) 5162 5163 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 5164 (((INSTANCE) == TIM2) || \ 5165 ((INSTANCE) == TIM3)) 5166 5167 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 5168 (((INSTANCE) == TIM2) || \ 5169 ((INSTANCE) == TIM3)) 5170 5171 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 5172 (((INSTANCE) == TIM2) || \ 5173 ((INSTANCE) == TIM3)) 5174 5175 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 5176 (((INSTANCE) == TIM2) || \ 5177 ((INSTANCE) == TIM3)) 5178 5179 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 5180 (((INSTANCE) == TIM2) || \ 5181 ((INSTANCE) == TIM3)) 5182 5183 #define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U 5184 5185 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 5186 ((((INSTANCE) == TIM2) && \ 5187 (((CHANNEL) == TIM_CHANNEL_1) || \ 5188 ((CHANNEL) == TIM_CHANNEL_2) || \ 5189 ((CHANNEL) == TIM_CHANNEL_3) || \ 5190 ((CHANNEL) == TIM_CHANNEL_4))) \ 5191 || \ 5192 (((INSTANCE) == TIM3) && \ 5193 (((CHANNEL) == TIM_CHANNEL_1) || \ 5194 ((CHANNEL) == TIM_CHANNEL_2) || \ 5195 ((CHANNEL) == TIM_CHANNEL_3) || \ 5196 ((CHANNEL) == TIM_CHANNEL_4)))) 5197 5198 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U 5199 5200 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 5201 (((INSTANCE) == TIM2) || \ 5202 ((INSTANCE) == TIM3)) 5203 5204 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U 5205 5206 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 5207 (((INSTANCE) == TIM2) || \ 5208 ((INSTANCE) == TIM3)) 5209 5210 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 5211 (((INSTANCE) == TIM2) || \ 5212 ((INSTANCE) == TIM3)) 5213 5214 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 5215 (((INSTANCE) == TIM2) || \ 5216 ((INSTANCE) == TIM3)) 5217 5218 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U 5219 5220 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5221 ((INSTANCE) == TIM3)) 5222 5223 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 5224 ((INSTANCE) == TIM3)) 5225 5226 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U 5227 5228 /****************************** END TIM Instances *****************************/ 5229 5230 5231 /******************** USART Instances : Synchronous mode **********************/ 5232 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5233 ((INSTANCE) == USART2)) 5234 5235 /******************** UART Instances : Asynchronous mode **********************/ 5236 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5237 ((INSTANCE) == USART2) ) 5238 5239 /******************** UART Instances : Half-Duplex mode **********************/ 5240 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5241 ((INSTANCE) == USART2) ) 5242 5243 /******************** UART Instances : LIN mode **********************/ 5244 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5245 ((INSTANCE) == USART2) ) 5246 5247 /****************** UART Instances : Hardware Flow control ********************/ 5248 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5249 ((INSTANCE) == USART2) ) 5250 5251 /********************* UART Instances : Smard card mode ***********************/ 5252 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5253 ((INSTANCE) == USART2) ) 5254 5255 /*********************** UART Instances : IRDA mode ***************************/ 5256 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5257 ((INSTANCE) == USART2) ) 5258 5259 /***************** UART Instances : Multi-Processor mode **********************/ 5260 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5261 ((INSTANCE) == USART2) ) 5262 5263 /***************** UART Instances : DMA mode available **********************/ 5264 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5265 ((INSTANCE) == USART2)) 5266 5267 /****************************** RTC Instances *********************************/ 5268 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 5269 5270 /**************************** WWDG Instances *****************************/ 5271 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 5272 5273 5274 5275 5276 #define RCC_HSE_MIN 4000000U 5277 #define RCC_HSE_MAX 16000000U 5278 5279 #define RCC_MAX_FREQUENCY 72000000U 5280 5281 /** 5282 * @} 5283 */ 5284 /******************************************************************************/ 5285 /* For a painless codes migration between the STM32F1xx device product */ 5286 /* lines, the aliases defined below are put in place to overcome the */ 5287 /* differences in the interrupt handlers and IRQn definitions. */ 5288 /* No need to update developed interrupt code when moving across */ 5289 /* product lines within the same STM32F1 Family */ 5290 /******************************************************************************/ 5291 5292 /* Aliases for __IRQn */ 5293 #define ADC1_2_IRQn ADC1_IRQn 5294 5295 5296 /* Aliases for __IRQHandler */ 5297 #define ADC1_2_IRQHandler ADC1_IRQHandler 5298 5299 5300 /** 5301 * @} 5302 */ 5303 5304 /** 5305 * @} 5306 */ 5307 5308 5309 #ifdef __cplusplus 5310 } 5311 #endif /* __cplusplus */ 5312 5313 #endif /* __STM32F101x6_H */ 5314 5315 5316 5317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 5318
