| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_dw_stm32.h | 22 static inline int clk_enable_st_stm32f4_fsotg(const struct usb_dw_stm32_clk *const clk) in clk_enable_st_stm32f4_fsotg() argument
26 if (!device_is_ready(clk->dev)) { in clk_enable_st_stm32f4_fsotg()
30 if (clk->pclken_len > 1) { in clk_enable_st_stm32f4_fsotg()
33 ret = clock_control_configure(clk->dev, in clk_enable_st_stm32f4_fsotg()
34 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
40 ret = clock_control_get_rate(clk->dev, in clk_enable_st_stm32f4_fsotg()
41 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
52 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in clk_enable_st_stm32f4_fsotg()
|
| /Zephyr-latest/tests/net/ptp/clock/src/ |
| D | main.c | 308 const struct device *clk; in iface_cb() local
315 clk = net_eth_get_ptp_clock(iface); in iface_cb()
316 if (!clk) { in iface_cb()
415 const struct device *clk; in test_ptp_clock_interfaces() local
419 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
420 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
424 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
425 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
428 clk = net_eth_get_ptp_clock(eth_interfaces[non_ptp_interface]); in test_ptp_clock_interfaces()
429 zassert_is_null(clk, "Clock found for interface %p\n", in test_ptp_clock_interfaces()
[all …]
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_arm_scmi.c | 20 clock_control_subsys_t clk, bool on) in scmi_clock_on_off() argument
29 clk_id = POINTER_TO_UINT(clk); in scmi_clock_on_off()
43 static int scmi_clock_on(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_on() argument
45 return scmi_clock_on_off(dev, clk, true); in scmi_clock_on()
48 static int scmi_clock_off(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_off() argument
50 return scmi_clock_on_off(dev, clk, false); in scmi_clock_off()
54 clock_control_subsys_t clk, uint32_t *rate) in scmi_clock_get_rate() argument
62 clk_id = POINTER_TO_UINT(clk); in scmi_clock_get_rate()
|
| D | clock_control_smartbond.c | 47 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk);
208 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_on() local
213 switch (clk) { in smartbond_clock_control_on()
232 pll_requests = 1 << (clk - SMARTBOND_CLK_PLL96M); in smartbond_clock_control_on()
260 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_off() local
265 switch (clk) { in smartbond_clock_control_off()
303 pll_requests &= ~(1 << (clk - SMARTBOND_CLK_PLL96M)); in smartbond_clock_control_off()
327 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk) in smartbond_source_clock() argument
342 if (clk == SMARTBOND_CLK_SYS_CLK) { in smartbond_source_clock()
343 clk = sys_clk_src[CRG_TOP->CLK_CTRL_REG & in smartbond_source_clock()
[all …]
|
| D | clock_control_r8a779f0_cpg_mssr.c | 110 static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a779f0_cpg_core_clock_endisable() argument
117 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in r8a779f0_cpg_core_clock_endisable()
123 if (clk->rate > 0) { in r8a779f0_cpg_core_clock_endisable()
125 uintptr_t rate = clk->rate; in r8a779f0_cpg_core_clock_endisable()
127 ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, in r8a779f0_cpg_core_clock_endisable()
144 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a779f0_cpg_mssr_start_stop() local
151 if (clk->domain == CPG_MOD) { in r8a779f0_cpg_mssr_start_stop()
156 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a779f0_cpg_mssr_start_stop()
158 } else if (clk->domain == CPG_CORE) { in r8a779f0_cpg_mssr_start_stop()
159 ret = r8a779f0_cpg_core_clock_endisable(dev, clk, enable); in r8a779f0_cpg_mssr_start_stop()
|
| D | clock_control_r8a7795_cpg_mssr.c | 115 static int r8a7795_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a7795_cpg_core_clock_endisable() argument
122 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in r8a7795_cpg_core_clock_endisable()
128 if (clk->rate > 0) { in r8a7795_cpg_core_clock_endisable()
130 uintptr_t rate = clk->rate; in r8a7795_cpg_core_clock_endisable()
132 ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, in r8a7795_cpg_core_clock_endisable()
150 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a7795_cpg_mssr_start_stop() local
157 if (clk->domain == CPG_MOD) { in r8a7795_cpg_mssr_start_stop()
162 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a7795_cpg_mssr_start_stop()
164 } else if (clk->domain == CPG_CORE) { in r8a7795_cpg_mssr_start_stop()
165 ret = r8a7795_cpg_core_clock_endisable(dev, clk, enable); in r8a7795_cpg_mssr_start_stop()
|
| D | clock_control_rpi_pico.c | 57 #define CLK_SRC_IS(clk, src) \ argument
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk) argument
73 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \ argument
75 #define SRC_CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, SRC_CLOCK(clk)) argument
100 #define CLOCK_AUX_SOURCE(clk) _CONCAT(_CONCAT(AUXSTEM_, clk), _CONCAT(AUXSRC_, SRC_CLOCK(clk))) argument
175 enum rpi_pico_clkid clk; member
331 clock_hw_t *clock_hw = &config->clocks_regs->clk[id]; in rpi_pico_get_clock_src()
344 clock_hw_t *clock_hw = &clocks_hw->clk[id]; in rpi_pico_get_clock_src()
367 clock_hw_t *clock_hw = &clocks_hw->clk[id]; in rpi_pico_get_clock_src()
[all …]
|
| /Zephyr-latest/drivers/fpga/ |
| D | fpga_ice40_bitbang.c | 47 struct gpio_dt_spec clk; member
71 volatile gpio_port_pins_t *clear, gpio_port_pins_t clk, size_t n) in fpga_ice40_send_clocks() argument
74 *clear |= clk; in fpga_ice40_send_clocks()
76 *set |= clk; in fpga_ice40_send_clocks()
83 gpio_port_pins_t clk, gpio_port_pins_t pico, uint8_t *z, in fpga_ice40_spi_send_data() argument
96 *clear |= clk; in fpga_ice40_spi_send_data()
107 *set |= clk; in fpga_ice40_spi_send_data()
127 gpio_port_pins_t clk; in fpga_ice40_load() local
135 if (!device_is_ready(config_bitbang->clk.port)) { in fpga_ice40_load()
147 clk = BIT(config_bitbang->clk.pin); in fpga_ice40_load()
[all …]
|
| /Zephyr-latest/drivers/memc/ |
| D | memc_stm32.c | 44 const struct device *clk; in memc_stm32_init() local
54 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in memc_stm32_init()
56 if (!device_is_ready(clk)) { in memc_stm32_init()
61 r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]); in memc_stm32_init()
69 r = clock_control_configure(clk, (clock_control_subsys_t)&config->pclken[1], NULL); in memc_stm32_init()
|
| /Zephyr-latest/boards/atmel/sam/sam4l_ek/ |
| D | sam4l_ek.dts | 71 clk = <4>;
81 std-clk-slew-lim = <0>;
82 std-clk-strength-low = "0.5";
86 hs-clk-slew-lim = <0>;
87 hs-clk-strength-high = "0.5";
88 hs-clk-strength-low = "0.5";
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_i2c.c | 28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock() argument
35 (clock_control_subsys_t) clk, in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
62 (clock_control_subsys_t) clk, in i2c_set_clock()
|
| /Zephyr-latest/soc/nxp/kinetis/kwx/ |
| D | soc_kw4xz.c | 18 #define CLOCK_NODEID(clk) \ argument
19 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
21 #define CLOCK_DIVIDER(clk) \ argument
22 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| D | soc_kw2xd.c | 29 #define CLOCK_NODEID(clk) \ argument
30 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
32 #define CLOCK_DIVIDER(clk) \ argument
33 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-latest/soc/nxp/kinetis/k2x/ |
| D | soc.c | 30 #define CLOCK_NODEID(clk) \ argument
31 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
33 #define CLOCK_DIVIDER(clk) \ argument
34 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-latest/soc/nxp/kinetis/kl2x/ |
| D | soc.c | 17 #define CLOCK_NODEID(clk) \ argument
18 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
20 #define CLOCK_DIVIDER(clk) \ argument
21 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_pl011_ambiq.h | 25 static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk) in pl011_ambiq_clk_set() argument
29 switch (clk) { in pl011_ambiq_clk_set()
50 static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) in clk_enable_ambiq_uart() argument
53 return pl011_ambiq_clk_set(dev, clk); in clk_enable_ambiq_uart()
182 static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
184 return clk_enable_ambiq_uart(dev, clk); \
201 static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk) \
203 return clk_enable_ambiq_uart(dev, clk); \
|
| /Zephyr-latest/soc/st/stm32/common/ |
| D | stm32_backup_sram.c | 28 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in stm32_backup_sram_init() local
30 if (!device_is_ready(clk)) { in stm32_backup_sram_init()
35 ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken); in stm32_backup_sram_init()
|
| /Zephyr-latest/samples/sensor/lps22hh_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
|
| /Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
|
| /Zephyr-latest/soc/nxp/kinetis/kv5x/ |
| D | soc.c | 22 #define CLOCK_NODEID(clk) \ argument
23 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
25 #define CLOCK_DIVIDER(clk) \ argument
26 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-latest/dts/arm/st/f2/ |
| D | stm32f207.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
|
| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f407.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
|
| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_dwc2_vendor_quirks.h | 30 static inline int stm32f4_fsotg_enable_clk(const struct usb_dw_stm32_clk *const clk) in stm32f4_fsotg_enable_clk() argument
34 if (!device_is_ready(clk->dev)) { in stm32f4_fsotg_enable_clk()
38 if (clk->pclken_len > 1) { in stm32f4_fsotg_enable_clk()
41 ret = clock_control_configure(clk->dev, in stm32f4_fsotg_enable_clk()
42 (void *)&clk->pclken[1], in stm32f4_fsotg_enable_clk()
48 ret = clock_control_get_rate(clk->dev, in stm32f4_fsotg_enable_clk()
49 (void *)&clk->pclken[1], in stm32f4_fsotg_enable_clk()
60 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in stm32f4_fsotg_enable_clk()
|
| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | soc.c | 25 #define CLOCK_NODEID(clk) \ argument
26 DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
28 #define CLOCK_DIVIDER(clk) \ argument
29 DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
| /Zephyr-latest/subsys/net/l2/ethernet/gptp/ |
| D | gptp_user_api.c | 57 const struct device *clk; in gptp_event_capture() local
66 clk = net_eth_get_ptp_clock(GPTP_PORT_IFACE(port)); in gptp_event_capture()
67 if (clk) { in gptp_event_capture()
68 ptp_clock_get(clk, slave_time); in gptp_event_capture()
|
