1 /*
2 * Copyright (c) 2021 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32_backup_sram
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11
12 #include <stm32_ll_pwr.h>
13
14 #include <zephyr/logging/log.h>
15 LOG_MODULE_REGISTER(stm32_backup_sram, CONFIG_SOC_LOG_LEVEL);
16
17 struct stm32_backup_sram_config {
18 struct stm32_pclken pclken;
19 };
20
stm32_backup_sram_init(const struct device * dev)21 static int stm32_backup_sram_init(const struct device *dev)
22 {
23 const struct stm32_backup_sram_config *config = dev->config;
24
25 int ret;
26
27 /* enable clock for subsystem */
28 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
29
30 if (!device_is_ready(clk)) {
31 LOG_ERR("clock control device not ready");
32 return -ENODEV;
33 }
34
35 ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken);
36 if (ret < 0) {
37 LOG_ERR("Could not initialize backup SRAM clock (%d)", ret);
38 return ret;
39 }
40
41 /* enable write access to backup domain */
42 LL_PWR_EnableBkUpAccess();
43 while (!LL_PWR_IsEnabledBkUpAccess()) {
44 }
45
46 /* enable backup sram regulator (required to retain backup SRAM content
47 * while in standby or VBAT modes).
48 */
49 LL_PWR_EnableBkUpRegulator();
50 while (!LL_PWR_IsEnabledBkUpRegulator()) {
51 }
52
53 return 0;
54 }
55
56 static const struct stm32_backup_sram_config config = {
57 .pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
58 .enr = DT_INST_CLOCKS_CELL(0, bits) },
59 };
60
61 DEVICE_DT_INST_DEFINE(0, stm32_backup_sram_init, NULL, NULL, &config,
62 POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, NULL);
63
