Searched refs:well (Results 276 – 300 of 401) sorted by relevance
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| /Zephyr-latest/doc/kernel/services/timing/ |
| D | clocks.rst | 354 and :c:macro:`K_NO_WAIT`, and works identically for absolute timeouts as well
358 past. For simple cases, :c:func:`sys_timepoint_expired` can be used as well.
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| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 104 The page-tables-specified-in-virtual-memory trick works very well in
204 doesn't match Zephyr's architecture well, as we tend to assume
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| /Zephyr-latest/boards/espressif/esp_wrover_kit/doc/ |
| D | index.rst | 107 | USB Port | USB interface. Power supply for the board as well as the |
200 D/C (Data / Control) signal for the LCD as well as the Card Detect signal read from the SD card
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| /Zephyr-latest/subsys/mgmt/mcumgr/grp/img_mgmt/ |
| D | Kconfig | 129 number as well.
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| /Zephyr-latest/doc/connectivity/networking/ |
| D | overview.rst | 83 well as several IPSO Smart Objects. (`LwM2M specification 1.1.1`_) is
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| /Zephyr-latest/doc/services/llext/ |
| D | build.rst | 159 contain the compile flags needed by the project, as well as other build-related
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| /Zephyr-latest/doc/services/sensing/ |
| D | index.rst | 46 cross host OSes support and as well as IoT sensor solutions.
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| /Zephyr-latest/boards/st/stm32h7s78_dk/doc/ |
| D | index.rst | 191 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/doc/services/ |
| D | formatted_output.rst | 6 Applications as well as Zephyr itself requires infrastructure to format
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| /Zephyr-latest/boards/st/nucleo_wb55rg/doc/ |
| D | nucleo_wb55rg.rst | 192 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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| /Zephyr-latest/doc/develop/flash_debug/ |
| D | nordic_segger.rst | 29 drive corresponding to a USB Mass Storage device as well as a serial port should come up
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| /Zephyr-latest/boards/st/nucleo_l552ze_q/doc/ |
| D | nucleol552ze_q.rst | 217 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/samples/net/sockets/echo_client/ |
| D | README.rst | 175 You can verify TLS communication with a Linux host as well. See
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| /Zephyr-latest/boards/st/nucleo_h745zi_q/doc/ |
| D | index.rst | 109 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/boards/st/nucleo_h7s3l8/doc/ |
| D | index.rst | 173 oscillator, as well as the main PLL clock. By default, the System clock is
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| /Zephyr-latest/samples/subsys/mgmt/hawkbit/ |
| D | README.rst | 32 Bluetooth LE, 6lowpan, 802.15.4 or OpenThread configurations as well as the
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| /Zephyr-latest/doc/connectivity/networking/conn_mgr/ |
| D | implementation.rst | 35 …ce to the bound iface, the connectivity implementation it is bound to, as well as a pointer to a p…
343 …uld be possible to configure builds that include Connectivity Manager, as well as the iface that w…
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| /Zephyr-latest/boards/native/doc/ |
| D | bsim_boards_design.rst | 209 The threading description, as well as the general SOC and board architecture
367 - WordSize: The bsim targets, as well as normal embedded targets are 32 bit
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| /Zephyr-latest/doc/kernel/usermode/ |
| D | memory_domain.rst | 228 This does not scale particularly well when we are trying to contain multiple
411 child thread, that thread will belong to the domain as well.
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| /Zephyr-latest/boards/st/stm32h573i_dk/doc/ |
| D | index.rst | 174 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/stm32h747i_disco/doc/ |
| D | index.rst | 82 as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock
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| /Zephyr-latest/boards/st/stm32l562e_dk/doc/ |
| D | index.rst | 210 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/doc/connectivity/bluetooth/api/mesh/ |
| D | blob.rst | 21 parameters of the transfer according to the application and network configuration, as well as
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| /Zephyr-latest/boards/st/nucleo_h533re/doc/ |
| D | index.rst | 179 as well as main PLL clock. By default System clock is driven by PLL clock at
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| /Zephyr-latest/boards/st/nucleo_h563zi/doc/ |
| D | index.rst | 169 as well as main PLL clock. By default System clock is driven by PLL clock at
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