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Searched refs:sys_write32 (Results 51 – 75 of 191) sorted by relevance

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/Zephyr-latest/drivers/entropy/
Dentropy_cc13xx_cc26xx.c53 sys_write32(TRNG_FRODETUNE_FRO_MASK_M, TRNG_BASE + in start_trng()
56 sys_write32(TRNG_FROEN_FRO_MASK_M, TRNG_BASE + TRNG_O_FROEN); in start_trng()
58 sys_write32((CONFIG_ENTROPY_CC13XX_CC26XX_SHUTDOWN_THRESHOLD in start_trng()
85 sys_write32(0, TRNG_BASE + TRNG_O_ALARMMASK); in handle_shutdown_ovf()
86 sys_write32(0, TRNG_BASE + TRNG_O_ALARMSTOP); in handle_shutdown_ovf()
88 sys_write32(off, TRNG_BASE + TRNG_O_FRODETUNE); in handle_shutdown_ovf()
90 sys_write32(off, TRNG_BASE + TRNG_O_FROEN); in handle_shutdown_ovf()
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac.c174 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
181 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
188 sys_write32(reg_val, reg_addr); in dwxgmac_dma_init()
219 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
230 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
241 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
248 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
254 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
260 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
266 sys_write32(reg_val, reg_addr); in dwxgmac_dma_chnl_init()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_efinix_sapphire.c63 sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ENABLE_ADDR); in cfg_output_enable_bit()
65 sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ENABLE_ADDR); in cfg_output_enable_bit()
76 sys_write32(c_reg_val &= ~pin, GPIO_OUTPUT_ADDR); in cfg_output_bit()
78 sys_write32(c_reg_val |= pin, GPIO_OUTPUT_ADDR); in cfg_output_bit()
129 sys_write32(value, GPIO_OUTPUT_ADDR); in set_port()
Dgpio_stellaris.c63 sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET)); in gpio_stellaris_isr()
91 sys_write32(BIT(pin), mask_addr); in gpio_stellaris_configure()
93 sys_write32(0, mask_addr); in gpio_stellaris_configure()
156 sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_set_masked_raw()
167 sys_write32(mask, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_set_bits_raw()
178 sys_write32(0, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_clear_bits_raw()
192 sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, 0xff)); in gpio_stellaris_port_toggle_bits()
Dgpio_mchp_xec_v2.c84 sys_write32(r, addr); in xec_mask_write32()
155 sys_write32(pcr1, pcr1_addr); in gpio_xec_configure()
165 sys_write32(pcr1, pcr1_addr); in gpio_xec_configure()
179 sys_write32(pcr1, pcr1_addr); in gpio_xec_configure()
209 sys_write32(pcr1, pcr1_addr); /* configuration. may generate a single edge */ in gpio_xec_configure()
211 sys_write32(pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS), pcr1_addr); in gpio_xec_configure()
320 sys_write32(pcr1, pcr1_addr); in gpio_xec_pin_interrupt_configure()
348 sys_write32(sys_read32(pout_addr) | mask, pout_addr); in gpio_xec_port_set_bits_raw()
358 sys_write32(sys_read32(pout_addr) & ~mask, pout_addr); in gpio_xec_port_clear_bits_raw()
367 sys_write32(sys_read32(pout_addr) ^ mask, pout_addr); in gpio_xec_port_toggle_bits()
Dgpio_iproc.c80 sys_write32(value, base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_set_masked_raw()
90 sys_write32(mask, base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_set_bits_raw()
104 sys_write32(value, base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_clear_bits_raw()
118 sys_write32(value, base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_toggle_bits()
168 sys_write32(int_stat, base + IPROC_GPIO_INT_CLR_OFFSET); in gpio_iproc_isr()
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.c122 sys_write32((sys_read32(dest) & (~mask)) | (val & mask), dest); in dai_ssp_update_bits()
258 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_setup_initial_mclk_source()
301 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_check_current_mclk_source()
332 sys_write32(mdivr, dai_mn_base(dp) + MN_MDIVR(mclk_id)); in dai_ssp_set_mclk_divider()
376 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_mn_set_mclk_blob()
377 sys_write32(mdivr, dai_mn_base(dp) + MN_MDIVR(0)); in dai_ssp_mn_set_mclk_blob()
397 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_mn_release_mclk()
407 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_mn_release_mclk()
595 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_setup_initial_bclk_mn_source()
622 sys_write32(mdivc, dai_mn_base(dp) + MN_MDIVCTRL); in dai_ssp_reset_bclk_mn_source()
[all …]
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dsoc.c56 sys_write32(current | (1 << (idx & 0x1f)), in soc_enable_irq()
64 sys_write32(current & (~(1 << (idx & 0x1f))), in soc_disable_irq()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_sifive.c35 sys_write32(val, PINCTRL_IOF_SEL); in pinctrl_sifive_set()
40 sys_write32(val, PINCTRL_IOF_EN); in pinctrl_sifive_set()
Dpinctrl_nxp_s32.c41 sys_write32(pin->mscr.val, (base + SIUL2_MSCR(pin->mscr.idx))); in pinctrl_configure_pin()
50 sys_write32(pin->imcr.val, (base + SIUL2_IMCR(pin->imcr.idx))); in pinctrl_configure_pin()
/Zephyr-latest/drivers/watchdog/
Dwdt_dw.h310 sys_write32(control, base + WDT_CR); in dw_wdt_enable()
335 sys_write32(control, base + WDT_CR); in dw_wdt_response_mode_set()
351 sys_write32(control, base + WDT_CR); in dw_wdt_reset_pulse_length_set()
366 sys_write32(timeout, base + WDT_TORR); in dw_wdt_timeout_period_set()
393 sys_write32(timeout, base + WDT_TORR); in dw_wdt_timeout_period_init_set()
421 sys_write32(WDT_CRR_RESTART_KEY, base + WDT_CRR); in dw_wdt_counter_restart()
/Zephyr-latest/drivers/can/
Dcan_nrf.c42 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0); in can_nrf_irq_handler()
47 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1); in can_nrf_irq_handler()
154 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0); in can_nrf_init()
155 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1); in can_nrf_init()
156 sys_write32(CAN_INTEN_CORE0_Msk | CAN_INTEN_CORE1_Msk, config->wrapper + CAN_INTEN); in can_nrf_init()
157 sys_write32(1U, config->wrapper + CAN_TASKS_START); in can_nrf_init()
/Zephyr-latest/drivers/i3c/
Di3c_cdns.c742 sys_write32(MST_INT_MASK, config->base + MST_IDR); in cdns_i3c_interrupts_disable()
747 sys_write32(MST_INT_MASK, config->base + MST_ICR); in cdns_i3c_interrupts_clear()
759 sys_write32(val, config->base + TX_FIFO); in cdns_i3c_write_tx_fifo()
765 sys_write32(val, config->base + TX_FIFO); in cdns_i3c_write_tx_fifo()
777 sys_write32(val, config->base + SLV_DDR_TX_FIFO); in cdns_i3c_write_ddr_tx_fifo()
783 sys_write32(val, config->base + SLV_DDR_TX_FIFO); in cdns_i3c_write_ddr_tx_fifo()
796 sys_write32(val, config->base + IBI_DATA_FIFO); in cdns_i3c_write_ibi_fifo()
802 sys_write32(val, config->base + IBI_DATA_FIFO); in cdns_i3c_write_ibi_fifo()
960 sys_write32(~CTRL_DEV_EN & ctrl, config->base + CTRL); in cdns_i3c_set_prescalers()
963 sys_write32(PRESCL_CTRL0_I3C(prescl_i3c) | PRESCL_CTRL0_I2C(prescl_i2c), in cdns_i3c_set_prescalers()
[all …]
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc.c239 sys_write32(PCIE0_PERST_INTR, CRMU_MCU_EXTRA_EVENT_CLEAR); in iproc_pcie_perst()
260 sys_write32(PCIE0_PERST_INB_INTR, CRMU_MCU_EXTRA_EVENT_CLEAR); in iproc_pcie_hot_reset()
312 sys_write32(PCIE0_PERST_INTR, CRMU_MCU_EXTRA_EVENT_CLEAR); in iproc_pcie_reset_config()
317 sys_write32(data, PCIE_PERSTB_INTR_CTL_STS); in iproc_pcie_reset_config()
321 sys_write32(data, CRMU_MCU_EXTRA_EVENT_MASK); in iproc_pcie_reset_config()
331 sys_write32(PCIE0_PERST_INB_INTR, CRMU_MCU_EXTRA_EVENT_CLEAR); in iproc_pcie_reset_config()
336 sys_write32(data, PCIE_PERSTB_INTR_CTL_STS); in iproc_pcie_reset_config()
340 sys_write32(data, CRMU_MCU_EXTRA_EVENT_MASK); in iproc_pcie_reset_config()
399 sys_write32(data, PMON_LITE_PCIE_AXI_FILTER_0_CONTROL); in iproc_pcie_msix_pvm_config()
401 sys_write32(MSIX_TABLE_BASE, AXI_FILTER_0_ADDR_START_LOW); in iproc_pcie_msix_pvm_config()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower.c265 sys_write32(SHIM_CLKCTL_LPGPDMAFDCGB, SHIM_GPDMA_CLKCTL(0)); in power_init()
266 sys_write32(SHIM_CLKCTL_LPGPDMAFDCGB, SHIM_GPDMA_CLKCTL(1)); in power_init()
276 sys_write32(GENO_MDIVOSEL | GENO_DIOPTOSEL, DSP_INIT_GENO); in power_init()
277 sys_write32(IOPO_DMIC_FLAG | IOPO_I2SSEL_MASK, DSP_INIT_IOPO); in power_init()
/Zephyr-latest/drivers/ethernet/
Deth_cyclonev.c135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
229 sys_write32((uint32_t)&p->rx_desc_ring[0], in eth_cyclonev_setup_rxdesc()
265 sys_write32((uint32_t)&p->tx_desc_ring[0], in eth_cyclonev_setup_txdesc()
519 sys_write32(EMAC_DMAGRP_STATUS_TS_SET_MSK, in eth_cyclonev_send()
523 sys_write32(0, in eth_cyclonev_send()
560 sys_write32(EMAC_DMA_INT_EN_NIE_SET_MSK, in eth_cyclonev_isr()
568 sys_write32(EMAC_DMA_INT_EN_TIE_SET_MSK, in eth_cyclonev_isr()
576 sys_write32(EMAC_DMA_INT_EN_RIE_SET_MSK, in eth_cyclonev_isr()
623 sys_write32(cfg_reg_set, GMACGRP_MAC_CONFIG_ADDR(p->base_addr)); in eth_cyclonev_isr()
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_renesas_ra_icu.c64 sys_write32(cfg & ~BIT(IELSRn_IR_POS), IELSRn_REG(irqn)); in ra_icu_clear_int_flag()
98 sys_write32(event, IELSRn_REG(irqn)); in ra_icu_irq_connect_dynamic()
117 sys_write32(0, IELSRn_REG(irqn)); in ra_icu_irq_disconnect_dynamic()
/Zephyr-latest/soc/espressif/esp32/
Dsoc.h27 sys_write32(sys_read32(mem_addr) | v, mem_addr); in esp32_set_mask32()
32 sys_write32(sys_read32(mem_addr) & ~v, mem_addr); in esp32_clear_mask32()
/Zephyr-latest/drivers/serial/
Duart_efinix_sapphire.c78 sys_write32(prescaler, UART0_CLOCK_REG_ADDR); in uart_efinix_sapphire_init()
83 sys_write32(frame_config, UART0_FRAME_REG_ADDR); in uart_efinix_sapphire_init()
/Zephyr-latest/drivers/pwm/
Dpwm_sifive.c69 sys_write32(temp, addr); in sys_set_mask()
99 sys_write32(0, PWM_REG(config, REG_PWMCMP(i))); in pwm_sifive_init()
167 sys_write32((period_cycles >> pwmscale), PWM_REG(config, REG_PWMCMP0)); in pwm_sifive_set_cycles()
170 sys_write32((pulse_cycles >> pwmscale), in pwm_sifive_set_cycles()
/Zephyr-latest/drivers/timer/
Dhpet.c147 sys_write32(val, GCONF_REG); in hpet_gconf_set()
173 sys_write32(val, TIMER0_CONF_REG); in hpet_timer_conf_set()
202 sys_write32((uint32_t)val, TIMER0_COMPARATOR_LOW_REG); in hpet_timer_comparator_set()
203 sys_write32((uint32_t)(val >> 32), TIMER0_COMPARATOR_HIGH_REG); in hpet_timer_comparator_set()
252 sys_write32(val, INTR_STATUS_REG); in hpet_int_sts_set()
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h273 sys_write32(0x87, (mem_addr_t)wrapper + 0xC80); in usbhs_post_hibernation_entry()
274 sys_write32(0x87, (mem_addr_t)wrapper + 0xC84); in usbhs_post_hibernation_entry()
275 sys_write32(1, (mem_addr_t)wrapper + 0x004); in usbhs_post_hibernation_entry()
289 sys_write32(0, (mem_addr_t)wrapper + 0xC80); in usbhs_pre_hibernation_exit()
290 sys_write32(0, (mem_addr_t)wrapper + 0xC84); in usbhs_pre_hibernation_exit()
/Zephyr-latest/boards/snps/hsdk/
Dplatform.c16 sys_write32(HSDK_CREG_GPIO_MUX_REG, HSDK_CREG_GPIO_MUX_VAL); in hsdk_creg_gpio_mux_init()
/Zephyr-latest/drivers/spi/
Dspi_opentitan.c125 sys_write32(reg, cfg->base + SPI_HOST_CONFIGOPTS_REG_OFFSET); in spi_config()
169 sys_write32(fifo_word, cfg->base + SPI_HOST_TXDATA_REG_OFFSET); in spi_opentitan_xfer()
183 sys_write32(host_command_reg, cfg->base + SPI_HOST_COMMAND_REG_OFFSET); in spi_opentitan_xfer()
220 sys_write32(SPI_HOST_CONTROL_SW_RST_BIT, in spi_opentitan_init()
228 sys_write32(SPI_HOST_CONTROL_OUTPUT_EN_BIT | SPI_HOST_CONTROL_SPIEN_BIT, in spi_opentitan_init()
/Zephyr-latest/soc/espressif/esp32s3/
Dsoc.h32 sys_write32(sys_read32(mem_addr) | v, mem_addr); in esp32_set_mask32()
37 sys_write32(sys_read32(mem_addr) & ~v, mem_addr); in esp32_clear_mask32()

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