1 /*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #define DT_DRV_COMPAT nordic_nrf_can
7
8 #include <stdint.h>
9
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/device.h>
12 #include <zephyr/devicetree.h>
13 #include <zephyr/drivers/can.h>
14 #include <zephyr/drivers/can/can_mcan.h>
15 #include <zephyr/drivers/clock_control.h>
16 #include <zephyr/drivers/pinctrl.h>
17 #include <zephyr/irq.h>
18
19 /* nRF CAN wrapper offsets */
20 #define CAN_TASKS_START offsetof(NRF_CAN_Type, TASKS_START)
21 #define CAN_EVENTS_CORE_0 offsetof(NRF_CAN_Type, EVENTS_CORE[0])
22 #define CAN_EVENTS_CORE_1 offsetof(NRF_CAN_Type, EVENTS_CORE[1])
23 #define CAN_INTEN offsetof(NRF_CAN_Type, INTEN)
24
25 struct can_nrf_config {
26 uint32_t wrapper;
27 uint32_t mcan;
28 uint32_t mrba;
29 uint32_t mram;
30 const struct device *clock;
31 const struct pinctrl_dev_config *pcfg;
32 void (*irq_configure)(void);
33 uint16_t irq;
34 };
35
can_nrf_irq_handler(const struct device * dev)36 static void can_nrf_irq_handler(const struct device *dev)
37 {
38 const struct can_mcan_config *mcan_config = dev->config;
39 const struct can_nrf_config *config = mcan_config->custom;
40
41 if (sys_read32(config->wrapper + CAN_EVENTS_CORE_0) == 1U) {
42 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0);
43 can_mcan_line_0_isr(dev);
44 }
45
46 if (sys_read32(config->wrapper + CAN_EVENTS_CORE_1) == 1U) {
47 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1);
48 can_mcan_line_1_isr(dev);
49 }
50 }
51
can_nrf_get_core_clock(const struct device * dev,uint32_t * rate)52 static int can_nrf_get_core_clock(const struct device *dev, uint32_t *rate)
53 {
54 const struct can_mcan_config *mcan_config = dev->config;
55 const struct can_nrf_config *config = mcan_config->custom;
56
57 return clock_control_get_rate(config->clock, NULL, rate);
58 }
59
60 static DEVICE_API(can, can_nrf_api) = {
61 .get_capabilities = can_mcan_get_capabilities,
62 .start = can_mcan_start,
63 .stop = can_mcan_stop,
64 .set_mode = can_mcan_set_mode,
65 .set_timing = can_mcan_set_timing,
66 .send = can_mcan_send,
67 .add_rx_filter = can_mcan_add_rx_filter,
68 .remove_rx_filter = can_mcan_remove_rx_filter,
69 .get_state = can_mcan_get_state,
70 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
71 .recover = can_mcan_recover,
72 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
73 .get_core_clock = can_nrf_get_core_clock,
74 .get_max_filters = can_mcan_get_max_filters,
75 .set_state_change_callback = can_mcan_set_state_change_callback,
76 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
77 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
78 #ifdef CONFIG_CAN_FD_MODE
79 .set_timing_data = can_mcan_set_timing_data,
80 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
81 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
82 #endif /* CONFIG_CAN_FD_MODE */
83 };
84
can_nrf_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)85 static int can_nrf_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
86 {
87 const struct can_mcan_config *mcan_config = dev->config;
88 const struct can_nrf_config *config = mcan_config->custom;
89
90 return can_mcan_sys_read_reg(config->mcan, reg, val);
91 }
92
can_nrf_write_reg(const struct device * dev,uint16_t reg,uint32_t val)93 static int can_nrf_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
94 {
95 const struct can_mcan_config *mcan_config = dev->config;
96 const struct can_nrf_config *config = mcan_config->custom;
97
98 return can_mcan_sys_write_reg(config->mcan, reg, val);
99 }
100
can_nrf_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)101 static int can_nrf_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
102 {
103 const struct can_mcan_config *mcan_config = dev->config;
104 const struct can_nrf_config *config = mcan_config->custom;
105
106 return can_mcan_sys_read_mram(config->mram, offset, dst, len);
107 }
108
can_nrf_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)109 static int can_nrf_write_mram(const struct device *dev, uint16_t offset, const void *src,
110 size_t len)
111 {
112 const struct can_mcan_config *mcan_config = dev->config;
113 const struct can_nrf_config *config = mcan_config->custom;
114
115 return can_mcan_sys_write_mram(config->mram, offset, src, len);
116 }
117
can_nrf_clear_mram(const struct device * dev,uint16_t offset,size_t len)118 static int can_nrf_clear_mram(const struct device *dev, uint16_t offset, size_t len)
119 {
120 const struct can_mcan_config *mcan_config = dev->config;
121 const struct can_nrf_config *config = mcan_config->custom;
122
123 return can_mcan_sys_clear_mram(config->mram, offset, len);
124 }
125
126 static const struct can_mcan_ops can_mcan_nrf_ops = {
127 .read_reg = can_nrf_read_reg,
128 .write_reg = can_nrf_write_reg,
129 .read_mram = can_nrf_read_mram,
130 .write_mram = can_nrf_write_mram,
131 .clear_mram = can_nrf_clear_mram,
132 };
133
can_nrf_init(const struct device * dev)134 static int can_nrf_init(const struct device *dev)
135 {
136 const struct can_mcan_config *mcan_config = dev->config;
137 const struct can_nrf_config *config = mcan_config->custom;
138 int ret;
139
140 if (!device_is_ready(config->clock)) {
141 return -ENODEV;
142 }
143
144 ret = clock_control_on(config->clock, NULL);
145 if (ret < 0) {
146 return ret;
147 }
148
149 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
150 if (ret < 0) {
151 return ret;
152 }
153
154 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0);
155 sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1);
156 sys_write32(CAN_INTEN_CORE0_Msk | CAN_INTEN_CORE1_Msk, config->wrapper + CAN_INTEN);
157 sys_write32(1U, config->wrapper + CAN_TASKS_START);
158
159 config->irq_configure();
160
161 ret = can_mcan_configure_mram(dev, config->mrba, config->mram);
162 if (ret < 0) {
163 return ret;
164 }
165
166 ret = can_mcan_init(dev);
167 if (ret < 0) {
168 return ret;
169 }
170
171 return 0;
172 }
173
174 #define CAN_NRF_DEFINE(n) \
175 PINCTRL_DT_INST_DEFINE(n); \
176 \
177 static inline void can_nrf_irq_configure##n(void) \
178 { \
179 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), can_nrf_irq_handler, \
180 DEVICE_DT_INST_GET(n), 0); \
181 irq_enable(DT_INST_IRQN(n)); \
182 } \
183 \
184 static const struct can_nrf_config can_nrf_config##n = { \
185 .wrapper = DT_INST_REG_ADDR_BY_NAME(n, wrapper), \
186 .mcan = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
187 .mrba = CAN_MCAN_DT_INST_MRBA(n), \
188 .mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
189 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
190 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
191 .irq = DT_INST_IRQN(n), \
192 .irq_configure = can_nrf_irq_configure##n, \
193 }; \
194 \
195 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, can_mcan_nrf_cbs##n); \
196 \
197 static const struct can_mcan_config can_mcan_nrf_config##n = CAN_MCAN_DT_CONFIG_INST_GET( \
198 n, &can_nrf_config##n, &can_mcan_nrf_ops, &can_mcan_nrf_cbs##n); \
199 \
200 static struct can_mcan_data can_mcan_nrf_data##n = CAN_MCAN_DATA_INITIALIZER(NULL); \
201 \
202 DEVICE_DT_INST_DEFINE(n, can_nrf_init, NULL, &can_mcan_nrf_data##n, \
203 &can_mcan_nrf_config##n, POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
204 &can_nrf_api);
205
206 DT_INST_FOREACH_STATUS_OKAY(CAN_NRF_DEFINE)
207
