1 /*
2 * Copyright (c) 2023 Efinix Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT efinix_sapphire_uart0
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/uart.h>
11 #include <zephyr/init.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/types.h>
14
15 #define UART_IRQ DT_INST_IRQN(0)
16 #define UART0_BASE_ADDR DT_INST_REG_ADDR(0)
17
18 #define BSP_UART_DATA 0x00
19 #define BSP_UART_STATUS 0x04
20 #define BSP_UART_CLOCK_DIVIDER 0x08
21 #define BSP_UART_FRAME_CONFIG 0x0C
22
23 #define BSP_UART_WRITE_AVAILABILITY_MASK GENMASK(23, 16)
24 #define BSP_UART_READ_OCCUPANCY_MASK GENMASK(31, 24)
25
26 #define UART0_DATA_REG_ADDR UART0_BASE_ADDR + BSP_UART_DATA
27 #define UART0_STATUS_REG_ADDR UART0_BASE_ADDR + BSP_UART_STATUS
28 #define UART0_CLOCK_REG_ADDR UART0_BASE_ADDR + BSP_UART_CLOCK_DIVIDER
29 #define UART0_FRAME_REG_ADDR UART0_BASE_ADDR + BSP_UART_FRAME_CONFIG
30
31 #define UART0_SAMPLE_PER_BAUD 8
32 #define UART0_PARITY 0 /* Off */
33 #define UART0_STOP 0 /* 1 stop bit */
34
35
36 struct uart_efinix_sapphire_config {
37 uint32_t baudrate;
38 };
39
uart_efinix_sapphire_poll_out(const struct device * dev,unsigned char c)40 static void uart_efinix_sapphire_poll_out(const struct device *dev, unsigned char c)
41 {
42 /* uart_writeAvailability */
43 while ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_WRITE_AVAILABILITY_MASK) == 0) {
44 }
45
46 sys_write8(c, UART0_DATA_REG_ADDR);
47 }
48
uart_efinix_sapphire_poll_in(const struct device * dev,unsigned char * c)49 static int uart_efinix_sapphire_poll_in(const struct device *dev, unsigned char *c)
50 {
51
52 if ((sys_read32(UART0_STATUS_REG_ADDR) & BSP_UART_READ_OCCUPANCY_MASK) != 0) {
53 *c = (unsigned char)sys_read8(UART0_DATA_REG_ADDR);
54 return 0;
55 }
56
57 return -1;
58 }
59
60 static DEVICE_API(uart, uart_efinix_sapphire_api) = {
61 .poll_in = uart_efinix_sapphire_poll_in,
62 .poll_out = uart_efinix_sapphire_poll_out,
63 .err_check = NULL,
64 };
65
66 static const struct uart_efinix_sapphire_config uart_efinix_sapphire_cfg_0 = {
67 .baudrate = DT_INST_PROP(0, current_speed),
68 };
69
uart_efinix_sapphire_init(const struct device * dev)70 static int uart_efinix_sapphire_init(const struct device *dev)
71 {
72 ARG_UNUSED(dev);
73
74 uint32_t prescaler = ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC /
75 (uart_efinix_sapphire_cfg_0.baudrate * UART0_SAMPLE_PER_BAUD)) -
76 1) &
77 0xFFFFF;
78 sys_write32(prescaler, UART0_CLOCK_REG_ADDR);
79
80 /* 8 data bits, no parity, 1 stop bit */
81 uint32_t frame_config = (UART0_SAMPLE_PER_BAUD - 1) | UART0_PARITY << 8 | UART0_STOP << 16;
82
83 sys_write32(frame_config, UART0_FRAME_REG_ADDR);
84
85 return 0;
86 }
87
88 /* Device tree instance 0 init */
89 DEVICE_DT_INST_DEFINE(0, uart_efinix_sapphire_init, NULL, NULL, &uart_efinix_sapphire_cfg_0,
90 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, (void *)&uart_efinix_sapphire_api);
91
