1 /*
2 * Copyright (c) 2022 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT sifive_pinctrl
8
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>
13
14 #include <soc.h>
15
16 #define MAX_PIN_NUM DT_PROP(DT_INST_PARENT(0), ngpios)
17 #define PINCTRL_BASE_ADDR DT_INST_REG_ADDR(0)
18 #define PINCTRL_IOF_EN (PINCTRL_BASE_ADDR + 0x0)
19 #define PINCTRL_IOF_SEL (PINCTRL_BASE_ADDR + 0x4)
20
pinctrl_sifive_set(uint32_t pin,uint32_t func)21 static int pinctrl_sifive_set(uint32_t pin, uint32_t func)
22 {
23 uint32_t val;
24
25 if (func > SIFIVE_PINMUX_IOF1 || pin >= MAX_PIN_NUM) {
26 return -EINVAL;
27 }
28
29 val = sys_read32(PINCTRL_IOF_SEL);
30 if (func == SIFIVE_PINMUX_IOF1) {
31 val |= (SIFIVE_PINMUX_IOF1 << pin);
32 } else {
33 val &= ~(SIFIVE_PINMUX_IOF1 << pin);
34 }
35 sys_write32(val, PINCTRL_IOF_SEL);
36
37 /* Enable IO function for this pin */
38 val = sys_read32(PINCTRL_IOF_EN);
39 val |= BIT(pin);
40 sys_write32(val, PINCTRL_IOF_EN);
41
42 return 0;
43 }
44
45
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)46 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
47 {
48 ARG_UNUSED(reg);
49 int i;
50
51 for (i = 0; i < pin_cnt; i++) {
52 pinctrl_sifive_set(pins[i].pin, pins[i].iof);
53 }
54
55 return 0;
56 }
57
