1 /*
2 * Copyright (c) 2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef __SOC_H__
8 #define __SOC_H__
9 #include <soc/dport_reg.h>
10 #include <soc/rtc_cntl_reg.h>
11 #include <soc/soc_caps.h>
12 #include <esp32s3/rom/ets_sys.h>
13 #include <esp32s3/rom/spi_flash.h>
14 #include <esp32s3/rom/cache.h>
15 #include <esp_rom_uart.h>
16 #include <soc/extmem_reg.h>
17 #include <soc/ext_mem_defs.h>
18 #include <hal/cpu_hal.h>
19 #include <esp_rom_sys.h>
20
21 #include <zephyr/types.h>
22 #include <stdbool.h>
23 #include <zephyr/arch/xtensa/arch.h>
24
25 #include <xtensa/core-macros.h>
26 #include <esp_private/esp_clk.h>
27
28 void __esp_platform_start(void);
29
esp32_set_mask32(uint32_t v,uint32_t mem_addr)30 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
31 {
32 sys_write32(sys_read32(mem_addr) | v, mem_addr);
33 }
34
esp32_clear_mask32(uint32_t v,uint32_t mem_addr)35 static inline void esp32_clear_mask32(uint32_t v, uint32_t mem_addr)
36 {
37 sys_write32(sys_read32(mem_addr) & ~v, mem_addr);
38 }
39
esp_core_id(void)40 static inline uint32_t esp_core_id(void)
41 {
42 uint32_t id;
43
44 __asm__ volatile (
45 "rsr.prid %0\n"
46 "extui %0,%0,13,1" : "=r" (id));
47 return id;
48 }
49
50 extern void esp_rom_intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
51
52 extern int esp_rom_gpio_matrix_in(uint32_t gpio, uint32_t signal_index,
53 bool inverted);
54 extern int esp_rom_gpio_matrix_out(uint32_t gpio, uint32_t signal_index,
55 bool out_inverted,
56 bool out_enabled_inverted);
57
58 extern void esp_rom_uart_attach(void);
59 extern void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
60 extern int esp_rom_uart_tx_one_char(uint8_t chr);
61 extern int esp_rom_uart_rx_one_char(uint8_t *chr);
62 extern void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate);
63
64 extern void esp_rom_ets_set_appcpu_boot_addr(void *addr);
65 void esp_appcpu_start(void *entry_point);
66
67 extern int esp_rom_Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
68 uint32_t psize, uint32_t num, uint32_t fixed);
69 extern int esp_rom_Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,
70 uint32_t psize, uint32_t num, uint32_t fixed);
71
72 /* ROM functions which read/write internal i2c control bus for PLL, APLL */
73 extern uint8_t esp_rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
74 extern void esp_rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
75
76 #endif /* __SOC_H__ */
77
