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Searched refs:sys_read32 (Results 26 – 50 of 196) sorted by relevance

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/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c70 while (sys_read32(base) & rwp_mask) { in gic_wait_rwp()
154 val = sys_read32(ICFGR(base, idx)); in arm_gic_irq_set_priority()
215 val = sys_read32(ISENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_is_enabled()
226 val = sys_read32(ISPENDR(GET_DIST_BASE(intid), idx)); in arm_gic_irq_is_pending()
309 if (!(sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA))) { in gicv3_rdist_enable()
313 if (GICR_IIDR_PRODUCT_ID_GET(sys_read32(rdist + GICR_IIDR)) >= 0x2) { in gicv3_rdist_enable()
314 if (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) { in gicv3_rdist_enable()
317 while (sys_read32(rdist + GICR_PWRR) & BIT(GICR_PWRR_RDPD)) { in gicv3_rdist_enable()
324 while (sys_read32(rdist + GICR_WAKER) & BIT(GICR_WAKER_CA)) { in gicv3_rdist_enable()
336 unsigned int lpi_id_bits = MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), in gicv3_rdist_setup_lpis()
[all …]
Dintc_gic.c65 enabler = sys_read32(GICD_ISENABLERn + int_grp * 4); in arm_gic_irq_is_enabled()
78 enabler = sys_read32(GICD_ISPENDRn + int_grp * 4); in arm_gic_irq_is_pending()
118 val = sys_read32(GICD_ICFGRn + int_grp); in arm_gic_irq_set_priority()
143 irq = sys_read32(GICC_IAR); in arm_gic_get_active()
185 gic_irqs = sys_read32(GICD_TYPER) & 0x1f; in gic_dist_init()
274 val = sys_read32(GICC_CTLR); in gic_cpu_init()
Dintc_renesas_ra_icu.c32 uint32_t els = sys_read32(IELSRn_REG(i)) & UINT8_MAX; in ra_icu_query_exists_irq()
62 uint32_t cfg = sys_read32(IELSRn_REG(irqn)); in ra_icu_clear_int_flag()
70 *intcfg = sys_read32(IELSRn_REG(irq)); in ra_icu_query_irq_config()
/Zephyr-latest/soc/brcm/bcmvk/viper/a72/
Dsoc.c26 data = sys_read32(LS_ICFG_PMON_LITE_CLK_CTRL); in soc_early_init_hook()
30 data = sys_read32(LS_ICFG_PMON_LITE_SW_RESETN); in soc_early_init_hook()
/Zephyr-latest/drivers/i2c/
Di2c_xilinx_axi.c123 int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
146 if (sys_read32(config->base + REG_SR) & SR_SRW) { in i2c_xilinx_axi_target_isr()
163 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
185 sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_target_isr()
189 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
223 uint32_t int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_isr()
224 uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable; in i2c_xilinx_axi_isr()
231 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_isr()
247 sys_write32(ints_to_clear & sys_read32(config->base + REG_ISR), config->base + REG_ISR); in i2c_xilinx_axi_isr()
268 const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask; in i2c_xilinx_axi_wait_interrupt()
[all …]
Di2c_bcm_iproc.c180 val = sys_read32(base + CFG_OFFSET); in iproc_i2c_enable_disable()
195 val = sys_read32(base + CFG_OFFSET); in iproc_i2c_reset_controller()
219 val = sys_read32(base + S_ADDR_OFFSET); in iproc_i2c_target_set_address()
244 val = sys_read32(base + TIM_CFG_OFFSET); in iproc_i2c_target_init()
277 val = sys_read32(base + S_CMD_OFFSET); in iproc_i2c_check_target_status()
312 val = sys_read32(base + S_RX_OFFSET); in iproc_i2c_target_read()
382 val = sys_read32(base + IE_OFFSET); in iproc_i2c_target_isr()
442 val = sys_read32(base + S_FIFO_CTRL_OFFSET); in iproc_i2c_target_isr()
496 val = sys_read32(base + IE_OFFSET); in iproc_i2c_target_unregister()
530 val = sys_read32(base + M_CMD_OFFSET); in iproc_i2c_check_status()
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/Zephyr-latest/drivers/dma/
Ddma_iproc_pax_v2.c265 if ((sys_read32(RM_COMM_REG(pd, RM_COMM_MAIN_HW_INIT_DONE)) & in init_rm()
290 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
307 val = sys_read32(RM_COMM_REG(pd, RM_COMM_AXI_READ_BURST_THRESHOLD)); in rm_cfg_start()
314 val = sys_read32(RM_COMM_REG(pd, RM_COMM_FIFO_FULL_THRESHOLD)); in rm_cfg_start()
327 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
334 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
339 val = sys_read32(RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
346 val = sys_read32(RM_COMM_REG(pd, RM_COMM_AXI_CONTROL)); in rm_cfg_start()
355 val = sys_read32(RM_COMM_REG(pd, RM_COMM_BURST_LENGTH)); in rm_cfg_start()
362 val = sys_read32(RM_COMM_REG(pd, RM_COMM_BD_FETCH_MODE_CONTROL)); in rm_cfg_start()
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Ddma_iproc_pax_v1.c244 if ((sys_read32(RM_COMM_REG(pd, RM_COMM_MAIN_HW_INIT_DONE)) & in init_rm()
269 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
281 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
288 val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL)); in rm_cfg_start()
293 val = sys_read32(RM_COMM_REG(pd, RM_AE0_AE_CONTROL)); in rm_cfg_start()
300 val = sys_read32(RM_COMM_REG(pd, RM_COMM_AXI_CONTROL)); in rm_cfg_start()
313 val = sys_read32(RM_COMM_REG(pd, RM_COMM_MASK_SEQUENCE_MAX_COUNT)); in rm_cfg_start()
324 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_RECV_LS)); in rm_ring_clear_stats()
325 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_RECV_MS)); in rm_ring_clear_stats()
326 sys_read32(RM_RING_REG(pd, idx, RING_NUM_REQ_TRANS_LS)); in rm_ring_clear_stats()
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/Zephyr-latest/drivers/serial/
Duart_altera_jtag.c94 input_data = sys_read32(config->base + UART_ALTERA_JTAG_DATA_OFFSET); in uart_altera_jtag_poll_in()
133 while (!(sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET) & UART_WFIFO_MASK)) { in uart_altera_jtag_poll_out()
161 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_init()
215 ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_fifo_fill()
260 input_data = sys_read32(config->base + UART_ALTERA_JTAG_DATA_OFFSET); in uart_altera_jtag_fifo_read()
285 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_enable()
304 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_disable()
326 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_ready()
357 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_tx_complete()
383 uint32_t ctrl_val = sys_read32(config->base + UART_ALTERA_JTAG_CTRL_OFFSET); in uart_altera_jtag_irq_rx_enable()
[all …]
Duart_opentitan.c75 if (sys_read32(cfg->base + UART_STATUS_REG_OFFSET) & UART_STATUS_RXEMPTY_BIT) { in uart_opentitan_poll_in()
79 *c = sys_read32(cfg->base + UART_RDATA_REG_OFFSET); in uart_opentitan_poll_in()
88 while (sys_read32(cfg->base + UART_STATUS_REG_OFFSET) & in uart_opentitan_poll_out()
/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.h105 (sys_read32(SPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK)
110 (sys_read32(SPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK)
114 #define TX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_TX_NUM_MSK)
115 #define RX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_RX_NUM_MSK)
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.h109 (sys_read32(QSPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK)
114 (sys_read32(QSPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK)
118 #define TX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_TX_NUM_MSK)
119 #define RX_NUM_STAT(base) (sys_read32(QSPI_STAT(base)) & STAT_RX_NUM_MSK)
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h757 uint32_t status = sys_read32(CW_BASE + USSTS); in cw_upstream_ready()
761 return !(sys_read32(CW_BASE + USSTS) & USSTS_SMSTS); in cw_upstream_ready()
810 uint32_t cmd = sys_read32(CW_BASE + USCMD); in cw_upstream_enable_sent_intr()
826 uint32_t cmd = sys_read32(CW_BASE + USCMD); in cw_upstream_do_pw()
841 uint32_t sts = sys_read32(CW_BASE + USSTS); in cw_upstream_clear_msgsent()
852 WAIT_FOR(sys_read32(CW_BASE + USSTS) & USSTS_MSGSENT, 100, k_busy_wait(1)); in cw_upstream_wait_for_sent()
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c188 while (!(sys_read32(addr) & bit)) { in dwc2_wait_for_bit()
224 dtxfsts = sys_read32(reg); in dwc2_ftx_avail()
257 while (sys_read32(grstctl_reg) & USB_DWC2_GRSTCTL_RXFFLSH) { in dwc2_flush_rx_fifo()
270 while (sys_read32(grstctl_reg) & USB_DWC2_GRSTCTL_TXFFLSH) { in dwc2_flush_tx_fifo()
280 dieptxf = sys_read32((mem_addr_t)&base->dieptxf[f_idx]); in dwc2_get_txfdep()
291 dieptxf = sys_read32((mem_addr_t)&base->dieptxf[f_idx]); in dwc2_get_txfaddr()
481 diepctl = sys_read32(diepctl_reg); in dwc2_tx_fifo_write()
552 net_buf_add_le32(buf, sys_read32(UDC_DWC2_EP_FIFO(base, ep))); in dwc2_read_fifo()
559 sys_put_le32(sys_read32(UDC_DWC2_EP_FIFO(base, ep)), r); in dwc2_read_fifo()
567 (void)sys_read32(UDC_DWC2_EP_FIFO(base, ep)); in dwc2_read_fifo()
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/Zephyr-latest/drivers/i3c/
Di3c_cdns.c678 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_cmd_rsp_fifo_empty()
686 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_cmd_fifo_empty()
694 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_cmd_fifo_full()
702 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_ibi_rsp_fifo_empty()
710 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_tx_fifo_full()
718 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_rx_fifo_full()
726 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_rx_fifo_empty()
734 uint32_t mst_st = sys_read32(config->base + MST_STATUS0); in cdns_i3c_ibi_fifo_empty()
816 SLV_STATUS0_XFRD_BYTES(sys_read32(config->base + SLV_STATUS0)); in cdns_i3c_target_read_rx_fifo()
819 uint32_t rx_data = sys_read32(config->base + RX_FIFO); in cdns_i3c_target_read_rx_fifo()
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/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc_msi.c15 #define sys_read64(addr) (((uint64_t)(sys_read32(addr + 4)) << 32) | \
16 sys_read32(addr))
98 data = sys_read32(MSIX_VECTOR_OFF(msix_num) + MSIX_TBL_DATA_OFF); in generate_msix()
127 data = sys_read32(MSIX_VECTOR_OFF(msix_num) + MSIX_TBL_VECTOR_CTRL_OFF); in is_msix_vector_mask()
200 sys_read32(PMON_LITE_PCIE_INTERRUPT_STATUS)); in iproc_pcie_vector_mask_isr()
/Zephyr-latest/soc/nordic/nrf92/
Dsoc.c62 .vsup = sys_read32(FICR_ADDR_GET(HSFLL_NODE, vsup)), in trim_hsfll()
63 .coarse = sys_read32(FICR_ADDR_GET(HSFLL_NODE, coarse)), in trim_hsfll()
64 .fine = sys_read32(FICR_ADDR_GET(HSFLL_NODE, fine)) in trim_hsfll()
/Zephyr-latest/drivers/gpio/
Dgpio_mchp_xec_v2.c82 uint32_t r = (sys_read32(addr) & ~mask) | (val & mask); in xec_mask_write32()
145 pcr1 = sys_read32(pcr1_addr); in gpio_xec_configure()
181 pcr1 = sys_read32(pcr1_addr); in gpio_xec_configure()
291 pcr1 = sys_read32(pcr1_addr); in gpio_xec_pin_interrupt_configure()
323 sys_read32(pcr1_addr); in gpio_xec_pin_interrupt_configure()
348 sys_write32(sys_read32(pout_addr) | mask, pout_addr); in gpio_xec_port_set_bits_raw()
358 sys_write32(sys_read32(pout_addr) & ~mask, pout_addr); in gpio_xec_port_clear_bits_raw()
367 sys_write32(sys_read32(pout_addr) ^ mask, pout_addr); in gpio_xec_port_toggle_bits()
376 *value = sys_read32(pin_addr); in gpio_xec_port_get_raw()
410 uint32_t pcr1 = sys_read32(pcr1_addr); in gpio_xec_get_direction()
[all …]
Dgpio_iproc.c68 *value = sys_read32(base + IPROC_GPIO_DATA_IN_OFFSET); in gpio_iproc_port_get_raw()
78 value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_set_masked_raw()
102 value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_clear_bits_raw()
116 value = sys_read32(base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_toggle_bits()
165 int_stat = sys_read32(base + IPROC_GPIO_INT_STAT_OFFSET); in gpio_iproc_isr()
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.c55 data = sys_read32(phy_reg_data); in sdhc_cdns_write_phy_reg()
68 if (!WAIT_FOR(((sys_read32(cdn_srs_res) & CDNS_SRS11_ICS) in sdhc_cdns_wait_ics()
81 data = sys_read32(cdns_params.reg_base + SDHC_CDNS_SRS09); in sdhc_cdns_busy()
89 if (!WAIT_FOR((((sys_read32(cdns_params.reg_base + SDHC_CDNS_SRS09)) in sdhc_cdns_card_present()
244 value = sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS05); in sdhc_cdns_program_phy_reg()
252 value = sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS09); in sdhc_cdns_program_phy_reg()
255 value = sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS09); in sdhc_cdns_program_phy_reg()
378 sys_write32(((sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS09) in sdhc_cdns_host_set_clk()
515 sys_write32(((sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS09) & in sdhc_cdns_set_clk()
541 if (!WAIT_FOR(((sys_read32(cdns_params.reg_base + SDHC_CDNS_HRS00) & in sdhc_cdns_reset()
[all …]
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dsoc.c54 uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET); in soc_enable_irq()
62 uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_CLR_OFFSET); in soc_disable_irq()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_sifive.c29 val = sys_read32(PINCTRL_IOF_SEL); in pinctrl_sifive_set()
38 val = sys_read32(PINCTRL_IOF_EN); in pinctrl_sifive_set()
/Zephyr-latest/drivers/timer/
Dhpet.c104 high = sys_read32(MAIN_COUNTER_HIGH_REG); in hpet_counter_get()
105 low = sys_read32(MAIN_COUNTER_LOW_REG); in hpet_counter_get()
106 } while (high != sys_read32(MAIN_COUNTER_HIGH_REG)); in hpet_counter_get()
127 return sys_read32(CLK_PERIOD_REG); in hpet_counter_clk_period_get()
137 return sys_read32(GCONF_REG); in hpet_gconf_get()
160 return sys_read32(TIMER0_CONF_REG); in hpet_timer_conf_get()
/Zephyr-latest/drivers/watchdog/
Dwdt_opentitan.c42 (void) sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_setup()
53 if (!sys_read32(regs + OT_REG_WDOG_REGWEN_OFFSET)) { in ot_aontimer_disable()
58 uint32_t ctrl_val = sys_read32(regs + OT_REG_WDOG_CTRL_OFFSET); in ot_aontimer_disable()
115 if (!sys_read32(reg_base + OT_REG_WDOG_REGWEN_OFFSET)) { in ot_aontimer_install_timeout()
121 if (sys_read32(reg_base + OT_REG_WDOG_CTRL_OFFSET) & BIT(0)) { in ot_aontimer_install_timeout()
/Zephyr-latest/soc/espressif/esp32/
Dsoc.h27 sys_write32(sys_read32(mem_addr) | v, mem_addr); in esp32_set_mask32()
32 sys_write32(sys_read32(mem_addr) & ~v, mem_addr); in esp32_clear_mask32()

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