1 /*
2 * Copyright 2020 Broadcom
3 * Copyright 2024 Meta Platforms
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT brcm_iproc_i2c
9
10 #include <errno.h>
11 #include <stdint.h>
12
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/logging/log.h>
16
17 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
18 LOG_MODULE_REGISTER(iproc_i2c);
19
20 #include "i2c-priv.h"
21
22 /* Registers */
23 #define CFG_OFFSET 0x00
24 #define CFG_RESET_SHIFT 31
25 #define CFG_EN_SHIFT 30
26 #define CFG_M_RETRY_CNT_SHIFT 16
27 #define CFG_M_RETRY_CNT_MASK 0x0f
28
29 #define TIM_CFG_OFFSET 0x04
30 #define TIM_CFG_MODE_400_SHIFT 31
31 #define TIM_RAND_TARGET_STRETCH_SHIFT 24
32 #define TIM_RAND_TARGET_STRETCH_MASK 0x7f
33
34 #define S_ADDR_OFFSET 0x08
35 #define S_ADDR_OFFSET_ADDR0_MASK 0x7f
36 #define S_ADDR_OFFSET_ADDR0_SHIFT 0
37 #define S_ADDR_OFFSET_ADDR0_EN_BIT 7
38
39 #define M_FIFO_CTRL_OFFSET 0x0c
40 #define M_FIFO_RX_FLUSH_SHIFT 31
41 #define M_FIFO_TX_FLUSH_SHIFT 30
42 #define M_FIFO_RX_CNT_SHIFT 16
43 #define M_FIFO_RX_CNT_MASK 0x7f
44 #define M_FIFO_RX_THLD_SHIFT 8
45 #define M_FIFO_RX_THLD_MASK 0x3f
46
47 #define S_FIFO_CTRL_OFFSET 0x10
48 #define S_FIFO_RX_FLUSH_SHIFT 31
49 #define S_FIFO_TX_FLUSH_SHIFT 30
50
51 #define M_CMD_OFFSET 0x30
52 #define M_CMD_START_BUSY_SHIFT 31
53 #define M_CMD_STATUS_SHIFT 25
54 #define M_CMD_STATUS_MASK 0x07
55 #define M_CMD_STATUS_SUCCESS 0x0
56 #define M_CMD_STATUS_LOST_ARB 0x1
57 #define M_CMD_STATUS_NACK_ADDR 0x2
58 #define M_CMD_STATUS_NACK_DATA 0x3
59 #define M_CMD_STATUS_TIMEOUT 0x4
60 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
61 #define M_CMD_STATUS_RX_FIFO_FULL 0x6
62 #define M_CMD_SMB_PROT_SHIFT 9
63 #define M_CMD_SMB_PROT_QUICK 0x0
64 #define M_CMD_SMB_PROT_MASK 0xf
65 #define M_CMD_SMB_PROT_BLK_WR 0x7
66 #define M_CMD_SMB_PROT_BLK_RD 0x8
67 #define M_CMD_PEC_SHIFT 8
68 #define M_CMD_RD_CNT_MASK 0xff
69
70 #define S_CMD_OFFSET 0x34
71 #define S_CMD_START_BUSY_SHIFT 31
72 #define S_CMD_STATUS_SHIFT 23
73 #define S_CMD_STATUS_MASK 0x07
74 #define S_CMD_STATUS_TIMEOUT 0x5
75 #define S_CMD_STATUS_MASTER_ABORT 0x7
76
77 #define IE_OFFSET 0x38
78 #define IE_M_RX_FIFO_FULL_SHIFT 31
79 #define IE_M_RX_THLD_SHIFT 30
80 #define IE_M_START_BUSY_SHIFT 28
81 #define IE_M_TX_UNDERRUN_SHIFT 27
82 #define IE_S_RX_FIFO_FULL_SHIFT 26
83 #define IE_S_RX_THLD_SHIFT 25
84 #define IE_S_RX_EVENT_SHIFT 24
85 #define IE_S_START_BUSY_SHIFT 23
86 #define IE_S_TX_UNDERRUN_SHIFT 22
87 #define IE_S_RD_EN_SHIFT 21
88
89 #define IS_OFFSET 0x3c
90 #define IS_M_RX_FIFO_FULL_SHIFT 31
91 #define IS_M_RX_THLD_SHIFT 30
92 #define IS_M_START_BUSY_SHIFT 28
93 #define IS_M_TX_UNDERRUN_SHIFT 27
94 #define IS_S_RX_FIFO_FULL_SHIFT 26
95 #define IS_S_RX_THLD_SHIFT 25
96 #define IS_S_RX_EVENT_SHIFT 24
97 #define IS_S_START_BUSY_SHIFT 23
98 #define IS_S_TX_UNDERRUN_SHIFT 22
99 #define IS_S_RD_EN_SHIFT 21
100
101 #define M_TX_OFFSET 0x40
102 #define M_TX_WR_STATUS_SHIFT 31
103 #define M_TX_DATA_MASK 0xff
104
105 #define M_RX_OFFSET 0x44
106 #define M_RX_STATUS_SHIFT 30
107 #define M_RX_STATUS_MASK 0x03
108 #define M_RX_PEC_ERR_SHIFT 29
109 #define M_RX_DATA_SHIFT 0
110 #define M_RX_DATA_MASK 0xff
111
112 #define S_TX_OFFSET 0x48
113 #define S_TX_WR_STATUS_SHIFT 31
114
115 #define S_RX_OFFSET 0x4c
116 #define S_RX_STATUS_SHIFT 30
117 #define S_RX_STATUS_MASK 0x03
118 #define S_RX_DATA_SHIFT 0x0
119 #define S_RX_DATA_MASK 0xff
120
121 #define I2C_TIMEOUT_MSEC 100
122 #define TX_RX_FIFO_SIZE 64
123 #define M_RX_FIFO_MAX_THLD_VALUE (TX_RX_FIFO_SIZE - 1)
124 #define M_RX_FIFO_THLD_VALUE 50
125
126 #define I2C_MAX_TARGET_ADDR 0x7f
127
128 #define I2C_TARGET_RX_FIFO_EMPTY 0x0
129 #define I2C_TARGET_RX_START 0x1
130 #define I2C_TARGET_RX_DATA 0x2
131 #define I2C_TARGET_RX_END 0x3
132
133 #define IE_S_ALL_INTERRUPT_SHIFT 21
134 #define IE_S_ALL_INTERRUPT_MASK 0x3f
135
136 #define TARGET_CLOCK_STRETCH_TIME 25
137
138 /*
139 * To keep running in ISR for less time,
140 * max target read per interrupt is set to 10 bytes.
141 */
142 #define MAX_TARGET_RX_PER_INT 10
143
144 #define ISR_MASK_TARGET \
145 (BIT(IS_S_START_BUSY_SHIFT) | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EN_SHIFT) | \
146 BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT) | BIT(IS_S_RX_THLD_SHIFT))
147
148 #define ISR_MASK \
149 (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT) | BIT(IS_M_RX_THLD_SHIFT))
150
151 #define DEV_CFG(dev) ((struct iproc_i2c_config *)(dev)->config)
152 #define DEV_DATA(dev) ((struct iproc_i2c_data *)(dev)->data)
153 #define DEV_BASE(dev) ((DEV_CFG(dev))->base)
154
155 struct iproc_i2c_config {
156 mem_addr_t base;
157 uint32_t bitrate;
158 void (*irq_config_func)(const struct device *dev);
159 };
160
161 struct iproc_i2c_data {
162 struct i2c_target_config *target_cfg;
163 struct i2c_msg *msg;
164 uint32_t tx_bytes;
165 uint32_t rx_bytes;
166 uint32_t thld_bytes;
167 uint32_t tx_underrun;
168 struct k_sem device_sync_sem;
169 uint32_t target_int_mask;
170 bool rx_start_rcvd;
171 bool target_read_complete;
172 bool target_rx_only;
173 };
174
iproc_i2c_enable_disable(const struct device * dev,bool enable)175 static void iproc_i2c_enable_disable(const struct device *dev, bool enable)
176 {
177 mem_addr_t base = DEV_BASE(dev);
178 uint32_t val;
179
180 val = sys_read32(base + CFG_OFFSET);
181 if (enable) {
182 val |= BIT(CFG_EN_SHIFT);
183 } else {
184 val &= ~BIT(CFG_EN_SHIFT);
185 }
186 sys_write32(val, base + CFG_OFFSET);
187 }
188
iproc_i2c_reset_controller(const struct device * dev)189 static void iproc_i2c_reset_controller(const struct device *dev)
190 {
191 mem_addr_t base = DEV_BASE(dev);
192 uint32_t val;
193
194 /* put controller in reset */
195 val = sys_read32(base + CFG_OFFSET);
196 val |= BIT(CFG_RESET_SHIFT);
197 val &= ~BIT(CFG_EN_SHIFT);
198 sys_write32(val, base + CFG_OFFSET);
199
200 k_busy_wait(100);
201
202 /* bring controller out of reset */
203 sys_clear_bit(base + CFG_OFFSET, CFG_RESET_SHIFT);
204 }
205
206 #ifdef CONFIG_I2C_TARGET
207 /* Set target addr */
iproc_i2c_target_set_address(const struct device * dev,uint16_t addr)208 static int iproc_i2c_target_set_address(const struct device *dev, uint16_t addr)
209 {
210 mem_addr_t base = DEV_BASE(dev);
211 uint32_t val;
212
213 if ((addr == 0) && (addr > I2C_MAX_TARGET_ADDR)) {
214 LOG_ERR("Invalid target address(0x%x) received", addr);
215 return -EINVAL;
216 }
217
218 addr = ((addr & S_ADDR_OFFSET_ADDR0_MASK) | BIT(S_ADDR_OFFSET_ADDR0_EN_BIT));
219 val = sys_read32(base + S_ADDR_OFFSET);
220 val &= ~(S_ADDR_OFFSET_ADDR0_MASK | BIT(S_ADDR_OFFSET_ADDR0_EN_BIT));
221 val |= addr;
222 sys_write32(val, base + S_ADDR_OFFSET);
223
224 return 0;
225 }
226
iproc_i2c_target_init(const struct device * dev,bool need_reset)227 static int iproc_i2c_target_init(const struct device *dev, bool need_reset)
228 {
229 struct iproc_i2c_data *dd = DEV_DATA(dev);
230 mem_addr_t base = DEV_BASE(dev);
231 struct i2c_target_config *target_config = dd->target_cfg;
232 uint32_t val;
233 int ret;
234
235 if (need_reset) {
236 iproc_i2c_reset_controller(dev);
237 }
238
239 /* flush target TX/RX FIFOs */
240 val = BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT);
241 sys_write32(val, base + S_FIFO_CTRL_OFFSET);
242
243 /* Maximum target stretch time */
244 val = sys_read32(base + TIM_CFG_OFFSET);
245 val &= ~(TIM_RAND_TARGET_STRETCH_MASK << TIM_RAND_TARGET_STRETCH_SHIFT);
246 val |= (TARGET_CLOCK_STRETCH_TIME << TIM_RAND_TARGET_STRETCH_SHIFT);
247 sys_write32(val, base + TIM_CFG_OFFSET);
248
249 /* Set target address */
250 ret = iproc_i2c_target_set_address(dev, target_config->address);
251 if (ret) {
252 return ret;
253 }
254
255 /* clear all pending target interrupts */
256 sys_write32(ISR_MASK_TARGET, base + IS_OFFSET);
257
258 /* Enable interrupt register to indicate a valid byte in receive fifo */
259 val = BIT(IE_S_RX_EVENT_SHIFT);
260 /* Enable interrupt register to indicate target Rx FIFO Full */
261 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
262 /* Enable interrupt register to indicate a Master read transaction */
263 val |= BIT(IE_S_RD_EN_SHIFT);
264 /* Enable interrupt register for the target BUSY command */
265 val |= BIT(IE_S_START_BUSY_SHIFT);
266 dd->target_int_mask = val;
267 sys_write32(val, base + IE_OFFSET);
268
269 return ret;
270 }
271
iproc_i2c_check_target_status(const struct device * dev)272 static int iproc_i2c_check_target_status(const struct device *dev)
273 {
274 mem_addr_t base = DEV_BASE(dev);
275 uint32_t val;
276
277 val = sys_read32(base + S_CMD_OFFSET);
278 /* status is valid only when START_BUSY is cleared after it was set */
279 if (val & BIT(S_CMD_START_BUSY_SHIFT)) {
280 return -EBUSY;
281 }
282
283 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
284 if ((val == S_CMD_STATUS_TIMEOUT) || (val == S_CMD_STATUS_MASTER_ABORT)) {
285 if (val == S_CMD_STATUS_TIMEOUT) {
286 LOG_ERR("target random stretch time timeout");
287 } else if (val == S_CMD_STATUS_MASTER_ABORT) {
288 LOG_ERR("Master aborted read transaction");
289 }
290
291 /* re-initialize i2c for recovery */
292 iproc_i2c_enable_disable(dev, false);
293 iproc_i2c_target_init(dev, true);
294 iproc_i2c_enable_disable(dev, true);
295
296 return -ETIMEDOUT;
297 }
298
299 return 0;
300 }
301
iproc_i2c_target_read(const struct device * dev)302 static void iproc_i2c_target_read(const struct device *dev)
303 {
304 struct iproc_i2c_data *dd = DEV_DATA(dev);
305 struct i2c_target_config *target_cfg = dd->target_cfg;
306 mem_addr_t base = DEV_BASE(dev);
307 uint8_t rx_data, rx_status;
308 uint32_t rx_bytes = 0;
309 uint32_t val;
310
311 while (rx_bytes < MAX_TARGET_RX_PER_INT) {
312 val = sys_read32(base + S_RX_OFFSET);
313 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
314 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
315
316 if (rx_status == I2C_TARGET_RX_START) {
317 /* Start of SMBUS Master write */
318 target_cfg->callbacks->write_requested(target_cfg);
319 dd->rx_start_rcvd = true;
320 dd->target_read_complete = false;
321 } else if ((rx_status == I2C_TARGET_RX_DATA) && dd->rx_start_rcvd) {
322 /* Middle of SMBUS Master write */
323 target_cfg->callbacks->write_received(target_cfg, rx_data);
324 } else if ((rx_status == I2C_TARGET_RX_END) && dd->rx_start_rcvd) {
325 /* End of SMBUS Master write */
326 if (dd->target_rx_only) {
327 target_cfg->callbacks->write_received(target_cfg, rx_data);
328 }
329 target_cfg->callbacks->stop(target_cfg);
330 } else if (rx_status == I2C_TARGET_RX_FIFO_EMPTY) {
331 dd->rx_start_rcvd = false;
332 dd->target_read_complete = true;
333 break;
334 }
335
336 rx_bytes++;
337 }
338 }
339
iproc_i2c_target_rx(const struct device * dev)340 static void iproc_i2c_target_rx(const struct device *dev)
341 {
342 struct iproc_i2c_data *dd = DEV_DATA(dev);
343 mem_addr_t base = DEV_BASE(dev);
344
345 iproc_i2c_target_read(dev);
346
347 if (!dd->target_rx_only && dd->target_read_complete) {
348 /*
349 * In case of single byte master-read request,
350 * IS_S_TX_UNDERRUN_SHIFT event is generated before
351 * IS_S_START_BUSY_SHIFT event. Hence start target data send
352 * from first IS_S_TX_UNDERRUN_SHIFT event.
353 *
354 * This means don't send any data from target when
355 * IS_S_RD_EN_SHIFT event is generated else it will increment
356 * eeprom or other backend target driver read pointer twice.
357 */
358 dd->tx_underrun = 0;
359 dd->target_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
360
361 /* clear IS_S_RD_EN_SHIFT interrupt */
362 sys_write32(BIT(IS_S_RD_EN_SHIFT), base + IS_OFFSET);
363 }
364
365 /* enable target interrupts */
366 sys_write32(dd->target_int_mask, base + IE_OFFSET);
367 }
368
iproc_i2c_target_isr(const struct device * dev,uint32_t status)369 static void iproc_i2c_target_isr(const struct device *dev, uint32_t status)
370 {
371 struct iproc_i2c_data *dd = DEV_DATA(dev);
372 struct i2c_target_config *target_cfg = dd->target_cfg;
373 mem_addr_t base = DEV_BASE(dev);
374 uint32_t val;
375 uint8_t data;
376
377 LOG_DBG("iproc_i2c(0x%x): %s: sl_sts 0x%x", (uint32_t)base, __func__, status);
378
379 if (status & BIT(IS_S_RX_EVENT_SHIFT) || status & BIT(IS_S_RD_EN_SHIFT) ||
380 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
381 /* disable target interrupts */
382 val = sys_read32(base + IE_OFFSET);
383 val &= ~dd->target_int_mask;
384 sys_write32(val, base + IE_OFFSET);
385
386 if (status & BIT(IS_S_RD_EN_SHIFT)) {
387 /* Master-write-read request */
388 dd->target_rx_only = false;
389 } else {
390 /* Master-write request only */
391 dd->target_rx_only = true;
392 }
393
394 /*
395 * Clear IS_S_RX_EVENT_SHIFT &
396 * IS_S_RX_FIFO_FULL_SHIFT interrupt
397 */
398 val = BIT(IS_S_RX_EVENT_SHIFT);
399 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
400 val |= BIT(IS_S_RX_FIFO_FULL_SHIFT);
401 }
402 sys_write32(val, base + IS_OFFSET);
403
404 iproc_i2c_target_rx(dev);
405 }
406
407 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
408 dd->tx_underrun++;
409 if (dd->tx_underrun == 1) {
410 /* Start of SMBUS for Master Read */
411 target_cfg->callbacks->read_requested(target_cfg, &data);
412 } else {
413 /* Master read other than start */
414 target_cfg->callbacks->read_processed(target_cfg, &data);
415 }
416
417 sys_write32(data, base + S_TX_OFFSET);
418 /* start transfer */
419 val = BIT(S_CMD_START_BUSY_SHIFT);
420 sys_write32(val, base + S_CMD_OFFSET);
421
422 sys_write32(BIT(IS_S_TX_UNDERRUN_SHIFT), base + IS_OFFSET);
423 }
424
425 /* Stop received from master in case of master read transaction */
426 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
427 /*
428 * Disable interrupt for TX FIFO becomes empty and
429 * less than PKT_LENGTH bytes were output on the SMBUS
430 */
431 dd->target_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
432 sys_write32(dd->target_int_mask, base + IE_OFFSET);
433
434 /* End of SMBUS for Master Read */
435 val = BIT(S_TX_WR_STATUS_SHIFT);
436 sys_write32(val, base + S_TX_OFFSET);
437
438 val = BIT(S_CMD_START_BUSY_SHIFT);
439 sys_write32(val, base + S_CMD_OFFSET);
440
441 /* flush TX FIFOs */
442 val = sys_read32(base + S_FIFO_CTRL_OFFSET);
443 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
444 sys_write32(val, base + S_FIFO_CTRL_OFFSET);
445
446 target_cfg->callbacks->stop(target_cfg);
447
448 sys_write32(BIT(IS_S_START_BUSY_SHIFT), base + IS_OFFSET);
449 }
450
451 /* check target transmit status only if target is transmitting */
452 if (!dd->target_rx_only) {
453 iproc_i2c_check_target_status(dev);
454 }
455 }
456
iproc_i2c_target_register(const struct device * dev,struct i2c_target_config * target_config)457 static int iproc_i2c_target_register(const struct device *dev,
458 struct i2c_target_config *target_config)
459 {
460 struct iproc_i2c_data *dd = DEV_DATA(dev);
461 mem_addr_t base = DEV_BASE(dev);
462 int ret = 0;
463
464 if (dd->target_cfg) {
465 LOG_ERR("Target already registered");
466 return -EBUSY;
467 }
468
469 /* Save pointer to received target config */
470 dd->target_cfg = target_config;
471
472 ret = iproc_i2c_target_init(dev, false);
473 if (ret < 0) {
474 LOG_ERR("Failed to register iproc_i2c(0x%x) as target, ret %d", (uint32_t)base,
475 ret);
476 return ret;
477 }
478
479 return 0;
480 }
481
iproc_i2c_target_unregister(const struct device * dev,struct i2c_target_config * config)482 static int iproc_i2c_target_unregister(const struct device *dev, struct i2c_target_config *config)
483 {
484 uint32_t val;
485 mem_addr_t base = DEV_BASE(dev);
486 struct iproc_i2c_data *dd = DEV_DATA(dev);
487
488 if (!dd->target_cfg) {
489 return -EINVAL;
490 }
491
492 /* Erase the target address programmed */
493 sys_write32(0x0, base + S_ADDR_OFFSET);
494
495 /* disable all target interrupts */
496 val = sys_read32(base + IE_OFFSET);
497 val &= ~(IE_S_ALL_INTERRUPT_MASK << IE_S_ALL_INTERRUPT_SHIFT);
498 sys_write32(val, base + IE_OFFSET);
499
500 dd->target_cfg = NULL;
501
502 return 0;
503 }
504 #endif /* CONFIG_I2C_TARGET */
505
iproc_i2c_common_init(const struct device * dev)506 static void iproc_i2c_common_init(const struct device *dev)
507 {
508 mem_addr_t base = DEV_BASE(dev);
509 uint32_t val;
510
511 iproc_i2c_reset_controller(dev);
512
513 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
514 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
515 sys_write32(val, base + M_FIFO_CTRL_OFFSET);
516
517 /* disable all interrupts */
518 sys_write32(0, base + IE_OFFSET);
519
520 /* clear all pending interrupts */
521 sys_write32(~0, base + IS_OFFSET);
522 }
523
iproc_i2c_check_status(const struct device * dev,uint16_t dev_addr,struct i2c_msg * msg)524 static int iproc_i2c_check_status(const struct device *dev, uint16_t dev_addr, struct i2c_msg *msg)
525 {
526 mem_addr_t base = DEV_BASE(dev);
527 uint32_t val;
528 int rc;
529
530 val = sys_read32(base + M_CMD_OFFSET);
531 val >>= M_CMD_STATUS_SHIFT;
532 val &= M_CMD_STATUS_MASK;
533
534 switch (val) {
535 case M_CMD_STATUS_SUCCESS:
536 rc = 0;
537 break;
538
539 case M_CMD_STATUS_LOST_ARB:
540 LOG_ERR("lost bus arbitration");
541 rc = -EAGAIN;
542 break;
543
544 case M_CMD_STATUS_NACK_ADDR:
545 LOG_ERR("NAK addr:0x%02x", dev_addr);
546 rc = -ENXIO;
547 break;
548
549 case M_CMD_STATUS_NACK_DATA:
550 LOG_ERR("NAK data");
551 rc = -ENXIO;
552 break;
553
554 case M_CMD_STATUS_TIMEOUT:
555 LOG_ERR("bus timeout");
556 rc = -ETIMEDOUT;
557 break;
558
559 case M_CMD_STATUS_FIFO_UNDERRUN:
560 LOG_ERR("FIFO Under-run");
561 rc = -ENXIO;
562 break;
563
564 case M_CMD_STATUS_RX_FIFO_FULL:
565 LOG_ERR("RX FIFO full");
566 rc = -ETIMEDOUT;
567 break;
568
569 default:
570 LOG_ERR("Unknown Error : 0x%x", val);
571 iproc_i2c_enable_disable(dev, false);
572 iproc_i2c_common_init(dev);
573 iproc_i2c_enable_disable(dev, true);
574 rc = -EIO;
575 break;
576 }
577
578 if (rc < 0) {
579 /* flush both Master TX/RX FIFOs */
580 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
581 sys_write32(val, base + M_FIFO_CTRL_OFFSET);
582 }
583
584 return rc;
585 }
586
iproc_i2c_configure(const struct device * dev,uint32_t dev_cfg_raw)587 static int iproc_i2c_configure(const struct device *dev, uint32_t dev_cfg_raw)
588 {
589 mem_addr_t base = DEV_BASE(dev);
590
591 if (I2C_ADDR_10_BITS & dev_cfg_raw) {
592 LOG_ERR("10-bit addressing not supported");
593 return -ENOTSUP;
594 }
595
596 switch (I2C_SPEED_GET(dev_cfg_raw)) {
597 case I2C_SPEED_STANDARD:
598 sys_clear_bit(base + TIM_CFG_OFFSET, TIM_CFG_MODE_400_SHIFT);
599 break;
600 case I2C_SPEED_FAST:
601 sys_set_bit(base + TIM_CFG_OFFSET, TIM_CFG_MODE_400_SHIFT);
602 break;
603 default:
604 LOG_ERR("Only standard or Fast speed modes are supported");
605 return -ENOTSUP;
606 }
607
608 return 0;
609 }
610
iproc_i2c_read_valid_bytes(const struct device * dev)611 static void iproc_i2c_read_valid_bytes(const struct device *dev)
612 {
613 mem_addr_t base = DEV_BASE(dev);
614 struct iproc_i2c_data *dd = DEV_DATA(dev);
615 struct i2c_msg *msg = dd->msg;
616 uint32_t val;
617
618 /* Read valid data from RX FIFO */
619 while (dd->rx_bytes < msg->len) {
620 val = sys_read32(base + M_RX_OFFSET);
621
622 /* rx fifo empty */
623 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) {
624 break;
625 }
626
627 msg->buf[dd->rx_bytes] = (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
628 dd->rx_bytes++;
629 }
630 }
631
iproc_i2c_data_recv(const struct device * dev)632 static int iproc_i2c_data_recv(const struct device *dev)
633 {
634 struct iproc_i2c_data *dd = DEV_DATA(dev);
635 mem_addr_t base = DEV_BASE(dev);
636 struct i2c_msg *msg = dd->msg;
637 uint32_t bytes_left, val;
638
639 iproc_i2c_read_valid_bytes(dev);
640
641 bytes_left = msg->len - dd->rx_bytes;
642 if (bytes_left == 0) {
643 /* finished reading all data, disable rx thld event */
644 sys_clear_bit(base + IE_OFFSET, IS_M_RX_THLD_SHIFT);
645 } else if (bytes_left < dd->thld_bytes) {
646 /* set bytes left as threshold */
647 val = sys_read32(base + M_FIFO_CTRL_OFFSET);
648 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
649 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
650 sys_write32(val, base + M_FIFO_CTRL_OFFSET);
651 dd->thld_bytes = bytes_left;
652 }
653 /*
654 * if bytes_left >= dd->thld_bytes, no need to change the THRESHOLD.
655 * It will remain as dd->thld_bytes itself
656 */
657
658 return 0;
659 }
660
iproc_i2c_transfer_one(const struct device * dev,struct i2c_msg * msg,uint16_t dev_addr)661 static int iproc_i2c_transfer_one(const struct device *dev, struct i2c_msg *msg, uint16_t dev_addr)
662 {
663 mem_addr_t base = DEV_BASE(dev);
664 struct iproc_i2c_data *dd = DEV_DATA(dev);
665 uint32_t val, addr, tx_bytes, val_intr_en;
666 int rc;
667
668 if (!!(sys_read32(base + M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
669 LOG_ERR("Bus busy, prev xfer ongoing");
670 return -EBUSY;
671 }
672
673 LOG_DBG("%s: msg dev_addr 0x%x flags 0x%x len 0x%x val 0x%x\n", __func__, dev_addr,
674 msg->flags, msg->len, msg->buf[0]);
675
676 /* Save current i2c_msg */
677 dd->msg = msg;
678
679 addr = dev_addr << 1 | (msg->flags & I2C_MSG_READ ? 1 : 0);
680 sys_write32(addr, base + M_TX_OFFSET);
681
682 tx_bytes = MIN(msg->len, (TX_RX_FIFO_SIZE - 1));
683 if (!(msg->flags & I2C_MSG_READ)) {
684 /* Fill master TX fifo */
685 for (uint32_t i = 0; i < tx_bytes; i++) {
686 val = msg->buf[i];
687 /* For the last byte, set MASTER_WR_STATUS bit */
688 if (i == msg->len - 1) {
689 val |= BIT(M_TX_WR_STATUS_SHIFT);
690 }
691 sys_write32(val, base + M_TX_OFFSET);
692 }
693
694 dd->tx_bytes = tx_bytes;
695 }
696
697 /*
698 * Enable the "start busy" interrupt, which will be triggered after the
699 * transaction is done, i.e., the internal start_busy bit, transitions
700 * from 1 to 0.
701 */
702 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
703
704 if (!(msg->flags & I2C_MSG_READ) && (msg->len > dd->tx_bytes)) {
705 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
706 }
707
708 /*
709 * Program master command register (0x30) with protocol type and set
710 * start_busy_command bit to initiate the write transaction
711 */
712 val = BIT(M_CMD_START_BUSY_SHIFT);
713 if (msg->len == 0) {
714 /* SMBUS QUICK Command (Read/Write) */
715 val |= (M_CMD_SMB_PROT_QUICK << M_CMD_SMB_PROT_SHIFT);
716 } else if (msg->flags & I2C_MSG_READ) {
717 uint32_t tmp;
718
719 dd->rx_bytes = 0;
720
721 /* SMBUS Block Read Command */
722 val |= M_CMD_SMB_PROT_BLK_RD << M_CMD_SMB_PROT_SHIFT;
723 val |= msg->len;
724
725 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) {
726 dd->thld_bytes = M_RX_FIFO_THLD_VALUE;
727 } else {
728 dd->thld_bytes = msg->len;
729 }
730
731 /* set threshold value */
732 tmp = sys_read32(base + M_FIFO_CTRL_OFFSET);
733 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
734 tmp |= dd->thld_bytes << M_FIFO_RX_THLD_SHIFT;
735 sys_write32(tmp, base + M_FIFO_CTRL_OFFSET);
736
737 /* enable the RX threshold interrupt */
738 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
739 } else {
740 /* SMBUS Block Write Command */
741 val |= M_CMD_SMB_PROT_BLK_WR << M_CMD_SMB_PROT_SHIFT;
742 }
743
744 sys_write32(val_intr_en, base + IE_OFFSET);
745
746 sys_write32(val, base + M_CMD_OFFSET);
747
748 /* Wait for the transfer to complete or timeout */
749 rc = k_sem_take(&dd->device_sync_sem, K_MSEC(I2C_TIMEOUT_MSEC));
750
751 /* disable all interrupts */
752 sys_write32(0, base + IE_OFFSET);
753
754 if (rc != 0) {
755 /* flush both Master TX/RX FIFOs */
756 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
757 sys_write32(val, base + M_FIFO_CTRL_OFFSET);
758 return rc;
759 }
760
761 /* Check for Master Xfer status */
762 rc = iproc_i2c_check_status(dev, dev_addr, msg);
763
764 return rc;
765 }
766
iproc_i2c_transfer_multi(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)767 static int iproc_i2c_transfer_multi(const struct device *dev, struct i2c_msg *msgs,
768 uint8_t num_msgs, uint16_t addr)
769 {
770 int rc;
771 struct i2c_msg *msgs_chk = msgs;
772
773 if (!msgs_chk) {
774 return -EINVAL;
775 }
776
777 /* pre-check all msgs */
778 for (uint8_t i = 0; i < num_msgs; i++, msgs_chk++) {
779 if (!msgs_chk->buf) {
780 LOG_ERR("Invalid msg buffer");
781 return -EINVAL;
782 }
783
784 if (I2C_MSG_ADDR_10_BITS & msgs_chk->flags) {
785 LOG_ERR("10-bit addressing not supported");
786 return -ENOTSUP;
787 }
788 }
789
790 for (uint8_t i = 0; i < num_msgs; i++, msgs++) {
791 rc = iproc_i2c_transfer_one(dev, msgs, addr);
792 if (rc < 0) {
793 return rc;
794 }
795 }
796
797 return 0;
798 }
799
iproc_i2c_send_data(const struct device * dev)800 static void iproc_i2c_send_data(const struct device *dev)
801 {
802 mem_addr_t base = DEV_BASE(dev);
803 struct iproc_i2c_data *dd = DEV_DATA(dev);
804 struct i2c_msg *msg = dd->msg;
805 uint32_t tx_bytes = msg->len - dd->tx_bytes;
806
807 /* can only fill up to the FIFO size */
808 tx_bytes = MIN(tx_bytes, TX_RX_FIFO_SIZE);
809 for (uint32_t i = 0; i < tx_bytes; i++) {
810 /* start from where we left over */
811 uint32_t idx = dd->tx_bytes + i;
812
813 uint32_t val = msg->buf[idx];
814
815 /* mark the last byte */
816 if (idx == (msg->len - 1)) {
817 uint32_t tmp;
818
819 val |= BIT(M_TX_WR_STATUS_SHIFT);
820
821 /*
822 * Since this is the last byte, we should now
823 * disable TX FIFO underrun interrupt
824 */
825 tmp = sys_read32(base + IE_OFFSET);
826 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
827 sys_write32(tmp, base + IE_OFFSET);
828 }
829
830 /* load data into TX FIFO */
831 sys_write32(val, base + M_TX_OFFSET);
832 }
833
834 /* update number of transferred bytes */
835 dd->tx_bytes += tx_bytes;
836 }
837
iproc_i2c_master_isr(const struct device * dev,uint32_t status)838 static void iproc_i2c_master_isr(const struct device *dev, uint32_t status)
839 {
840 struct iproc_i2c_data *dd = DEV_DATA(dev);
841
842 /* TX FIFO is empty and we have more data to send */
843 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) {
844 iproc_i2c_send_data(dev);
845 }
846
847 /* RX FIFO threshold is reached and data needs to be read out */
848 if (status & BIT(IS_M_RX_THLD_SHIFT)) {
849 iproc_i2c_data_recv(dev);
850 }
851
852 /* transfer is done */
853 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
854 k_sem_give(&dd->device_sync_sem);
855 }
856 }
857
iproc_i2c_isr(void * arg)858 static void iproc_i2c_isr(void *arg)
859 {
860 const struct device *dev = (const struct device *)arg;
861 mem_addr_t base = DEV_BASE(dev);
862 uint32_t status;
863 uint32_t sl_status, curr_irqs;
864
865 curr_irqs = sys_read32(base + IE_OFFSET);
866 status = sys_read32(base + IS_OFFSET);
867
868 /* process only target interrupt which are enabled */
869 sl_status = status & curr_irqs & ISR_MASK_TARGET;
870 LOG_DBG("iproc_i2c(0x%x): sts 0x%x, sl_sts 0x%x, curr_ints 0x%x", (uint32_t)base, status,
871 sl_status, curr_irqs);
872
873 #ifdef CONFIG_I2C_TARGET
874 /* target events */
875 if (sl_status) {
876 iproc_i2c_target_isr(dev, sl_status);
877 return;
878 }
879 #endif
880
881 status &= ISR_MASK;
882 /* master events */
883 if (status) {
884 iproc_i2c_master_isr(dev, status);
885 sys_write32(status, base + IS_OFFSET);
886 }
887 }
888
iproc_i2c_init(const struct device * dev)889 static int iproc_i2c_init(const struct device *dev)
890 {
891 const struct iproc_i2c_config *config = DEV_CFG(dev);
892 struct iproc_i2c_data *dd = DEV_DATA(dev);
893 uint32_t bitrate = config->bitrate;
894 int error;
895
896 k_sem_init(&dd->device_sync_sem, 0, 1);
897
898 iproc_i2c_common_init(dev);
899
900 /* Set default clock frequency */
901 bitrate = i2c_map_dt_bitrate(bitrate);
902
903 if (dd->target_cfg == NULL) {
904 bitrate |= I2C_MODE_CONTROLLER;
905 }
906
907 error = iproc_i2c_configure(dev, bitrate);
908 if (error) {
909 return error;
910 }
911
912 config->irq_config_func(dev);
913
914 iproc_i2c_enable_disable(dev, true);
915
916 return 0;
917 }
918
919 static DEVICE_API(i2c, iproc_i2c_driver_api) = {
920 .configure = iproc_i2c_configure,
921 .transfer = iproc_i2c_transfer_multi,
922 #ifdef CONFIG_I2C_TARGET
923 .target_register = iproc_i2c_target_register,
924 .target_unregister = iproc_i2c_target_unregister,
925 #endif
926 #ifdef CONFIG_I2C_RTIO
927 .iodev_submit = i2c_iodev_submit_fallback,
928 #endif
929 };
930
931 #define IPROC_I2C_DEVICE_INIT(n) \
932 static void iproc_i2c_irq_config_func_##n(const struct device *dev) \
933 { \
934 ARG_UNUSED(dev); \
935 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), iproc_i2c_isr, \
936 DEVICE_DT_INST_GET(n), 0); \
937 \
938 irq_enable(DT_INST_IRQN(n)); \
939 } \
940 \
941 static const struct iproc_i2c_config iproc_i2c_config_##n = { \
942 .base = DT_INST_REG_ADDR(n), \
943 .irq_config_func = iproc_i2c_irq_config_func_##n, \
944 .bitrate = DT_INST_PROP(n, clock_frequency), \
945 }; \
946 \
947 static struct iproc_i2c_data iproc_i2c_data_##n; \
948 \
949 I2C_DEVICE_DT_INST_DEFINE(n, &iproc_i2c_init, NULL, &iproc_i2c_data_##n, \
950 &iproc_i2c_config_##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
951 &iproc_i2c_driver_api);
952
953 DT_INST_FOREACH_STATUS_OKAY(IPROC_I2C_DEVICE_INIT)
954
