Lines Matching refs:sys_read32
123 int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
146 if (sys_read32(config->base + REG_SR) & SR_SRW) { in i2c_xilinx_axi_target_isr()
163 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
185 sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_target_isr()
189 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
223 uint32_t int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_isr()
224 uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable; in i2c_xilinx_axi_isr()
231 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_isr()
247 sys_write32(ints_to_clear & sys_read32(config->base + REG_ISR), config->base + REG_ISR); in i2c_xilinx_axi_isr()
268 const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask; in i2c_xilinx_axi_wait_interrupt()
281 sys_read32(config->base + REG_SR), sys_read32(config->base + REG_ISR)); in i2c_xilinx_axi_wait_interrupt()
290 const uint32_t int_status = sys_read32(config->base + REG_ISR); in i2c_xilinx_axi_clear_interrupt()
304 if (!(sys_read32(config->base + REG_SR) & SR_RX_FIFO_EMPTY) && in i2c_xilinx_axi_wait_rx_full()
305 (sys_read32(config->base + REG_RX_FIFO_OCY) & RX_FIFO_OCY_MASK) + 1 >= read_bytes) { in i2c_xilinx_axi_wait_rx_full()
307 sys_read32(config->base + REG_SR), in i2c_xilinx_axi_wait_rx_full()
308 sys_read32(config->base + REG_RX_FIFO_OCY)); in i2c_xilinx_axi_wait_rx_full()
385 *read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_read_nondyn()
435 *read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_read_dyn()
467 if (sys_read32(config->base + REG_SR) & SR_BB) { in i2c_xilinx_axi_wait_not_busy()