| /Zephyr-latest/drivers/sensor/infineon/xmc4xxx_temp/ |
| D | Kconfig | 17 Offset adjustment is defined as a shift of the conversion result.
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| /Zephyr-latest/dts/arm/aspeed/ |
| D | ast10x0.dtsi | 48 reg-shift = <2>;
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| /Zephyr-latest/boards/qemu/malta/ |
| D | qemu_malta.dts | 47 reg-shift = <3>;
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32h7_clock.h | 83 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
85 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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| D | stm32u5_clock.h | 77 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
79 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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| D | stm32h5_clock.h | 76 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
78 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
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| /Zephyr-latest/drivers/spi/ |
| D | spi_bitbang.c | 173 const int shift = lsb ? i : (data->bits - 1 - i); in spi_bitbang_transceive() local
174 const int d = (w >> shift) & 0x1; in spi_bitbang_transceive()
205 r |= (b ? 0x1 : 0x0) << shift; in spi_bitbang_transceive()
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| /Zephyr-latest/boards/qemu/x86/ |
| D | qemu_x86_lakemont.dts | 48 reg-shift = <2>;
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| /Zephyr-latest/drivers/flash/ |
| D | soc_flash_nrf.c | 432 static void shift_write_context(uint32_t shift, struct flash_context *w_ctx) in shift_write_context() argument
434 w_ctx->flash_addr += shift; in shift_write_context()
435 w_ctx->data_addr += shift; in shift_write_context()
436 w_ctx->len -= shift; in shift_write_context()
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| /Zephyr-latest/drivers/adc/ |
| D | adc_stm32.c | 665 static void adc_stm32_oversampling_ratioshift(ADC_TypeDef *adc, uint32_t ratio, uint32_t shift) in adc_stm32_oversampling_ratioshift() argument
672 && (LL_ADC_GetOverSamplingShift(adc) == shift)) { in adc_stm32_oversampling_ratioshift()
677 LL_ADC_ConfigOverSamplingRatioShift(adc, ratio, shift); in adc_stm32_oversampling_ratioshift()
700 uint32_t shift = table_oversampling_shift[ratio]; in adc_stm32_oversampling() local
705 adc_stm32_oversampling_ratioshift(adc, table_oversampling_ratio[ratio], shift); in adc_stm32_oversampling()
712 adc_stm32_oversampling_ratioshift(adc, 1 << ratio, shift); in adc_stm32_oversampling()
774 uint32_t shift, uint32_t mask) in get_reg_value() argument
781 return ((*(volatile uint32_t *)addr >> shift) & mask); in get_reg_value()
785 uint32_t shift, uint32_t mask, uint32_t value) in set_reg_value() argument
792 MODIFY_REG(*(volatile uint32_t *)addr, (mask << shift), (value << shift)); in set_reg_value()
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| D | adc_stm32wb0.c | 305 const uint32_t shift = 4 * (Conversion & 7); in ll_adc_set_conversion_channel() local
307 MODIFY_REG((&ADCx->SEQ_1)[reg], ADC_SEQ_1_SEQ0 << shift, Channel << shift); in ll_adc_set_conversion_channel()
380 const uint32_t shift = (group_shift + type_shift); in ll_adc_set_calib_point_for_any() local
382 MODIFY_REG(ADCx->COMP_SEL, (ADC_COMP_SEL_OFFSET_GAIN0 << shift), (Point << shift)); in ll_adc_set_calib_point_for_any()
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| /Zephyr-latest/boards/snps/nsim/arc_v/ |
| D | rmx1xx.dtsi | 43 reg-shift = <2>;
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| /Zephyr-latest/include/zephyr/arch/x86/ |
| D | pagetables.ld | 9 * to not shift memory addresses that occur after this.
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| /Zephyr-latest/drivers/sensor/asahi_kasei/akm09918c/ |
| D | akm09918c_decoder.c | 71 out->shift = AKM09918C_SHIFT; in akm09918c_decoder_decode()
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| /Zephyr-latest/dts/nios2/intel/ |
| D | nios2f.dtsi | 42 reg-shift = <2>;
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_gicv3.c | 138 uint32_t shift; in arm_gic_irq_set_priority() local
152 shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2; in arm_gic_irq_set_priority()
155 val &= ~(GICD_ICFGR_MASK << shift); in arm_gic_irq_set_priority()
157 val |= (GICD_ICFGR_TYPE << shift); in arm_gic_irq_set_priority()
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| /Zephyr-latest/dts/x86/intel/ |
| D | alder_lake.dtsi | 169 reg-shift = <2>;
188 reg-shift = <2>;
208 reg-shift = <2>;
386 reg-shift = <0>;
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| /Zephyr-latest/dts/arm64/nxp/ |
| D | nxp_ls1046a.dtsi | 77 reg-shift = <2>;
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| /Zephyr-latest/drivers/display/ |
| D | ssd1322.c | 111 size_t shift = BITS_PER_SEGMENT * (seg_idx % SEGMENTS_PER_BYTE); in ssd1322_conv_mono01_grayscale() local
113 if (shift == 0) { in ssd1322_conv_mono01_grayscale()
116 buf_out[seg_idx / SEGMENTS_PER_BYTE] |= color << shift; in ssd1322_conv_mono01_grayscale()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_wb0.c | 255 const uint32_t shift = STM32_CLOCK_SHIFT_GET(pclken->enr); in stm32_clock_control_configure() local
268 sys_clear_bits(reg, STM32_CLOCK_MASK_GET(pclken->enr) << shift); in stm32_clock_control_configure()
269 sys_set_bits(reg, STM32_CLOCK_VAL_GET(pclken->enr) << shift); in stm32_clock_control_configure()
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| /Zephyr-latest/include/zephyr/dsp/ |
| D | basicmath.h | 288 DSP_FUNC_SCOPE void zdsp_scale_q7(const DSP_DATA q7_t *src, q7_t scale_fract, int8_t shift,
305 DSP_FUNC_SCOPE void zdsp_scale_q15(const DSP_DATA q15_t *src, q15_t scale_fract, int8_t shift,
322 DSP_FUNC_SCOPE void zdsp_scale_q31(const DSP_DATA q31_t *src, q31_t scale_fract, int8_t shift,
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| /Zephyr-latest/dts/arm/ti/ |
| D | am62x_m4.dtsi | 55 reg-shift = <2>;
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| /Zephyr-latest/include/zephyr/drivers/pinctrl/ |
| D | pinctrl_rcar_common.h | 18 uint8_t shift:5; /* bit shift 0 - 28 */ member
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.nrf_rtc | 43 effectively shift time into the future.
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| /Zephyr-latest/dts/arm64/rockchip/ |
| D | rk3568.dtsi | 85 reg-shift = <2>;
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