1/*
2 * Copyright (c) 2023 Texas Instruments Incorporated
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12
13/ {
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-m4f";
22			reg = <0>;
23		};
24	};
25
26	sram0: memory@0 {
27		compatible = "mmio-sram";
28		reg = <0x0 DT_SIZE_K(192)>;		/* 192 KB of SRAM (I-Code) */
29	};
30
31	sram1: memory1@40000 {
32		compatible = "mmio-sram";
33		reg = <0x40000 DT_SIZE_K(64)>;		/* 64 KB of SRAM (D-Code) */
34	};
35
36	sysclk: system-clock {
37		compatible = "fixed-clock";
38		clock-frequency = <DT_FREQ_M(400)>;
39		#clock-cells = <0>;
40	};
41
42	pinctrl: pinctrl@4084000 {
43		compatible = "ti,k3-pinctrl";
44		reg = <0x04084000 0x88>;
45		status = "okay";
46	};
47
48	uart0: serial@4a00000 {
49		compatible = "ns16550";
50		reg = <0x04a00000 0x200>;
51		interrupts = <24 4>;
52		interrupt-parent = <&nvic>;
53		clock-frequency = <DT_FREQ_M(48)>;
54		current-speed = <115200>;
55		reg-shift = <2>;
56		status = "disabled";
57	};
58
59	gpio0: gpio@4201010 {
60		compatible = "ti,davinci-gpio";
61		reg = <0x4201010 0x100>;
62		gpio-controller;
63		#gpio-cells = <2>;
64		ngpios = <24>;
65		status = "disabled";
66	};
67};
68
69&nvic {
70	arm,num-irq-priority-bits = <3>;
71};
72
73&systick {
74	status = "okay";
75};
76