1 /*
2 * Copyright (c) 2024 Lukasz Hawrylko
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "zephyr/sys/util.h"
8 #define DT_DRV_COMPAT solomon_ssd1322
9
10 #include <zephyr/logging/log.h>
11 LOG_MODULE_REGISTER(ssd1322, CONFIG_DISPLAY_LOG_LEVEL);
12
13 #include <string.h>
14 #include <zephyr/device.h>
15 #include <zephyr/init.h>
16 #include <zephyr/drivers/display.h>
17 #include <zephyr/drivers/gpio.h>
18 #include <zephyr/drivers/mipi_dbi.h>
19 #include <zephyr/kernel.h>
20
21 #define SSD1322_SET_COLUMN_ADDR 0x15
22 #define SSD1322_ENABLE_RAM_WRITE 0x5C
23 #define SSD1322_SET_ROW_ADDR 0x75
24 #define SSD1322_SET_REMAP 0xA0
25 #define SSD1322_SET_START_LINE 0xA1
26 #define SSD1322_SET_DISPLAY_OFFSET 0xA2
27 #define SSD1322_BLANKING_ON 0xA4
28 #define SSD1322_BLANKING_OFF 0xA6
29 #define SSD1322_EXIT_PARTIAL 0xA9
30 #define SSD1322_DISPLAY_OFF 0xAE
31 #define SSD1322_DISPLAY_ON 0xAF
32 #define SSD1322_SET_PHASE_LENGTH 0xB1
33 #define SSD1322_SET_CLOCK_DIV 0xB3
34 #define SSD1322_SET_GPIO 0xB5
35 #define SSD1322_SET_SECOND_PRECHARGE 0xB6
36 #define SSD1322_DEFAULT_GREYSCALE 0xB9
37 #define SSD1322_SET_PRECHARGE 0xBB
38 #define SSD1322_SET_VCOMH 0xBE
39 #define SSD1322_SET_CONTRAST 0xC1
40 #define SSD1322_SET_MUX_RATIO 0xCA
41 #define SSD1322_COMMAND_LOCK 0xFD
42
43 #define BITS_PER_SEGMENT 4
44 #define SEGMENTS_PER_BYTE (8 / BITS_PER_SEGMENT)
45
46 struct ssd1322_config {
47 const struct device *mipi_dev;
48 struct mipi_dbi_config dbi_config;
49 uint16_t height;
50 uint16_t width;
51 uint16_t column_offset;
52 uint8_t row_offset;
53 uint8_t start_line;
54 uint8_t mux_ratio;
55 bool remap_row_first;
56 bool remap_columns;
57 bool remap_rows;
58 bool remap_nibble;
59 bool remap_com_odd_even_split;
60 bool remap_com_dual;
61 uint8_t segments_per_pixel;
62 uint8_t *conversion_buf;
63 size_t conversion_buf_size;
64 };
65
ssd1322_write_command(const struct device * dev,uint8_t cmd,const uint8_t * buf,size_t len)66 static inline int ssd1322_write_command(const struct device *dev, uint8_t cmd, const uint8_t *buf,
67 size_t len)
68 {
69 const struct ssd1322_config *config = dev->config;
70
71 return mipi_dbi_command_write(config->mipi_dev, &config->dbi_config, cmd, buf, len);
72 }
73
ssd1322_blanking_on(const struct device * dev)74 static int ssd1322_blanking_on(const struct device *dev)
75 {
76 return ssd1322_write_command(dev, SSD1322_BLANKING_ON, NULL, 0);
77 }
78
ssd1322_blanking_off(const struct device * dev)79 static int ssd1322_blanking_off(const struct device *dev)
80 {
81 return ssd1322_write_command(dev, SSD1322_BLANKING_OFF, NULL, 0);
82 }
83
84 /*
85 * The controller uses 4-bit grayscale format, so one pixel is represented by 4 bits.
86 * Zephyr's display API does not support this format, so this uses mono01, and converts each 1-bit
87 * pixel to 1111 or 0000.
88 *
89 * buf_in: pointer to input buffer in mono01 format. This value will bel updated to point to
90 * the first byte after the last converted pixel.
91 * pixel_count: pointer to the total number of pixels in buf_in to convert. The number of
92 * converted pixels will be subtracted.
93 * returns the number of bytes written to buf_out.
94 */
ssd1322_conv_mono01_grayscale(const uint8_t ** buf_in,uint32_t * pixel_count,uint8_t * buf_out,size_t buf_out_size,uint8_t segments_per_pixel)95 static int ssd1322_conv_mono01_grayscale(const uint8_t **buf_in, uint32_t *pixel_count,
96 uint8_t *buf_out, size_t buf_out_size,
97 uint8_t segments_per_pixel)
98 {
99 /* Output buffer size gets rounded down to avoid splitting chunks in the middle of input
100 * bytes
101 */
102 uint16_t pixels_in_chunk =
103 MIN(*pixel_count,
104 ROUND_DOWN((buf_out_size * SEGMENTS_PER_BYTE) / segments_per_pixel, 8));
105
106 for (uint16_t in_idx = 0; in_idx < pixels_in_chunk; in_idx++) {
107 uint8_t color = ((*buf_in)[in_idx / 8] & BIT(in_idx % 8)) ? 0xF : 0;
108
109 for (size_t i = 0; i < segments_per_pixel; i++) {
110 size_t seg_idx = in_idx * segments_per_pixel + i;
111 size_t shift = BITS_PER_SEGMENT * (seg_idx % SEGMENTS_PER_BYTE);
112
113 if (shift == 0) {
114 buf_out[seg_idx / SEGMENTS_PER_BYTE] = color;
115 } else {
116 buf_out[seg_idx / SEGMENTS_PER_BYTE] |= color << shift;
117 }
118 }
119 }
120
121 buf_in += pixels_in_chunk / 8;
122 *pixel_count -= pixels_in_chunk;
123 return pixels_in_chunk * segments_per_pixel / SEGMENTS_PER_BYTE;
124 }
125
ssd1322_write_pixels(const struct device * dev,const uint8_t * buf,uint32_t pixel_count)126 static int ssd1322_write_pixels(const struct device *dev, const uint8_t *buf, uint32_t pixel_count)
127 {
128 const struct ssd1322_config *config = dev->config;
129 struct display_buffer_descriptor mipi_desc;
130
131 while (pixel_count > 0) {
132 size_t len;
133 int ret;
134
135 /* Other formats, such as RGB888 to grayscale could be added by switching here */
136 len = ssd1322_conv_mono01_grayscale(&buf, &pixel_count, config->conversion_buf,
137 config->conversion_buf_size,
138 config->segments_per_pixel);
139
140 /* As the MIPI DBI interface also does not support 4bit grayscale, it is disguised
141 * as a single row of mono01 pixels. While this could theoretically cause issues
142 * with some mipi-dbi implementations, the SPI-based driver ignores this metadata,
143 * and is likely the most relevant in practice.
144 */
145 mipi_desc.buf_size = len;
146 mipi_desc.width = len * 8;
147 mipi_desc.height = 1;
148 mipi_desc.pitch = mipi_desc.width;
149 ret = mipi_dbi_write_display(config->mipi_dev, &config->dbi_config,
150 config->conversion_buf, &mipi_desc,
151 PIXEL_FORMAT_MONO01);
152 if (ret < 0) {
153 return ret;
154 }
155 }
156 return 0;
157 }
158
ssd1322_write(const struct device * dev,const uint16_t x,const uint16_t y,const struct display_buffer_descriptor * desc,const void * buf)159 static int ssd1322_write(const struct device *dev, const uint16_t x, const uint16_t y,
160 const struct display_buffer_descriptor *desc, const void *buf)
161 {
162 const struct ssd1322_config *config = dev->config;
163 size_t buf_len;
164 int ret;
165 uint8_t cmd_data[2];
166 int32_t pixel_count = desc->width * desc->height;
167
168 if (desc->pitch < desc->width) {
169 LOG_ERR("Pitch is smaller than width");
170 return -EINVAL;
171 }
172
173 buf_len = MIN(desc->buf_size, desc->height * desc->width / 8);
174 if (buf == NULL || buf_len == 0U) {
175 LOG_ERR("Display buffer is not available");
176 return -EINVAL;
177 }
178
179 if (desc->pitch > desc->width) {
180 LOG_ERR("Unsupported mode");
181 return -EINVAL;
182 }
183
184 LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch,
185 desc->width, desc->height, buf_len);
186
187 cmd_data[0] = config->column_offset + (x >> 2) * config->segments_per_pixel;
188 cmd_data[1] =
189 config->column_offset + ((x + desc->width) >> 2) * config->segments_per_pixel - 1;
190 ret = ssd1322_write_command(dev, SSD1322_SET_COLUMN_ADDR, cmd_data, 2);
191 if (ret < 0) {
192 return ret;
193 }
194
195 cmd_data[0] = y;
196 cmd_data[1] = y + desc->height - 1;
197 ret = ssd1322_write_command(dev, SSD1322_SET_ROW_ADDR, cmd_data, 2);
198 if (ret < 0) {
199 return ret;
200 }
201
202 ret = ssd1322_write_command(dev, SSD1322_ENABLE_RAM_WRITE, NULL, 0);
203 if (ret < 0) {
204 return ret;
205 }
206
207 return ssd1322_write_pixels(dev, buf, pixel_count);
208 }
209
ssd1322_set_contrast(const struct device * dev,const uint8_t contrast)210 static int ssd1322_set_contrast(const struct device *dev, const uint8_t contrast)
211 {
212 return ssd1322_write_command(dev, SSD1322_SET_CONTRAST, &contrast, 1);
213 }
214
ssd1322_get_capabilities(const struct device * dev,struct display_capabilities * caps)215 static void ssd1322_get_capabilities(const struct device *dev, struct display_capabilities *caps)
216 {
217 const struct ssd1322_config *config = dev->config;
218
219 memset(caps, 0, sizeof(struct display_capabilities));
220 caps->x_resolution = config->width;
221 caps->y_resolution = config->height;
222 caps->supported_pixel_formats = PIXEL_FORMAT_MONO01;
223 caps->current_pixel_format = PIXEL_FORMAT_MONO01;
224 }
225
ssd1322_init_device(const struct device * dev)226 static int ssd1322_init_device(const struct device *dev)
227 {
228 int ret;
229 uint8_t data[2];
230 const struct ssd1322_config *config = dev->config;
231
232 ret = mipi_dbi_reset(config->mipi_dev, 1);
233 if (ret < 0) {
234 return ret;
235 }
236 k_usleep(100);
237
238 ret = ssd1322_write_command(dev, SSD1322_DISPLAY_OFF, NULL, 0);
239 if (ret < 0) {
240 return ret;
241 }
242
243 data[0] = 0x91;
244 ret = ssd1322_write_command(dev, SSD1322_SET_CLOCK_DIV, data, 1);
245 if (ret < 0) {
246 return ret;
247 }
248
249 data[0] = config->mux_ratio - 1;
250 ret = ssd1322_write_command(dev, SSD1322_SET_MUX_RATIO, data, 1);
251 if (ret < 0) {
252 return ret;
253 }
254
255 data[0] = config->start_line;
256 ret = ssd1322_write_command(dev, SSD1322_SET_START_LINE, data, 1);
257 if (ret < 0) {
258 return ret;
259 }
260
261 data[0] = config->row_offset;
262 ret = ssd1322_write_command(dev, SSD1322_SET_DISPLAY_OFFSET, data, 1);
263 if (ret < 0) {
264 return ret;
265 }
266
267 data[0] = 0x00;
268 data[1] = 0x01;
269 WRITE_BIT(data[0], 0, config->remap_row_first);
270 WRITE_BIT(data[0], 1, config->remap_columns);
271 WRITE_BIT(data[0], 2, config->remap_nibble);
272 WRITE_BIT(data[0], 4, config->remap_rows);
273 WRITE_BIT(data[0], 5, config->remap_com_odd_even_split);
274 WRITE_BIT(data[1], 4, config->remap_com_dual);
275 ret = ssd1322_write_command(dev, SSD1322_SET_REMAP, data, 2);
276 if (ret < 0) {
277 return ret;
278 }
279
280 data[0] = 0x00;
281 ret = ssd1322_write_command(dev, SSD1322_SET_GPIO, data, 1);
282 if (ret < 0) {
283 return ret;
284 }
285
286 ret = ssd1322_write_command(dev, SSD1322_DEFAULT_GREYSCALE, NULL, 0);
287 if (ret < 0) {
288 return ret;
289 }
290
291 data[0] = 0xE2;
292 ret = ssd1322_write_command(dev, SSD1322_SET_PHASE_LENGTH, data, 1);
293 if (ret < 0) {
294 return ret;
295 }
296
297 data[0] = 0x1F;
298 ret = ssd1322_write_command(dev, SSD1322_SET_PRECHARGE, data, 1);
299 if (ret < 0) {
300 return ret;
301 }
302
303 data[0] = 0x08;
304 ret = ssd1322_write_command(dev, SSD1322_SET_SECOND_PRECHARGE, data, 1);
305 if (ret < 0) {
306 return ret;
307 }
308
309 data[0] = 0x07;
310 ret = ssd1322_write_command(dev, SSD1322_SET_VCOMH, data, 1);
311 if (ret < 0) {
312 return ret;
313 }
314
315 ret = ssd1322_write_command(dev, SSD1322_EXIT_PARTIAL, NULL, 0);
316 if (ret < 0) {
317 return ret;
318 }
319
320 ret = ssd1322_blanking_on(dev);
321 if (ret < 0) {
322 return ret;
323 }
324
325 ret = ssd1322_write_command(dev, SSD1322_DISPLAY_ON, NULL, 0);
326 if (ret < 0) {
327 return ret;
328 }
329
330 return 0;
331 }
332
ssd1322_init(const struct device * dev)333 static int ssd1322_init(const struct device *dev)
334 {
335 const struct ssd1322_config *config = dev->config;
336
337 if (!device_is_ready(config->mipi_dev)) {
338 LOG_ERR("MIPI not ready!");
339 return -ENODEV;
340 }
341
342 int ret = ssd1322_init_device(dev);
343
344 if (ret < 0) {
345 LOG_ERR("Failed to initialize device, err = %d", ret);
346 return -EIO;
347 }
348
349 return 0;
350 }
351
352 static DEVICE_API(display, ssd1322_driver_api) = {
353 .blanking_on = ssd1322_blanking_on,
354 .blanking_off = ssd1322_blanking_off,
355 .write = ssd1322_write,
356 .set_contrast = ssd1322_set_contrast,
357 .get_capabilities = ssd1322_get_capabilities,
358 };
359
360 #define SSD1322_CONV_BUFFER_SIZE(node_id) \
361 DIV_ROUND_UP(DT_PROP(node_id, width) * DT_PROP(node_id, height) * \
362 DT_PROP(node_id, segments_per_pixel), \
363 SEGMENTS_PER_BYTE)
364
365 #define SSD1322_DEFINE(node_id) \
366 static uint8_t conversion_buf##node_id[SSD1322_CONV_BUFFER_SIZE(node_id)]; \
367 static const struct ssd1322_config config##node_id = { \
368 .height = DT_PROP(node_id, height), \
369 .width = DT_PROP(node_id, width), \
370 .column_offset = DT_PROP(node_id, column_offset), \
371 .row_offset = DT_PROP(node_id, row_offset), \
372 .start_line = DT_PROP(node_id, start_line), \
373 .mux_ratio = DT_PROP(node_id, mux_ratio), \
374 .remap_row_first = DT_PROP(node_id, remap_row_first), \
375 .remap_columns = DT_PROP(node_id, remap_columns), \
376 .remap_rows = DT_PROP(node_id, remap_rows), \
377 .remap_nibble = DT_PROP(node_id, remap_nibble), \
378 .remap_com_odd_even_split = DT_PROP(node_id, remap_com_odd_even_split), \
379 .remap_com_dual = DT_PROP(node_id, remap_com_dual), \
380 .segments_per_pixel = DT_PROP(node_id, segments_per_pixel), \
381 .mipi_dev = DEVICE_DT_GET(DT_PARENT(node_id)), \
382 .dbi_config = {.mode = MIPI_DBI_MODE_SPI_4WIRE, \
383 .config = MIPI_DBI_SPI_CONFIG_DT( \
384 node_id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8), 0)}, \
385 .conversion_buf = conversion_buf##node_id, \
386 .conversion_buf_size = sizeof(conversion_buf##node_id), \
387 }; \
388 \
389 DEVICE_DT_DEFINE(node_id, ssd1322_init, NULL, NULL, &config##node_id, POST_KERNEL, \
390 CONFIG_DISPLAY_INIT_PRIORITY, &ssd1322_driver_api);
391
392 DT_FOREACH_STATUS_OKAY(solomon_ssd1322, SSD1322_DEFINE)
393
