| /Zephyr-latest/dts/arm/st/wl/ |
| D | stm32wl.dtsi | 133 rctl: reset-controller { label
134 compatible = "st,stm32-rcc-rctl";
245 resets = <&rctl STM32_RESET(APB2, 14U)>;
254 resets = <&rctl STM32_RESET(APB1L, 17U)>;
263 resets = <&rctl STM32_RESET(APB1H, 0U)>;
373 resets = <&rctl STM32_RESET(APB2, 11U)>;
390 resets = <&rctl STM32_RESET(APB1L, 0U)>;
412 resets = <&rctl STM32_RESET(APB2, 17U)>;
434 resets = <&rctl STM32_RESET(APB2, 18U)>;
456 resets = <&rctl STM32_RESET(AHB3, 16U)>;
|
| /Zephyr-latest/dts/arm/st/f7/ |
| D | stm32f746.dtsi | 20 resets = <&rctl STM32_RESET(APB2, 26U)>;
|
| D | stm32f767.dtsi | 21 resets = <&rctl STM32_RESET(APB2, 26U)>;
|
| D | stm32f722.dtsi | 40 resets = <&rctl STM32_RESET(APB2, 7U)>;
|
| /Zephyr-latest/dts/arm/st/g0/ |
| D | stm32g0.dtsi | 121 rctl: reset-controller { label
122 compatible = "st,stm32-rcc-rctl";
227 resets = <&rctl STM32_RESET(APB1H, 14U)>;
236 resets = <&rctl STM32_RESET(APB1L, 17U)>;
256 resets = <&rctl STM32_RESET(APB1H, 11U)>;
278 resets = <&rctl STM32_RESET(APB1L, 1U)>;
300 resets = <&rctl STM32_RESET(APB1H, 15U)>;
322 resets = <&rctl STM32_RESET(APB1H, 17U)>;
344 resets = <&rctl STM32_RESET(APB1H, 18U)>;
|
| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f437.dtsi | 18 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| D | stm32f429.dtsi | 28 resets = <&rctl STM32_RESET(APB2, 26U)>;
|
| D | stm32f446.dtsi | 38 resets = <&rctl STM32_RESET(APB1, 18U)>;
47 resets = <&rctl STM32_RESET(APB1, 19U)>;
56 resets = <&rctl STM32_RESET(APB1, 20U)>;
|
| D | stm32f427.dtsi | 39 resets = <&rctl STM32_RESET(APB1, 30U)>;
48 resets = <&rctl STM32_RESET(APB1, 31U)>;
|
| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l4r9.dtsi | 21 resets = <&rctl STM32_RESET(APB2, 26U)>;
|
| /Zephyr-latest/dts/arm/st/l0/ |
| D | stm32l0.dtsi | 134 rctl: reset-controller { label
135 compatible = "st,stm32-rcc-rctl";
217 resets = <&rctl STM32_RESET(APB1, 17U)>;
226 resets = <&rctl STM32_RESET(APB1, 18U)>;
257 resets = <&rctl STM32_RESET(APB1, 0U)>;
279 resets = <&rctl STM32_RESET(APB2, 2U)>;
|
| D | stm32l031.dtsi | 17 resets = <&rctl STM32_RESET(APB2, 5U)>;
|
| D | stm32l010Xb.dtsi | 30 resets = <&rctl STM32_RESET(APB2, 5U)>;
|
| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h747.dtsi | 23 resets = <&rctl STM32_RESET(APB3, 4U)>;
|
| D | stm32h7b0.dtsi | 22 resets = <&rctl STM32_RESET(AHB2, 4U)>;
|
| /Zephyr-latest/dts/arm/st/wb/ |
| D | stm32wb.dtsi | 168 rctl: reset-controller { label
169 compatible = "st,stm32-rcc-rctl";
258 resets = <&rctl STM32_RESET(APB2, 14U)>;
328 resets = <&rctl STM32_RESET(APB1H, 0U)>;
337 resets = <&rctl STM32_RESET(APB2, 11U)>;
354 resets = <&rctl STM32_RESET(APB1L, 0U)>;
376 resets = <&rctl STM32_RESET(APB2, 17U)>;
398 resets = <&rctl STM32_RESET(APB2, 18U)>;
518 resets = <&rctl STM32_RESET(AHB2, 16U)>;
|
| /Zephyr-latest/dts/arm/st/l1/ |
| D | stm32l151Xc.dtsi | 26 resets = <&rctl STM32_RESET(APB1, 3U)>;
|
| D | stm32l152Xc.dtsi | 26 resets = <&rctl STM32_RESET(APB1, 3U)>;
|
| D | stm32l152Xe.dtsi | 26 resets = <&rctl STM32_RESET(APB1, 3U)>;
|
| /Zephyr-latest/dts/arm/gd/gd32l23x/ |
| D | gd32l233rc.dtsi | 28 resets = <&rctl GD32_RESET_UART4>;
|
| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f302.dtsi | 75 resets = <&rctl STM32_RESET(APB2, 11U)>;
92 resets = <&rctl STM32_RESET(APB1, 2U)>;
|
| D | stm32f334.dtsi | 18 resets = <&rctl STM32_RESET(APB2, 11U)>;
|
| /Zephyr-latest/dts/arm/st/wb0/ |
| D | stm32wb0.dtsi | 130 rctl: reset-controller { label
131 compatible = "st,stm32-rcc-rctl";
186 resets = <&rctl STM32_RESET(APB1, 10)>;
195 resets = <&rctl STM32_RESET(APB1, 8)>;
|
| /Zephyr-latest/dts/arm/st/c0/ |
| D | stm32c071.dtsi | 17 resets = <&rctl STM32_RESET(APB1L, 0U)>;
|
| /Zephyr-latest/dts/arm/st/f0/ |
| D | stm32f031.dtsi | 17 resets = <&rctl STM32_RESET(APB1, 0U)>;
|
