| /Zephyr-latest/include/zephyr/posix/ |
| D | syslog.h | 49 #define LOG_MASK(mask) ((mask) & BIT_MASK(LOG_DEBUG + 1)) argument
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_max32.c | 40 static int api_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in api_port_set_masked_raw() argument
45 MXC_GPIO_OutPut(cfg->regs, mask, value); in api_port_set_masked_raw()
85 gpio_cfg.mask = BIT(pin); in api_pin_configure()
152 gpio_cfg.mask = BIT(pin); in api_pin_interrupt_configure()
156 MXC_GPIO_DisableInt(cfg->regs, gpio_cfg.mask); in api_pin_interrupt_configure()
159 MXC_GPIO_ClearFlags(cfg->regs, (MXC_GPIO_GetFlags(cfg->regs) & gpio_cfg.mask)); in api_pin_interrupt_configure()
192 MXC_GPIO_EnableInt(cfg->regs, gpio_cfg.mask); in api_pin_interrupt_configure()
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| D | gpio_rt1718s.c | 41 uint16_t alert, mask; in rt1718s_alert_worker() local
48 rt1718s_reg_burst_read(dev, RT1718S_REG_ALERT_MASK, (uint8_t *)&mask, in rt1718s_alert_worker()
49 sizeof(mask))) { in rt1718s_alert_worker()
60 alert &= mask; in rt1718s_alert_worker()
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| D | gpio_mchp_xec_v2.c | 80 static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val) in xec_mask_write32() argument
82 uint32_t r = (sys_read32(addr) & ~mask) | (val & mask); in xec_mask_write32()
334 uint32_t mask, in gpio_xec_port_set_masked_raw() argument
339 xec_mask_write32(pout_addr, mask, value); in gpio_xec_port_set_masked_raw()
344 static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask) in gpio_xec_port_set_bits_raw() argument
348 sys_write32(sys_read32(pout_addr) | mask, pout_addr); in gpio_xec_port_set_bits_raw()
354 uint32_t mask) in gpio_xec_port_clear_bits_raw() argument
358 sys_write32(sys_read32(pout_addr) & ~mask, pout_addr); in gpio_xec_port_clear_bits_raw()
363 static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask) in gpio_xec_port_toggle_bits() argument
367 sys_write32(sys_read32(pout_addr) ^ mask, pout_addr); in gpio_xec_port_toggle_bits()
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| D | gpio_eos_s3.c | 211 uint32_t mask, in gpio_eos_s3_port_set_masked_raw() argument
218 target_value = ((output_states & ~mask) | (value & mask)); in gpio_eos_s3_port_set_masked_raw()
225 uint32_t mask) in gpio_eos_s3_port_set_bits_raw() argument
229 MISC_CTRL->IO_OUTPUT |= (mask & GPIOS_MASK); in gpio_eos_s3_port_set_bits_raw()
235 uint32_t mask) in gpio_eos_s3_port_clear_bits_raw() argument
239 MISC_CTRL->IO_OUTPUT &= ~(mask & GPIOS_MASK); in gpio_eos_s3_port_clear_bits_raw()
245 uint32_t mask) in gpio_eos_s3_port_toggle_bits() argument
251 target_value = output_states ^ mask; in gpio_eos_s3_port_toggle_bits()
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| D | gpio_gecko.c | 237 uint32_t mask, in gpio_gecko_port_set_masked_raw() argument
243 GPIO_PortOutSetVal(gpio_index, value, mask); in gpio_gecko_port_set_masked_raw()
249 uint32_t mask) in gpio_gecko_port_set_bits_raw() argument
254 GPIO_PortOutSet(gpio_index, mask); in gpio_gecko_port_set_bits_raw()
260 uint32_t mask) in gpio_gecko_port_clear_bits_raw() argument
265 GPIO_PortOutClear(gpio_index, mask); in gpio_gecko_port_clear_bits_raw()
271 uint32_t mask) in gpio_gecko_port_toggle_bits() argument
276 GPIO_PortOutToggle(gpio_index, mask); in gpio_gecko_port_toggle_bits()
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| D | gpio_rt1718s_port.c | 106 static int gpio_rt1718s_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in gpio_rt1718s_port_set_masked_raw() argument
117 if (mask & BIT(pin)) { in gpio_rt1718s_port_set_masked_raw()
139 static int gpio_rt1718s_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask) in gpio_rt1718s_port_set_bits_raw() argument
149 if (mask & BIT(pin)) { in gpio_rt1718s_port_set_bits_raw()
166 static int gpio_rt1718s_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask) in gpio_rt1718s_port_clear_bits_raw() argument
176 if (mask & BIT(pin)) { in gpio_rt1718s_port_clear_bits_raw()
193 static int gpio_rt1718s_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask) in gpio_rt1718s_port_toggle_bits() argument
203 if (mask & BIT(pin)) { in gpio_rt1718s_port_toggle_bits()
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| /Zephyr-latest/boards/seeed/wio_terminal/ |
| D | grove_connectors.dtsi | 10 gpio-map-mask = <0xffffffff 0xffffffc0>;
18 gpio-map-mask = <0xffffffff 0xffffffc0>;
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_spi.c | 76 int icm42688_spi_update_register(const struct spi_dt_spec *bus, uint16_t reg, uint8_t mask, in icm42688_spi_update_register() argument
86 temp &= ~mask; in icm42688_spi_update_register()
87 temp |= FIELD_PREP(mask, data); in icm42688_spi_update_register()
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | timestamp.c | 24 #define BITS_COPY(dest, src, mask) ((dest) = ((dest) & ~(mask)) | ((src) & (mask))) argument
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| /Zephyr-latest/drivers/rtc/ |
| D | rtc_ll_stm32.c | 569 const struct rtc_time *timeptr, uint16_t mask) in rtc_stm32_init_ll_alrm_struct() argument
581 if (mask & RTC_ALARM_TIME_MASK_SECOND) { in rtc_stm32_init_ll_alrm_struct()
586 if (mask & RTC_ALARM_TIME_MASK_MINUTE) { in rtc_stm32_init_ll_alrm_struct()
591 if (mask & RTC_ALARM_TIME_MASK_HOUR) { in rtc_stm32_init_ll_alrm_struct()
596 if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) { in rtc_stm32_init_ll_alrm_struct()
609 } else if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) { in rtc_stm32_init_ll_alrm_struct()
693 uint16_t *mask) in rtc_stm32_alarm_get_supported_fields() argument
695 if (mask == NULL) { in rtc_stm32_alarm_get_supported_fields()
705 *mask = (uint16_t)RTC_STM32_SUPPORTED_ALARM_FIELDS; in rtc_stm32_alarm_get_supported_fields()
710 static int rtc_stm32_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, in rtc_stm32_alarm_get_time() argument
[all …]
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| /Zephyr-latest/include/zephyr/drivers/gpio/ |
| D | gpio_mmio32.h | 24 uint32_t mask; member
56 .mask = _mask, \
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | timer.h | 57 static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask) in arm_arch_timer_set_irq_mask() argument
63 if (mask) { in arm_arch_timer_set_irq_mask()
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32wb0_clock.h | 52 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
55 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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| D | stm32f1_clock.h | 53 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
56 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_stm32.c | 66 uint8_t mask; member
450 uint32_t mask = rngp->mask; in rng_pool_get() local
466 available = (last - first) & mask; in rng_pool_get()
475 rngp->first_alloc = (first + len) & mask; in rng_pool_get()
480 first = (first + 1) & mask; in rng_pool_get()
516 uint8_t mask = rngp->mask; in rng_pool_put() local
519 if (((last - first) & mask) == mask) { in rng_pool_put()
524 rngp->last = (last + 1) & mask; in rng_pool_put()
535 rngp->mask = size - 1; in rng_pool_init()
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| /Zephyr-latest/drivers/sensor/ti/tmp112/ |
| D | tmp112.c | 44 static uint16_t set_config_flags(struct tmp112_data *data, uint16_t mask, in set_config_flags() argument
47 return (data->config_reg & ~mask) | (value & mask); in set_config_flags()
50 static int tmp112_update_config(const struct device *dev, uint16_t mask, in tmp112_update_config() argument
55 const uint16_t new_val = set_config_flags(data, mask, val); in tmp112_update_config()
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| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_rf2xx_iface.h | 66 uint8_t mask,
80 uint8_t mask,
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| /Zephyr-latest/soc/ite/ec/common/ |
| D | soc_dt.h | 16 DT_PHA(IT8XXX2_DT_INST_WUCCTRL(inst, idx), wucs, mask)
40 .mask = IT8XXX2_DEV_WUC_MASK(idx, inst), \
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| /Zephyr-latest/include/zephyr/net/ |
| D | net_pkt_filter.h | 404 struct net_eth_addr mask; member
428 .mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
445 .mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
462 .mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
479 .mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
496 .mask.addr = { __VA_ARGS__ }, \
514 .mask.addr = { __VA_ARGS__ }, \
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| /Zephyr-latest/drivers/mfd/ |
| D | mfd_npm1300.c | 63 uint8_t mask; member
107 if ((buf[offset] & event_reg[i].mask) != 0U) { in work_callback()
111 event_reg[i].mask); in work_callback()
219 uint8_t mask) in mfd_npm1300_reg_update() argument
230 reg = (reg & ~mask) | (data & mask); in mfd_npm1300_reg_update()
286 event_reg[i].mask); in mfd_npm1300_add_callback()
294 event_reg[i].mask); in mfd_npm1300_add_callback()
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| /Zephyr-latest/include/zephyr/dt-bindings/adc/ |
| D | stm32_adc.h | 37 #define STM32_ADC(real_val, reg_val, mask, shift, reg) \ argument
40 (((mask) & STM32_ADC_MASK_MASK) << STM32_ADC_MASK_SHIFT) | \
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| /Zephyr-latest/arch/xtensa/core/ |
| D | xtensa_backtrace.c | 21 static int mask, cause; variable
30 pc = (pc & 0x3fffffff) | mask; in xtensa_cpu_process_stack_pc()
137 mask = stk_frame.pc & 0xc0000000; in xtensa_backtrace_print()
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| /Zephyr-latest/subsys/bluetooth/host/ |
| D | hci_core.c | 3328 uint64_t mask = 0U; in le_set_event_mask() local
3338 mask |= BT_EVT_MASK_LE_ADVERTISING_REPORT; in le_set_event_mask()
3342 mask |= BT_EVT_MASK_LE_ADV_SET_TERMINATED; in le_set_event_mask()
3343 mask |= BT_EVT_MASK_LE_SCAN_REQ_RECEIVED; in le_set_event_mask()
3344 mask |= BT_EVT_MASK_LE_EXT_ADVERTISING_REPORT; in le_set_event_mask()
3345 mask |= BT_EVT_MASK_LE_SCAN_TIMEOUT; in le_set_event_mask()
3347 mask |= BT_EVT_MASK_LE_PER_ADV_SYNC_ESTABLISHED; in le_set_event_mask()
3348 mask |= BT_EVT_MASK_LE_PER_ADVERTISING_REPORT; in le_set_event_mask()
3349 mask |= BT_EVT_MASK_LE_PER_ADV_SYNC_LOST; in le_set_event_mask()
3350 mask |= BT_EVT_MASK_LE_PAST_RECEIVED; in le_set_event_mask()
[all …]
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| /Zephyr-latest/arch/x86/core/ |
| D | x86_mmu.c | 82 pentry_t mask; member
123 .mask = 0x7FFFFFFFFFFFF000ULL,
134 .mask = 0x7FFFFFFFFFFFF000ULL,
150 .mask = 0x7FFFFFFFFFFFF000ULL,
155 .mask = 0xFFFFF000U,
166 .mask = 0x07FFFFFFFFFFF000ULL,
171 .mask = 0xFFFFF000U,
309 return entry & paging_levels[level].mask; in get_entry_phys()
759 virtmap, entry & info->mask, buf); in dump_entry()
1005 pentry_t *old_val_ptr, pentry_t mask, uint32_t options) in page_map_set() argument
[all …]
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