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Searched refs:cycles (Results 176 – 200 of 206) sorted by relevance

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/Zephyr-latest/drivers/espi/
DKconfig.it8xxx2131 # Port 80 and 81 I/O cycles share the same interrupt source and there is no
/Zephyr-latest/drivers/ethernet/
DKconfig.nxp_s32_netc82 RX interrupt coalescing timer threshold, in units of NETC clock cycles.
/Zephyr-latest/doc/services/portability/posix/implementation/
Dindex.rst39 the other library or subsystem. This reduces the likelihood of dependency cycles in code. When
/Zephyr-latest/drivers/pwm/
Dpwm_renesas_ra.c191 uint64_t *cycles) in pwm_renesas_ra_get_cycles_per_sec() argument
206 *cycles = (uint64_t)info.clock_frequency; in pwm_renesas_ra_get_cycles_per_sec()
Dpwm_renesas_rz_gpt.c169 uint64_t *cycles) in pwm_rz_gpt_get_cycles_per_sec() argument
185 *cycles = (uint64_t)info.clock_frequency; in pwm_rz_gpt_get_cycles_per_sec()
Dpwm_stm32.c760 uint32_t channel, uint64_t *cycles) in pwm_stm32_get_cycles_per_sec() argument
765 *cycles = (uint64_t)(data->tim_clk / (cfg->prescaler + 1)); in pwm_stm32_get_cycles_per_sec()
Dpwm_nxp_s32_emios.c567 uint32_t channel, uint64_t *cycles) in pwm_nxp_s32_get_cycles_per_sec() argument
580 *cycles = data->emios_clk / (internal_prescaler + 1); in pwm_nxp_s32_get_cycles_per_sec()
584 *cycles = data->emios_clk / ((internal_prescaler + 1) * (global_prescaler + 1)); in pwm_nxp_s32_get_cycles_per_sec()
/Zephyr-latest/drivers/dma/
DKconfig.xilinx_axi_dma100 CONFIG_DMA_XILINX_AXI_DMA_INTERRUPT_TIMEOUT * 125 * DMA_CLOCK_PERIOD cycles.
/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3.dts499 * default period is 1000 cycles <-> 20ms.
565 * default period is 1000 cycles <-> 20ms.
/Zephyr-latest/doc/releases/
Dindex.rst29 for at least two cycles, meaning that the project supports the most recent two
Dmigration-guide-4.0.rst246 the driver dynamically configures the division ratio by specified cycles.
Drelease-notes-1.11.rst465 * :github:`6164` - timer: cortex_m: Incorrect read of clock cycles counter after idle tickless peri…
/Zephyr-latest/tests/subsys/rtio/rtio_api/src/
Dtest_rtio_api.c677 uint64_t cycles = timing_cycles_get(&start_time, &end_time); in _test_rtio_throughput() local
678 uint64_t ns = timing_cycles_to_ns(cycles); in _test_rtio_throughput()
/Zephyr-latest/boards/cdns/xt-sim/doc/
Dindex.rst143 a. Set ``Hardware clock cycles per second`` to appropriate value
/Zephyr-latest/dts/riscv/
Driscv32-litex-vexriscv.dtsi157 "cycles",
/Zephyr-latest/subsys/debug/
DKconfig284 int "Spin lock holding time limit in cycles"
289 Assert at the time of unlocking the number of system clock cycles
/Zephyr-latest/boards/st/nucleo_wba52cg/doc/
Dnucleo_wba52cg.rst92 - 1 MB flash memory with ECC, including 256 Kbytes with 100 cycles
/Zephyr-latest/boards/st/nucleo_wba55cg/doc/
Dnucleo_wba55cg.rst90 - 1 MB flash memory with ECC, including 256 Kbytes with 100 cycles
/Zephyr-latest/doc/kernel/services/timing/
Dclocks.rst124 numbers of nanoseconds, microseconds, ticks and cycles, respectively.
136 cycles and ticks variants of this API.
/Zephyr-latest/dts/arm/st/g0/
Dstm32g0.dtsi418 * cycles, the sampling in a single ADC conversion or in
/Zephyr-latest/doc/develop/test/
Dtwister.rst903 For example, to extract three data fields ``metric``, ``cycles``,
910 - "(?P<metric>.*):(?P<cycles>.*) cycles, (?P<nanoseconds>.*) ns"
1004 - command: "kernel cycles"
1005 expected: "cycles: .* hw cycles"
/Zephyr-latest/kernel/
DKconfig524 - Thread total execution cycles
525 - System total execution cycles
815 of cycles per tick should be chosen so that 1 millisecond is exactly
874 is assuming 1 GHz CPU and 2 cycles per loop. Reality is certainly
/Zephyr-latest/doc/kernel/memory_management/
Dheap.rst91 complete within 1-200 cycles. One complexity is that the search of
/Zephyr-latest/boards/native/doc/
Darch_soc.rst131 /* Wait for a number of CPU cycles */
/Zephyr-latest/doc/kernel/services/threads/
Dindex.rst538 execution cycles of a thread.

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