1 /*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <zephyr/kernel.h>
7 #include <zephyr/device.h>
8 #include <zephyr/irq.h>
9 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
10 #include <zephyr/drivers/pwm.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include "r_gpt.h"
13 #include "r_gpt_cfg.h"
14 #include <zephyr/logging/log.h>
15 #include <stdio.h>
16
17 LOG_MODULE_REGISTER(pwm_renesas_ra, CONFIG_PWM_LOG_LEVEL);
18
19 #define DT_DRV_COMPAT renesas_ra_pwm
20
21 #define MAX_PIN 2U
22 #define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END 0x6U
23 #define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END 0x9U
24 #define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT 4
25 #define GPT_PRV_GTIO_TOGGLE_COMPARE_MATCH 0x3U
26
27 struct pwm_renesas_ra_capture_data {
28 pwm_capture_callback_handler_t callback;
29 void *user_data;
30 uint64_t period;
31 uint64_t pulse;
32 bool is_pulse_capture;
33 bool is_busy;
34 uint32_t overflows;
35 bool continuous;
36 };
37
38 struct pwm_renesas_ra_data {
39 gpt_instance_ctrl_t fsp_ctrl;
40 timer_cfg_t fsp_cfg;
41 gpt_extended_cfg_t extend_cfg;
42 uint16_t capture_a_event;
43 uint16_t overflow_event;
44
45 #ifdef CONFIG_PWM_CAPTURE
46 struct pwm_renesas_ra_capture_data capture;
47 #endif /* CONFIG_PWM_CAPTURE */
48 };
49
50 struct pwm_renesas_ra_config {
51 const struct device *clock_dev;
52 struct clock_control_ra_subsys_cfg clock_subsys;
53 const struct pinctrl_dev_config *pincfg;
54 };
55
pwm_renesas_ra_gtior_calculate(gpt_pin_level_t const stop_level)56 static uint32_t pwm_renesas_ra_gtior_calculate(gpt_pin_level_t const stop_level)
57 {
58 /* The stop level is used as both the initial level and the stop level. */
59 uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t)stop_level << R_GPT0_GTIOR_OADFLT_Pos) |
60 ((uint32_t)stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
61
62 uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
63
64 /* Calculate the gtior value for PWM mode only */
65 gtior |= gtion;
66
67 return gtior;
68 }
69
pwm_renesas_ra_apply_gtior_config(gpt_instance_ctrl_t * const p_ctrl,timer_cfg_t const * const p_cfg)70 static int pwm_renesas_ra_apply_gtior_config(gpt_instance_ctrl_t *const p_ctrl,
71 timer_cfg_t const *const p_cfg)
72 {
73 gpt_extended_cfg_t *p_extend = (gpt_extended_cfg_t *)p_cfg->p_extend;
74 uint32_t gtior = p_extend->gtior_setting.gtior;
75
76 #if GPT_CFG_OUTPUT_SUPPORT_ENABLE
77
78 /* Check if custom GTIOR settings are provided. */
79 if (p_extend->gtior_setting.gtior == 0) {
80 /* If custom GTIOR settings are not provided, calculate GTIOR. */
81 if (p_extend->gtioca.output_enabled) {
82 uint32_t gtioca_gtior =
83 pwm_renesas_ra_gtior_calculate(p_extend->gtioca.stop_level);
84
85 gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos;
86 }
87
88 if (p_extend->gtiocb.output_enabled) {
89 uint32_t gtiocb_gtior =
90 pwm_renesas_ra_gtior_calculate(p_extend->gtiocb.stop_level);
91
92 gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos;
93 }
94 }
95 #endif
96
97 #if GPT_PRV_EXTRA_FEATURES_ENABLED == GPT_CFG_OUTPUT_SUPPORT_ENABLE
98 gpt_extended_pwm_cfg_t const *p_pwm_cfg = p_extend->p_pwm_cfg;
99
100 if (NULL != p_pwm_cfg) {
101 /* Check if custom GTIOR settings are provided. */
102 if (p_extend->gtior_setting.gtior == 0) {
103 /* If custom GTIOR settings are not provided, set gtioca_disable_settings
104 * and gtiocb_disable_settings.
105 */
106 gtior |= (uint32_t)(p_pwm_cfg->gtioca_disable_setting
107 << R_GPT0_GTIOR_OADF_Pos);
108 gtior |= (uint32_t)(p_pwm_cfg->gtiocb_disable_setting
109 << R_GPT0_GTIOR_OBDF_Pos);
110 }
111 }
112 #endif
113
114 /* Check if custom GTIOR settings are provided. */
115 if (p_extend->gtior_setting.gtior == 0) {
116 /*
117 * If custom GTIOR settings are not provided, configure the noise filter for
118 * the GTIOC pins.
119 */
120 gtior |= (uint32_t)(p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos);
121 gtior |= (uint32_t)(p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos);
122 }
123
124 /* Set the I/O control register. */
125 p_ctrl->p_reg->GTIOR = gtior;
126
127 return 0;
128 }
129
pwm_renesas_ra_set_cycles(const struct device * dev,uint32_t pin,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)130 static int pwm_renesas_ra_set_cycles(const struct device *dev, uint32_t pin, uint32_t period_cycles,
131 uint32_t pulse_cycles, pwm_flags_t flags)
132 {
133 struct pwm_renesas_ra_data *data = dev->data;
134 uint32_t pulse;
135 fsp_err_t err;
136
137 if (pin >= MAX_PIN) {
138 LOG_ERR("Only valid for gtioca and gtiocb pins");
139 return -EINVAL;
140 }
141
142 if ((data->fsp_ctrl.variant == TIMER_VARIANT_16_BIT && period_cycles > UINT16_MAX) ||
143 (data->fsp_ctrl.variant == TIMER_VARIANT_32_BIT && period_cycles > UINT32_MAX)) {
144 LOG_ERR("Out of range period cycles are not valid");
145 return -EINVAL;
146 }
147
148 /* gtioca and gtiocb setting */
149 if (pin == GPT_IO_PIN_GTIOCA) {
150 data->extend_cfg.gtioca.output_enabled = true;
151 } else {
152 data->extend_cfg.gtiocb.output_enabled = true;
153 }
154
155 pulse = (flags & PWM_POLARITY_INVERTED) ? period_cycles - pulse_cycles : pulse_cycles;
156
157 /* Apply gtio output setting */
158 pwm_renesas_ra_apply_gtior_config(&data->fsp_ctrl, &data->fsp_cfg);
159
160 /* Stop timer */
161 err = R_GPT_Stop(&data->fsp_ctrl);
162 if (err != FSP_SUCCESS) {
163 return -EIO;
164 }
165
166 /* Update period cycles, reflected at an overflow */
167 err = R_GPT_PeriodSet(&data->fsp_ctrl, period_cycles);
168 if (err != FSP_SUCCESS) {
169 return -EIO;
170 }
171
172 /* Update pulse cycles, reflected at an overflow */
173 err = R_GPT_DutyCycleSet(&data->fsp_ctrl, pulse, pin);
174 if (err != FSP_SUCCESS) {
175 return -EIO;
176 }
177
178 /* Start timer */
179 err = R_GPT_Start(&data->fsp_ctrl);
180 if (err != FSP_SUCCESS) {
181 return -EIO;
182 }
183
184 LOG_DBG("channel %u, pin %u, pulse %u, period %u, prescaler: %u.", data->fsp_cfg.channel,
185 pin, pulse_cycles, period_cycles, data->fsp_cfg.source_div);
186
187 return 0;
188 };
189
pwm_renesas_ra_get_cycles_per_sec(const struct device * dev,uint32_t pin,uint64_t * cycles)190 static int pwm_renesas_ra_get_cycles_per_sec(const struct device *dev, uint32_t pin,
191 uint64_t *cycles)
192 {
193 struct pwm_renesas_ra_data *data = dev->data;
194 timer_info_t info;
195 fsp_err_t err;
196
197 if (pin >= MAX_PIN) {
198 LOG_ERR("Only valid for gtioca and gtiocb pins");
199 return -EINVAL;
200 }
201
202 err = R_GPT_InfoGet(&data->fsp_ctrl, &info);
203 if (err != FSP_SUCCESS) {
204 return -EIO;
205 }
206 *cycles = (uint64_t)info.clock_frequency;
207
208 return 0;
209 };
210
211 #ifdef CONFIG_PWM_CAPTURE
212 extern void gpt_capture_compare_a_isr(void);
213 extern void gpt_counter_overflow_isr(void);
214
enable_irq(IRQn_Type const irq,uint32_t priority,void * p_context)215 static void enable_irq(IRQn_Type const irq, uint32_t priority, void *p_context)
216 {
217 if (irq >= 0) {
218 R_BSP_IrqCfgEnable(irq, priority, p_context);
219 }
220 }
disable_irq(IRQn_Type irq)221 static void disable_irq(IRQn_Type irq)
222 {
223 /* Disable interrupts. */
224 if (irq >= 0) {
225 R_BSP_IrqDisable(irq);
226 R_FSP_IsrContextSet(irq, NULL);
227 }
228 }
229
pwm_renesas_ra_configure_capture(const struct device * dev,uint32_t pin,pwm_flags_t flags,pwm_capture_callback_handler_t cb,void * user_data)230 static int pwm_renesas_ra_configure_capture(const struct device *dev, uint32_t pin,
231 pwm_flags_t flags, pwm_capture_callback_handler_t cb,
232 void *user_data)
233 {
234 struct pwm_renesas_ra_data *data = dev->data;
235
236 if (pin != GPT_IO_PIN_GTIOCA) {
237 LOG_ERR("Feature only support for gtioca");
238 return -EINVAL;
239 }
240 if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
241 LOG_ERR("No PWWM capture type specified");
242 return -EINVAL;
243 }
244 if ((flags & PWM_CAPTURE_TYPE_MASK) == PWM_CAPTURE_TYPE_BOTH) {
245 LOG_ERR("Cannot capture both period and pulse width");
246 return -ENOTSUP;
247 }
248 if (data->capture.is_busy) {
249 LOG_ERR("Capture already active on this pin");
250 return -EBUSY;
251 }
252
253 if (flags & PWM_CAPTURE_TYPE_PERIOD) {
254 data->capture.is_pulse_capture = false;
255
256 if (flags & PWM_POLARITY_INVERTED) {
257 data->extend_cfg.start_source =
258 (gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
259 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
260 GPT_SOURCE_NONE);
261 data->extend_cfg.capture_a_source = data->extend_cfg.start_source;
262
263 } else {
264 data->extend_cfg.start_source =
265 (gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
266 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
267 GPT_SOURCE_NONE);
268 data->extend_cfg.capture_a_source = data->extend_cfg.start_source;
269 }
270 } else {
271 data->capture.is_pulse_capture = true;
272
273 if (flags & PWM_POLARITY_INVERTED) {
274 data->extend_cfg.start_source =
275 (gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
276 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
277 GPT_SOURCE_NONE);
278
279 data->extend_cfg.capture_a_source =
280 (gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
281 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
282 GPT_SOURCE_NONE);
283 } else {
284 data->extend_cfg.start_source =
285 (gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
286 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
287 GPT_SOURCE_NONE);
288
289 data->extend_cfg.capture_a_source =
290 (gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
291 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
292 GPT_SOURCE_NONE);
293 }
294 }
295
296 data->capture.callback = cb;
297 data->capture.user_data = user_data;
298 data->capture.continuous = flags & PWM_CAPTURE_MODE_CONTINUOUS;
299
300 if (data->capture.continuous) {
301 data->extend_cfg.stop_source = data->extend_cfg.capture_a_source;
302 data->extend_cfg.clear_source = data->extend_cfg.start_source;
303 } else {
304 data->extend_cfg.stop_source = (gpt_source_t)(GPT_SOURCE_NONE);
305 data->extend_cfg.clear_source = (gpt_source_t)(GPT_SOURCE_NONE);
306 }
307
308 return 0;
309 }
310
pwm_renesas_ra_enable_capture(const struct device * dev,uint32_t pin)311 static int pwm_renesas_ra_enable_capture(const struct device *dev, uint32_t pin)
312 {
313 struct pwm_renesas_ra_data *data = dev->data;
314 fsp_err_t err;
315
316 if (pin != GPT_IO_PIN_GTIOCA) {
317 LOG_ERR("Feature only support for gtioca");
318 return -EINVAL;
319 }
320
321 if (data->capture.is_busy) {
322 LOG_ERR("Capture already active on this pin");
323 return -EBUSY;
324 }
325
326 if (!data->capture.callback) {
327 LOG_ERR("PWM capture not configured");
328 return -EINVAL;
329 }
330
331 data->capture.is_busy = true;
332
333 /* Enable capture source */
334 err = R_GPT_Enable(&data->fsp_ctrl);
335 if (err != FSP_SUCCESS) {
336 return -EIO;
337 }
338
339 /* Enable interruption */
340 enable_irq(data->fsp_cfg.cycle_end_irq, data->fsp_cfg.cycle_end_irq, &data->fsp_ctrl);
341 enable_irq(data->extend_cfg.capture_a_irq, data->extend_cfg.capture_a_ipl, &data->fsp_ctrl);
342
343 R_ICU->IELSR[data->fsp_cfg.cycle_end_irq] = (elc_event_t)data->overflow_event;
344 R_ICU->IELSR[data->extend_cfg.capture_a_irq] = (elc_event_t)data->capture_a_event;
345
346 return 0;
347 }
348
pwm_renesas_ra_disable_capture(const struct device * dev,uint32_t pin)349 static int pwm_renesas_ra_disable_capture(const struct device *dev, uint32_t pin)
350 {
351 struct pwm_renesas_ra_data *data = dev->data;
352 fsp_err_t err;
353
354 if (pin != GPT_IO_PIN_GTIOCA) {
355 LOG_ERR("Feature only support for gtioca");
356 return -EINVAL;
357 }
358 data->capture.is_busy = false;
359
360 /* Disable interruption */
361 disable_irq(data->fsp_cfg.cycle_end_irq);
362 disable_irq(data->extend_cfg.capture_a_irq);
363
364 R_ICU->IELSR[data->fsp_cfg.cycle_end_irq] = (elc_event_t)ELC_EVENT_NONE;
365 R_ICU->IELSR[data->extend_cfg.capture_a_irq] = (elc_event_t)ELC_EVENT_NONE;
366
367 /* Disable capture source */
368 err = R_GPT_Disable(&data->fsp_ctrl);
369 if (err != FSP_SUCCESS) {
370 return -EIO;
371 }
372
373 /* Stop timer */
374 err = R_GPT_Stop(&data->fsp_ctrl);
375 if (err != FSP_SUCCESS) {
376 return -EIO;
377 }
378
379 /* Clear timer */
380 err = R_GPT_Reset(&data->fsp_ctrl);
381 if (err != FSP_SUCCESS) {
382 return -EIO;
383 }
384
385 return 0;
386 }
387
fsp_callback(timer_callback_args_t * p_args)388 static void fsp_callback(timer_callback_args_t *p_args)
389 {
390 const struct device *dev = p_args->p_context;
391 struct pwm_renesas_ra_data *data = dev->data;
392 timer_info_t info;
393
394 (void)R_GPT_InfoGet(&data->fsp_ctrl, &info);
395
396 uint64_t period = info.period_counts;
397
398 /* The maximum period is one more than the maximum 16,32-bit number, but will be reflected
399 * as 0
400 */
401 if (period == 0U) {
402 if (data->fsp_ctrl.variant == TIMER_VARIANT_16_BIT) {
403 period = UINT16_MAX + 1U;
404 } else {
405 period = UINT32_MAX + 1U;
406 }
407 }
408
409 /* Capture event */
410 if (p_args->event == TIMER_EVENT_CAPTURE_A) {
411 if (p_args->capture != 0U) {
412 if (data->capture.is_pulse_capture == true) {
413 data->capture.pulse =
414 (data->capture.overflows * period) + p_args->capture;
415 data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0,
416 data->capture.pulse, 0,
417 data->capture.user_data);
418 } else {
419 data->capture.period =
420 (data->capture.overflows * period) + p_args->capture;
421 data->capture.callback(dev, GPT_IO_PIN_GTIOCA, data->capture.period,
422 0, 0, data->capture.user_data);
423 }
424 data->capture.overflows = 0U;
425 /* Disable capture in single mode */
426 if (data->capture.continuous == false) {
427 pwm_renesas_ra_disable_capture(dev, GPT_IO_PIN_GTIOCA);
428 }
429 }
430 } else if (p_args->event == TIMER_EVENT_CYCLE_END) {
431 data->capture.overflows++;
432 } else {
433 data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0, 0, -ECANCELED,
434 data->capture.user_data);
435 }
436 }
437
438 #endif /* CONFIG_PWM_CAPTURE */
439
440 static const struct pwm_driver_api pwm_renesas_ra_driver_api = {
441 .get_cycles_per_sec = pwm_renesas_ra_get_cycles_per_sec,
442 .set_cycles = pwm_renesas_ra_set_cycles,
443 #ifdef CONFIG_PWM_CAPTURE
444 .configure_capture = pwm_renesas_ra_configure_capture,
445 .enable_capture = pwm_renesas_ra_enable_capture,
446 .disable_capture = pwm_renesas_ra_disable_capture,
447 #endif /* CONFIG_PWM_CAPTURE */
448 };
449
pwm_renesas_ra_init(const struct device * dev)450 static int pwm_renesas_ra_init(const struct device *dev)
451 {
452 struct pwm_renesas_ra_data *data = dev->data;
453 const struct pwm_renesas_ra_config *cfg = dev->config;
454 int err;
455
456 if (!device_is_ready(cfg->clock_dev)) {
457 LOG_ERR("clock control device not ready");
458 return -ENODEV;
459 }
460
461 err = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys);
462 if (err < 0) {
463 LOG_ERR("Could not initialize clock (%d)", err);
464 return err;
465 }
466
467 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
468 if (err) {
469 LOG_ERR("Failed to configure pins for PWM (%d)", err);
470 return err;
471 }
472
473 #if defined(CONFIG_PWM_CAPTURE)
474 data->fsp_cfg.p_callback = fsp_callback;
475 data->fsp_cfg.p_context = dev;
476 #endif /* defined(CONFIG_PWM_CAPTURE) */
477
478 data->fsp_cfg.p_extend = &data->extend_cfg;
479
480 err = R_GPT_Open(&data->fsp_ctrl, &data->fsp_cfg);
481 if (err != FSP_SUCCESS) {
482 return -EIO;
483 }
484
485 return 0;
486 }
487
488 #define _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) ELC_EVENT_GPT##channel##_CAPTURE_COMPARE_A
489 #define _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) ELC_EVENT_GPT##channel##_COUNTER_OVERFLOW
490
491 #define ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel)
492 #define ELC_EVENT_GPT_COUNTER_OVERFLOW(channel) _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel)
493
494 #ifdef CONFIG_PWM_CAPTURE
495 #define PWM_RA_IRQ_CONFIG_INIT(index) \
496 do { \
497 \
498 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, gtioca, irq), \
499 DT_INST_IRQ_BY_NAME(index, gtioca, priority), \
500 gpt_capture_compare_a_isr, NULL, 0); \
501 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, overflow, irq), \
502 DT_INST_IRQ_BY_NAME(index, overflow, priority), \
503 gpt_counter_overflow_isr, NULL, 0); \
504 } while (0)
505
506 #else
507 #define PWM_RA_IRQ_CONFIG_INIT(index)
508 #endif /* CONFIG_PWM_CAPTURE */
509
510 #define PWM_RA8_INIT(index) \
511 PINCTRL_DT_INST_DEFINE(index); \
512 static const gpt_extended_cfg_t g_timer1_extend_##index = { \
513 .gtioca = \
514 { \
515 .output_enabled = false, \
516 .stop_level = GPT_PIN_LEVEL_LOW, \
517 }, \
518 .gtiocb = \
519 { \
520 .output_enabled = false, \
521 .stop_level = GPT_PIN_LEVEL_LOW, \
522 }, \
523 .start_source = (gpt_source_t)(GPT_SOURCE_NONE), \
524 .stop_source = (gpt_source_t)(GPT_SOURCE_NONE), \
525 .clear_source = (gpt_source_t)(GPT_SOURCE_NONE), \
526 .count_up_source = (gpt_source_t)(GPT_SOURCE_NONE), \
527 .count_down_source = (gpt_source_t)(GPT_SOURCE_NONE), \
528 .capture_a_source = (gpt_source_t)(GPT_SOURCE_NONE), \
529 .capture_b_source = (gpt_source_t)(GPT_SOURCE_NONE), \
530 .capture_a_ipl = DT_INST_IRQ_BY_NAME(index, gtioca, priority), \
531 .capture_b_ipl = BSP_IRQ_DISABLED, \
532 .capture_a_irq = DT_INST_IRQ_BY_NAME(index, gtioca, irq), \
533 .capture_b_irq = FSP_INVALID_VECTOR, \
534 .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, \
535 .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, \
536 .p_pwm_cfg = NULL, \
537 .gtior_setting.gtior = (0x0U), \
538 }; \
539 static struct pwm_renesas_ra_data pwm_renesas_ra_data_##index = { \
540 .fsp_cfg = \
541 { \
542 .mode = TIMER_MODE_PWM, \
543 .source_div = DT_INST_PROP(index, divider), \
544 .channel = DT_INST_PROP(index, channel), \
545 .cycle_end_ipl = DT_INST_IRQ_BY_NAME(index, overflow, priority), \
546 .cycle_end_irq = DT_INST_IRQ_BY_NAME(index, overflow, irq), \
547 }, \
548 .extend_cfg = g_timer1_extend_##index, \
549 .capture_a_event = ELC_EVENT_GPT_CAPTURE_COMPARE_A(DT_INST_PROP(index, channel)), \
550 .overflow_event = ELC_EVENT_GPT_COUNTER_OVERFLOW(DT_INST_PROP(index, channel)), \
551 }; \
552 static const struct pwm_renesas_ra_config pwm_renesas_ra_config_##index = { \
553 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
554 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)), \
555 .clock_subsys = { \
556 .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(index, 0, mstp), \
557 .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(index, 0, stop_bit), \
558 }}; \
559 static int pwm_renesas_ra_init_##index(const struct device *dev) \
560 { \
561 PWM_RA_IRQ_CONFIG_INIT(index); \
562 int err = pwm_renesas_ra_init(dev); \
563 if (err != 0) { \
564 return err; \
565 } \
566 return 0; \
567 } \
568 DEVICE_DT_INST_DEFINE(index, pwm_renesas_ra_init_##index, NULL, \
569 &pwm_renesas_ra_data_##index, &pwm_renesas_ra_config_##index, \
570 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &pwm_renesas_ra_driver_api);
571
572 DT_INST_FOREACH_STATUS_OKAY(PWM_RA8_INIT);
573
