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/Zephyr-latest/soc/cdns/sample_controller32/include/
Dxtensa-sample-controller32.ld14 #include <xtensa/config/core-isa.h>
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/
Dxtensa-cavs-linker.ld17 #include <xtensa/config/core-isa.h>
/Zephyr-latest/doc/project/
Dtsc.rst53 core members in working groups and committees.
/Zephyr-latest/drivers/bluetooth/hci/
DKconfig228 Bluetooth HCI driver for communication with CMAC core
/Zephyr-latest/boards/native/nrf_bsim/doc/
Dnrf52_bsim.rst205 These nRF bsim boards use the `native simulator`_ at their core, so you can chose with which
/Zephyr-latest/boards/nxp/frdm_k22f/doc/
Dindex.rst293 …k22-120-mhz-cost-effective-full-speed-usb-microcontrollers-mcus-based-on-arm-cortex-m4-core:K22_120
/Zephyr-latest/boards/st/nucleo_l552ze_q/doc/
Dnucleol552ze_q.rst36 Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core.
/Zephyr-latest/boards/st/nucleo_h7s3l8/doc/
Dindex.rst46 Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core.
/Zephyr-latest/modules/openthread/
DCMakeLists.txt159 -DOPENTHREAD_PROJECT_CORE_CONFIG_FILE="openthread-core-zephyr-config.h"
/Zephyr-latest/dts/common/nordic/
Dnrf9280.dtsi368 reg-names = "wrapper", "core";
383 reg-names = "wrapper", "core";
/Zephyr-latest/doc/releases/
Drelease-notes-3.1.rst476 * STM32: Prevented the core from entering stop modes during entropy operations.
644 * Added v1.1 implementation of core LwM2M objects.
1059 …* Introduced inter core messaging backend (icmsg) that relies on simple inter core messaging buffer
1321 * :github:`45876` - boards: h747/h745: Update dual core flash and debug instructions
1390 * :github:`45486` - MCUBootloader can't building for imxrt1160_evk_cm7 core
1490 * :github:`44797` - x86: Interrupt handling not working for cores <> core0 - VMs not having core 0 …
1644 * :github:`43830` - LPC55S69 Not flashing to second core.
1738 * :github:`43258` - HCI core data buffer overflow with ESP32-C3 in Peripheral HR sample
1908 * :github:`40620` - zephyr with cadence xtensa core dsp LX7 ，helloworld program cannot be entered …
Drelease-notes-2.4.rst35 * CVE-2020-10066: Incorrect Error Handling in Bluetooth HCI core
298 * Enabled SMP on HSDK board, including dual core and quad core configurations.
864 * Added the ability to do core dump when fatal error is encountered.
1087 * :github:`27833` - [Coverity CID :212958] Out-of-bounds access in arch/x86/core/x86_mmu.c
1088 * :github:`27832` - [Coverity CID :212957] Out-of-bounds access in arch/x86/core/x86_mmu.c
1201 * :github:`27319` - [Coverity CID :211523] Bad bit shift operation in arch/arc/core/mpu/arc_mpu_v2_…
1394 * :github:`26362` - arc gdb failed to load core dump file
1404 * :github:`26352` - [Coverity CID :211049] Macro compares unsigned to 0 in arch/x86/core/x86_mmu.c
1626 * :github:`24301` - Support for multi core STM32 H75/H77 boards
Drelease-notes-4.0.rst241 * Added NXP i.MX93's Cortex-M33 core
357 * Added Thingy53 forwarding of network core pins to network core for SPI peripheral (disabled
367 * Added support for the NXP ``imx8qm`` and ``imx8qxp`` DSP core to enable the openAMP sample
610 * Added possibility to run STM32H7 flash driver from Cortex-M4 core.
739 * Added support for i.MX93 M33 core
Drelease-notes-3.6.rst78 * Common Cortex-M MPU code moved to ``arch/arm/core/mpu``.
153 * Added support for NXP MIMXRT595 DSP core.
212 It is now possible to run the BLE controller or 802.15.4 driver in the net core, and application
213 and BT host in the app core.
897 * Added support for object core, which allows to track networks sockets and
/Zephyr-latest/
D.ruff-excludes.toml28 "./arch/xtensa/core/gen_vectors.py" = [
33 "./arch/xtensa/core/gen_zsr.py" = [
36 "./arch/xtensa/core/xtensa_intgen.py" = [
1134 "./scripts/west_commands/fetchers/core.py" = [
1436 "./arch/xtensa/core/gen_vectors.py",
1437 "./arch/xtensa/core/gen_zsr.py",
1438 "./arch/xtensa/core/xtensa_intgen.py",
1678 "./scripts/west_commands/fetchers/core.py",
1688 "./scripts/west_commands/runners/core.py",
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi57 core-clock = <200000000>;
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx4.dtsi154 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */
/Zephyr-latest/doc/contribute/documentation/
Dgeneration.rst127 sudo pacman -S graphviz doxygen librsvg texlive-core texlive-bin \
/Zephyr-latest/boards/raspberrypi/rpi_pico/doc/
Dindex.rst20 - Dual core Arm Cortex-M0+ processor running up to 133MHz
/Zephyr-latest/boards/st/stm32wb5mmg/doc/
Dstm32wb5mmg.rst165 To operate bluetooth on STM32WB5MMG, Cortex-M0 core should be flashed with
/Zephyr-latest/doc/hardware/porting/
Dsoc_porting.rst22 - CPU core: a particular CPU instance of a given architecture.
Darch.rst102 depends on the exception, but most often the core kernel itself is responsible
153 implementation description for ARC in :zephyr_file:`arch/arc/core/isr_wrapper.S`.
173 :zephyr_file:`arch/arm/core/cortex_m/fault.c` for an example.
312 :zephyr_file:`arch/arm/core/cortex_m/Kconfig`).
/Zephyr-latest/boards/nxp/frdm_k64f/doc/
Dindex.rst374 …x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120
/Zephyr-latest/doc/develop/test/
Dpytest.rst110 the core of pytest harness plugin. It is required to launch DUT (initialize logging, flash device,
/Zephyr-latest/arch/
DKconfig637 states of the architecture core blocks are restored to the
873 This option, when enabled, indicates to the core kernel that an MPU
1100 Integrated on-core cache controller

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