Searched refs:core (Results 351 – 375 of 877) sorted by relevance
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | probe_rs.py | 6 from runners.core import RunnerCaps, ZephyrBinaryRunner
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| D | xsdb.py | 11 from runners.core import RunnerCaps, RunnerConfig, ZephyrBinaryRunner
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| /Zephyr-latest/boards/mediatek/mt8186/ |
| D | mt8186_adsp.dts | 34 compatible = "cdns,xtensa-core-intc";
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| /Zephyr-latest/dts/common/nordic/ |
| D | nrf5340_shared_sram_partition.dtsi | 16 * By default the last 64 kB of application core SRAM is allocated as shared
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| /Zephyr-latest/boards/mediatek/mt8188/ |
| D | mt8188_adsp.dts | 35 compatible = "cdns,xtensa-core-intc";
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| /Zephyr-latest/soc/st/stm32/stm32u5x/ |
| D | Kconfig | 29 All clocks in the core domain are stopped.
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| /Zephyr-latest/samples/subsys/ipc/openamp/remote/boards/ |
| D | mimxrt1160_evk_mimxrt1166_cm4.overlay | 10 /* Switch to lpuart2, since primary core uses lpuart1 */
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| D | mimxrt1170_evk_mimxrt1176_cm4.overlay | 10 /* Switch to lpuart2, since primary core uses lpuart1 */
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| /Zephyr-latest/samples/boards/nordic/system_off/ |
| D | README.rst | 30 nRF52 core output
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| /Zephyr-latest/modules/hal_nordic/nrfs/dvfs/ |
| D | Kconfig | 35 This value depends on the secdom core performance and shouldn't be touched by the user.
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| /Zephyr-latest/boards/m5stack/m5stack_cores3/doc/ |
| D | index.rst | 12 - ESP32-S3 chip (dual-core Xtensa LX7 processor @240MHz, WIFI, OTG and CDC functions)
261 .. _`M5Stack CoreS3 Documentation`: http://docs.m5stack.com/en/core/CoreS3
262 …ic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/K128%20CoreS3/Sch_M…
263 .. _`M5Stack CoreS3 SE Documentation`: https://docs.m5stack.com/en/core/M5CoreS3%20SE
264 …tic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/products/core/M5CORES3%20SE/M5_Co…
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| /Zephyr-latest/samples/userspace/syscall_perf/ |
| D | README.rst | 21 Both threads are showing the number of core clock cycles and the number of
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| /Zephyr-latest/arch/arm64/ |
| D | Kconfig | 32 rsource "core/Kconfig"
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| /Zephyr-latest/boards/nxp/mimxrt1160_evk/ |
| D | mimxrt1160_evk_mimxrt1166_cm4.dts | 51 * timer will be used instead of systick, as allows the core clock to
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| /Zephyr-latest/boards/weact/usb2canfdv1/doc/ |
| D | index.rst | 24 configured to provide a system clock of 60 MHz. This allows generating a FDCAN1 core clock of 80
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| /Zephyr-latest/soc/nuvoton/npcx/ |
| D | Kconfig | 106 This sets the clock ratio (core clock / SPI clock)
111 The SPI flash clock has the same frequency as the core clock.
116 The core clock frequency is twice the flash clock frequency.
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| /Zephyr-latest/boards/renesas/ek_ra4e2/doc/ |
| D | index.rst | 6 The RA4E2 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core
12 The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
18 - 100 MHz, Arm® Cortex®-M33 core
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| /Zephyr-latest/boards/renesas/ek_ra4m3/doc/ |
| D | index.rst | 7 Arm® Cortex®-M33 core with TrustZone. In concert with the secure crypto engine, it
14 The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
21 - 100 MHz Arm® Cortex®-M33 core
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| /Zephyr-latest/boards/renesas/ek_ra4m2/doc/ |
| D | index.rst | 7 Cortex®-M33 core. In concert with the secure crypto engine, it offers secure element
13 The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
20 - 100 MHz Arm® Cortex®-M33 core
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| /Zephyr-latest/doc/build/flashing/ |
| D | configuration.rst | 9 configuring when commands are ran for groups of board targets. As an example: a multi-core SoC
43 network CPU cores, and will only reset the network or application core after all images for the
44 respective core have been flashed.
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| /Zephyr-latest/boards/renesas/voice_ra4e1/doc/ |
| D | index.rst | 10 48pin package as the core logic device, with QSPI flash, OPAMP and power devices chosen from the
13 The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
19 - 100 MHz, Arm® Cortex®-M33 core
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| /Zephyr-latest/boards/sifive/hifive_unleashed/doc/ |
| D | index.rst | 7 multi-core 64bit RISC-V SoC.
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| /Zephyr-latest/boards/sifive/hifive_unmatched/doc/ |
| D | index.rst | 7 multi-core 64bit RISC-V SoC.
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| /Zephyr-latest/boards/nxp/mimxrt1170_evk/ |
| D | mimxrt1170_evk_mimxrt1176_cm4.dts | 51 * timer will be used instead of systick, as allows the core clock to
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.nxp_s32 | 29 Number of SIUL2 external interrupts grouped into a single core
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