1/* Copyright 2024 The ChromiumOS Authors
2 * SPDX-License-Identifier: Apache-2.0
3 */
4#include <mem.h>
5
6/dts-v1/;
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10
11	sram0: memory@4e100000 {
12		 device_type = "memory";
13		 compatible = "mmio-sram";
14		 reg = <0x4e100000 DT_SIZE_K(1024)>;
15	};
16
17	dram0: memory@60000000 {
18		device_type = "memory";
19		compatible = "mmio-sram";
20		reg = <0x60000000 DT_SIZE_M(16)>;
21	};
22
23	dram1: memory@61000000 {
24		device_type = "memory";
25		compatible = "mmio-sram";
26		reg = <0x61000000 DT_SIZE_K(1024)>;
27	};
28
29	soc {
30		#address-cells = <1>;
31		#size-cells = <1>;
32
33		core_intc: core_intc@0 {
34			compatible = "cdns,xtensa-core-intc";
35			reg = <0 4>;
36			interrupt-controller;
37			#interrupt-cells = <3>;
38		};
39
40		intc2: intc@10680010 {
41			compatible = "mediatek,adsp_intc";
42			interrupt-controller;
43			#interrupt-cells = <3>;
44			reg = <0x10680010 4>;
45			status-reg = <0x10680050>;
46			interrupts = <2 0 0>;
47			mask = <0x3f>;
48			interrupt-parent = <&core_intc>;
49		};
50
51		ostimer64: ostimer64@10683080 {
52			compatible = "mediatek,ostimer64";
53			reg = <0x10683080 28>;
54		};
55
56		ostimer0: ostimer@10683000 {
57			compatible = "mediatek,ostimer";
58			reg = <0x10683000 16>;
59			interrupt-parent = <&core_intc>;
60			interrupts = <18 0 0>;
61		};
62
63		mbox0: mbox@10686100 {
64			compatible = "mediatek,mbox";
65			reg = <0x10686100 16>;
66			interrupt-parent = <&intc2>;
67			interrupts = <1 0 0>;
68		};
69
70		mbox1: mbox@10687100 {
71			compatible = "mediatek,mbox";
72			reg = <0x10687100 16>;
73			interrupt-parent = <&intc2>;
74			interrupts = <2 0 0>;
75		};
76	}; /* soc */
77
78	chosen { };
79	aliases { };
80};
81