1/* Copyright 2024 The ChromiumOS Authors
2 * SPDX-License-Identifier: Apache-2.0
3 */
4#include <mem.h>
5
6/dts-v1/;
7/ {
8
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	sram0: memory@4e100000 {
13		 device_type = "memory";
14		 compatible = "mmio-sram";
15		 reg = <0x4e100000 DT_SIZE_K(512)>;
16	};
17
18	dram0: memory@60000000 {
19		device_type = "memory";
20		compatible = "mmio-sram";
21		reg = <0x60000000 DT_SIZE_M(15)>;
22	};
23
24	dram1: memory@61000000 {
25		device_type = "memory";
26		compatible = "mmio-sram";
27		reg = <0x61000000 DT_SIZE_K(1024)>;
28	};
29
30	soc {
31		#address-cells = <1>;
32		#size-cells = <1>;
33
34		core_intc: core_intc@0 {
35			compatible = "cdns,xtensa-core-intc";
36			reg = <0 4>;
37			interrupt-controller;
38			#interrupt-cells = <3>;
39		};
40
41		intc2: intc@10b80010 {
42			compatible = "mediatek,adsp_intc";
43			interrupt-controller;
44			#interrupt-cells = <3>;
45			reg = <0x10b80010 4>;
46			status-reg = <0x10b80050>;
47			interrupts = <2 0 0>;
48			mask = <0x3f>;
49			interrupt-parent = <&core_intc>;
50		};
51
52		ostimer64: ostimer64@10b83080 {
53			compatible = "mediatek,ostimer64";
54			reg = <0x10b83080 28>;
55		};
56
57		ostimer0: ostimer@10b83000 {
58			compatible = "mediatek,ostimer";
59			reg = <0x10b83000 16>;
60			interrupt-parent = <&core_intc>;
61			interrupts = <18 0 0>;
62		};
63
64		mbox0: mbox@10b86100 {
65			compatible = "mediatek,mbox";
66			reg = <0x10b86100 16>;
67			interrupt-parent = <&intc2>;
68			interrupts = <1 0 0>;
69		};
70
71		mbox1: mbox@10b87100 {
72			compatible = "mediatek,mbox";
73			reg = <0x10b87100 16>;
74			interrupt-parent = <&intc2>;
75			interrupts = <2 0 0>;
76		};
77	}; /* soc */
78
79	chosen { };
80	aliases { };
81};
82