1/*
2 * Copyright (c) 2021 Nordic Semiconductor ASA
3 * Copyright (c) 2024 Embeint Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * This file specifies the default shared memory region used for inter-procesor
8 * communication between the application and network cores.
9 *
10 * This file, or a board specific variant of it, must be included by both
11 * cpuapp and cpunet application to ensure both processors have the same
12 * expectations of the memory region used. If a board specific variant is
13 * used, it is up to the author to ensure the shared memory region resides in
14 * the memory range allocated to the non-secure image (sram0_ns).
15 *
16 * By default the last 64 kB of application core SRAM is allocated as shared
17 * memory (sram0_shared) which is divided in:
18 * - 32 kB CPUAPP to CPUNET communication (cpuapp_cpunet_ipc_shm)
19 * - 32 kB CPUNET to CPUAPP communication (cpunet_cpuapp_ipc_shm)
20 */
21
22/ {
23	chosen {
24		zephyr,ipc_shm = &sram0_shared;
25	};
26
27	reserved-memory {
28		#address-cells = <1>;
29		#size-cells = <1>;
30		ranges;
31
32		sram0_shared: memory@20070000 {
33			#address-cells = <1>;
34			#size-cells = <1>;
35			/* Last 64 kB of sram0 */
36			reg = <0x20070000 0x10000>;
37
38			cpuapp_cpunet_ipc_shm: memory@20070000 {
39				reg = <0x20070000 DT_SIZE_K(32)>;
40			};
41
42			cpunet_cpuapp_ipc_shm: memory@20078000 {
43				reg = <0x20078000 DT_SIZE_K(32)>;
44			};
45		};
46	};
47};
48