| /Zephyr-latest/boards/snps/hsdk4xd/support/ |
| D | openocd.cfg | 30 # Contains quad-core ARC HS4x.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS4x core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS4x core 3
80 # Enable L2 cache support for core 3.
84 # ARC HS4x core 4
96 # Enable L2 cache support for core 4.
100 # ARC HS4x core 1
111 # Enable L2 cache support for core 1.
|
| /Zephyr-latest/boards/snps/hsdk/support/ |
| D | openocd.cfg | 30 # Contains quad-core ARC HS38.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS38 core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS38 core 3
80 # Enable L2 cache support for core 3.
84 # ARC HS38 core 4
96 # Enable L2 cache support for core 4.
100 # ARC HS38 core 1
111 # Enable L2 cache support for core 1.
|
| D | openocd-2-cores.cfg | 30 # Contains quad-core ARC HS38.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS38 core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS38 core 1
80 # Enable L2 cache support for core 1.
|
| /Zephyr-latest/dts/arm/raspberrypi/rpi_pico/ |
| D | m33.dtsi | 9 /* Model in the device tree a Cortex-M33 core being 'plugged' into each
10 * 'socket' within the SoC. Within the datasheet these are core 0 and core 1.
|
| /Zephyr-latest/drivers/sensor/ams/ams_iAQcore/ |
| D | Kconfig | 1 # iAQ-core Digital VOC sensor configuration options
7 bool "iAQ-core Digital VOC sensor"
12 Enable driver for iAQ-core Digital VOC sensor.
|
| /Zephyr-latest/modules/hal_infineon/core-lib/ |
| D | CMakeLists.txt | 5 # Add core-lib
6 zephyr_include_directories(${ZEPHYR_HAL_INFINEON_MODULE_DIR}/core-lib/include)
|
| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | multiprocessing.c | 229 for (int core = 0; core < num_cpus; core++) { in send_ipi() local
230 if ((core != curr) && soc_cpus_active[core] && in send_ipi()
231 ((cpu_bitmap & BIT(core)) != 0)) { in send_ipi()
232 IDC[core].agents[1].ipc.idr = msg | INTEL_ADSP_IPC_BUSY; in send_ipi()
|
| /Zephyr-latest/soc/infineon/cat1a/ |
| D | Kconfig | 34 bool "Dual-core support [activate Cortex-M4]"
44 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6
45 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
50 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE
51 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
|
| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | Kconfig | 35 bool "LPC54114 Cortex-M0 second core"
37 Driver for second core startup
41 hex "Address the second core will boot at"
44 This is the address the second core will boot from. Additionally this
51 # Move the LMA address of second core into flash
|
| /Zephyr-latest/boards/nxp/mimxrt1170_evk/ |
| D | board.cmake | 20 board_runner_args(linkserver "--core=cm7")
23 …ove V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
30 board_runner_args(linkserver "--core=cm4")
|
| /Zephyr-latest/boards/nxp/mimxrt1180_evk/doc/ |
| D | index.rst | 6 The dual core i.MX RT1180 runs on the Cortex-M33 core at 240 MHz and on the
154 | GPIO_AON_08 | LPUART1_TX | UART Console M33 core |
156 | GPIO_AON_09 | LPUART1_RX | UART Console M33 core |
158 | GPIO_AON_19 | LPUART12_TX | UART Console M7 core |
160 | GPIO_AON_20 | LPUART12_RX | UART Console M7 core |
171 UART for M7 core is connected to USB-to-UART J60 connector.
178 running at 240MHz. When targeting the M7 core, SysTick will also be used,
185 configured for the CM7 console core and the remaining are not used.
244 When debugging cm33 core, need to ensure the SW5 on "0100" mode.
245 When debugging cm7 core, need to ensure the SW5 on "0001" mode.
[all …]
|
| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 14 SoC series (single core ARM Cortex-A9).
20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
|
| /Zephyr-latest/modules/hal_infineon/ |
| D | CMakeLists.txt | 16 ## Add core-lib sources for CAT1 devices
17 add_subdirectory(core-lib)
46 ## Add core-lib sources for CAT1 devices
47 add_subdirectory_ifndef(CONFIG_SOC_FAMILY_INFINEON_CAT1 core-lib)
|
| /Zephyr-latest/drivers/firmware/scmi/ |
| D | CMakeLists.txt | 5 # SCMI core files
6 zephyr_library_sources_ifdef(CONFIG_ARM_SCMI core.c)
|
| /Zephyr-latest/boards/nxp/lpcxpresso55s69/ |
| D | board.cmake | 14 board_runner_args(linkserver "--core=all")
20 board_runner_args(linkserver "--core=cm33_core0")
23 board_runner_args(linkserver "--core=cm33_core1")
|
| /Zephyr-latest/boards/nordic/nrf5340dk/doc/ |
| D | index.rst | 12 The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
14 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
16 the **application core**
17 * a secondary Arm Cortex-M33 core, with a reduced feature set, running at
18 a fixed 64 MHz, referred to as the **network core**.
21 core on the nRF5340 SoC. The ``nrf5340dk/nrf5340/cpunet`` build target provides
22 support for the network core on the nRF5340 SoC.
161 - Implementation Defined Attribution Unit (`IDAU`_) on the application core.
171 nRF5340 application core supports the Armv8-M Security Extension.
175 nRF5340 network core does not support the Armv8-M Security Extension.
[all …]
|
| /Zephyr-latest/boards/udoo/udoo_neo_full/doc/ |
| D | index.rst | 8 composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4
9 core running up to 227 MHz for high CPU performance and real-time response.
10 Zephyr was ported to run on the Cortex-M4 core only. In a future release, it
11 will also communicate with the Cortex-A9 core (running Linux) via OpenAMP.
16 - MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core
129 on the board with the on-chip PLL to generate core clock.
130 PLL settings for M4 core are set via code running on the A9 core.
135 The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the
136 remaining are used by the A9 core or not used.
141 The M4 core does not have a flash memory and is not provided a clock
[all …]
|
| /Zephyr-latest/scripts/tracing/ |
| D | trace_capture_usb.py | 10 import usb.core
43 usb_device = usb.core.find(idVendor=vendor_id, idProduct=product_id)
53 except usb.core.USBError as e:
60 except usb.core.USBError as e:
|
| /Zephyr-latest/samples/drivers/ipm/ipm_mcux/ |
| D | README.rst | 10 Some NXP microcontrollers from LPC family are dual-core, this
12 processor core to the other.
15 - :zephyr:board:`lpcxpresso54114`, two core processors (Cortex-M4F and Cortex-M0+)
16 - :zephyr:board:`lpcxpresso55s69`, two core processors (dual Cortex-M33)
|
| /Zephyr-latest/soc/nxp/mcx/mcxn/ |
| D | Kconfig | 39 bool "MCXN94X's second core"
42 Indicates the second core will be enabled, and the part will run
43 in dual core mode.
|
| /Zephyr-latest/boards/nordic/nrf7002dk/doc/ |
| D | index.rst | 19 The nRF5340 host is a dual-core SoC based on the Arm® Cortex®-M33 architecture.
22 * A full-featured Arm Cortex-M33F core with DSP instructions, FPU, and Armv8-M Security Extension,
23 running at up to 128 MHz, referred to as the application core.
24 * A secondary Arm Cortex-M33 core, with a reduced feature set, running at a fixed 64 MHz,
25 referred to as the network core.
27 The ``nrf7002dk/nrf5340/cpuapp`` board target provides support for the application core on the
29 core on the nRF5340 SoC.
165 * Implementation Defined Attribution Unit (`IDAU`_) on the application core.
176 The nRF5340 application core supports the Armv8-M Security Extension.
180 The nRF5340 network core does not support the Armv8-M Security Extension.
[all …]
|
| /Zephyr-latest/soc/nordic/common/vpr/ |
| D | Kconfig.sysbuild | 10 VPR launcher is a minimal sample built for an ARM core that starts given VPR core.
|
| /Zephyr-latest/boards/st/nucleo_h745zi_q/ |
| D | nucleo_h745zi_q_stm32h745xx_m7_defconfig | 13 # Enable UART ( disable to assign to M4 core)
16 # Console ( disable to assign to M4 core)
|
| /Zephyr-latest/boards/openisa/rv32m1_vega/support/ |
| D | openocd_rv32m1_vega_zero_riscy.cfg | 25 # Select the TAP core we are using
28 # Select the debug unit core we are using. This debug unit as an option.
38 # Select core 1
46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
|
| /Zephyr-latest/boards/st/nucleo_h755zi_q/ |
| D | nucleo_h755zi_q_stm32h755xx_m7_defconfig | 13 # Enable UART (disable to assign to M4 core)
16 # Console (disable to assign to M4 core)
|
