Searched refs:cache (Results 251 – 275 of 319) sorted by relevance
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66 - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory
59 - 256-Kbyte unified level 2 cache
61 - 1-Kbyte instruction cache allowing 0-wait-state execution from flash memory
73 - ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
71 - ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
61 - 256-Kbyte unified level 2 cache
35 (sizeof(memory_area) - offsetof(struct spsc_pbuf, ext.cache.data)) : in test_spsc_pbuf_flags()
29 d-cache-line-size = <32>;43 d-cache-line-size = <32>;
32 d-cache-line-size = <32>;43 d-cache-line-size = <32>;
133 * File system: Added API to flush cache of an opened file.214 * ``ZEP-767`` - Add FS API to flush cache of an open file
131 /* Various memory-map dependent cache attribute settings: */
20 d-cache-line-size = <64>;
28 * The IPv6 neighbor cache can be disabled if not needed, and its size can be
51 - 256-Kbyte unified level 2 cache
39 Set if the L1 or L2 cache is present in the SoC.
451 * when flash cache is disabled */578 /* logging sections should be placed in RAM area to avoid flash cache disabled issues */
157 /* Various memory-map dependent cache attribute settings: */
90 sd 3:0:0:0: [sdb] Assuming drive cache: write through
11 with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory inte…
260 4. Locking regions of the tests and/or the RTOS in cache is
814 cache = CMakeCache.from_file(cmake_cache_path)816 cache = {}818 for k in iter(cache):
543 * when flash cache is disabled */670 /* logging sections should be placed in RAM area to avoid flash cache disabled issues */
275 * when flash cache is disabled */
106 different cache, performance or power behavior, peripheral devices may
272 $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target
