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/Zephyr-latest/drivers/
DCMakeLists.txt23 add_subdirectory_ifdef(CONFIG_CACHE_MANAGEMENT cache)
DKconfig15 source "drivers/cache/Kconfig"
/Zephyr-latest/kernel/
DKconfig.smp109 running on cache-incoherent architectures only. Note that
111 assumes cache coherence to any memory passed to the kernel.
/Zephyr-latest/doc/develop/west/
Dconfig.rst237 * - ``update.name-cache``
239 ``--name-cache`` option's value if not given on the command line.
243 * - ``update.path-cache``
245 ``--path-cache`` option's value if not given on the command line.
/Zephyr-latest/soc/nxp/s32/s32k1/
DKconfig123 bool "Code cache"
/Zephyr-latest/modules/lz4/
DKconfig20 cost of speed, due to cache locality. Memory usage 2^value (10 -> 1KB,
/Zephyr-latest/drivers/serial/
Duart_max32.c52 uint8_t cache[MAX32_UART_TX_CACHE_NUM][CONFIG_UART_TX_CACHE_LEN]; member
546 ret = uart_max32_tx_dma_load(dev, tx->cache[tx->cache_id], in uart_max32_async_tx_callback()
567 tx->cache[!(tx->cache_id)]); in uart_max32_async_tx_callback()
647 data->async.tx.cache[0]); in api_tx()
652 ret = uart_max32_tx_dma_load(dev, use_cache ? data->async.tx.cache[0] : ((uint8_t *)buf), in api_tx()
/Zephyr-latest/share/zephyr-package/cmake/
DZephyrConfigVersion.cmake35 # First check to see if user has provided a Zephyr base manually and it is first run (cache not set…
52 # ZEPHYR_BASE was set in cache from earlier run or in environment (first run),
/Zephyr-latest/subsys/net/ip/
DKconfig.ipv655 int "Number of IPv6 PMTU destination cache entries"
148 bool "Neighbor cache"
151 The value depends on your network needs. Neighbor cache should
348 module-str = Log level for IPv6 neighbor cache
/Zephyr-latest/soc/nordic/nrf53/
DKconfig344 Instruction and Data cache is available on nRF5340 CPUAPP
347 Instruction cache only (I-Cache) is available in nRF5340
351 # TF-M nRF53 platform enables the cache unconditionally.
/Zephyr-latest/dts/x86/intel/
Dalder_lake.dtsi22 d-cache-line-size = <64>;
29 d-cache-line-size = <64>;
/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_cavs25_tgph.dtsi20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
Dintel_adsp_cavs25.dtsi20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
/Zephyr-latest/boards/adafruit/feather_stm32f405/doc/
Dindex.rst16 - 192KB RAM total - 128 KB RAM + 64 KB program-only/cache RAM
/Zephyr-latest/doc/contribute/style/
Dcmake.rst65 When defining cache variables using ``option`` or ``set(... CACHE ...)``, use
/Zephyr-latest/tests/subsys/ipc/ipc_sessions/interoperability/
DKconfig.icmsg_v181 reader and writer. It optionally embeds cache and memory barrier
/Zephyr-latest/cmake/modules/
Dwest.cmake76 # cache the value so the Zephyr Eclipse plugin knows how to invoke West.
/Zephyr-latest/doc/develop/toolchains/
Dcustom_cmake.rst41 If you do this, ``-C <initial-cache>`` `cmake option`_ may useful. If you save
/Zephyr-latest/soc/nordic/nrf52/
DKconfig73 bool "The instruction cache (I-Cache)"
/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst19 to two separate transactions: one for actual data and another for cache line
/Zephyr-latest/modules/mbedtls/
DKconfig.tls-generic462 bool "SSL session cache support"
464 "This option enables simple SSL cache implementation (server side)."
469 int "Default timeout for SSL cache entires"
473 int "Maximum number of SSL cache entires"
/Zephyr-latest/boards/snps/em_starterkit/doc/
Dindex.rst31 access to 128KB DRAM with i-cache and d-cache. The configuration file for EM7D
296 * ``GH-2647``: Zephyr needs i-cache API (all targets)
/Zephyr-latest/boards/raspberrypi/rpi_5/doc/
Dindex.rst11 …rm Cortex-A76 CPU, with cryptography extensions, 512KB per-core L2 caches and a 2MB shared L3 cache
/Zephyr-latest/boards/st/nucleo_u575zi_q/doc/
Dindex.rst86 - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
88 - 4-Kbyte data cache for external memories
/Zephyr-latest/soc/intel/intel_adsp/
DKconfig103 Need to power cache SRAM banks on.

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