1# NXP S32K1XX MCUs series
2
3# Copyright 2023-2024 NXP
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_SERIES_S32K1
7	select ARM
8	select HAS_NXP_S32_HAL
9	select HAS_MCUX
10	select CPU_HAS_NXP_SYSMPU
11	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
12	select MPU_ALLOW_FLASH_WRITE if !XIP
13	select CLOCK_CONTROL
14	select HAS_MCUX_LPUART
15	select HAS_MCUX_LPI2C
16	select HAS_MCUX_LPSPI
17	select HAS_MCUX_FTM
18	select HAS_MCUX_FLEXCAN
19	select HAS_MCUX_WDOG32
20	select HAS_MCUX_RTC
21	select HAS_MCUX_ADC12
22	select SOC_EARLY_INIT_HOOK
23	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
24
25config SOC_S32K116
26	select CPU_CORTEX_M0PLUS
27
28config SOC_S32K118
29	select CPU_CORTEX_M0PLUS
30
31config SOC_S32K142
32	select CPU_CORTEX_M4
33	select CPU_CORTEX_M_HAS_DWT
34	select CPU_HAS_FPU
35	select HAS_MCUX_CACHE
36
37config SOC_S32K142W
38	select CPU_CORTEX_M4
39	select CPU_CORTEX_M_HAS_DWT
40	select CPU_HAS_FPU
41	select HAS_MCUX_CACHE
42
43config SOC_S32K144
44	select CPU_CORTEX_M4
45	select CPU_CORTEX_M_HAS_DWT
46	select CPU_HAS_FPU
47	select HAS_MCUX_CACHE
48
49config SOC_S32K144W
50	select CPU_CORTEX_M4
51	select CPU_CORTEX_M_HAS_DWT
52	select CPU_HAS_FPU
53	select HAS_MCUX_CACHE
54
55config SOC_S32K146
56	select CPU_CORTEX_M4
57	select CPU_CORTEX_M_HAS_DWT
58	select CPU_HAS_FPU
59	select HAS_MCUX_CACHE
60
61config SOC_S32K148
62	select CPU_CORTEX_M4
63	select CPU_CORTEX_M_HAS_DWT
64	select CPU_HAS_FPU
65	select HAS_MCUX_CACHE
66
67if SOC_SERIES_S32K1
68
69config WDOG_INIT
70	bool
71	default y
72
73config NXP_S32_FLASH_CONFIG
74	bool "NXP S32 flash configuration field"
75	default y if XIP && !BOOTLOADER_MCUBOOT
76	help
77	  Include the 16-byte flash configuration field that stores default
78	  protection settings (loaded on reset) and security information that
79	  allows the MCU to restrict access to the FTFx module.
80
81if NXP_S32_FLASH_CONFIG
82
83config NXP_S32_FLASH_CONFIG_OFFSET
84	hex "NXP S32 flash configuration field offset"
85	default 0x400
86
87config NXP_S32_FLASH_CONFIG_FSEC
88	hex "Flash security byte (FSEC)"
89	range 0 0xff
90	default 0xfe
91	help
92	  Configures the reset value of the FSEC register, which includes
93	  backdoor key access, mass erase, factory access, and flash security
94	  options.
95
96config NXP_S32_FLASH_CONFIG_FOPT
97	hex "Flash nonvolatile option byte (FOPT)"
98	range 0 0xff
99	default 0xff
100	help
101	  Configures the reset value of the FOPT register, which includes boot,
102	  NMI, and EzPort options.
103
104config NXP_S32_FLASH_CONFIG_FEPROT
105	hex "EEPROM protection byte (FEPROT)"
106	range 0 0xff
107	default 0xff
108	help
109	  Configures the reset value of the FEPROT register for FlexNVM
110	  devices. For program flash only devices, this byte is reserved.
111
112config NXP_S32_FLASH_CONFIG_FDPROT
113	hex "Data flash protection byte (FDPROT)"
114	range 0 0xff
115	default 0xff
116	help
117	  Configures the reset value of the FDPROT register for FlexNVM
118	  devices. For program flash only devices, this byte is reserved.
119
120endif # NXP_S32_FLASH_CONFIG
121
122config NXP_S32_ENABLE_CODE_CACHE
123	bool "Code cache"
124	default y
125	depends on HAS_MCUX_CACHE
126
127endif # SOC_SERIES_S32K1
128