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Searched refs:base (Results 76 – 100 of 833) sorted by relevance

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/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wdog.c22 WDOG_Type *base; member
38 WDOG_Type *base = config->base; in mcux_wdog_setup() local
51 WDOG_Init(base, &data->wdog_config); in mcux_wdog_setup()
61 WDOG_Type *base = config->base; in mcux_wdog_disable() local
63 WDOG_Deinit(base); in mcux_wdog_disable()
122 WDOG_Type *base = config->base; in mcux_wdog_feed() local
129 WDOG_Refresh(base); in mcux_wdog_feed()
139 WDOG_Type *base = config->base; in mcux_wdog_isr() local
142 flags = WDOG_GetStatusFlags(base); in mcux_wdog_isr()
143 WDOG_ClearStatusFlags(base, flags); in mcux_wdog_isr()
[all …]
Dwdt_mcux_wwdt.c26 WWDT_Type *base; member
41 WWDT_Type *base = config->base; in mcux_wwdt_setup() local
48 WWDT_Init(base, &data->wwdt_config); in mcux_wwdt_setup()
58 WWDT_Type *base = config->base; in mcux_wwdt_disable() local
60 WWDT_Deinit(base); in mcux_wwdt_disable()
139 WWDT_Type *base = config->base; in mcux_wwdt_feed() local
146 WWDT_Refresh(base); in mcux_wwdt_feed()
156 WWDT_Type *base = config->base; in mcux_wwdt_isr() local
159 flags = WWDT_GetStatusFlags(base); in mcux_wwdt_isr()
160 WWDT_ClearStatusFlags(base, flags); in mcux_wwdt_isr()
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_mcux_lpc_rtc.c25 RTC_Type *base; member
43 uint32_t current = RTC_GetSecondsTimerCount(config->base); in mcux_lpc_rtc_isr()
47 if ((RTC_GetStatusFlags(config->base) & RTC_CTRL_ALARM1HZ_MASK) && in mcux_lpc_rtc_isr()
64 if (RTC_GetStatusFlags(config->base) & RTC_CTRL_ALARM1HZ_MASK) { in mcux_lpc_rtc_isr()
65 RTC_ClearStatusFlags(config->base, kRTC_AlarmFlag); in mcux_lpc_rtc_isr()
69 if (RTC_GetStatusFlags(config->base) & RTC_CTRL_WAKE1KHZ_MASK) { in mcux_lpc_rtc_isr()
70 RTC_ClearStatusFlags(config->base, kRTC_WakeupFlag); in mcux_lpc_rtc_isr()
72 if (config->base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK) { in mcux_lpc_rtc_isr()
89 RTC_EnableTimer(config->base, true); in mcux_lpc_rtc_start()
100 RTC_EnableTimer(config->base, false); in mcux_lpc_rtc_stop()
[all …]
Dcounter_mcux_lptmr.c21 LPTMR_Type *base; member
40 LPTMR_EnableInterrupts(config->base, in mcux_lptmr_start()
42 LPTMR_StartTimer(config->base); in mcux_lptmr_start()
51 LPTMR_DisableInterrupts(config->base, in mcux_lptmr_stop()
53 LPTMR_StopTimer(config->base); in mcux_lptmr_stop()
62 *ticks = LPTMR_GetCurrentTimerCount(config->base); in mcux_lptmr_get_value()
80 if (config->base->CSR & LPTMR_CSR_TEN_MASK) { in mcux_lptmr_set_top_value()
85 LPTMR_StopTimer(config->base); in mcux_lptmr_set_top_value()
86 LPTMR_SetTimerPeriod(config->base, cfg->ticks); in mcux_lptmr_set_top_value()
87 LPTMR_StartTimer(config->base); in mcux_lptmr_set_top_value()
[all …]
Dcounter_mcux_ctimer.c37 CTIMER_Type *base; member
50 CTIMER_StartTimer(config->base); in mcux_lpc_ctimer_start()
59 CTIMER_StopTimer(config->base); in mcux_lpc_ctimer_stop()
64 static uint32_t mcux_lpc_ctimer_read(CTIMER_Type *base) in mcux_lpc_ctimer_read() argument
66 return CTIMER_GetTimerCountValue(base); in mcux_lpc_ctimer_read()
72 *ticks = mcux_lpc_ctimer_read(config->base); in mcux_lpc_ctimer_get_value()
81 CTIMER_Type *base = config->base; in mcux_lpc_ctimer_get_top_value() local
84 if (base->MR[NUM_CHANNELS] != 0) { in mcux_lpc_ctimer_get_top_value()
85 return base->MR[NUM_CHANNELS]; in mcux_lpc_ctimer_get_top_value()
100 uint32_t current = mcux_lpc_ctimer_read(config->base); in mcux_lpc_ctimer_set_alarm()
[all …]
/Zephyr-latest/drivers/sdhc/
Dimx_usdhc.c54 USDHC_Type *base; member
163 static void imx_usdhc_select_1_8v(USDHC_Type *base, bool enable_1_8v) in imx_usdhc_select_1_8v() argument
167 UDSHC_SelectVoltage(base, enable_1_8v); in imx_usdhc_select_1_8v()
209 uint32_t status = USDHC_GetPresentStatusFlags(cfg->base); in imx_usdhc_error_recovery()
213 USDHC_Reset(cfg->base, kUSDHC_ResetCommand, 100U); in imx_usdhc_error_recovery()
216 (USDHC_GetAdmaErrorStatusFlags(cfg->base) != 0U)) { in imx_usdhc_error_recovery()
218 USDHC_Reset(cfg->base, kUSDHC_DataInhibitFlag, 100U); in imx_usdhc_error_recovery()
239 USDHC_GetCapability(cfg->base, &caps); in imx_usdhc_init_host_props()
268 imx_usdhc_select_1_8v(cfg->base, false); in imx_usdhc_reset()
269 USDHC_EnableDDRMode(cfg->base, false, 0U); in imx_usdhc_reset()
[all …]
/Zephyr-latest/kernel/include/
Dpriority_q.h71 sys_dlist_remove(&thread->base.qnode_dlist); in z_priq_dumb_remove()
80 thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); in z_priq_dumb_best()
98 thread->base.order_key = pq->next_order_key; in z_priq_rb_add()
108 RB_FOR_EACH_CONTAINER(&pq->tree, t, base.qnode_rb) { in z_priq_rb_add()
109 t->base.order_key = pq->next_order_key; in z_priq_rb_add()
114 rb_insert(&pq->tree, &thread->base.qnode_rb); in z_priq_rb_add()
119 rb_remove(&pq->tree, &thread->base.qnode_rb); in z_priq_rb_remove()
132 thread = CONTAINER_OF(n, struct k_thread, base.qnode_rb); in z_priq_rb_best()
154 thread = CONTAINER_OF(n, struct k_thread, base.qnode_dlist); in z_priq_mq_best()
192 struct prio_info pos = get_prio_info(thread->base.prio); in z_priq_mq_add()
[all …]
/Zephyr-latest/lib/libc/minimal/source/stdlib/
Dqsort.c32 #define A(k) ((uint8_t *)base + size * (k))
52 static void sift_down(void *base, int start, int end, size_t size, struct qsort_comp *cmp) in sift_down() argument
79 static void heapify(void *base, int nmemb, size_t size, struct qsort_comp *cmp) in heapify() argument
84 sift_down(base, start, nmemb, size, cmp); in heapify()
88 static void heap_sort(void *base, int nmemb, size_t size, struct qsort_comp *cmp) in heap_sort() argument
92 heapify(base, nmemb, size, cmp); in heap_sort()
96 sift_down(base, 0, end, size, cmp); in heap_sort()
100 void qsort_r(void *base, size_t nmemb, size_t size, in qsort_r() argument
111 heap_sort(base, nmemb, size, &cmp); in qsort_r()
114 void qsort(void *base, size_t nmemb, size_t size, in qsort() argument
[all …]
/Zephyr-latest/drivers/serial/
Duart_mcux_lpsci.c19 UART0_Type *base; member
39 uint32_t flags = LPSCI_GetStatusFlags(config->base); in mcux_lpsci_poll_in()
43 *c = LPSCI_ReadByte(config->base); in mcux_lpsci_poll_in()
54 while (!(LPSCI_GetStatusFlags(config->base) in mcux_lpsci_poll_out()
58 LPSCI_WriteByte(config->base, c); in mcux_lpsci_poll_out()
64 uint32_t flags = LPSCI_GetStatusFlags(config->base); in mcux_lpsci_err_check()
79 LPSCI_ClearStatusFlags(config->base, kLPSCI_RxOverrunFlag | in mcux_lpsci_err_check()
95 (LPSCI_GetStatusFlags(config->base) in mcux_lpsci_fifo_fill()
98 LPSCI_WriteByte(config->base, tx_data[num_tx++]); in mcux_lpsci_fifo_fill()
111 (LPSCI_GetStatusFlags(config->base) in mcux_lpsci_fifo_read()
[all …]
Duart_msp432p4xx.c24 unsigned long base; member
41 .base = DT_INST_REG_ADDR(0),
140 MAP_UART_initModule(config->base, &UartConfig); in uart_msp432p4xx_init()
143 MAP_UART_enableModule(config->base); in uart_msp432p4xx_init()
160 *c = MAP_UART_receiveData(config->base); in uart_msp432p4xx_poll_in()
170 MAP_UART_transmitData(config->base, c); in uart_msp432p4xx_poll_out()
181 MAP_UART_transmitData(config->base, tx_data[num_tx]); in uart_msp432p4xx_fifo_fill()
182 if (MAP_UART_getInterruptStatus(config->base, in uart_msp432p4xx_fifo_fill()
202 config->base, EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG)) { in uart_msp432p4xx_fifo_read()
204 rx_data[num_rx++] = MAP_UART_receiveData(config->base); in uart_msp432p4xx_fifo_read()
[all …]
Duart_rv32m1_lpuart.c20 LPUART_Type *base; member
43 uint32_t flags = LPUART_GetStatusFlags(config->base); in rv32m1_lpuart_poll_in()
47 *c = LPUART_ReadByte(config->base); in rv32m1_lpuart_poll_in()
58 while (!(LPUART_GetStatusFlags(config->base) in rv32m1_lpuart_poll_out()
62 LPUART_WriteByte(config->base, c); in rv32m1_lpuart_poll_out()
68 uint32_t flags = LPUART_GetStatusFlags(config->base); in rv32m1_lpuart_err_check()
83 LPUART_ClearStatusFlags(config->base, kLPUART_RxOverrunFlag | in rv32m1_lpuart_err_check()
99 (LPUART_GetStatusFlags(config->base) in rv32m1_lpuart_fifo_fill()
102 LPUART_WriteByte(config->base, tx_data[num_tx++]); in rv32m1_lpuart_fifo_fill()
115 (LPUART_GetStatusFlags(config->base) in rv32m1_lpuart_fifo_read()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_rp1.c15 #define GPIO_STATUS(base, n) (base + 0x8 * n) argument
16 #define GPIO_CTRL(base, n) (GPIO_STATUS(base, n) + 0x4) argument
30 #define RIO_OUT(base) (base) argument
31 #define RIO_OE(base) (base + 0x4) argument
32 #define RIO_IN(base) (base + 0x8) argument
37 #define RIO_OUT_SET(base) (RIO_OUT(base) + RIO_SET) argument
38 #define RIO_OUT_CLR(base) (RIO_OUT(base) + RIO_CLR) argument
40 #define RIO_OE_SET(base) (RIO_OE(base) + RIO_SET) argument
41 #define RIO_OE_CLR(base) (RIO_OE(base) + RIO_CLR) argument
43 #define PADS_CTRL(base, n) (base + 0x4 * (n + 1)) argument
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.c286 static void esai_commit_config(ESAI_Type *base, in esai_commit_config() argument
291 base->TCCR &= ~(ESAI_TCCR_THCKD_MASK | ESAI_TCCR_TFSD_MASK | in esai_commit_config()
297 base->TCCR |= ESAI_TCCR_THCKD(cfg->hclk_dir) | in esai_commit_config()
308 base->TCR &= ~(ESAI_TCR_PADC_MASK | ESAI_TCR_TFSR_MASK | in esai_commit_config()
312 base->TCR |= ESAI_TCR_PADC(cfg->zero_pad_en) | in esai_commit_config()
320 base->ECR &= ~(ESAI_ECR_ETI_MASK | in esai_commit_config()
323 base->ECR |= ESAI_ECR_ETI(cfg->hclk_src) | in esai_commit_config()
326 base->TFCR &= ~(ESAI_TFCR_TFWM_MASK | ESAI_TFCR_TWA_MASK); in esai_commit_config()
327 base->TFCR |= ESAI_TFCR_TFWM(cfg->watermark) | in esai_commit_config()
330 ESAI_TxSetSlotMask(base, cfg->slot_mask); in esai_commit_config()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_mcux.c24 PWM_Type *base; member
70 PWM_StopTimer(config->base, 1U << config->index); in mcux_pwm_set_cycles_internal()
82 status = PWM_SetupPwm(config->base, config->index, in mcux_pwm_set_cycles_internal()
93 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
96 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
99 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
101 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
106 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
109 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
112 PWM_SetVALxValue(config->base, config->index, in mcux_pwm_set_cycles_internal()
[all …]
Dpwm_mcux_qtmr.c24 TMR_Type *base; member
71 config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); in mcux_qtmr_pwm_set_cycles()
73 QTMR_StopTimer(config->base, channel); in mcux_qtmr_pwm_set_cycles()
76 config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
77 config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
80 config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
81 config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
83 reg = config->base->CHANNEL[channel].CSCTRL; in mcux_qtmr_pwm_set_cycles()
89 config->base->CHANNEL[channel].CSCTRL = reg; in mcux_qtmr_pwm_set_cycles()
91 reg = config->base->CHANNEL[channel].CTRL; in mcux_qtmr_pwm_set_cycles()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_dw_common.c39 status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS); in dw_dma_isr()
45 status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK); in dw_dma_isr()
46 status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR); in dw_dma_isr()
49 status_err = dw_read(dev_cfg->base, DW_STATUS_ERR); in dw_dma_isr()
52 dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err); in dw_dma_isr()
56 dw_write(dev_cfg->base, DW_CLEAR_BLOCK, status_block); in dw_dma_isr()
57 dw_write(dev_cfg->base, DW_CLEAR_TFR, status_tfr); in dw_dma_isr()
416 dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_UNMASK(channel)); in dw_dma_config()
420 dw_write(dev_cfg->base, DW_MASK_TFR, DW_CHAN_UNMASK(channel)); in dw_dma_config()
423 dw_write(dev_cfg->base, DW_MASK_ERR, DW_CHAN_UNMASK(channel)); in dw_dma_config()
[all …]
/Zephyr-latest/drivers/adc/
Dadc_cc32xx.c49 unsigned long base; member
67 static inline void start_sampling(unsigned long base, int ch) in start_sampling() argument
69 MAP_ADCChannelEnable(base, ch); in start_sampling()
71 while (!MAP_ADCFIFOLvlGet(base, ch)) { in start_sampling()
73 MAP_ADCFIFORead(base, ch); in start_sampling()
75 MAP_ADCIntClear(base, ch, ISR_MASK); in start_sampling()
76 MAP_ADCIntEnable(base, ch, ISR_MASK); in start_sampling()
90 start_sampling(config->base, s_channel[i]); in adc_context_start_sampling()
120 MAP_ADCIntDisable(config->base, ch, ISR_MASK); in adc_cc32xx_init()
121 MAP_ADCChannelDisable(config->base, ch); in adc_cc32xx_init()
[all …]
/Zephyr-latest/kernel/
Dtimeslicing.c30 if (thread->base.slice_ticks != 0) { in slice_time()
31 ret = thread->base.slice_ticks; in slice_time()
43 && !z_is_prio_higher(thread->base.prio, slice_max_prio) in thread_is_sliceable()
48 ret |= thread->base.slice_ticks != 0; in thread_is_sliceable()
94 thread->base.slice_ticks = thread_slice_ticks; in k_thread_time_slice_set()
95 thread->base.slice_expired = expired; in k_thread_time_slice_set()
96 thread->base.slice_data = data; in k_thread_time_slice_set()
119 if (curr->base.slice_expired) { in z_time_slice()
121 curr->base.slice_expired(curr, curr->base.slice_data); in z_time_slice()
Dusage.c63 thread->base.usage.total += cycles; in sched_thread_update_usage()
66 thread->base.usage.current += cycles; in sched_thread_update_usage()
68 if (thread->base.usage.longest < thread->base.usage.current) { in sched_thread_update_usage()
69 thread->base.usage.longest = thread->base.usage.current; in sched_thread_update_usage()
83 if (thread->base.usage.track_usage) { in z_sched_usage_start()
84 thread->base.usage.num_windows++; in z_sched_usage_start()
85 thread->base.usage.current = 0; in z_sched_usage_start()
110 if (cpu->current->base.usage.track_usage) { in z_sched_usage_stop()
142 if (cpu->current->base.usage.track_usage) { in z_sched_cpu_usage()
165 _kernel.cpus[cpu_id].idle_thread->base.usage.total; in z_sched_cpu_usage()
[all …]
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c64 #define UDC_DWC2_EP_FIFO(base, idx) ((mem_addr_t)base + 0x1000 * (idx + 1)) argument
174 return config->base; in dwc2_get_base()
207 struct usb_dwc2_reg *const base = dwc2_get_base(dev); in dwc2_get_dxepctl_reg() local
211 return (mem_addr_t)&base->out_ep[ep_idx].doepctl; in dwc2_get_dxepctl_reg()
213 return (mem_addr_t)&base->in_ep[ep_idx].diepctl; in dwc2_get_dxepctl_reg()
220 struct usb_dwc2_reg *const base = dwc2_get_base(dev); in dwc2_ftx_avail() local
221 mem_addr_t reg = (mem_addr_t)&base->in_ep[idx].dtxfsts; in dwc2_ftx_avail()
253 struct usb_dwc2_reg *const base = dwc2_get_base(dev); in dwc2_flush_rx_fifo() local
254 mem_addr_t grstctl_reg = (mem_addr_t)&base->grstctl; in dwc2_flush_rx_fifo()
263 struct usb_dwc2_reg *const base = dwc2_get_base(dev); in dwc2_flush_tx_fifo() local
[all …]
/Zephyr-latest/include/zephyr/shell/
Dshell_string_conv.h32 long shell_strtol(const char *str, int base, int *err);
49 unsigned long shell_strtoul(const char *str, int base, int *err);
66 unsigned long long shell_strtoull(const char *str, int base, int *err);
83 bool shell_strtobool(const char *str, int base, int *err);
/Zephyr-latest/drivers/i2c/
Di2c_mcux_flexcomm.c30 I2C_Type *base; member
67 I2C_Type *base = config->base; in mcux_flexcomm_configure() local
100 I2C_MasterSetBaudRate(base, baudrate, clock_freq); in mcux_flexcomm_configure()
106 static void mcux_flexcomm_master_transfer_callback(I2C_Type *base, in mcux_flexcomm_master_transfer_callback() argument
114 ARG_UNUSED(base); in mcux_flexcomm_master_transfer_callback()
141 I2C_Type *base = config->base; in mcux_flexcomm_transfer() local
174 status = I2C_MasterTransferNonBlocking(base, in mcux_flexcomm_transfer()
181 I2C_MasterTransferAbort(base, &data->handle); in mcux_flexcomm_transfer()
193 I2C_MasterTransferAbort(base, &data->handle); in mcux_flexcomm_transfer()
282 static void i2c_target_transfer_callback(I2C_Type *base, in i2c_target_transfer_callback() argument
[all …]
/Zephyr-latest/tests/unit/timeutil/
Dtest_sync.c50 zassert_equal(ss.base.ref, 0, in test_state_update()
59 zassert_equal(ss.base.ref, 1, in test_state_update()
69 zassert_equal(ss.base.ref, 1, in test_state_update()
71 zassert_equal(ss.base.local, 0, in test_state_update()
87 zassert_equal(ss.base.ref, 1, in test_state_update()
89 zassert_equal(ss.base.local, 0, in test_state_update()
130 zassert_equal(ss.base.ref, si.ref, in test_state_set_skew()
132 zassert_equal(ss.base.local, si.local, in test_state_set_skew()
144 zassert_equal(ss.base.ref, si.ref, in test_state_set_skew()
146 zassert_equal(ss.base.local, si.local, in test_state_set_skew()
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_nxp_s32.c33 mem_addr_t base; in pinctrl_configure_pin() local
37 base = siul2_bases[pin->mscr.inst]; in pinctrl_configure_pin()
38 __ASSERT_NO_MSG(base != 0); in pinctrl_configure_pin()
41 sys_write32(pin->mscr.val, (base + SIUL2_MSCR(pin->mscr.idx))); in pinctrl_configure_pin()
46 base = siul2_bases[pin->imcr.inst]; in pinctrl_configure_pin()
47 __ASSERT_NO_MSG(base != 0); in pinctrl_configure_pin()
50 sys_write32(pin->imcr.val, (base + SIUL2_IMCR(pin->imcr.idx))); in pinctrl_configure_pin()
/Zephyr-latest/drivers/pcie/host/
Dptm.c24 static int pcie_ptm_root_setup(const struct device *dev, uint32_t base) in pcie_ptm_root_setup() argument
30 cap.raw = pcie_conf_read(config->pcie->bdf, base + PTM_CAP_REG_OFFSET); in pcie_ptm_root_setup()
39 pcie_conf_write(config->pcie->bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in pcie_ptm_root_setup()
74 uint32_t base; in DT_INST_FOREACH_STATUS_OKAY() local
78 base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_PTM); in DT_INST_FOREACH_STATUS_OKAY()
79 if (base == 0) { in DT_INST_FOREACH_STATUS_OKAY()
84 cap.raw = pcie_conf_read(bdf, base + PTM_CAP_REG_OFFSET); in DT_INST_FOREACH_STATUS_OKAY()
92 pcie_conf_write(bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in DT_INST_FOREACH_STATUS_OKAY()

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