39 	status_intr = dw_read(dev_cfg->base, DW_INTR_STATUS);  in dw_dma_isr()
45 	status_block = dw_read(dev_cfg->base, DW_STATUS_BLOCK);  in dw_dma_isr()
46 	status_tfr = dw_read(dev_cfg->base, DW_STATUS_TFR);  in dw_dma_isr()
49 	status_err = dw_read(dev_cfg->base, DW_STATUS_ERR);  in dw_dma_isr()
52 		dw_write(dev_cfg->base, DW_CLEAR_ERR, status_err);  in dw_dma_isr()
56 	dw_write(dev_cfg->base, DW_CLEAR_BLOCK, status_block);  in dw_dma_isr()
57 	dw_write(dev_cfg->base, DW_CLEAR_TFR, status_tfr);  in dw_dma_isr()
416 		dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_UNMASK(channel));  in dw_dma_config()
420 		dw_write(dev_cfg->base, DW_MASK_TFR, DW_CHAN_UNMASK(channel));  in dw_dma_config()
423 	dw_write(dev_cfg->base, DW_MASK_ERR, DW_CHAN_UNMASK(channel));  in dw_dma_config()
428 	dw_write(dev_cfg->base, DW_CLEAR_TFR, 0x1 << channel);  in dw_dma_config()
429 	dw_write(dev_cfg->base, DW_CLEAR_BLOCK, 0x1 << channel);  in dw_dma_config()
430 	dw_write(dev_cfg->base, DW_CLEAR_SRC_TRAN, 0x1 << channel);  in dw_dma_config()
431 	dw_write(dev_cfg->base, DW_CLEAR_DST_TRAN, 0x1 << channel);  in dw_dma_config()
432 	dw_write(dev_cfg->base, DW_CLEAR_ERR, 0x1 << channel);  in dw_dma_config()
443 	return dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel);  in dw_dma_is_enabled()
467 			dw_read(dev_cfg->base, DW_DMA_CHAN_EN), chan_data->state);  in dw_dma_start()
493 	dw_write(dev_cfg->base, DW_LLP(channel), llp);  in dw_dma_start()
495 		lli->ctrl_lo, masked_ctrl_lo, dw_read(dev_cfg->base, DW_LLP(channel)));  in dw_dma_start()
500 	dw_write(dev_cfg->base, DW_SAR(channel), (uint32_t)(lli->sar & DW_ADDR_MASK_32));  in dw_dma_start()
501 	dw_write(dev_cfg->base, DW_SAR_HI(channel), (uint32_t)(lli->sar >> DW_ADDR_RIGHT_SHIFT));  in dw_dma_start()
502 	dw_write(dev_cfg->base, DW_DAR(channel), (uint32_t)(lli->dar & DW_ADDR_MASK_32));  in dw_dma_start()
503 	dw_write(dev_cfg->base, DW_DAR_HI(channel), (uint32_t)(lli->dar >> DW_ADDR_RIGHT_SHIFT));  in dw_dma_start()
505 	dw_write(dev_cfg->base, DW_SAR(channel), lli->sar);  in dw_dma_start()
506 	dw_write(dev_cfg->base, DW_DAR(channel), lli->dar);  in dw_dma_start()
510 	dw_write(dev_cfg->base, DW_CTRL_LOW(channel), lli->ctrl_lo);  in dw_dma_start()
511 	dw_write(dev_cfg->base, DW_CTRL_HIGH(channel), lli->ctrl_hi);  in dw_dma_start()
514 	dw_write(dev_cfg->base, DW_CFG_LOW(channel), chan_data->cfg_lo);  in dw_dma_start()
515 	dw_write(dev_cfg->base, DW_CFG_HIGH(channel), chan_data->cfg_hi);  in dw_dma_start()
520 		chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel))  in dw_dma_start()
525 		chan_data->cfg_hi, dw_read(dev_cfg->base, DW_LLP(channel))  in dw_dma_start()
534 		dw_write(dev_cfg->base, DW_DSR(channel),  in dw_dma_start()
542 	dw_write(dev_cfg->base, DW_DMA_CHAN_EN, DW_CHAN_UNMASK(channel));  in dw_dma_start()
595 	dw_write(dev_cfg->base, DW_CFG_LOW(channel),  in dw_dma_stop()
599 	bool fifo_empty = WAIT_FOR(dw_read(dev_cfg->base, DW_CFG_LOW(channel)) & DW_CFGL_FIFO_EMPTY,  in dw_dma_stop()
612 	dw_write(dev_cfg->base, DW_DMA_CHAN_EN, DW_CHAN_MASK(channel));  in dw_dma_stop()
615 	bool is_disabled = WAIT_FOR(!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel)),  in dw_dma_stop()
656 	dw_write(dev_cfg->base, DW_CFG_LOW(channel), chan_data->cfg_lo);  in dw_dma_resume()
688 	dw_write(dev_cfg->base, DW_CFG_LOW(channel),  in dw_dma_suspend()
707 	if (dw_read(dev_cfg->base, DW_DMA_CFG) != 0) {  in dw_dma_setup()
708 		dw_write(dev_cfg->base, DW_DMA_CFG, 0x0);  in dw_dma_setup()
712 		if (!dw_read(dev_cfg->base, DW_DMA_CFG)) {  in dw_dma_setup()
726 		dw_read(dev_cfg->base, DW_DMA_CHAN_EN);  in dw_dma_setup()
731 	dw_write(dev_cfg->base, DW_DMA_CFG, 1);  in dw_dma_setup()
734 	dw_write(dev_cfg->base, DW_MASK_TFR, DW_CHAN_MASK_ALL);  in dw_dma_setup()
735 	dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_MASK_ALL);  in dw_dma_setup()
736 	dw_write(dev_cfg->base, DW_MASK_SRC_TRAN, DW_CHAN_MASK_ALL);  in dw_dma_setup()
737 	dw_write(dev_cfg->base, DW_MASK_DST_TRAN, DW_CHAN_MASK_ALL);  in dw_dma_setup()
738 	dw_write(dev_cfg->base, DW_MASK_ERR, DW_CHAN_MASK_ALL);  in dw_dma_setup()
742 	dw_write(dev_cfg->base, DW_FIFO_PART1_HI,  in dw_dma_setup()
744 	dw_write(dev_cfg->base, DW_FIFO_PART1_LO,  in dw_dma_setup()
746 	dw_write(dev_cfg->base, DW_FIFO_PART0_HI,  in dw_dma_setup()
748 	dw_write(dev_cfg->base, DW_FIFO_PART0_LO,  in dw_dma_setup()
758 static int dw_dma_avail_data_size(const struct device *dev, uint32_t base,  in dw_dma_avail_data_size()  argument
763 	int32_t write_ptr = dw_read(base, DW_DAR(channel));  in dw_dma_avail_data_size()
791 static int dw_dma_free_data_size(const struct device *dev, uint32_t base,  in dw_dma_free_data_size()  argument
795 	int32_t read_ptr = dw_read(base, DW_SAR(channel));  in dw_dma_free_data_size()
838 		stat->pending_length = dw_dma_avail_data_size(dev, dev_cfg->base, chan_data,  in dw_dma_get_status()
843 		stat->free = dw_dma_free_data_size(dev, dev_cfg->base, chan_data, channel);  in dw_dma_get_status()
847 	if (!(dw_read(dev_cfg->base, DW_DMA_CHAN_EN) & DW_CHAN(channel))) {  in dw_dma_get_status()