1 /*
2 * Copyright (c) 2018 Foundries.io
3 * Copyright (c) 2017, NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT openisa_rv32m1_lpuart
9
10 #include <errno.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/uart.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/irq.h>
15 #include <fsl_lpuart.h>
16 #include <soc.h>
17 #include <zephyr/drivers/pinctrl.h>
18
19 struct rv32m1_lpuart_config {
20 LPUART_Type *base;
21 const struct device *clock_dev;
22 clock_control_subsys_t clock_subsys;
23 clock_ip_name_t clock_ip_name;
24 uint32_t clock_ip_src;
25 uint32_t baud_rate;
26 uint8_t hw_flow_control;
27 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
28 void (*irq_config_func)(const struct device *dev);
29 #endif
30 const struct pinctrl_dev_config *pincfg;
31 };
32
33 struct rv32m1_lpuart_data {
34 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
35 uart_irq_callback_user_data_t callback;
36 void *cb_data;
37 #endif
38 };
39
rv32m1_lpuart_poll_in(const struct device * dev,unsigned char * c)40 static int rv32m1_lpuart_poll_in(const struct device *dev, unsigned char *c)
41 {
42 const struct rv32m1_lpuart_config *config = dev->config;
43 uint32_t flags = LPUART_GetStatusFlags(config->base);
44 int ret = -1;
45
46 if (flags & kLPUART_RxDataRegFullFlag) {
47 *c = LPUART_ReadByte(config->base);
48 ret = 0;
49 }
50
51 return ret;
52 }
53
rv32m1_lpuart_poll_out(const struct device * dev,unsigned char c)54 static void rv32m1_lpuart_poll_out(const struct device *dev, unsigned char c)
55 {
56 const struct rv32m1_lpuart_config *config = dev->config;
57
58 while (!(LPUART_GetStatusFlags(config->base)
59 & kLPUART_TxDataRegEmptyFlag)) {
60 }
61
62 LPUART_WriteByte(config->base, c);
63 }
64
rv32m1_lpuart_err_check(const struct device * dev)65 static int rv32m1_lpuart_err_check(const struct device *dev)
66 {
67 const struct rv32m1_lpuart_config *config = dev->config;
68 uint32_t flags = LPUART_GetStatusFlags(config->base);
69 int err = 0;
70
71 if (flags & kLPUART_RxOverrunFlag) {
72 err |= UART_ERROR_OVERRUN;
73 }
74
75 if (flags & kLPUART_ParityErrorFlag) {
76 err |= UART_ERROR_PARITY;
77 }
78
79 if (flags & kLPUART_FramingErrorFlag) {
80 err |= UART_ERROR_FRAMING;
81 }
82
83 LPUART_ClearStatusFlags(config->base, kLPUART_RxOverrunFlag |
84 kLPUART_ParityErrorFlag |
85 kLPUART_FramingErrorFlag);
86
87 return err;
88 }
89
90 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
rv32m1_lpuart_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)91 static int rv32m1_lpuart_fifo_fill(const struct device *dev,
92 const uint8_t *tx_data,
93 int len)
94 {
95 const struct rv32m1_lpuart_config *config = dev->config;
96 int num_tx = 0U;
97
98 while ((len - num_tx > 0) &&
99 (LPUART_GetStatusFlags(config->base)
100 & kLPUART_TxDataRegEmptyFlag)) {
101
102 LPUART_WriteByte(config->base, tx_data[num_tx++]);
103 }
104
105 return num_tx;
106 }
107
rv32m1_lpuart_fifo_read(const struct device * dev,uint8_t * rx_data,const int len)108 static int rv32m1_lpuart_fifo_read(const struct device *dev, uint8_t *rx_data,
109 const int len)
110 {
111 const struct rv32m1_lpuart_config *config = dev->config;
112 int num_rx = 0U;
113
114 while ((len - num_rx > 0) &&
115 (LPUART_GetStatusFlags(config->base)
116 & kLPUART_RxDataRegFullFlag)) {
117
118 rx_data[num_rx++] = LPUART_ReadByte(config->base);
119 }
120
121 return num_rx;
122 }
123
rv32m1_lpuart_irq_tx_enable(const struct device * dev)124 static void rv32m1_lpuart_irq_tx_enable(const struct device *dev)
125 {
126 const struct rv32m1_lpuart_config *config = dev->config;
127 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
128
129 LPUART_EnableInterrupts(config->base, mask);
130 }
131
rv32m1_lpuart_irq_tx_disable(const struct device * dev)132 static void rv32m1_lpuart_irq_tx_disable(const struct device *dev)
133 {
134 const struct rv32m1_lpuart_config *config = dev->config;
135 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
136
137 LPUART_DisableInterrupts(config->base, mask);
138 }
139
rv32m1_lpuart_irq_tx_complete(const struct device * dev)140 static int rv32m1_lpuart_irq_tx_complete(const struct device *dev)
141 {
142 const struct rv32m1_lpuart_config *config = dev->config;
143 uint32_t flags = LPUART_GetStatusFlags(config->base);
144
145 return (flags & kLPUART_TxDataRegEmptyFlag) != 0U;
146 }
147
rv32m1_lpuart_irq_tx_ready(const struct device * dev)148 static int rv32m1_lpuart_irq_tx_ready(const struct device *dev)
149 {
150 const struct rv32m1_lpuart_config *config = dev->config;
151 uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
152
153 return (LPUART_GetEnabledInterrupts(config->base) & mask)
154 && rv32m1_lpuart_irq_tx_complete(dev);
155 }
156
rv32m1_lpuart_irq_rx_enable(const struct device * dev)157 static void rv32m1_lpuart_irq_rx_enable(const struct device *dev)
158 {
159 const struct rv32m1_lpuart_config *config = dev->config;
160 uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
161
162 LPUART_EnableInterrupts(config->base, mask);
163 }
164
rv32m1_lpuart_irq_rx_disable(const struct device * dev)165 static void rv32m1_lpuart_irq_rx_disable(const struct device *dev)
166 {
167 const struct rv32m1_lpuart_config *config = dev->config;
168 uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
169
170 LPUART_DisableInterrupts(config->base, mask);
171 }
172
rv32m1_lpuart_irq_rx_full(const struct device * dev)173 static int rv32m1_lpuart_irq_rx_full(const struct device *dev)
174 {
175 const struct rv32m1_lpuart_config *config = dev->config;
176 uint32_t flags = LPUART_GetStatusFlags(config->base);
177
178 return (flags & kLPUART_RxDataRegFullFlag) != 0U;
179 }
180
rv32m1_lpuart_irq_rx_pending(const struct device * dev)181 static int rv32m1_lpuart_irq_rx_pending(const struct device *dev)
182 {
183 const struct rv32m1_lpuart_config *config = dev->config;
184 uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
185
186 return (LPUART_GetEnabledInterrupts(config->base) & mask)
187 && rv32m1_lpuart_irq_rx_full(dev);
188 }
189
rv32m1_lpuart_irq_err_enable(const struct device * dev)190 static void rv32m1_lpuart_irq_err_enable(const struct device *dev)
191 {
192 const struct rv32m1_lpuart_config *config = dev->config;
193 uint32_t mask = kLPUART_NoiseErrorInterruptEnable |
194 kLPUART_FramingErrorInterruptEnable |
195 kLPUART_ParityErrorInterruptEnable;
196
197 LPUART_EnableInterrupts(config->base, mask);
198 }
199
rv32m1_lpuart_irq_err_disable(const struct device * dev)200 static void rv32m1_lpuart_irq_err_disable(const struct device *dev)
201 {
202 const struct rv32m1_lpuart_config *config = dev->config;
203 uint32_t mask = kLPUART_NoiseErrorInterruptEnable |
204 kLPUART_FramingErrorInterruptEnable |
205 kLPUART_ParityErrorInterruptEnable;
206
207 LPUART_DisableInterrupts(config->base, mask);
208 }
209
rv32m1_lpuart_irq_is_pending(const struct device * dev)210 static int rv32m1_lpuart_irq_is_pending(const struct device *dev)
211 {
212 return (rv32m1_lpuart_irq_tx_ready(dev)
213 || rv32m1_lpuart_irq_rx_pending(dev));
214 }
215
rv32m1_lpuart_irq_update(const struct device * dev)216 static int rv32m1_lpuart_irq_update(const struct device *dev)
217 {
218 return 1;
219 }
220
rv32m1_lpuart_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)221 static void rv32m1_lpuart_irq_callback_set(const struct device *dev,
222 uart_irq_callback_user_data_t cb,
223 void *cb_data)
224 {
225 struct rv32m1_lpuart_data *data = dev->data;
226
227 data->callback = cb;
228 data->cb_data = cb_data;
229 }
230
rv32m1_lpuart_isr(const struct device * dev)231 static void rv32m1_lpuart_isr(const struct device *dev)
232 {
233 struct rv32m1_lpuart_data *data = dev->data;
234
235 if (data->callback) {
236 data->callback(dev, data->cb_data);
237 }
238 }
239 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
240
rv32m1_lpuart_init(const struct device * dev)241 static int rv32m1_lpuart_init(const struct device *dev)
242 {
243 const struct rv32m1_lpuart_config *config = dev->config;
244 lpuart_config_t uart_config;
245 uint32_t clock_freq;
246 int err;
247
248 /* set clock source */
249 /* TODO: Don't change if another core has configured */
250 CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
251
252 if (!device_is_ready(config->clock_dev)) {
253 return -ENODEV;
254 }
255
256 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
257 &clock_freq)) {
258 return -EINVAL;
259 }
260
261 LPUART_GetDefaultConfig(&uart_config);
262 uart_config.enableTx = true;
263 uart_config.enableRx = true;
264 if (config->hw_flow_control) {
265 uart_config.enableRxRTS = true;
266 uart_config.enableTxCTS = true;
267 }
268 uart_config.baudRate_Bps = config->baud_rate;
269
270 LPUART_Init(config->base, &uart_config, clock_freq);
271
272 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
273 if (err != 0) {
274 return err;
275 }
276
277 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
278 config->irq_config_func(dev);
279 #endif
280
281 return 0;
282 }
283
284 static DEVICE_API(uart, rv32m1_lpuart_driver_api) = {
285 .poll_in = rv32m1_lpuart_poll_in,
286 .poll_out = rv32m1_lpuart_poll_out,
287 .err_check = rv32m1_lpuart_err_check,
288 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
289 .fifo_fill = rv32m1_lpuart_fifo_fill,
290 .fifo_read = rv32m1_lpuart_fifo_read,
291 .irq_tx_enable = rv32m1_lpuart_irq_tx_enable,
292 .irq_tx_disable = rv32m1_lpuart_irq_tx_disable,
293 .irq_tx_complete = rv32m1_lpuart_irq_tx_complete,
294 .irq_tx_ready = rv32m1_lpuart_irq_tx_ready,
295 .irq_rx_enable = rv32m1_lpuart_irq_rx_enable,
296 .irq_rx_disable = rv32m1_lpuart_irq_rx_disable,
297 .irq_rx_ready = rv32m1_lpuart_irq_rx_full,
298 .irq_err_enable = rv32m1_lpuart_irq_err_enable,
299 .irq_err_disable = rv32m1_lpuart_irq_err_disable,
300 .irq_is_pending = rv32m1_lpuart_irq_is_pending,
301 .irq_update = rv32m1_lpuart_irq_update,
302 .irq_callback_set = rv32m1_lpuart_irq_callback_set,
303 #endif
304 };
305
306 #define RV32M1_LPUART_DECLARE_CFG(n, IRQ_FUNC_INIT) \
307 static const struct rv32m1_lpuart_config rv32m1_lpuart_##n##_cfg = {\
308 .base = (LPUART_Type *)DT_INST_REG_ADDR(n), \
309 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
310 .clock_subsys = \
311 (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
312 .clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
313 .clock_ip_src = kCLOCK_IpSrcFircAsync, \
314 .baud_rate = DT_INST_PROP(n, current_speed), \
315 .hw_flow_control = DT_INST_PROP(n, hw_flow_control), \
316 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
317 IRQ_FUNC_INIT \
318 }
319
320 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
321 #define RV32M1_LPUART_CONFIG_FUNC(n) \
322 static void rv32m1_lpuart_config_func_##n(const struct device *dev) \
323 { \
324 IRQ_CONNECT(DT_INST_IRQN(n), 0, rv32m1_lpuart_isr, \
325 DEVICE_DT_INST_GET(n), 0); \
326 \
327 irq_enable(DT_INST_IRQN(n)); \
328 }
329 #define RV32M1_LPUART_IRQ_CFG_FUNC_INIT(n) \
330 .irq_config_func = rv32m1_lpuart_config_func_##n,
331 #define RV32M1_LPUART_INIT_CFG(n) \
332 RV32M1_LPUART_DECLARE_CFG(n, RV32M1_LPUART_IRQ_CFG_FUNC_INIT(n))
333 #else
334 #define RV32M1_LPUART_CONFIG_FUNC(n)
335 #define RV32M1_LPUART_IRQ_CFG_FUNC_INIT
336 #define RV32M1_LPUART_INIT_CFG(n) \
337 RV32M1_LPUART_DECLARE_CFG(n, RV32M1_LPUART_IRQ_CFG_FUNC_INIT)
338 #endif
339
340 #define RV32M1_LPUART_INIT(n) \
341 PINCTRL_DT_INST_DEFINE(n); \
342 \
343 static struct rv32m1_lpuart_data rv32m1_lpuart_##n##_data; \
344 \
345 static const struct rv32m1_lpuart_config rv32m1_lpuart_##n##_cfg;\
346 \
347 DEVICE_DT_INST_DEFINE(n, \
348 rv32m1_lpuart_init, \
349 NULL, \
350 &rv32m1_lpuart_##n##_data, \
351 &rv32m1_lpuart_##n##_cfg, \
352 PRE_KERNEL_1, \
353 CONFIG_SERIAL_INIT_PRIORITY, \
354 &rv32m1_lpuart_driver_api); \
355 \
356 RV32M1_LPUART_CONFIG_FUNC(n) \
357 \
358 RV32M1_LPUART_INIT_CFG(n);
359
360 DT_INST_FOREACH_STATUS_OKAY(RV32M1_LPUART_INIT)
361
