Lines Matching refs:base
24 TMR_Type *base; member
71 config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); in mcux_qtmr_pwm_set_cycles()
73 QTMR_StopTimer(config->base, channel); in mcux_qtmr_pwm_set_cycles()
76 config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
77 config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
80 config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
81 config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
83 reg = config->base->CHANNEL[channel].CSCTRL; in mcux_qtmr_pwm_set_cycles()
89 config->base->CHANNEL[channel].CSCTRL = reg; in mcux_qtmr_pwm_set_cycles()
91 reg = config->base->CHANNEL[channel].CTRL; in mcux_qtmr_pwm_set_cycles()
104 config->base->CHANNEL[channel].CTRL = reg; in mcux_qtmr_pwm_set_cycles()
106 QTMR_StartTimer(config->base, channel, kQTMR_PriSrcRiseEdge); in mcux_qtmr_pwm_set_cycles()
146 QTMR_Init(config->base, i, &qtmr_config); in mcux_qtmr_pwm_init()
162 .base = (TMR_Type *)DT_INST_REG_ADDR(n), \