286 static void esai_commit_config(ESAI_Type *base,  in esai_commit_config()  argument
291 		base->TCCR &= ~(ESAI_TCCR_THCKD_MASK | ESAI_TCCR_TFSD_MASK |  in esai_commit_config()
297 		base->TCCR |= ESAI_TCCR_THCKD(cfg->hclk_dir) |  in esai_commit_config()
308 		base->TCR &= ~(ESAI_TCR_PADC_MASK | ESAI_TCR_TFSR_MASK |  in esai_commit_config()
312 		base->TCR |= ESAI_TCR_PADC(cfg->zero_pad_en) |  in esai_commit_config()
320 		base->ECR &= ~(ESAI_ECR_ETI_MASK |  in esai_commit_config()
323 		base->ECR |= ESAI_ECR_ETI(cfg->hclk_src) |  in esai_commit_config()
326 		base->TFCR &= ~(ESAI_TFCR_TFWM_MASK | ESAI_TFCR_TWA_MASK);  in esai_commit_config()
327 		base->TFCR |= ESAI_TFCR_TFWM(cfg->watermark) |  in esai_commit_config()
330 		ESAI_TxSetSlotMask(base, cfg->slot_mask);  in esai_commit_config()
332 		base->RCCR &= ~(ESAI_RCCR_RHCKD_MASK | ESAI_RCCR_RFSD_MASK |  in esai_commit_config()
338 		base->RCCR |= ESAI_RCCR_RHCKD(cfg->hclk_dir) |  in esai_commit_config()
349 		base->RCR &= ~(ESAI_RCR_RFSR_MASK | ESAI_RCR_RFSL_MASK |  in esai_commit_config()
353 		base->RCR |= ESAI_RCR_RFSR(cfg->fsync_early) |  in esai_commit_config()
360 		base->ECR &= ~(ESAI_ECR_ERI_MASK |  in esai_commit_config()
363 		base->ECR |= ESAI_ECR_ERI(cfg->hclk_src) |  in esai_commit_config()
366 		base->RFCR &= ~(ESAI_RFCR_RFWM_MASK | ESAI_RFCR_RWA_MASK);  in esai_commit_config()
367 		base->RFCR |= ESAI_RFCR_RFWM(cfg->watermark) |  in esai_commit_config()
370 		EASI_RxSetSlotMask(base, cfg->slot_mask);  in esai_commit_config()
383 	ESAI_Type *base;  in esai_config_set()  local
398 	base = UINT_TO_ESAI(data->regmap);  in esai_config_set()
417 	ESAI_Enable(base, true);  in esai_config_set()
420 	base->PCRC &= ~ESAI_PCRC_PC_MASK;  in esai_config_set()
421 	base->PRRC &= ~ESAI_PRRC_PDC_MASK;  in esai_config_set()
503 	ESAI_Enable(base, true);  in esai_config_set()
505 	esai_dump_register_data(base);  in esai_config_set()
507 	esai_commit_config(base, DAI_DIR_TX, &tx_config);  in esai_config_set()
508 	esai_commit_config(base, DAI_DIR_RX, &rx_config);  in esai_config_set()
511 	base->TFCR |= ESAI_TFCR_TIEN_MASK;  in esai_config_set()
517 	esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_TX, BIT(0), true);  in esai_config_set()
518 	esai_tx_rx_enable_disable_fifo_usage(base, DAI_DIR_RX, BIT(0), true);  in esai_config_set()
521 	base->PCRC = data->pcrc;  in esai_config_set()
522 	base->PRRC = data->prrc;  in esai_config_set()
527 	esai_dump_register_data(base);  in esai_config_set()
550 	ESAI_Type *base;  in esai_trigger_start()  local
554 	base = UINT_TO_ESAI(data->regmap);  in esai_trigger_start()
565 	esai_tx_rx_enable_disable_fifo(base, dir, true);  in esai_trigger_start()
575 			ESAI_WriteData(base, 0x0);  in esai_trigger_start()
580 	esai_tx_rx_enable_disable(base, dir, BIT(0), true);  in esai_trigger_start()
589 	ESAI_Type *base;  in esai_trigger_stop()  local
592 	base = UINT_TO_ESAI(data->regmap);  in esai_trigger_stop()
603 	esai_tx_rx_enable_disable(base, dir, BIT(0), false);  in esai_trigger_stop()
606 	esai_tx_rx_enable_disable_fifo(base, dir, false);  in esai_trigger_stop()