| /Zephyr-latest/drivers/firmware/scmi/ |
| D | Kconfig | 52 they exist, otherwise use base protocol channels).
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| /Zephyr-latest/boards/renesas/rzg3s_smarc/ |
| D | rzg3s_smarc_r9a08g045s33gbg_cm33.dts | 69 * The base addr and size depends on ATF-F configuration, which is running on Cortex-A55 and
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| /Zephyr-latest/cmake/toolchain/llvm/ |
| D | target.cmake | 15 set(triple armv8m.base-none-eabi)
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | Kconfig | 46 the base of SRAM1.
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| /Zephyr-latest/include/zephyr/kernel/ |
| D | thread.h | 261 struct _thread_base base; member
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| /Zephyr-latest/kernel/include/ |
| D | kernel_internal.h | 131 thread->base.swap_data = data; in z_thread_return_value_set_with_data()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_ambiq_spic.c | 31 uint32_t base; member
435 am_hal_iom_initialize((cfg->base - IOM0_BASE) / cfg->size, &data->iom_handler)) { in spi_ambiq_init()
513 .base = DT_INST_REG_ADDR(n), \
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| D | spi_ifx_cat1.c | 186 if (data->obj.base != NULL) { in spi_config()
210 Cy_SCB_SPI_SetActiveSlaveSelectPolarity(data->obj.base, CY_SCB_SPI_SLAVE_SELECT0, in spi_config()
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| /Zephyr-latest/drivers/dma/ |
| D | dma_intel_adsp_gpdma.c | 77 dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i])); in intel_adsp_gpdma_dump_registers()
84 dw_read(dw_cfg->base, ip_reg_offs[i])); in intel_adsp_gpdma_dump_registers()
532 .base = DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/subsys/net/l2/ethernet/gptp/ |
| D | Kconfig | 130 int "Set initial pdelay request interval in Log2 base"
138 int "Set initial sync interval in Log2 base"
146 int "Set initial announce interval in Log2 base"
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| /Zephyr-latest/boards/others/black_f407ve/doc/ |
| D | index.rst | 27 See also board descriptions at `STM32-base website`_,
226 .. _STM32-base website:
227 https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html
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| /Zephyr-latest/include/zephyr/arch/x86/ |
| D | memory.ld | 22 * for all sections are relative to the base virtual address for the kernel.
38 /* Virtual base address for the kernel; with CONFIG_MMU this is not necessarily
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| /Zephyr-latest/arch/arm64/core/ |
| D | fatal.c | 309 else if ((arch_current_thread()->base.user_options & K_USER) != 0 && in z_arm64_stack_corruption_check()
438 if (((arch_current_thread()->base.user_options & K_USER) != 0) && in z_arm64_do_kernel_oops()
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| /Zephyr-latest/subsys/jwt/ |
| D | jwt.c | 208 builder->base = buffer; in jwt_init_builder()
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| /Zephyr-latest/drivers/power_domain/ |
| D | power_domain_gpio_monitor.c | 42 dev->pm->base.usage = 0; in pd_on_domain_visitor()
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| /Zephyr-latest/subsys/bluetooth/audio/shell/ |
| D | bap_broadcast_assistant.c | 58 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(data); in pa_decode_base() local
62 if (base == NULL) { in pa_decode_base()
66 base_size = bt_bap_base_get_size(base); in pa_decode_base()
75 memcmp(base, received_base, (size_t)base_size) != 0) { in pa_decode_base()
76 (void)memcpy(received_base, base, base_size); in pa_decode_base()
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_mcux_ip3511.c | 44 uintptr_t base; member
712 LOG_DBG("Initialized USB controller %x", (uint32_t)config->base); in udc_mcux_init()
755 if (ip3511_fs_base[i] == config->base) { in udc_mcux_get_hal_driver_id()
765 if (ip3511_hs_base[i] == config->base) { in udc_mcux_get_hal_driver_id()
918 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/arch/xtensa/core/ |
| D | ptables.c | 163 if ((thread->base.user_options & K_USER) != 0U) { in thread_page_tables_get()
687 if ((thread->base.user_options & K_USER) == K_USER) { in xtensa_mmu_tlb_shootdown()
974 is_user = (thread->base.user_options & K_USER) != 0; in arch_mem_domain_thread_add()
1020 if ((thread->base.user_options & K_USER) == 0) { in arch_mem_domain_thread_remove()
1024 if ((thread->base.thread_state & _THREAD_DEAD) == 0) { in arch_mem_domain_thread_remove()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_npcm.c | 189 #define NPCM_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + NPCM_PWDWN_CTL_OFFSET(n))) argument
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| /Zephyr-latest/arch/arm/core/mpu/ |
| D | Kconfig | 24 alignment of MPU region base address and size.
27 to have power-of-two alignment for base address and region size.
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| /Zephyr-latest/drivers/counter/ |
| D | counter_andes_atcpit100.c | 34 #define PIT_BASE (((const struct atcpit100_config *)(dev)->config)->base)
53 uint32_t base; member
491 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/cmake/ |
| D | llext-edk.cmake | 11 # directories (build/zephyr, zephyr base, west top dir and application source
22 # - ZEPHYR_BASE: Path to the zephyr base directory.
61 # <install-dir>/include/zephyr/include/generated, files coming from zephyr base at
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_cdns_ll.c | 298 uintptr_t base; in sdhc_cdns_prepare() local
323 base = cdns_params.reg_base; in sdhc_cdns_prepare()
594 uintptr_t base; in sdhc_cdns_send_cmd() local
600 base = cdns_params.reg_base; in sdhc_cdns_send_cmd()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_lpc11u6x.h | 172 struct lpc11u6x_uartx_regs *base; member
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| /Zephyr-latest/soc/nordic/nrf54l/ |
| D | Kconfig | 74 of base resources on while in sleep. The advantage of having a constant
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