1# Memory Protection Unit (MPU) configuration options
2
3# Copyright (c) 2017 Linaro Limited
4# SPDX-License-Identifier: Apache-2.0
5
6if CPU_HAS_MPU
7
8config ARM_MPU
9	bool "ARM MPU Support"
10	select MPU
11	select SRAM_REGION_PERMISSIONS
12	select THREAD_STACK_INFO
13	select ARCH_HAS_EXECUTABLE_PAGE_BIT
14	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
15	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
16	select MPU_GAP_FILLING if AARCH32_ARMV8_R
17	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS
18	select MEM_DOMAIN_ISOLATED_STACKS
19	help
20	  MCU implements Memory Protection Unit.
21
22	  Notes:
23	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
24	  alignment of MPU region base address and size.
25
26	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
27	  to have power-of-two alignment for base address and region size.
28
29	  The ARMv8-M MPU requires the active MPU regions be non-overlapping.
30	  As a result of this, the ARMv8-M MPU needs to fully partition the
31	  memory map when programming dynamic memory regions (e.g. PRIV stack
32	  guard, user thread stack, and application memory domains), if the
33	  system requires PRIV access policy different from the access policy
34	  of the ARMv8-M background memory map. The application developer may
35	  enforce full PRIV (kernel) memory partition by enabling the
36	  CONFIG_MPU_GAP_FILLING option.
37	  By not enforcing full partition, MPU may leave part of kernel
38	  SRAM area covered only by the default ARMv8-M memory map. This
39	  is fine for User Mode, since the background ARM map does not
40	  allow nPRIV access at all. However, since the background map
41	  policy allows instruction fetches by privileged code, forcing
42	  this Kconfig option off prevents the system from directly
43	  triggering MemManage exceptions upon accidental attempts to
44	  execute code from SRAM in XIP builds.
45	  Since this does not compromise User Mode, we make the skipping
46	  of full partitioning the default behavior for the ARMv8-M MPU
47	  driver.
48
49config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
50	int
51	default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
52	default 64 if ARM_MPU && AARCH32_ARMV8_R
53	default 32 if ARM_MPU
54	default 4
55	help
56	  Minimum size (and alignment) of an ARM MPU region. Use this
57	  symbol to guarantee minimum size and alignment of MPU regions.
58	  A minimum 4-byte alignment is enforced in ARM builds without
59	  support for Memory Protection.
60
61if ARM_MPU
62
63config MPU_STACK_GUARD
64	bool "Thread Stack Guards"
65	help
66	  Enable Thread Stack Guards via MPU
67
68config MPU_STACK_GUARD_MIN_SIZE_FLOAT
69	int
70	depends on MPU_STACK_GUARD
71	depends on FPU_SHARING
72	default 128
73	help
74	  Minimum size (and alignment when applicable) of an ARM MPU
75	  region, which guards the stack of a thread that is using the
76	  Floating Point (FP) context. The width of the guard is set to
77	  128, to accommodate the length of a Cortex-M exception stack
78	  frame when the floating point context is active. The FP context
79	  is only stacked in sharing FP registers mode, therefore, the
80	  option is applicable only when FPU_SHARING is selected.
81
82config MPU_ALLOW_FLASH_WRITE
83	bool "Add MPU access to write to flash"
84	help
85	  Enable this to allow MPU RWX access to flash memory
86
87config MPU_DISABLE_BACKGROUND_MAP
88	bool "Disables the default background address map"
89	help
90	  Enable this to turn off the default background MPU address map. Your
91	  SoC definition should likely provide its own custom MPU regions.
92
93config CUSTOM_SECTION_ALIGN
94	bool "Custom Section Align"
95	help
96	  MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
97	  wasting in linker scripts defined memory sections. Use this symbol
98	  to guarantee user custom section align size to avoid more memory used
99	  for respect alignment. But that needs carefully configure MPU region
100	  and sub-regions(ARMv7-M) to cover this feature.
101
102config CUSTOM_SECTION_MIN_ALIGN_SIZE
103	int "Custom Section Align Size"
104	default 32
105	help
106	  Custom align size of memory section in linker scripts. Usually
107	  it should consume less alignment memory. Although this alignment
108	  size is configured by users, it must also respect the power of
109	  two regulation if hardware requires.
110
111endif # ARM_MPU
112
113endif # CPU_HAS_MPU
114