1/*
2 * Copyright (c) 2024 EPAM Systems
3 * Copyright (c) 2024 Renesas Electronics Corporation
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <freq.h>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
13#include <arm/renesas/rz/rzg/r9a08g045.dtsi>
14#include "rzg3s_smarc-pinctrl.dtsi"
15
16/ {
17	model = "Renesas RZ/G3S SMARC";
18	compatible = "renesas,rzg3s-smarc";
19
20	chosen {
21		zephyr,sram = &sram_mcpu0;
22		zephyr,flash = &spi_flash;
23		zephyr,console = &scif1;
24		zephyr,shell-uart = &scif1;
25	};
26
27	aliases {
28		sw0 = &sw_1;
29		sw1 = &sw_2;
30		sw2 = &sw_3;
31	};
32
33	buttons {
34		compatible = "gpio-keys";
35
36		sw_1: button_1 {
37			gpios = <&gpio18 0 GPIO_ACTIVE_LOW>;
38			label = "SW1";
39			zephyr,code = <INPUT_KEY_1>;
40		};
41
42		sw_2: button_2 {
43			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
44			label = "SW2";
45			zephyr,code = <INPUT_KEY_2>;
46		};
47
48		sw_3: button_3 {
49			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
50			label = "SW3";
51			zephyr,code = <INPUT_KEY_3>;
52		};
53	};
54
55	ddr: memory@60000000 {
56		compatible ="zephyr,memory-region", "mmio-sram";
57		reg = <0x60000000 DT_SIZE_M(16)>;
58		zephyr,memory-region = "DDR";
59		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
60	};
61
62	sram_mcpu0: memory@23000 {
63		compatible = "mmio-sram";
64		reg = <0x23000 DT_SIZE_K(243)>;
65	};
66
67	/*
68	 * This node is defined to enable west flash support.
69	 * The base addr and size depends on ATF-F configuration, which is running on Cortex-A55 and
70	 * loading Zephyr app from xSPI flash.
71	 */
72	spi_flash: memory@80200000 {
73		compatible = "mmio-sram";
74		reg = <0x80200000 DT_SIZE_K(256)>;
75	};
76
77};
78
79&scif1 {
80	current-speed = <115200>;
81	pinctrl-0 = <&scif1_pins>;
82	pinctrl-names = "default";
83	status = "okay";
84};
85
86&gpio0{
87	status = "okay";
88};
89
90&gpio18{
91	status = "okay";
92};
93