| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
9 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
10 They will be applied in case no `bias-foo` or `driver-bar` properties
13 compatible: "st,stm32-pinctrl"
21 remap-pa11:
26 remap-pa12:
31 remap-pa11-pa12:
36 child-binding:
41 - name: pincfg-node.yaml
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| /Zephyr-latest/boards/96boards/aerocore2/ |
| D | 96b_aerocore2.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <st/f4/stm32f427v(g-i)tx-pinctrl.dtsi>
18 zephyr,shell-uart = &uart7;
25 compatible = "gpio-leds";
39 volt-sensor0 = &vref;
40 volt-sensor1 = &vbat;
50 clock-frequency = <DT_FREQ_M(24)>;
55 div-m = <24>;
56 mul-n = <336>;
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| /Zephyr-latest/boards/st/stm32mp157c_dk2/ |
| D | stm32mp157c_dk2.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/mp1/stm32mp157cacx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32MP157-DK2 board";
15 compatible = "st,stm32mp157c-dk2";
24 * zephyr,shell-uart = &usart3;
31 compatible = "gpio-leds";
39 compatible = "gpio-keys";
55 clock-frequency = <DT_FREQ_M(209)>;
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| /Zephyr-latest/include/zephyr/dt-bindings/gpio/ |
| D | stm32-gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
16 * - Bit 8: Configure a GPIO pin to power on the system after Poweroff.
17 * - Bit 10..9: Configure the output speed of a GPIO pin.
25 * This flag is reserved to GPIO pins that are associated with wake-up pins
26 * in STM32 PWR devicetree node, through the property "wkup-gpios".
35 /** Configure the GPIO pin output speed to be low */
38 /** Configure the GPIO pin output speed to be medium */
41 /** Configure the GPIO pin output speed to be high */
44 /** Configure the GPIO pin output speed to be very high */
|
| /Zephyr-latest/boards/96boards/stm32_sensor_mez/ |
| D | 96b_stm32_sensor_mez.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f446v(c-e)tx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32f446-b96b-f446ve";
18 zephyr,shell-uart = &uart4;
24 compatible = "gpio-leds";
40 compatible = "gpio-keys";
61 clock-frequency = <DT_FREQ_M(16)>;
66 div-m = <8>;
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| /Zephyr-latest/boards/oct/osd32mp1_brk/ |
| D | osd32mp1_brk.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 model = "Octavo Systems OSD32MP1-BRK";
13 compatible = "oct,osd32mp1-brk";
22 * zephyr,shell-uart = &usart2;
29 compatible = "gpio-leds";
38 compatible = "gpio-keys";
53 slew-rate = "very-high-speed";
57 pinctrl-0 = <&usart2_tx_pf5 &usart2_rx_pf4>;
[all …]
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| /Zephyr-latest/boards/96boards/argonkey/ |
| D | 96b_argonkey.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
18 zephyr,shell-uart = &usart1;
24 compatible = "gpio-leds";
36 compatible = "gpio-keys";
57 clock-frequency = <DT_FREQ_M(16)>;
62 div-m = <8>;
63 mul-n = <84>;
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| /Zephyr-latest/boards/adafruit/feather_stm32f405/ |
| D | adafruit_feather_stm32f405.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f405rgtx-pinctrl.dtsi>
18 zephyr,shell-uart = &usart3;
25 compatible = "gpio-leds";
42 clock-frequency = <DT_FREQ_M(12)>;
47 div-m = <12>;
48 mul-n = <336>;
49 div-p = <2>;
50 div-q = <7>;
[all …]
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| /Zephyr-latest/boards/renesas/ek_ra6m2/doc/ |
| D | index.rst | 7 for applications that require a high-performance Arm® Cortex®-M4 core at a very attractive
11 The key features of the EK-RA6M2 board are categorized in three groups as follow:
15 - 120MHz Arm Cortex-M4 based RA6M2 MCU in 144 pins, LQFP package
16 - Native pin access through 4 x 40-pin male headers
17 - MCU and USB current measurement points for precision current consumption measurement
18 - Multiple clock sources - RA6M2 MCU oscillator and sub-clock oscillator crystals,
24 - USB Full Speed device
25 - 5V input through USB debug
27 - Three Debug modes
29 - Debug on-board (SWD)
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| /Zephyr-latest/boards/makerbase/mks_canable_v20/doc/ |
| D | index.rst | 6 The Makerbase MKS CANable V2.0 board features an ARM Cortex-M4 based STM32G431C8 MCU
10 - STM32 microcontroller in LQFP48 package
11 - USB Type-C connector (J1)
12 - CAN-Bus connector (J2)
13 - ST-LINK/V3E debugger/programmer header (J4)
14 - USB VBUS power supply (5 V)
15 - Three LEDs: red/power_led (D1), blue/stat_led (D2), green/word_led (D3)
16 - One push-button for RESET
17 - Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell.
19 The LED red/power_led (D1) is connected directly to on-board 3.3 V and not controllable by the MCU.
[all …]
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| /Zephyr-latest/boards/renesas/ek_ra4w1/doc/ |
| D | index.rst | 6 The Renesas RA4W1 is the first Bluetooth® 5.0 Low Energy fully compliant with 2Mbit High-Throughput
8 that require a high-performance Arm® Cortex®-M4 core at a very attractive price point. The RA4W1 MCU
9 has full function support for Bluetooth 5.0 Low Energy long-range and mesh networking, and provides
15 - R7FA4W1AD2CNG
16 - QFN-56 package
17 - On-chip memory: 512-KB ROM, 96-KB RAM, 8-KB data flash memory
19 **Power-supply voltage**
21 - USB connector: 5-V input
22 - Power-supply IC: 5-V input, 3.3-V output
23 - External power-supply header*1: 3.3-V input, 2 pins x 1
[all …]
|
| /Zephyr-latest/boards/adi/max32660evsys/doc/ |
| D | index.rst | 7 use board. A MAX32625PICO-based debug adapter comes attached to the main
9 module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink
11 alone measures 0.65in x 0.95in. External connections terminate in a dual-row
12 header footprint compatible with both thru-hole and SMT applications. This
13 board provides a powerful processing subsystem in a very small space that
21 - MAX32660 MCU:
23 - High-Efficiency Microcontroller for Wearable Devices
25 - Internal Oscillator Operates Up to 96MHz
26 - 256KB Flash Memory
27 - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode
[all …]
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| /Zephyr-latest/boards/renesas/ek_ra6m1/doc/ |
| D | index.rst | 7 series for applications that require a high-performance Arm® Cortex®-M4 core at
8 a very attractive price point. The RA6M1 is built on a highly efficient 40nm process
14 The key features of the EK-RA6M1 board are categorized in three groups as follow:
18 - R7FA6M1AD3CFP
19 - 100-pin LQFP package
20 - 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
21 - 256 KB SRAM
22 - 512 KB code flash memory
23 - 8 KB data flash memory
27 - A Device USB connector for the Main MCU
[all …]
|
| /Zephyr-latest/boards/st/stm32g081b_eval/ |
| D | stm32g081b_eval.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g081rbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32g081-eval";
18 zephyr,shell-uart = &usart3;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
83 volt-sensor0 = &vref;
84 volt-sensor1 = &vbat;
[all …]
|
| /Zephyr-latest/boards/st/disco_l475_iot1/ |
| D | disco_l475_iot1.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/l4/stm32l475v(c-e-g)tx-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics B-L475E-IOT01Ax board";
15 compatible = "st,stm32l475-disco-iot";
19 zephyr,shell-uart = &usart1;
22 zephyr,code-partition = &slot0_partition;
23 zephyr,flash-controller = &mx25r6435f;
24 zephyr,bt-c2h-uart = &usart1;
[all …]
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_wb0.c | 4 * SPDX-License-Identifier: Apache-2.0
43 # error slow-clock source is not enabled
53 # error Invalid device selected as slow-clock
66 "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
108 * NOTE: (size - 1) is required to get the correct count, in measure_lsi_frequency()
113 (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1)); in measure_lsi_frequency()
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
155 * = ------------------------------------------------ in measure_lsi_frequency()
163 * = ------------------------------------------------ in measure_lsi_frequency()
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|
| /Zephyr-latest/drivers/i2c/ |
| D | i2c_sam4l_twim.c | 3 * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
14 * Very long transfers are allowed using NCMDR register. DMA is not
33 #include "i2c-priv.h"
35 /** I2C bus speed [Hz] in Standard Mode */
37 /** I2C bus speed [Hz] in Fast Mode */
39 /** I2C bus speed [Hz] in Fast Plus Mode */
41 /** I2C bus speed [Hz] in High Speed Mode */
107 static int i2c_clk_set(const struct device *dev, uint32_t speed) in i2c_clk_set() argument
109 const struct i2c_sam_twim_dev_cfg *const cfg = dev->config; in i2c_clk_set()
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|
| /Zephyr-latest/boards/nxp/mimxrt700_evk/doc/ |
| D | index.rst | 6 The new i.MX RT700 CPU architecture is composed of a high-performance main-compute subsystem,
7 a secondary “always-on” sense-compute subsystem and specialized coprocessors.
9 The main-compute subsystem has a primary Arm® Cortex®-M33 running at 325 MHz, with an integrated
11 The sense-compute subsystem has a second Arm® Cortex®-M33 and an integrated Cadence® Tensilica®
15 The HiFi4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architectur…
17 high-performance numerical tasks such as audio and image processing and supports both fixed-point a…
18 floating-point operations.
26 - Main Compute Subsystem:
27 - Arm Cortex-M33 up to 325 MHz
28 - HiFi 4 DSP up to 325 MHz
[all …]
|
| /Zephyr-latest/subsys/usb/device_next/class/ |
| D | usbd_dfu.c | 4 * SPDX-License-Identifier: Apache-2.0
17 * It is very unlikely that anyone would need more than one instance of the DFU
22 * interface for the run-time mode, and the other with a number of user-defined
28 * user to disable the device with run-time mode and enable a device with DFU
44 /* DFU Functional Descriptor used for Run-Time und DFU mode */
56 /* Common class data for both run-time and DFU instances. */
70 /* Run-Time mode interface descriptor */
73 /* Run-Time mode descriptors. No endpoints, identical for high and full speed. */
82 * at least one for NULL. No endpoints, identical for high and full speed.
144 usbd_msg_pub_simple(data->ctx, USBD_MSG_DFU_APP_DETACH, 0); in runtime_detach_work()
[all …]
|
| /Zephyr-latest/doc/services/logging/ |
| D | cs_stm.rst | 3 Multi-domain logging using ARM Coresight STM
6 The Arm CoreSight SoC-400 is a comprehensive library of components for the creation of debug and
8 is integrated into a CoreSight system, designed primarily for high-bandwidth trace of
9 instrumentation embedded into software. This instrumentation is made up of memory-mapped writes to
26 capture the data (e.g. J-Trace PRO).
40 Data from ETR is handled on the device. It can be forwarded as-is to the host (e.g. using UART),
41 where a host tool is decoding the data or data can be decoded on-chip to output the data in human r…
65 There may be cases when logging is too slow (even though it is very fast). For cases like that a de…
68 * :c:func:`log_frontend_stmesp_tp` - It accepts single argument - index. Index is between
70 * :c:func:`log_frontend_stmesp_tp_d32` - It accepts two arguments - index and user data.
[all …]
|
| /Zephyr-latest/boards/nxp/mimxrt595_evk/doc/ |
| D | index.rst | 7 for low-power HMI applications by combining a graphics engine and a streamlined
8 Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33
9 core. These devices are designed to unlock the potential of display-based applications
10 with a secure, power-optimized embedded processor.
12 i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces
13 to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly
20 - MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP
21 - Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug o…
22 - USB2.0 high-speed host and device with micro USB connector and external crystal
23 - Octal/Quad/pSRAM external memories via FlexSPI
[all …]
|
| /Zephyr-latest/drivers/ethernet/ |
| D | dsa_ksz8xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
48 #define PRV_DATA(ctx) ((struct ksz8xxx_data *const)(ctx)->prv_data)
75 spi_write_dt(&pdev->spi, &tx); in dsa_ksz8xxx_write_reg()
113 if (!spi_transceive_dt(&pdev->spi, &tx, &rx)) { in dsa_ksz8xxx_read_reg()
154 * Wait for SPI of KSZ8794 being fully operational - up to 10 ms
157 tmp != KSZ8XXX_CHIP_ID0_ID_DEFAULT && timeout > 0; timeout--) {
164 return -ENODEV;
183 return -ENODEV;
196 * According to KSZ8794 manual - write to static mac address table
254 * According to KSZ8794 manual - read from static mac address table
[all …]
|
| /Zephyr-latest/boards/nxp/mimxrt685_evk/doc/ |
| D | index.rst | 6 The i.MX RT600 is a crossover MCU family optimized for 32-bit immersive audio
7 playback and voice user interface applications combining a high-performance
8 Cadence Tensilica HiFi 4 audio DSP core with a next-generation Cortex-M33
10 potential of voice-assisted end nodes with a secure, power-optimized embedded
13 The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several
14 high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI
15 interface with an on-the-fly decryption engine.
20 - MIMXRT685SFVKB Cortex-M33 (300 MHz, 128 KB TCM) core processor with Cadence Xtensa HiFi4 DSP
21 - Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug o…
22 - High speed USB port with micro A/B connector for the host or device functionality
[all …]
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| /Zephyr-latest/doc/releases/ |
| D | migration-guide-3.5.rst | 21 taking a ``void *mem`` pointer instead of a ``void **mem`` double-pointer.
28 * :c:macro:`CONTAINER_OF` now performs type checking, this was very commonly
37 * The default C library used on most targets has changed from the built-in
47 increase by 8-16 bytes.
68 * Picolibc removes the ``-ffreestanding`` compiler option. This allows
71 the Zephyr required type -- ``int main(void)``.
100 * ``psa-arch-tests``
102 * ``tf-m-tests``
103 * ``tflite-micro``
107 To enable them again use the ``west config manifest.project-filter -- +<module
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| /Zephyr-latest/subsys/bluetooth/host/ |
| D | Kconfig | 3 # Copyright (c) 2016-2020 Nordic Semiconductor ASA
4 # Copyright (c) 2015-2016 Intel Corporation
5 # SPDX-License-Identifier: Apache-2.0
8 bool "Dedicated workqueue for long-running tasks."
11 Adds an API for a workqueue dedicated to long-running tasks.
23 int "Long workqueue priority. Should be pre-emptible."
58 # the worst-case stack size if an out-of-tree controller is used.
70 # Hidden option for Co-Operative Tx thread priority
80 The host defines some events as high priority to avoid race conditions and deadlocks.
81 High priority events are always processed in the context of the caller of bt_recv()
[all …]
|
