Lines Matching +full:very +full:- +full:high +full:- +full:speed

7 use board. A MAX32625PICO-based debug adapter comes attached to the main
9 module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink
11 alone measures 0.65in x 0.95in. External connections terminate in a dual-row
12 header footprint compatible with both thru-hole and SMT applications. This
13 board provides a powerful processing subsystem in a very small space that
21 - MAX32660 MCU:
23   - High-Efficiency Microcontroller for Wearable Devices
25      - Internal Oscillator Operates Up to 96MHz
26      - 256KB Flash Memory
27      - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode
28      - 16KB Instruction Cache
29      - Memory Protection Unit (MPU)
30      - Low 1.1V VCORE Supply Voltage
31      - 3.6V GPIO Operating Range
32      - Internal LDO Provides Operation from Single Supply
33      - Wide Operating Temperature: -40°C to +105°C
35   - Power Management Maximizes Uptime for Battery Applications
37      - 85µA/MHz Active Executing from Flash
38      - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V
39      - 450nA Ultra-Low Power RTC at VDD=1.8V
40      - Internal 80kHz Ring Oscillator
42   - Optimal Peripheral Mix Provides Platform Scalability
44      - Up to 14 General-Purpose I/O Pins
45      - Up to Two SPI
46      - I2S
47      - Up to Two UARTs
48      - Up to Two I2C, 3.4Mbps High Speed
49      - Four-Channel Standard DMA Controller
50      - Three 32-Bit Timers
51      - Watchdog Timer
52      - CMOS-Level 32.768kHz RTC Output
54 - Benefits and Features of MAX32660-EVSYS:
56   - DIP Breakout Board
58      - 100mil Pitch Dual Inline Pin Headers
59      - Breadboard Compatible
61   - Integrated Peripherals
63      - Red Indicator LED
64      - User Pushbutton
66   - MAX32625PICO-Based Debug Adapter
68      - CMSIS-DAP SWD Debugger
69      - Virtual UART Console
76 +-----------+------------+-------------------------------------+
79 | NVIC      | on-chip    | nested vector interrupt controller  |
80 +-----------+------------+-------------------------------------+
81 | SYSTICK   | on-chip    | systick                             |
82 +-----------+------------+-------------------------------------+
83 | CLOCK     | on-chip    | clock and reset control             |
84 +-----------+------------+-------------------------------------+
85 | GPIO      | on-chip    | gpio                                |
86 +-----------+------------+-------------------------------------+
87 | UART      | on-chip    | serial                              |
88 +-----------+------------+-------------------------------------+
97 development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial
98 interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4).
106    a Segger J-Link with Segger's native tooling by overriding the runner,
107    appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
120 - `MAX32660EVSYS web page`_
123 …https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max326…