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/Zephyr-latest/dts/bindings/interrupt-controller/
Dst,stm32-exti.yaml3 compatible: "st,stm32-exti"
5 include: [base.yaml, interrupt-controller.yaml]
14 interrupt-names:
17 num-lines:
22 line-ranges:
26 Description of the input lines range for each interrupt line supported
27 by the external interrupt controller. For each line a couple of integers is
28 provided: the number of the first line of the range start and the length
31 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
33 Above property provides event-range for 7 lines.
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dadi,adp5585-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,adp5585-gpio"
8 include: gpio-controller.yaml
11 "#gpio-cells":
19 gpio-reserved-ranges:
23 Ranges of GPIOs reserved unavailable on port expander.
25 5, 6, 7 is reserved. That's to say, GPIO R0~R4 occupy line
26 number 0~4, GPIO C0~C4 occupy line number 8~12.
28 gpio-cells:
29 - pin
[all …]
Dgpio-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
7 "gpio-controller":
11 "#gpio-cells":
19 This property indicates the number of in-use slots of available slots
28 gpio-reserved-ranges:
31 If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
36 For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
38 gpio-line-names:
39 type: string-array
44 child-binding:
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/Zephyr-latest/dts/x86/intel/
Dlakemont.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
18 d-cache-line-size = <64>;
27 interrupt-controller;
28 #interrupt-cells = <3>;
34 interrupt-controller;
35 #interrupt-cells = <3>;
44 #address-cells = <1>;
[all …]
Datom.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
17 d-cache-line-size = <64>;
25 #address-cells = <1>;
26 #interrupt-cells = <3>;
28 interrupt-controller;
34 interrupt-controller;
35 #interrupt-cells = <3>;
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Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "intel,alder-lake", "intel,x86_64";
22 d-cache-line-size = <64>;
28 compatible = "intel,alder-lake";
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Draptor_lake_p.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
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/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu540.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 tlclk: tl-clk {
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/Zephyr-latest/boards/snps/nsim/arc_v/
Drmx1xx.dtsi2 #address-cells = <1>;
3 #size-cells = <1>;
6 timebase-frequency = <5000000>;
7 #address-cells = <1>;
8 #size-cells = <0>;
14 clock-frequency = <5000000>;
17 cpu0_intc: interrupt-controller {
18 compatible = "riscv,cpu-intc";
19 interrupt-controller;
20 #address-cells = <0>;
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/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnucleo_f767zi.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
10 stepper-motors = <&drv8424 0>;
23 gpio-controller;
25 #gpio-cells = <2>;
27 gpio-reserved-ranges = <7 1>;
29 gpio-line-names =
45 dir-gpios = <&arduino_header 18 0>; /* D12 */
46 step-gpios = <&arduino_header 19 0>; /* D13 */
47 sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
[all …]
Dmimxrt1060_evk_mimxrt1062_qspi_B.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
10 stepper-motors = <&drv8424 0>;
23 gpio-controller;
25 #gpio-cells = <2>;
27 gpio-reserved-ranges = <7 1>;
29 gpio-line-names =
45 dir-gpios = <&arduino_header 9 0>; /* D3 */
46 step-gpios = <&arduino_header 10 0>; /* D4 */
47 sleep-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gd32_exti.c4 * SPDX-License-Identifier: Apache-2.0
19 /** Unsupported line indicator */
25 /** @brief EXTI line ranges hold by a single ISR */
33 /** @brief EXTI line interrupt callback. */
57 /** @brief Obtain line IRQ number if enabled. */
58 #define EXTI_LINE_IRQ_COND(enabled, line) \ argument
59 COND_CODE_1(enabled, (DT_INST_IRQ_BY_NAME(0, line, irq)), (EXTI_NOTSUP))
92 struct gd32_exti_data *data = dev->data; in gd32_exti_isr()
95 for (uint8_t i = range->min; i <= range->max; i++) { in gd32_exti_isr()
99 if (data->cbs[i].cb != NULL) { in gd32_exti_isr()
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/Zephyr-latest/scripts/dts/
Dgen_defines.py3 # Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
6 # SPDX-License-Identifier: BSD-3-Clause
11 # Note: Do not access private (_-prefixed) identifiers from edtlib here (and
25 sys.path.insert(0, os.path.join(os.path.dirname(__file__), 'python-devicetree',
46 with open(args.header_out, "w", encoding="utf-8") as header_file:
58 # Check to see if we have duplicate "zephyr,memory-region" property values.
61 if 'zephyr,memory-region' in node.props:
62 region = node.props['zephyr,memory-region'].val
64 sys.exit(f"ERROR: Duplicate 'zephyr,memory-region' ({region}) properties "
74 out_comment("Node's name with unit-address:")
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/Zephyr-latest/arch/nios2/core/
Dcache.c4 * SPDX-License-Identifier: Apache-2.0
44 * The Nios II does not support hardware cache coherency for multi-master
45 * or multi-processor systems and software coherency must be implemented
47 * in Zephyr additional APIs for flushing ranges of the data cache will need
83 * For an unaligned flush request, we've got one more line left. in z_nios2_dcache_flush_no_writeback()
88 if (((uint32_t) start) & (ALT_CPU_DCACHE_LINE_SIZE - 1)) { in z_nios2_dcache_flush_no_writeback()
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
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/Zephyr-latest/scripts/footprint/
Dsize_report3 # Copyright (c) 2016, 2020-2024 Intel Corporation
5 # SPDX-License-Identifier: Apache-2.0
49 DT_LOCATION = re.compile(r"\(DW_OP_addr: ([0-9a-f]+)\)")
64 def is_symbol_in_ranges(sym, ranges): argument
67 lies within any of these address ranges.
69 for bound in ranges:
189 sec_end = sec_start + (sec_size - 1 if sec_size else 0)
191 f"0x{sec_start:08x}-0x{sec_end:08x} "
199 Parse ELF header to find out the address ranges of ROM or RAM sections
213 sec_end = sec_start + (size - 1 if size else 0)
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/Zephyr-latest/scripts/dts/python-devicetree/src/devicetree/
Dedtlib.py3 # SPDX-License-Identifier: BSD-3-Clause
17 but a binding can also come from a 'child-binding:' key in the binding for the
23 The top-level entry points for the library are the EDT and Binding classes.
31 # --------------------
47 # - Consider using @property for APIs that don't need parameters. It makes
51 # - Think about the data type of the thing you're exposing. Exposing something
55 # - Avoid get_*() prefixes on functions. Name them after the thing they return
60 # - Don't expose dtlib stuff directly.
62 # - Add documentation for any new APIs you add.
108 The free-form description of the binding, or None.
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/Zephyr-latest/scripts/kconfig/
Dkconfiglib.py1 # Copyright (c) 2011-2019, Ulf Magnusson
2 # SPDX-License-Identifier: ISC
9 from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt)
27 $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | git am
28 …$ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | patch -…
30 Warning: Not passing -p1 to patch will cause the wrong file to be patched.
43 $ git am Kconfiglib/makefile.patch (or 'patch -p1 < Kconfiglib/makefile.patch')
53 ----------------
61 --------------
69 --------------------------------
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/Zephyr-latest/drivers/gpio/
Dgpio_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
33 #define GPIO_READ(r) sys_read16(config->gpio_base + (r))
34 #define GPIO_WRITE(r, v) sys_write16((v), config->gpio_base + (r))
35 #define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
43 uint8_t line; member
86 const struct gpio_nxp_s32_config *config = dev->config; in nxp_s32_gpio_configure()
91 return -ENOTSUP; in nxp_s32_gpio_configure()
[all …]
/Zephyr-latest/subsys/usb/usb_c/
Dusbc_tc_snk_states.c4 * SPDX-License-Identifier: Apache-2.0
20 struct usbc_port_data *data = dev->data; in sink_power_sub_states()
24 struct tc_sm_t *tc = data->tc; in sink_power_sub_states()
26 /* Get the active CC line */ in sink_power_sub_states()
27 cc = tc->cc_polarity ? tc->cc2 : tc->cc1; in sink_power_sub_states()
31 * This sub-state supports Sinks consuming current within the in sink_power_sub_states()
32 * lowest range (default) of Source-supplied current. in sink_power_sub_states()
38 * This sub-state supports Sinks consuming current within the in sink_power_sub_states()
39 * two lower ranges (default and 1.5 A) of Source-supplied in sink_power_sub_states()
46 * This sub-state supports Sinks consuming current within all in sink_power_sub_states()
[all …]
/Zephyr-latest/boards/nordic/nrf52840dk/
Dnrf52840dk_nrf52840.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "nrf52840dk_nrf52840-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "nordic,nrf52840-dk-nrf52840";
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
22 zephyr,bt-c2h-uart = &uart0;
27 compatible = "gpio-leds";
[all …]
/Zephyr-latest/arch/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
192 line option for gen_isr_tables.py.
195 # Hidden Kconfig option representing the default little-endian architecture
[all …]
/Zephyr-latest/dts/arm/st/l0/
Dstm32l0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32l0_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/dts/arm/st/c0/
Dstm32c0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/dma/stm32_dma.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]
/Zephyr-latest/dts/arm/st/f0/
Dstm32f0.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv6-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32f0_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32f0_1_3_reset.h>
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